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18 views19 pages

SJSU_EE288_lecture24_Oversampled_ADC2

Uploaded by

Ahmed Shafeek
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE288 Data Conversions/Analog Mixed-Signal ICs

Spring 2018

Lecture 24: Oversampled ADC 2

Prof. Sang-Soo Lee


[email protected]
ENG-259

1
Signals and Spectra in Oversampling ADC

2
First-Order Noise Shaping

3
First-Order Noise Shaping

4
First-Order Modulator SC Implementation

5
Switched-Capacitor Integrator
• Output of a continuous-time integrator can
be expressed as

• In Fig. (a), resistor R carries a current of (VA – VB)/R


• In Fig. (b), CS is alternately connected to A and B at a clock rate fCK
• Average current flowing from A to B is the charge moved in one clock period
• Can be viewed as a resistor of value

6
Switched-Capacitor Integrator

• Fig. (a) shows discrete-time integrator


• In every clock cycle, C1 absorbs a charge equal to C1Vin
when S1 is on and deposits it on C2 when S2 is on
• If Vin is constant, output changes by VinC1/C2 every clock
cycle [Fig. (b)]
• Final value of Vout after clock cycle can be written as

7
Switched-Capacitor Integrator

• Input-dependent charge injection of S1 introduces


nonlinearity in output voltage
• Nonlinear capacitance at node P resulting from
source/drain junctions of S1 and S2 leads to a nonlinear
charge-to-voltage conversion when C1 is switched to X

• Charge stored on the total junction capacitance, Cj is not


equal to Vin0Cj, but rather equal to

8
Switched-Capacitor Integrator

• Circuit of Fig. (a) resolves the issues in the simple integrator


• In sampling mode [Fig. (b)], S1 and S3 are on, S2 and S4 are
off, allowing voltage across C1 to track Vin while op amp and C2
hold previous value
• In the transition to integration mode, S3 turns off first, injecting
a constant charge onto C1, S1 turns off next, and subsequently
S2 and S4 turn on
• Charge stored on C1 is transferred to C2 through the virtual
ground node

9
Second-Order ∆Σ Modulator

10
Shaped Quantization Noise

11
Noise Shaping Rate

12
SQNR Improvement

13
Higher Order Modulator using Cascade of 2-stages

14
2nd-Order (1-1) Cascaded ∆Σ Modulator

15
MASH (Multi-stAge noise SHaping) structure

if

16
3rd-Order (1-1-1) Cascaded ∆Σ Modulator

17
3rd-Order (2-1) Cascaded ∆Σ Modulator

18
Summary of ∆Σ ADC

19

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