UNIT I

COMBINATIONAL LOGIC
Combinational Circuits – Analysis and Design Procedures - Binary Adder- Subtractor -Decimal Adder -
Binary Multiplier - Magnitude Comparator - Decoders – Encoders – Multiplexers - Introduction to HDL –
HDL Models of Combinational circuits.

COMBINATIONAL CIRCUITS
 A combinational circuit consists of logic gates whose outputs at any time are determined from only the
present combination of inputs.
 A combinational circuit performs an operation that can be specified logically by a set of Boolean
functions.

Sequential circuits:
 Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of
the inputs and the state of the storage elements.
 Because the state of the storage elements is a function of previous inputs, the outputs of a sequential
circuit depend not only on present values of inputs, but also on past inputs, and the circuit behavior must
be specified by a time sequence of inputs and internal states.

ANALYSIS PROCEDURE

Explain the analysis procedure. Analyze the combinational circuit the following logic diagram.
(May
2015)

 The analys is o f a co mbinat ional circuit requir es t hat we det er mine t he funct io n t hat
t he cir cuit implement s.
 The analys is can be per for med manually by finding t he Boolean funct io ns or trut h
t able or by using a co mput er simulat io n program.
 The first st ep in t he analys is is t o make t hat t he given circuit is co mbinat ional o r
sequent ial.
 Once t he logic diagram is ver ified t o be combinat ional, one can proceed t o obt ain t he
out put Boolean funct io ns or t he t rut h t able.
 To obtain the output Boolean functions from a logic diagram,
 Label all gate outputs that are a function of input variables with arbitrary symbols or names.
Determine the Boolean functions for each gate output.
 Label the gates that are a function of input variables and previously labeled gates with other
arbitrary symbols or names. Find the Boolean functions for these gates.
 Repeat the process in step 2 until the outputs of the circuit are obtained.
 By repeated substitution of previously defined functions, obtain the output Boolean functions in
terms of input variables.

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 Logic diagramforanalysis example

The Boolean functions for the above outputs are,

 Proceed to obtain the truth table for the outputs of those gates which are a function of previously
defined values until the columns for all outputs are determined.

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 DESIGNPROCEDURE
Explain the procedure involved in designing combinational circuits.
 The design of combinational circuits starts from the specification of the design objective and culminates
in a logic circuit diagram or a set of Boolean functions from which the logic diagram can be obtained.
 The procedure involved involves the following steps,
 From the specifications of the circuit, determine the required number of inputs and outputs and assign a
symbol to each.
 Derive the truth table that defines the required relationship between inputs and outputs.
 Obtain the simplified Boolean functions for each output as a function of the input variables.
 Draw the logic diagram and verify the correctness of the design.

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CIRCUITS FOR ARITHMETIC OPERATIONS

Half adder:
Construct a half adder with necessary diagrams. (Nov-06,May- 07)

 A half-adder is an arithmetic circuit block that can be used to add two bits and produce two outputs
SUM and CARRY.
 The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth Table:

Logic Diagram: Half adder using NAND gate:

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 Full adder:
Design a full adder using NAND and NOR gates respectively. (Nov -10)

 A Full-adder is an arithmetic circuit block that can be used to add three bits and produce two outputs
SUM and CARRY.
 The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth table:

Karnaugh map:

K-Map for Sum K-Map for Carry

 The simplified Boolean expressions of the outputs are
S = X′A′B + X′AB′ + XA′B′ + XAB
C = AB + BX + AX

Logic diagram:

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 The Boolean expressions of S and C are modified as follows

Full adder using Two half adder:

 Logic diagram according to the modified expression is shown Figure.

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Half subtractor:
Design a half subtractor circuit. (Nov-2009)

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 A half-subtractor is a combinational circuit that can be used to subtract one binary digit from anotherto
produce a DIFFERENCE output and a BORROW output.
 The BORROW output here specifies whether a ‘1’ has been borrowed to perform the subtraction. The
Boolean expression for difference and borrow is:

Logic diagram:

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Full subtractor:

Design a full subtractor. (Nov-2009,07)

 A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and also takes
into consideration whether a ‘1’ has already been borrowed by the previous adjacent lower minuend bit
or not.
 As a result, there are three bits to be handled at the input of a full subtractor, namely the two bits to be
subtracted and a borrow bit designated as Bin .
 There are two outputs, namely the DIFFERENCE output D and the BORROW output Bo. The
BORROW output bit tells whether the minuend bit needs to borrow a ‘1’ from the next possible higher
minuend bit. The Boolean expression for difference and barrow is:

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 K-Map:

Full subtractor using two half subtractor:

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Parallel Binary Adder: (Ripple Carry Adder):

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 Explain about four bit adder. (or) Design of 4 bit binary adder – subtractor circuit. (Apr – 2019)
 A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected
to the input carry of the next full adder in the chain.
 Addition of n-bit numbers requires a chain of n- full adders or a chain of one-half adder and n-1 full
adders. In the former case, the input carry to the least significant position is fixed at 0.
 Figure shows the interconnection of four full-adder (FA) circuits to provide a four-bit binary ripple carry
adder.
 The carries are connected in a chain through the full adders. The input carry to the adder is C0, and it
ripples through the full adders to the output carry C4. The S outputs generate the required sum bits.
Example: Consider the two binary numbers A = 1011and B = 0011. Their sum S = 1110 is formed with
the four-bit adder as follows:

 The carry output of lower order stage is connected to the carry input of the next higher order stage.
Hence this type of adder is called ripple carry adder.
 In a 4-bit binary adder, where each full adder has a propagation delay of tp ns, the output in the fourth
stage will be generated only after 4tp ns.
 The magnitude of such delay is prohibitive for high speed computers.
 One method of speeding up this process is look-ahead carry addition which eliminates ripple carry
delay.

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Complement of a number:
1’s complement:
The 1’s complement of a binary number is formed bychanging 1 to 0 and 0 to 1.
Example:
1. The 1’s complement of 1011000 is 0100111.
2. The 1’s complement of 0101101 is 1010010.
2’s complement:
The 2’s complement of a binary number is formed by adding 1 with 1’s complement of a binary
number.
Example:
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 1. The 2’s complement of 1101100 is 0010100
2. The 2’s complement of 0110111 is 1001001

Subtraction using 2’s complement addition:

 The subtraction of unsigned binary number can be done by means of complements.
 Subtraction of A-B can be done by taking 2’s complement of B and adding it to A.
 Check the resulting number. If carry present, the number is positive and remove the carry.
 If no carry present, the resulting number is negative, take the 2’s complement of result and put
negative sign.
Example:
Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y - X by using 2’s complements.
Solution:
(a) X = 1010100
2’s complement of Y = + 0111101
Sum= 10010001
Discard end carry. Answer: X - Y = 0010001
(b) Y = 1000011
2’s complement of X= + 0101100
Sum= 1101111
There is no end carry. Therefore, the answer is Y - X = -(2’s complement of 1101111) =-0010001.

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Parallel Binary Subtractor:

 The subtraction of unsigned binary numbers can be done most conveniently by meansof complements.
The subtraction A - B canbe done by taking the 2’s complement of B and adding it to A . The 2’s
complement canbe obtained by taking the 1’s complement and adding 1 to the least significant pair
ofbits. The 1’s complement can be implemented with inverters, and a 1 can be added tothe sum through
the input carry.
 The circuit for subtracting A - B consists of an adder with inverters placed betweeneach data input B and
the corresponding input of the full adder. The input carry Cin mustbe equal to 1 when subtraction is

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 performed. The operation thus performed becomes A,plus the 1’s complement of B , plus 1. This is equal
to Aplus the 2’s complement of B.
 For unsigned numbers, that gives A-B if A>=B or the 2’s complement of B - Aif A <B. For signed
numbers, the result is A - B, provided that there is no overflow.

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Fast adder (or) Carry Look Ahead adder:

Design a carry look ahead adder circuit. (Nov-2010)
 The carry look ahead adder is based on the principle of looking at the lower order bits of the augend
and addend to see if a higher order carry is to be generated.
 It uses two functions carry generate and carry propagate.

Consider the circuit of the full adder shown in Fig. If we define two new binaryvariables

the output sum and carry can respectively be expressed as

Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1,regardless of
the input carry Ci. Pi is called a carry propagate, because it determines whether a carry into stage i will
propagate into stage i + 1 (i.e., whether an assertion of Ci will propagate to an assertion of Ci+1 ).

We now write the Boolean functions for the carry outputs of each stage and substitutethe value
of each Ci from the previous equations:

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 The construction of a four-bit adder with a carry lookahead scheme is shown in Fig.
 Each sum output requires two exclusive-OR gates.
 The output of the first exclusive-OR gate generates the Pi variable, and the AND gate generates the Gi
variable.
 The carries are propagated through the carry look ahead generator and applied as inputs to the second
exclusive-OR gate.
 All output carries are generated after a delay through two levels of gates.
 Thus, outputs S1 through S3 have equal propagation delay times. The two-level circuit for the output
carry C4 is not shown. This circuit can easily be derived by the equation-substitution method.

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 ******************************

4 bit-Parallel adder/subtractor:
Explain about binary parallel / adder subtractor. [NOV – 2019]
 The addition and subtraction operations can be combined into one circuit with one common binary adder
by including an exclusive-OR gate with each full adder. A four-bit adder–subtractor circuit is shown in
Fig.
 The mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1, the
circuit becomes a subtractor.

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 It performs the operations of both addition and subtraction.
 It has two 4bit inputs A3A2A1 A0 and B3B2B1B0.
 The mode input M controls the operation when M=0 the circuit is an adder and when M=1 the circuits
become subtractor.
 Each exclusive-OR gate receives input M and one of the inputs of B .
 When M = 0, we have B xor0 = B. The full adders receive the value of B , the input carry is 0, and the
circuit performs A plus B . This results in sum S3S2S1S0and carry C4.
 When M = 1, we have B xor 1 = B’ and C0 = 1. The B inputs are all complemented and a 1 is added
through the input carry thus producing 2’s complement of B.
 Now the data A3A2A1 A0will be added with 2’s complement of B3B2B1B0to produce the sum i.e., A-B if
A≥B or the 2’s complement of B-A if A<B.

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Comparators
Design a 2 bit magnitude comparator. (May 2006)

It is a combinational circuit that compares two numbers and determines their relative magnitude. The
output of comparator is usually 3 binary variables indicating:
A<B, A=B, A>B

1-bitcomparator: Let’s begin with 1bit comparator and from the name we can easily make out that this
circuit would be used to compare 1bit binary numbers.
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 A B A>B A=B A<B
0 0 0 1 0
1 0 1 0 0
0 1 0 0 1
1 1 0 1 0

For a 2-bit comparator we have four inputs A1 A0 and B1 B0 and three output E (is 1 if two numbers are
equal) G (is 1 when A>B) and L (is 1 when A<B) If we use truth table and K-map the result is

Design of 2 – bit Magnitude Comparator.

The truth table of 2-bit comparator is given in table below

Truth table:

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K-Map:

Logic Diagram:

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 ********************

4 bit magnitude comparator:

Design a 4 bit magnitude comparators. (Apr – 2019)

Input

Function Equation

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 *************************

BCD Adder:
Design to perform BCD addition.(or) What is BCD adder? Design an adder to perform arithmetic
addition of two decimal bits in BCD. (May -08)(Apr 2017,2018)[Nov – 2019]

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 Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a
previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 9 + 9 + 1
= 19, the 1 in the sum being an input carry.
 Suppose we apply two BCD digits to a four-bit binary adder. The adder will form the sum in binary and
produce a result that ranges from 0 through 19. These binary numbers are listed in Table and are labeled
by symbols K, Z8, Z4, Z2, and Z1. K is the carry, and the subscripts under the letter Z represent the
weights 8, 4, 2, and 1 that can be assigned to the four bits in the BCD code.

 A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in Fig. The two
decimal digits, together with the input carry, are first added in the top four-bit adder to produce the
binary sum.

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 When the output carry is equal to 0, nothing is added to the binary sum. When it is equal to 1, binary
0110 is added to the binary sum through the bottom four-bit adder.
 The condition for a correction and an output carry can be expressed by the Boolean function
C = K + Z8Z4 + Z8Z2
 The output carry generated from the bottom adder can be ignored, since it supplies information already
available at the output carry terminal.
 A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from
one stage must be connected to the input carry of the next higher order stage.

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Binary Multiplier:
Explain about binary Multiplier.
 Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers.
The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. Each
such multiplication forms a partial product.
 Successive partial products are shifted one position to the left. The final product is obtained from the
sum of the partial products.

 A combinational circuit binary multiplier with more bits can be constructed in a similar fashion.
 A bit of the multiplier is ANDed with each bit of the multiplicand in as many levels as there are bits in
the multiplier.
 The binary output in each level of AND gates is added with the partial product of the previous level to
form a new partial product. The last level produces the product.

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 *************************************

CODE CONVERSION
Design a binary to gray converter. (Nov-2009)(Nov
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2017)
Binary to Grayconverter

Gray code is unit distance code.

Input code: Binary [B3 B2 B1 B0]
output code: Gray [G3 G2 G1 G0]

Truth Table

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-MAP FORG3: K-MAP FORG2:

G3=B3 G2=B3’B2+B3B2’=B3 B2

K-MAP FORG1: K-MAP FORG0:

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G1=B1’B2+B1B2’=B1 B2 G0=B1’ B0+B1B0’=B1 B0

Logic diagram:

Gray to Binary converter:

Design a gray to binary converter.(OR) Design a combinational circuit that converts a four bit gray
code to a four bit binary number using exclusive – OR gates. (Nov-2009) [NOV – 2019]
Gray code is unit distance code.
Input code: Gray [G3 G2 G1 G0]
output code: Binary [B3 B2 B1 B0]

Truth Table:

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K-Map:

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 Logic Diagram:

BCD to Excess -3 converter:

Design a combinational circuits to convert binary coded decimal number into an excess-3 code.

 Excess-3 code is modified form of BCD code. (Nov-06,09,10, May-08,10)

 Excess -3 code is derived from BCD code by adding 3to each coded number.

Truth table:

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K-Map:

Logic Diagram

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Excess -3 to BCD converter:
Design a combinational circuit to convert Excess-3 to BCD code. (May 2007)

Truth table:

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Design Binary to BCD converter.
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Truth table:

K-map:

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Logic diagram:

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DECODERS AND ENCODERS

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 Decoder:
Explain about decoders with necessary diagrams. (Apr 2018)(Nov 2018)

 A decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines. If the n -bit coded information has unused combinations, the decoder may
have fewer than 2n outputs.
 The purpose of a decoder is to generate the 2n (or fewer) minterms of n input variables, shown below for
two input variables.

2 to 4 decoder:

3 to 8 Decoder:
Design 3 to 8 line decoder with necessary diagram. May -10)
Truth table:

Logic diagram:

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 Design for 3 to 8 decoder with 2 to 4 decoder:

 Not that the two to four decoder design shown earlier, with its enable inputs can be used to build a three
to eight decoder as follows.

Implementation of Boolean function using decoder:

 Since the three to eight decoder provides all the minterms of three variables, the realisation of a
function in terms of the sum of products can be achieved using a decoder and OR gates as follows.
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Example: Implement full adder using decoder.

Sum is given by ∑m(1, 2, 4, 7) while Carry is given by ∑m(3, 5, 6, 7) as given by the minterms
each of the OR gates are connected to.

Design for 4 to 16 decoder using 3 to 8 decoder: Design 5 to 32 decoder using 3 to 8 and 2 to 4 decoder:

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BCD to seven segment decoder

Design a BCD to seven segment code converter. (May-06,10, Nov- 09)

Truth table:

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K-Map:

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 Logic Diagram:

 The specification above requires that the output be zeroes (none of the segments are lighted up) when
the input is not a BCD digit.
 In practical implementations, this may defer to allow representation of hexadecimal digits using the
seven segments.
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 Encoder:
Explain about encoders. (Nov 2018)
 An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or
fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code
corresponding to the input value.

Octal to Binary Encoder:

 The encoder can be implemented with OR gates whose inputs are determined directly from the truth
table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
 Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These conditions can
be expressed by the following Boolean output functions:

The encoder can be implemented with three OR gates.

Truth table:

 Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated when all the
inputs are 0; but this output is the same as when D0 is equal to 1. The discrepancy can be resolved by
providing one more output to indicate whether at least one input is equal to 1.

Logic Diagram:

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Priority Encoder:
Design a priority encoder with logic diagram.(or) Explain the logic diagram of a 4 – input priority
encoder. (Apr – 2019)
A priority encoder is an encoder circuit that includes the priority function. The operationof the
priority encoder is such that if two or more inputs are equal to 1 at the same time,the input having the
highest priority will take precedence.
Truth table:

Modified Truth table:

K-Map:

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Logic Equations:

Logic diagram:

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MULTIPLEXERS AND DEMULTIPLEXERS

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 Multiplexer: (MUX)
Design a 2:1 and 4:1 multiplexer.

 A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. The selection of a particular input line is controlled by a set of selection
lines.
 Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
selected.

2 to 1 MUX:

A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of an
AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1 mux
is given in the table below.

 To derive the gate level implementation of 2:1 mux we need to have truth table as shown in figure. And
once we have the truth table, we can draw the K-map as shown in figure for all the cases when Y is
equal to '1'.
Truth table:

Logic Diagram:

4 to 1 MUX:
 A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines I0 to I3 is applied to one input
of an AND gate.

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 Selection lines S0 and S1 are decoded to select a particular AND gate.
 The truth table for the 4:1 mux is given in the table below.

Logic Diagram:

Truth Table:
SELECT OUTPUT
INPUT
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Problems :
Example: Implement the Boolean expression using MUX
F(A,B,C,D) = ∑m(0,1,5,6,8,10,12,15) (Apr 2017, Nov 2017)

Example: Implement the boolean function using Multiplexer. [NOV – 2019]

F (x, y, z) = Σm (1, 2, 6, 7)

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 Solution:
Implementation table:

Multiplexer Implementation:

Example: 32:1 Multiplexer using 8:1 Mux (Nov 2018) (Apr – 2019)

DEMULTIPLEXERS:
Explain about demultiplexers.

 The de-multiplexer performs the inverse function of a multiplexer, that is it receives information on one
line and transmits its onto one of 2n possible output lines.

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 The selection is by n input select lines. Example: 1-to-4 De-multiplexer

Logic Diagram: Truth Table:

INPUT OUTPUT

E D S0 S1 Y0 Y1 Y2 Y3

1 1 0 0 1 0 0 0

1 1 0 1 0 1 0 0

1 1 1 0 0 0 1 0

1 1 1 1 0 0 0 1

Example:
1. Implement full adder using De-multiplexer.

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2. Implement the following functions using de-multiplexer.
f1 (A,B,C) = ∑m(1,5,7), f2 (A,B,C) = ∑m(3,6,7)
Solution:

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Parity Checker / Generator:

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 A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or
even. The message, including the parity bit, is transmitted and then checked at the receiving end for
errors. An error is detected if the checked parity does not correspond with the one transmitted.
 The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that
checks the parity in the receiver is called a parity checker.
 In even parity system, the parity bit is ‘0’ if there are even number of 1s in the data and the parity bit
is ‘1’ if there are odd number of 1s in the data.
 In odd parity system, the parity bit is ‘1’ if there are even number of 1s in the data and the parity bit is
‘0’ if there are odd number of 1s in the data.

3-bit Even Parity generator:

Truth Table:

Logic Diagram:

4-bit Even parity checker:

Truth Table:

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 Logic Diagram:

INTRODUCTION TO HDL

 In electronics, a hardware description language or HDL is any language from a class of computer
languages and/or programming languages for formal description of digital logic and electronic circuits.
 HDLs are used to write executable specifications of some piece of hardware.
 A simulation program, designed to implement the underlying semantics of the language statements,
coupled with simulating the progress of time, provides the hardware designer with the ability to model a
piece of hardware before it is created physically.
 Logic synthesis is the process of deriving a list of components and their interconnection (called net list)
from the model of a digital system.
 Logic Simulation is the representation of the structure and behavior of a digital logic synthesis through
the use of a computer.
 The standard HDLs that supported by IEEE.
 VHDL (very High Speed Integrated Circuit HDL)
 Verilog HDL

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 HDL MODELS OF COMBINATIONAL CIRCUITS

The Verilog HDL model of a combinational circuit can be described in any one of the following
modeling styles,

Gate level modeling-using instantiations of predefined and user defined primitive gates.
Dataflow modeling using continuous assignment with the keyword assign.
Behavioral modeling using procedural assignment statements with the keyword always.

Gate level modeling

In this type, a circuit is specified by its logic gates and their interconnections. Gate level modeling
provides a textual description of a schematic diagram. The verilog HDL includes 12basic gates as
predefined primitives. They are and, nand, or, nor, xor, xnor, not &buf.

Data flow modeling

Data flow modeling of combinational logic uses a number of operators that act on operands to produce
desired results. Verilog HDL provides about 30 different operators. Data flow modeling uses continuous
assignments and the keyword assign. A continuous assignment is a statement that assigns a value to a
net. The data type family net is used to represent a physical connection between circuit elements.

HDL for2-to-4 line decoder

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 Behavioral modeling

 Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to
describe sequential circuits, but can also be used to describe combinational circuits.
 Behavioral descriptions use the keyword always, followed by an optional event control expression and a
list of procedural assignment statements.

UNIT II
COMBINATIONAL LOGIC
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 TWO MARK QUESTIONS & ANSWERS

1) Define combinational logic. (May 2008, 2016)

A combinational circuit consists of logic gates whose outputs at any time are determined from
only the
present combination of inputs. A combinational circuit performs an operation that canbe specified
logically by a set of Boolean functions.

2) What are sequential circuits?

Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function
of the inputs and the state of the storage elements. Because the state of the storage elements is a function
of previous inputs, the outputs of a sequential circuit depend not only on present values of inputs, but also
on past inputs, and the circuit behavior must be specified by a time sequence of inputs and internal states.

3) Write the design procedure for combinational circuits?

The procedure involves the following steps:
1. From the specifications of the circuit, determine the required number of inputs and outputs and assign
a symbol to each.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input variables.
4. Draw the logic diagram and verify the correctness of the design (manually or by simulation).

4) What is Half adder?

A half-adder is an arithmetic circuit block that can be used to add two bits and produce two
outputs SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth Table:

5) Draw the logic diagram of half adder using NAND gate. (May 2006,13)

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Logic Diagram: Half adder using NAND gate:

6) What is Full adder? Draw the truth table of full adder. (Apr 2018)
A Full-adder is an arithmetic circuit block that can be used to add three bits and produce two
outputs SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations

7) Draw the Logic diagram of full adder.

8) What is Half subtractor? (May 2005)

A half-subtractor is a combinational circuit that can be used to subtract one binary digit from
another to produce a DIFFERENCE output and a BORROW output. The BORROW output here specifies
whether a ‘1’ has been borrowed to perform the subtraction. The Boolean expression for difference and
borrow is:

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 Logic diagram:

9) Draw Full adder using Two half adder. (Apr – 2019)

10) What is Full subtractor? Write the truth table of full subtractor. (Nov 2017)
A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and
also takes into consideration whether a ‘1’ has already been borrowed by the previous adjacent lower
minuend bit or not. As a result, there are three bits to be handled at the input of a full subtractor, namely
the two bits to be subtracted and a borrow bit designated as Bin . There are two outputs, namely the
DIFFERENCE output D and the BORROW output Bo. The BORROW output bit tells whether the
minuend bit needs to borrow a ‘1’ from the next possible higher minuend bit. The Boolean expression for
difference and barrow is:

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 11) Draw Full subtractor using two half subtractor.

12) What is Parallel Binary Adder (Ripple Carry Adder)?

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.It can
beconstructed with full adders connected in cascade, with the output carryfrom each full adder connected
to the input carry of the next full adder in the chain.
13) Draw the logic diagram for four bit binary parallel adder.

14) What is 1’s complement of a number?

The 1’s complement of a binary number is formed bychanging 1 to 0 and 0 to 1.
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 Example:
1. The 1’s complement of 1011000 is 0100111.
2. The 1’s complement of 0101101 is 1010010.
15) What is 2’s complement of a number?
The 2’s complement of a binary number is formed by adding 1 with 1’s complement of a binary
number.
Example:
1) The 2’s complement of 1101100 is 0010100
2) The 2’s complement of 0110111 is 1001001

16) How Subtraction of binary numbers perform using 2’s complement addition?
 The subtraction of unsigned binary number can be done by means of complements.
 Subtraction of A-B can be done by taking 2’s complement of B and adding it to A.
 Check the resulting number. If carry present, the number is positive and remove the carry.
 If no carry present, the resulting number is negative, take the 2’s complement of result and put
negative sign.

17) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y - X by using 2’s complements.
Solution:
(c) X = 1010100
2’s complement of Y = + 0111101
Sum= 10010001
Discard end carry. Answer: X - Y = 0010001

(d) Y = 1000011
2’s complement of X= + 0101100
Sum= 1101111
There is no end carry. Therefore, the answer is Y - X = -(2’s complement of 1101111) =-0010001.

18) Draw the logic diagram of Parallel Binary Subtractor.

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 19) Draw 1:8 Demux using two 1:4 demux. (Nov 2018)

20) Draw the logic diagram of 2’s complement adder/subtractor. (May 2013)

The mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1,
the circuit becomes a subtractor.

21) What is Magnitude Comparator? [NOV – 2019]

The comparison of two numbers is an operation that determines whether one number is
greater than, less than, or equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers A and B and determines their relative magnitudes.

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 The outcome of the comparison is specified by three binary variables that indicate whether A
> B, A = B, or A < B.

22) Design a 1-bit Magnitude Comparator.

Truth table:

Logic Circuits:

23) What is Decoder? What are binary decoders? (Nov 2017)

A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. If the n -bit coded information hasunused combinations, the
decoder may have fewer than 2 n outputs.

The purpose of a decoder is to generate the 2n (or fewer) minterms of n input variables, shown below
for two input variables.

24) Design a 3 to 8 decoder with 2 to 4 decoder.

Not that the two to four decoder design shown earlier, with its enable inputs can be used to build a
three to eight decoder as follows.

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 25) What is Encoder? (May 2012)
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder
has 2n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary
code corresponding to the input value.
26) What is Priority Encoder? (Apr 2017)
A priority encoder is an encoder circuit that includes the priority function. The operation of
the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.

27) Define Multiplexer (MUX) (or) Data Selector. (Dec 2006, May 2011) [NOV – 2019]
A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is controlled by
a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations
determine which input is selected.

28) What is De-multiplexer?

The de-multiplexer performs the inverse function of a multiplexer, that is it receives information on
one line and transmits its onto one of 2n possible output lines. The selection is by n input select
lines.
29) What is Parity?
A parity bit is an extra bit included with a binary message to make the number of 1’s either
odd or even. The message, including the parity bit, is transmitted and then checked at the receiving

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 end for errors. An error is detected if the checked parity does not correspond with the one
transmitted.
30) What is Parity Checker / Generator:
The circuit that generates the parity bit in the transmitter is called a parity generator. The
circuit that checks the parity in the receiver is called a parity checker.
31) What is even parity and odd parity?
In even parity system, the parity bit is ‘0’ if there are even number of 1s in the data and the
parity bit is ‘1’ if there are odd number of 1s in the data.
In odd parity system, the parity bit is ‘1’ if there are even number of 1s in the data and the
parity bit is ‘0’ if there are odd number of 1s in the data.
31) Give the applications of Demultiplexer.
i) It finds its application in Data transmission system with error detection.
ii) One simple application is binary to Decimal decoder.

32) Mention the uses of Demultiplexer.

Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only
in computers, but any time information from one source can be fed to several places.

33) Give other name for Multiplexer and Demultiplexer.

Multiplexer is otherwise called as Data selector.
Demultiplexer is otherwise called as Data distributor.
34) What is the function of the enable input in a Multiplexer?
The function of the enable input in a MUX is to control the operation of the unit.
35) List out the applications of decoder? (Dec 2006)
a. Decoders are used in counter system.
b. They are used in analog to digital converter.
c. Decoder outputs can be used to drive a display system.

36) What is the Application of Mux?

1. They are used as a data selector to select one output of many data inputs.
2. They can be used to implement combinational logic circuits
3. They are used in time multiplexing systems.
4. They are used in frequency multiplexing systems.
5. They are used in A/D & D/A Converter.
6. They are used in data acquisition system.

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37) List out the applications of comparators?
a. Comparators are used as a part of the address decoding circuitry in computers to select a
specific input/output device for the storage of data.
b. They are used to actuate circuitry to drive the physical variable towards the
reference value.
c. They are used in control applications.
38) What is carry look-ahead addition?
The speed with which an addition is performed limited by the time required forthe carries to
propagate or ripple through all of the stage of the adder. One method ofspeeding up the process is by
eliminating the ripple carry delay.

39) What is the Difference between Decoder & Demux.?

S.No Decoder Demux
1 Decoder is a many inputs to many Demux is a single input to many outputs
Outputs
2 There are no selection lines. The selection of specific output line is
controlled by the value of selection lines.

40) How Binary to Gray Code Conversion done?

Consider b1, b2, b3, b4 and b5 is the Binary Number and it is need be converted into Grey Code.
1. Write Most Significant Bit (MSB) is same as the MSB in Binary Number.

2. The second bit of the Grey code can be found by performing the Exclusive-OR (EX-OR)
operation between the First and second bits of the Binary Number.

3. The Third bit of the Grey code can be found by performing the Exclusive-OR (EX-OR) operation
between the Third and Second bits of the given Binary Number; and so on

EX-OR Operation:
1. Both the bits are 0 or 1 then the output of EX-OR gate will be 0.
2. Any one of the bit in two bits is 1 then the output of EX-OR gate will be 1.

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41) How Gray Code to Binary Conversion done?
Consider g0, g1, g2 and g3 is the Gray Code and it is need be converted into Binary Number. The
steps for Binary to Gray Code Conversion needs to be reversed to find out the equivalent Binary
Number

1. The Most Significant Bit (MSB) of the Binary is same as the First MSB of the Gray Code.

2. If the second Gray Bit is 0 then the second bit of the Binary is bit will be same as that of the First
Binary bit; if the Second Gray Bit is 1 then the Second Bit of the Binary will be inverse of its
previous binary bit. Refer the below image for easy understanding of Gray to Binary Conversion

32) Draw the circuit for 4 to 1 line multiplexer. (Apr 2017) [NOV – 2019]
Logic Diagram:

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Truth Table:
SELECT OUTPUT
INPUT
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

42) What do you meant by HDL?

Hardware description language (HDL)- hardware description language or HDL is any
language from a class of computer languages and/or programming languages for formal
description of digital logic and electronic circuits.

43) List the Verilog HDL model of a combinational circuits.

Gate level modeling-using instantiations of predefined and user defined primitive gates.
Dataflow modeling using continuous assignment with the keyword assign.
Behavioral modeling using procedural assignment statements with the keyword always.

44) What is meant by Gate level modeling?

In this type, a circuit is specified by its logic gates and their interconnections. Gate level
modeling provides a textual description of a schematic diagram.

45) What is meant by data flow modeling?

Data flow modeling of combinational logic uses a number of operators that act on
operands to produce desired results. Verilog HDL provides about 30 different operators.

46) What is meant by Behavioral modeling?

Behavioral modeling represents digital circuits at a functional and algorithmic level. It is
used mostly to describe sequential circuits, but can also be used to describe combinational
circuits.

47) What is Verilog?

Verilog is a general purpose hardware descriptor language. It has similar in syntax to the C
programming language. It can be used to model a digital system at many levels of abstraction
ranging from the algorithmic level to the switch level.

48) Define logic synthesis and simulation.

Logic synthesis is the process of deriving a list of components and their interconnection (called
netlist) from the model of a digital system.

Logic Simulation is the representation of the structure and behavior of a digital logic synthesis
through the use of a computer.

49) List the standard HDLs that supported by IEEE.

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  VHDL (very High Speed Integrated Circuit HDL)
 Verilog HDL
50) Write the truth table of 2 to 4 line decoder and draw its logic diagram. (Apr – 2019)

2 to 4 decoder:

51) State the different modeling techniques used in HDL. (Apr 2018)
 Gate level modeling
 Data flow modeling
 Behavioral modeling

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