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GRACE COLLEGE OF ENGINEERING

Mullakadu -628005

E
CO
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E

EC3352 --DIGITAL SYSTEM DESIGN LABORATORY

AC

LAB MANUAL
GR

ODD SEMESTER
YEAR/SEM: II/III

PREPARED BY
Mrs.E.M.Umaselvi, AP/ECE

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LIST OF EXPERIMENTS

1.Design of adders and subtractors & code converters.

2.Design of Multiplexers & Demultiplexers.
3.Design of Encoders and Decoders.
4.Design of Magnitude Comparators
5.Design and implementation of counters using flip-flops

E
6.Design and implementation of shift registers.

CO
E
AC
GR

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INDEX
Ex.No TITLE

1 STUDY OF LOGIC GATES

2a
CODE CONVERTOR
2b ADDER AND SUBTRACTOR
2c 4-BIT ADDER AND SUBTRACTOR
3 ENCODER AND DECODER
4 MAGNITUDE COMPARATOR
5 MULTIPLEXER AND DEMULTIPLEXER
6 SHIFT REGISTER

E
7a SYNCHRONOUS COUNTER
7b ASYNCHRONOUS COUNTER
CO
E
AC
GR

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Ex.No.-1 STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1

E
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
CO
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
E
AND GATE:
AC

The AND gate performs a logical multiplication commonly known as AND

function. The output is high when both the inputs are high. The output is low level
when any one of the inputs is low.

OR GATE:
GR

The OR gate performs a logical addition commonly known as OR function.

The output is high when any one of the inputs is high. The output is low level when
both the inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both
inputs are high.

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X- OR GATE:
The output is high when any one of the inputs is high. The output is low
when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

AND GATE

SYMBOL PIN DIAGRAM

E
CO
E
AC

OR GATE
GR

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NOT GATE

SYMBOL PIN DIAGRAM

E
CO
E
EX-OR GATE

SYMBOL PIN DIAGRAM

AC
GR

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2-INPUT NAND GATE

SYMBOL PIN DIAGRAM

E
CO
3-INPUT NAND GATE
E
AC
GR

RESULT:

The logic gates are studied and its truth tables are verified.

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Ex.No.-2a CODE CONVERTOR

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1

E
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5.
6.
IC TRAINER KIT
PATCH CORDS
CO -
-
1
35

THEORY:
E
The availability of large variety of codes for the same discrete elements of
AC

information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible even
though each uses different binary code.
GR

The bit combination assigned to binary code to gray code. Since each code uses
four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a
non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input
lines must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.

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A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D has been used to
implement partially each of three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

Binary Input Gray Code Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1

E
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0
0
1
1
0
0
CO
0
1
0
0
1
1
1
1
0
1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
E
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
AC

1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
GR

1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3

G3=B3

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K-Map for G2

E
K-Map for G1
CO
E
AC
GR

K-Map for G0

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LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

E
TRUTH TABLE:
CO
GRAY CODE BINARY CODE
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
E
0 0 0 1 0 0 0 1
AC

0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
GR

0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

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K-Map for B3:

B3=G3
K-Map for B2:

E
CO
E
AC

K-Map for B1:

GR

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K-Map for B0:

LOGIC DIAGRAM:

E
CO
E
AC
GR

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BCD to Excess 3 Convertor

E
K-Map for E3:
CO
E
AC
GR

E3=B3+B2(B0+B1)
K-Map for E2:

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K-Map for E1:

E
K-Map for E0:
CO
E
AC
GR

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EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

E
1 0 0 0 0 1 0 1

1 0 0
CO1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0
E
1 1 0 0 1 0 0 1
AC

EXCESS-3 TO BCD CONVERTOR

GR

K-Map for A:

A=X1X2+X3X4X1

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K-Map for B:

K-Map for C:

E
CO
E
AC
GR

K-Map for D:

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EXCESS-3 TO BCD CONVERTOR

E
CO
E
AC

PROCEDURE:
GR

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the following 4-bit converters are designed and constructed.

(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

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Ex.No.-2b ADDER AND SUBTRACTOR

AIM:
To design and construct half adder, full adder, half subtractor and
full subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1

E
6. PATCH CORDS - 23

THEORY:
CO
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
E
called as a carry signal from the addition of the less significant bits sum from the X-OR
Gate the carry out from the AND gate.
AC

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but
GR

a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry
output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor
has two input and two outputs. The outputs are difference and borrow. The difference can
be applied using X-OR Gate, borrow output can be implemented using an AND Gate and
an inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A B.
The output will be difference output of full subtractor. The expression AB assembles the
borrow output of the half subtractor and the second term is the inverted difference output
of first X-OR.

26

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HALF ADDER

K-Map for SUM: K-Map for CARRY:

E
1
1 CO
1
E
SUM = A’B + AB’ CARRY = AB
AC

LOGIC DIAGRAM:
GR

27

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FULL ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

E
K-Map for SUM CO
E
1
1
AC

1 1
GR

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY

CARRY = AB + BC + AC
28

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LOGIC DIAGRAM:

FULL ADDER USING TWO HALF ADDER

HALF SUBTRACTOR

E
TRUTH TABLE:
A B CO
BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
E
1 1 0 0
AC

K-Map for DIFFERENCE

GR

DIFFERENCE = A’B + AB’

K-Map for BORROW

BORROW = A’B
29

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LOGIC DIAGRAM

FULL SUBTRACTOR

TRUTH TABLE:
A B C BORROW DIFFERENCE

E
0 0 0 0 0
0 0 1 1 1
0
0
1
1
0
1
CO1
1
1
0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
E
1 1 1 1 1
AC

K-Map for Difference

GR

1 1

1 1

Difference = A’B’C + A’BC’ + AB’C’ +

ABC K-Map for Borrow

30

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Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

E
CO
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR
E
AC
GR

PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus, the half adder, full adder, half subtractor and full subtractor
circuits are designed, constructed and verified the truth table using logic gates.
31

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Ex.No.-2c 4-BIT ADDER AND SUBTRACTOR

AIM:

To design and implement 4-bit adder and subtractor using basic gates and MSI
device IC 7483.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1

E
4. PATCH CORDS - 40

THEORY:
CO
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
E
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends
bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to
AC

left, with subscript 0 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C0 and it ripples through the full
adder to the output carry C4.
GR

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C0 must be
equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal
digits must be represented in BCD and should appear in the form listed in the columns.

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ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.

PIN DIAGRAM FOR IC 7483:

E
4-BIT BINARY ADDER
CO
LOGIC DIAGRAM:
E
AC
GR

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4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:

E
CO
4- BIT BINARY ADDER/SUBTRACTOR
E
LOGIC DIAGRAM:
AC
GR

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TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:

E
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) CO
Observe the logical output and verify with the truth tables.
E
AC
GR

RESULT:

Thus the 4-bit adder and subtractor using basic gates and MSI
device IC 7483 isdesigned and implemented.

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Ex. No. 3 Decoders and Encoders

Aim
To be familiar with basics of conversion from binary to decimal by usingdecoder
networks.

Theory
1. Decoder
The process of taking some type of code and determining what it represents in terms
of a recognizable number or character is called decoding. A decoder is a combinational logic

E
circuit that performs the decoding function, and produce an output that indicates the (meaning)
of the input code. CO
The decoder is an important part of the system which selects the cells to be read from and
write into. This particular circuit is called a decoder matrix, or simply a decoder, and has a
characteristic that for each of the possible 2n binary input number which can be taken by the n
E
input cells, the matrix will have a unique one of its 2n output lines selected.
AC

n 2n
Input n×2n Output
Decoder
GR

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The decoder is called n to m where m < 2n for example two to four line decoder,Fig. (1) shows a
two to four line decoder and its truth table.
W0
X1
2×4 W1
X2 W2
Decoder
W3

INPUTS OUTPUTS
X2 X1 W0 W1 W2 W3
0 0 1 0 0 0
0 1 0 1 0 0

E
1 0 0 0 1 0
1 1 0 CO 0 0 1

Table (1)
Two to Four Decoder Truth Table
E
AC

W0
GR

X2
W1

X1
W2

W3

Fig. (1)
Two to Four Line Decoder

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The BCD Decoder

The BCD decoder converts each BCD code (8421) into one of ten possible decimal
digit indications. It is typically referred to as a 1 of 10 or 4 to 10 lines decoder, although other
types of decoder also fall into this category (such as an Execs – 3 decoder). A list of the ten
BCD code words and their corresponding decoding functions is shown in Table (2). Each of
these decoding functions is implemented with NAND gates to provide active LOW outputs, as
shown in Fig. (2).

DECIMAL OUTPUTS LOGIC FUNCTION

DIGIT 0 1 2 3 4 5 6 7 8 9 (X)
0 0 1 1 1 1 1 1 1 1 1 DCB A

E
1 1 0 1 1 1 1 1 1 1 1 DCB A
2
3
1
1
1
1
0
1
1
0
1
1
CO
1
1
1
1
1
1
1
1
1
1
DCB A
DCB A
4 1 1 1 1 0 1 1 1 1 1 DCB A
E
5 1 1 1 1 1 0 1 1 1 1 DCB A
AC

6 1 1 1 1 1 1 0 1 1 1 DCB A
7 1 1 1 1 1 1 1 0 1 1 DCB A
GR

8 1 1 1 1 1 1 1 1 0 1 DCB A
9 1 1 1 1 1 1 1 1 1 0 DCB A

Table (2)
Truth Table of BDC to Decimal Decoder

The 7442 is an integrated circuit BCD to Decimal decoder. Note that onthis device the
inputs are A, B, C, and D where A is the least significant bit.

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A
B
0
C
D
A
B
1
C
D
A
B
2
C
A D
A
B 3
Each C
variable and D
B its A
complement B
BCD 4

E
are C
INPUT connected D

C
CO
to
appropriate
decode gate
input.
C
B
A
5
D
A
B
6
E
C
D D
A
AC

B 7
C
D
A
GR

B 8
C
D
A
B 9
C
D

Fig (2)
Logic for BCD Decoder.

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2. Encoder
An encoder is a combinational logic circuit that generate n output linesfrom 2n (or
less) inputs. It has the reverse function of the decoder.

2n n
Input 2n×n Output
Encoder

An encoder accepts digit on its inputs, such as a decimal or octal digit, and
converts it to a coded output, such as a binary or BCD. Encoder can also be devised to encode

E
various symbol and alphabetic characters. This process of converting from familiar symbols
or numbers to a coded format is called encoding.
CO
Figure (2) shown a four to two line encoder and its truth table.

INPUTS OUTPUTS
E
W3 W2 W1 W0 X2 X1
AC

0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
GR

1 0 0 0 1 1

Table (3)
Truth Table of Four to Two Line Encoder.

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W1
X1

W3

X2
W2

Fig. (3)
Four to Two line Encoder

Procedure

E
1. Construct a circuit as shown in Fig. (1), set data switches as shownin the two to four lines
CO
decoder output table. Record the output indications of L1 to L4.
2. Install one 7442 BCD to Decimal Decoder in the logic lab.breadboard. Set
data switches as shown in the BCD to Decimal Decoder outputtable in Fig. (2). Record the output
E
indications output pins.
3. Construct the circuit as shown in Fig. (3), set data switches as shown in the four to two
AC

line encoder truth table. Record the outputindications of L1 & L2.

GR

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Ex.No.-4 MAGNITUDE COMPARATOR

AIM:

To design and implement the magnitude comparator using MSI device.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE COMPARATOR IC 7485 2

E
6. IC TRAINER KIT - 1
7. PATCH CORDS CO - 30

THEORY:

The comparison of two numbers is an operator that determine one number is greater
E
than, less than (or) equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers A and B and determine their relative magnitude. The
AC

outcome of the comparator is specified by three binary variables that indicate whether
A>B, A=B (or) A<B.

A=A3 A2 A1 A0
GR

B=B3 B2 B1 B0

The equality of the two numbers and B is displayed in a combinational circuit

designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs of
significant digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as

1 1 1 1
A>B = A3B3 + X3A2B2 + X3X2A1B1 + X3X2X1A0B0
1 1 1 1
A<B = A3 B3 + X3A2 B2 + X3X2A1 B1 + X3X2X1A0 B0

41

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The same circuit can be used to compare the relative magnitude of two
BCD digits. Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

฀ ฀ ฀ ฀

x3 x2 x1 x0

PIN DIAGRAM FOR IC 7485:

E
CO
E
AC
GR

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E
CO
PROCEDURE:
(i) Connections are given as per circuit diagram.
E
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AC
GR

RESULT:

Thus the magnitude comparator using MSI device is designed and implemented.

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Ex.No.-5 MULTIPLEXER AND DEMULTIPLEXER

AIM:

To design and implement the multiplexer and demultiplexer using logic gates
and study of IC 74150 and IC 74154.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1

E
3. PATCH CORDS - 32

THEORY:
CO
MULTIPLEXER:
E
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
AC

binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there
n
GR

are 2 input line and n selection lines whose bit combination determine which input is

selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.

44

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4:1 MULTIPLEXER

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’

E
0 1 D1 → D1 S1’ S0
1 0 CO D2 → D2 S1 S0’
1 1 D3→D3S1S0

Y=D0S1’S0’+D1S1’S0+D2S1S0’+D3S1S0
E
TRUTH TABLE:
AC

S1 S0 Y = OUTPUT

0 0 D0
GR

0 1 D1

1 0 D2

1 1 D3

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CIRCUIT DIAGRAM FOR MULTIPLEXER:

E
CO
1:4 DEMULTIPLEXER

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

E
AC
GR

FUNCTION TABLE:

S1 S0 INPUT
0 0 X→D0=XS1’S0’
0 1 X→D1=XS1’S0
1 0 X→D2=XS1S0’
1 1 X→D3=XS1S0

Y=XS1’S0’+XS1’S0+XS1S0’+XS1S0

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TRUTH TABLE:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

LOGIC DIAGRAM FOR DEMULTIPLEXER:

E
CO
E
AC
GR

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PIN DIAGRAM FOR IC 74150:

E
PIN DIAGRAM FOR IC 74154:

CO
E
AC
GR

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the multiplexer and demultiplexer using logic gates are designed
and implemented.

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Ex.No.-6 SHIFT REGISTER

AIM:

To design and implement the following shift registers

(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

E
2. OR GATE IC 7432 1

3. IC TRAINER KIT
CO - 1

4. PATCH CORDS - 35

THEORY:
E
A register is capable of shifting its binary information in one or both directions is
AC

known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
GR

simplest possible shift register is one that uses only flip flop. The output of a given flip flop
is connected to the input of next flip flop of the register. Each clock pulse shifts the content
of register one bit position to right.

PIN DIAGRAM OF IC 7474:

49

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SERIAL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

E
CLK Serial In Serial Out
1
2
3
1
0
0
CO 0
0
0
4 1 1
5 X 0
E
6 X 0
AC

7 X 1

SERIAL IN PARALLEL OUT

GR

LOGIC DIAGRAM:

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TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

PARALLEL IN SERIAL OUT

LOGIC DIAGRAM:

E
CO
E
AC

TRUTH TABLE:
GR

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

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PARALLEL IN PARALLEL OUT

LOGIC DIAGRAM:

E
TRUTH TABLE:

CLK
D
DATA INPUT
D D
COD Q
OUTPUT
Q Q Q
A B C D A B C D
1 1 0 0 1 1 0 0 1
E
2 1 0 1 0 1 0 1 0
AC

PROCEDURE:
(i) Connections are given as per circuit diagram.
GR

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
The Serial in serial out, Serial in parallel out, Parallel in serial out
and Parallel in parallel out shift registers are designed and implemented.

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Ex.No.-7a SYNCHRONOUS COUNTER (UP- DOWN COUNTER)

AIM:

To design and implement synchronous counter.

APPARATUS REQUIRED:

S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
2. JK Flip Flop IC 7473 2
3. D Flip Flop IC 7473 1
4. NAND gate IC 7400 1
5. Connecting wires As required

E
THEORY: CO
Synchronous Counters are so called because the clock input of all the individual
flip-flops within the counter are all clocked together at the same time by the same clock
signal
E

A counter is a register capable of counting number of clock pulse arriving at its

AC

clock input. Counter represents the number of clock pulses arrived. A specified sequence
of states appears as counter output. This is the main difference between a register and a
GR

counter. There are two types of counter, synchronous and asynchronous. In synchronous
common clock is given to all flip flop and in asynchronous first flip flop is clocked by
external pulse and then each successive flip flop is clocked by Q or Q output of previous
stage. A soon the clock of second stage is triggered by output of first stage. Because of
inherent propagation delay time all flip flops are not activated at same time which results
in asynchronous operation.

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PIN DIAGRAM FOR IC 7476:

CIRCUIT DIAGRAM:

E
CO
E
AC

TRUTH TABLE:
GR

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PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

E
CO
E
AC
GR

RESULT:

Thus the synchronous counter are designed and implemented.

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Ex.No.-7b ASYNCHRONOUS COUNTER

AIM:

To design and implement Asynchronous counter.

APPARATUS REQUIRED:

S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
2. JK Flip Flop IC 7473 2
3. D Flip Flop IC 7473 1
4. NAND gate IC 7400 1
5. Connecting wires As required

E
THEORY: CO
Asynchronous decade counter is also called as ripple counter. In a ripple counter
the flip flop output transition serves as a source for triggering other flip flops. In other
words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses
E
but rather by the transition that occurs in other flip flops. The term asynchronous refers to
the events that do not occur at the same time. With respect to the counter operation,
AC

asynchronous means that the flip flop within the counter are not made to change states at
exactly the same time, they do not because the clock pulses are not connected directly to
GR

the clock input of each flip flop in the counter.

A counter is a register capable of counting number of clock pulse arriving at its

clock input. Counter represents the number of clock pulses arrived. A specified sequence
of states appears as counter output. This is the main difference between a register and a
counter. There are two types of counter, synchronous and asynchronous. In synchronous
common clock is given to all flip flop and in asynchronous first flip flop is clocked by
external pulse and then each successive flip flop is clocked by Q or Q output of previous
stage. A soon the clock of second stage is triggered by output of first stage. Because of
inherent propagation delay time all flip flops are not activated at same time which results
in asynchronous operation.

53

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PIN DIAGRAM FOR IC 7476:

E
CO
E
AC
GR

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LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

E
TRUTH TABLE:
CO
CLK QA QB QC QD
E
0 0 0 0 0
1 1 0 0 0
AC

2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
GR

5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the asynchronous counter are designed and implemented.

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E
CO
E
AC
GR

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