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DPP - Daily Practice Problems

Name : Date :

Start Time : End Time :

SYLLABUS : SEMICONDUCTOR ELECTRONICS-2 (Junction transistor, transistor action, characteristics of a

58
transistor, transistor as an amplifier, logic gates)

Max. Marks : 112 Time : 60 min.

GENERAL INSTRUCTIONS
• The Daily Practice Problem Sheet contains 28 MCQ's. For each question only one option is correct. Darken the correct
circle/ bubble in the Response Grid provided on each page.
• You have to evaluate your Response Grids yourself with the help of solution booklet.
• Each correct answer will get you 4 marks and 1 mark shall be deduced for each incorrect answer. No mark will be given/
deducted if no bubble is filled. Keep a timer in front of you and stop immediately at the end of 60 min.
• The sheet follows a particular syllabus. Do not attempt the sheet before you have completed your preparation for that
syllabus. Refer syllabus sheet in the starting of the book for the syllabus of all the DPP sheets.
• After completing the sheet check your answers with the solution booklet and complete the Result Grid. Finally spend time
to analyse your performance and revise the areas which emerge out as weak in your evaluation.

DIRECTIONS (Q.1-Q.20) : There are 20 multiple choice Q.3 In an NPN transistor 1010 electrons enter the emitter in
questions. Each] question has 4 choices (a), (b), (c) and (d), 10–6 s and 2% electrons recombine with holes in base,
out of which ONLY ONE choice is correct. then a and b respectively are
(a) a = 0.98, b = 49 (b) a = 49, b = 0.98
Q.1 A NPN transistor conducts when (c) a = 0.49, b = 98 (d) a = 98, b = 0.49
(a) both collector and emitter are positive with respect
Q.4 If l1, l2 , l3 are the lengths of the emitter, base and collector
to the base
(b) collector is positive and emitter is negative with of a transistor then
respect to the base (a) l1 = l2 = l3 (b) l3 < l2 > l1
(c) collector is positive and emitter is at same potential (c) l3 < l1 < l2 (d) l3 > l1 > l2
as the base Q.5 In an NPN transistor circuit, the collector current is 10
(d) both collector and emitter are negative with respect mA. If 90% of the electrons emitted reach the collector,
to the base the emitter current (iE) and base current (iB) are given by
Q.2 In the case of constants a and b of a transistor (a) iE = -1mA, iB = 9mA (b) iE = 9mA, iB = -1mA
(a) a = b (b) b < 1, a > 1
(c) iE = 1mA, iB = 11mA (d) iE = 11mA, iB = 1mA
(c) a = b2 (d) b > 1, a < 1

RESPONSE GRID 1. 2. 3. 4. 5.
Space for Rough Work
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Q.6 The transfer ratio of a transistor is 50. The input resistance Q.12 For the given combination of gates, if the logic states of
of the transistor when used in the common-emitter inputs A, B, C are as follows A = B = C = 0 and
configuration is 1 kW. The peak value for an A.C input
A = B = 1,
voltage of 0.01 V peak is
C = 0 then the logic states of output D are
(a) 100 μA (b) 0.01 mA
(c) 0.25 mA (d) 500 μA
Q.7 For transistor, the current amplification factor is 0.8. The
transistor is connected in common emitter configuration. (a) 0, 0 (b) 0, 1 (c) 1, 0 (d) 1, 1
The change in the collector current when the base current Q.13 Correct statement for ‘NOR’ gate is that, it gives
changes by 6 mA is (a) high output when both the inputs are low
(a) 6 mA (b) 4.8 mA (b) low output when both the inputs are low
(c) 24 mA (d) 8 mA (c) high output when both the inputs are high
Q.8 In NPN transistor the collector current is 10 mA. If 90% (d) None of these
of electrons emitted reach the collector, then Q.14 A gate has the following truth table
(a) emitter current will be 9 mA P 1 1 0 0
(b) emitter current will be 11.1 mA Q 1 0 1 0
(c) base current will be 0.1 mA
(d) base current will be 0.01 mA R 1 0 0 0
Q.9 In a transistor in CE configuration, the ratio of power gain The gate is
to voltage gain is (a) NOR (b) OR (c) NAND (d) AND
(a) a (b) b / a Q.15 What will be the input of A and B for the Boolean
(c) ba (d) b expression ( A + B).( A.B) = 1
Q.10 The following truth table corresponds to the logic gate (a) 0, 0 (b) 0, 1 (c) 1, 0 (d) 1, 1
Q.16 To get an output 1 from the circuit shown in the figure, the
A 0 0 1 1 input can be
B 0 1 0 1
X 0 1 1 1
(a) NAND (b) OR
(c) AND (d) XOR
Q.11 The truth table shown in figure is for (a) A = 0, B = 1, C = 0 (b) A = 1, B = 0, C = 0
A 0 0 1 1 (c) A = 1, B = 0, C = 1 (d) A = 1, B = 1, C = 0
Q.17 The truth-table given below is for which gate?
B 0 1 0 1
A 0 0 1 1
Y 1 0 0 1
B 0 1 0 1
(a) XOR (b) AND
C 1 1 1 0
(c) XNOR (d) OR
(a) XOR (b) OR (c) AND (d) NAND

6. 7. 8. 9. 10.
RESPONSE
11. 12. 13. 14. 15.
GRID
16. 17.

Space for Rough Work

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Q.18 The combination of gates shown below produces Q.22 Given below are symbols for some logic gates. The XOR
gate and NOR gate are respectively
(1) (2)

(3) (4)
(a) AND gate (b) XOR gate Q.23 Given below are four logic gates symbol (figure). Those
(c) NOR gate (d) NAND gate for OR, NOR and NAND are respectively
Q.19 Figure gives a system of logic gates. From the study of A y A y
(1) (2) B
truth table it can be found that to produce a high output (1) B
at R, we must have A y A y
(3) B (4) B

DIRECTIONS (Q.24-Q.25) : Read the passage given below

and answer the questions that follows :
Doping changes the fermi energy of a semiconductor. Consider
(a) X = 0, Y = 1 (b) X = 1, Y = 1 silicon, with a gap of 1.11 eV between the top of the valence
(c) X = 1, Y = 0 (d) X = 0, Y = 0 bond and the bottom of the conduction band. At 300K the Fermi
Q.20 In the case of a common emitter transistor as/an amplifier, level of the pure material is nearly at the mid-point of the gap.
the ratio Ic /Ie is 0.96, then the current gain (b) of the amplifier Suppose that silicon is doped with donor atoms, each of which
is has a state 0.15 eV below the bottom of the silicon conduction
(a) 6 (b) 48 band, and suppose further that doping raises the Fermi level to
(c) 24 (d) 12 0.11 eV below the bottom of that band.
DIRECTIONS (Q.21-Q.23) : In the following questions, Conduction Band

more than one of the answers given are correct. Select the
correct answers and mark it according to the following Fermi Donor
1.11eV level level
codes:
Codes :
(a) 1, 2 and 3 are correct (b) 1 and 2 are correct
(c) 2 and 4 are correct (d) 1 and 3 are correct Valence Band

Q.21 Which of the following are false? Q.24 For both pure and doped silicon, calculate the probability
(1) Common base transistor is commonly used because that a state at the bottom of the silicon conduction band is
current gain is maximum occupied? (e4.524 = 70.38)
(2) Common collector is commonly used because current (a) 5.20 × 10–2 (b) 1.40 × 10–2
gain is maximum (c) 10.5 × 10 –2 (d) 14 × 10–2
(3) Common emitter is the least used transistor Q.25 Calculate the probability that a donor state in the doped
(4) Common emitter is commonly used because current material is occupied? e–1.547 = 0.212
gain is maximum (a) 0.824 (b) 0.08
(c) 0.008 (d) 8.2

RESPONSE 18. 19. 20. 21. 22.

GRID 23. 24. 25.

Space for Rough Work

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DIRECTIONS (Q. 26-Q.28) : Each of these questions contains Q.27 Statement -1 : The following circuit represents ‘OR’ gate
two statements: Statement-1 (Assertion) and Statement-2
(Reason). Each of these questions has four alternative choices,
only one of which is the correct answer. You have to select the
correct choice. Statement-2 : For the above circuit Y = X = A + B = A + B

(a) Statement-1 is True, Statement-2 is True; Statement-2 is a Q.28 Statement -1 : De-morgan’s theorem A + B = A.B may be
correct explanation for Statement-1. explained by the following circuit
(b) Statement-1 is True, Statement-2 is True; Statement-2 is
NOT a correct explanation for Statement-1.
(c) Statement -1 is False, Statement-2 is True.
(d) Statement -1 is True, Statement-2 is False.
Q.26 Statement -1 : The logic gate NOT cannot be built by using
diode.
Statement -2 : In the following circuit, for output 1 inputs
Statement -2 : The output voltage and the input voltage of
A,B,C are 1, 0, 1.
the diode have 180° phase difference.

RESPONSE GRID 26. 27. 28.

DAILY PRA CTICE PROBLEM SHEET 58 - PHYSICS

Total Questions 28 Total Marks 112
Attempted Correct
Incorrect N et Score
Cut-off Score 26 Qualifying Score 46
Success Gap = Net Score – Qualifying Score
Net Score = (Correct × 4) – (Incorrect × 1)

Space for Rough Work