OUTLINE

 Overview of Embedded System

y
 Elements of an Embedded System
 Components of ES Hardware
 Processor/Core
CHAPTER 3  Memory
ELEMENTS OF EMBEDDED SYSTEMS  Sensor and Actuator
 Communication Interface
 Support Circuits
 Interrupt Controller
 Embedded Firmware
1

OVERVIEW OF EMBEDDED SYSTEM OVERVIEW OF EMBEDDED SYSTEM…

 An Embedded System has three main components  Note the following about the terms firmware and ROM image
 Hardware
 Similar to Computer (Processor, Memory, I/O Subsystem, Timers, Peripherals)  Firmware
 Refers to the control algorithm (Program instructions) and or the configuration settings that
an embedded system developer dumps into the code (Program) memory of the embedded
 Application Software system
 Developed to perform certain functionalities  Responsible for controlling the various peripherals of the embedded hardware and generating
 Generating response in accordance with the functional requirements of the ES response in accordance with the functional requirements of the product
 Imparts intelligence to the Embedded system  Imparts intelligence to an Embedded system
 May concurrently perform a series of tasks or processes or threads  Can be developed
p on top p of an embedded operating
p g system
y or without an operating
p g system
y
 Usually stored in ROM/Flash  Sometime ES referred to contain HW and Software (Firmware)

 Real Time Operating System (RTOS)  ROM Image

 The instruction code and the data in the final development phase of ES that are placed in the
 Supervises
p the application
pp software runningg on HW and organizes
g access to a resource
ROM or flash
fl h memory, containing
t i i allll the
th tasks
t k that
th t are executed
t d when
h the
th system
t runs
according to the priorities of tasks  The final stage software
 Employed in ES products demanding real‐time response, i.e. having real time constraints  May contain boot up program, application programs, ISRs, RTOS, Input data and vector
and deadlines addresses
 RTOS respond in a timely and predictable manner to events
 Small scale embedded system may not need an RTOS 3 4
 ELEMENTS OF AN EMBEDDED SYSTEM ELEMENTS OF AN EMBEDDED SYSTEM…
 Diagram depicting the elements of an Embedded System  A typical ES contains a single chip controller (processor) which acts as the
master brain
b i off the
h system
 Core of the ES
 The program (code) memory holds the control algorithm (Program
Instructions)) and other important
p configuration
g settings
g ((details),
), which
imparts intelligence to the ES ‐‐‐‐ The firmware

 ES are basically designed to regulate physical variable

 The control is achieved by processing the information coming from the
sensors and user interfaces and controlling some actuators that regulate the
physical variable
 The sensor information is passed to the processor after signal conditioning
and
d digitization
di iti ti
 The core of the system performs some predefined operations on input
data with the help of embedded firmware in the system
 The core then sends some actuating signals to the actuator connected to
5 the output port of the system 6

ELEMENTS OF AN EMBEDDED SYSTEM… COMPONENTS OF ES HARDWARE

 There are two types of memories used in any embedded system  Components of embedded system hardware
 ROM (Fixed
(Fi d Memory)
M )  Processor/Core
 Used for storing code or program
 Memory
 The user cannot change the firmware in this type of memory
 The most common types of memories used in embedded systems for control algorithm  Sensor and Actuators
storage are  I/O
/ Subsystem
y
 OTP, PROM, UVEPROM, EEPROM and FLASH  Communication Interfaces
 RAM (Working Memory)  Supervisory systems and Support
 Temporary memory for performing arithmetic operations or control algorithm execution  Interrupt Controller
 Most common types are
 SRAM, DRAM, NRAM  Signal conditioning

 User interface input devices usually include Keyboards, push button, switches
etc.
 U interface
User i t f output
t t devices
d i i l d LEDs,
include LED LCDs,
LCD Piezoelectric
Pi l t i buzzers
b etc
t
 The requirement of type of user interface changes from application to
application based on domain
 An embedded system without a control algorithm implemented memory will
nott be
b capable
bl off making
ki any decision
d i i depending
d di on the
th situational
it ti l as wellll as 7 8
real world changes
 COMPONENTS OF ES HARDWARE PROCESSOR/CORE
PROCESSOR/CORE GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS
 Embedded systems are built around a central  General Purpose and Domain Specific Processors could be further
classified into
core  Microprocessors
 Microcontrollers
 The core of the ES falls into any one of the  Digital Signal Processors (DSP)

following categories  Almost 80% of embedded systems are processor/controller based

 General Purpose and Domain Specific Processors  The processor may be 𝝁𝑷 or a 𝝁𝑪 or DSP, depending on the
 Application Specific Integrated Circuits (ASICs) domain and application
 Most of the embedded system in the industrial control and
 Programmable
P bl Logic
L i Devices
D i (PLD )
(PLDs) monitoring applications make use of the commonly available 𝝁𝑷
 Commercial off‐the‐shelf Components (COTS) or 𝝁𝑪
9
 But domains which require signal processing such as speech 10
coding, speech reorganization etc. make use of DSPs

GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS
MICROPROCESSOR MICROCONTROLLER
 A silicon chip
p representing
p g a central p
processingg unit ((CPU))  A highly integrated silicon chip containing
 CPU, RAM, Special and General purpose Registers
 In general the CPU contains the Arithmetic and Logic Unit (ALU),
 On Chip ROM/FLASH memory
control unit and working registers  Timer and Interrupt control units and dedicated I/O ports
 Microprocessor is a dependent unit and requires other
hardware units for proper functioning  Contains all the necessary functional blocks for independent working
 Can be considered as a super set of microprocessors
 Memory, Timer Unit, and Interrupt controller etc
 Heavilyy utilized in the embedded domain in p place of microprocessors
p
 IIntel
t l claims
l i th
the credit
dit for
f d l i
developing th
the fi t
first  Cheap, cost effective and readily available in the market
Microprocessor unit ‐ Intel 4004  Can be
 A 4 bit processor which was released in Nov 1971, designed for  General purpose (like Intel 8051, designed for generic applications and
calculators domains) OR
 Application specific (Like Automotive AVR from Atmel Corporation designed
 Key players in the microprocessors market are
specifically for automotive applications)
 Intel, AMD, Freescale, GLOBALFOUNDRIES, TI, Cyrix, NVIDIA,  Texas Instrument
Instrument’ss TMS 1000 is considered as the world
world’ss first
Qualcomm, MediaTek etc 11 12
microcontroller
 GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS
MICROPROCESSOR VS. MICROCONTROLLER MICROPROCESSOR VS. MICROCONTROLLER…
Microprocessor Microcontroller
A silicon chip representing a CPU, which is capable of Highly integrated chip that contains a CPU, scratch
performing arithmetic as well as logical operations pad RAM, special and general purpose register arrays,
according to a pre‐defined set of instructions on chip ROM/FLASH memory for program storage,
timer and interrupt control units and dedicated I/O
ports
A dependent unit. It requires the combination of A self‐contained unit and it doesn’t require external
other chips like timers, program and data interrupt controller, timer, UART, etc. for its
memory chips, interrupt controllers, etc. for functioning
functioning
Most of the time general purpose in design Mostly application‐oriented or domain‐specific
and operation

Doesn t contain a built in I/O port.

Doesn’t port The I/O port Most of the processors contain multiple builtbuilt‐in
in
functionality needs to be implemented with the help I/O ports which can be operated as a single 8 or
of external programmable peripheral interface chips 16 or 32 bit port or as individual port pins
like 8255
Targeted for high end market where performance is Targeted for embedded market where performance is
13 important not so critical (At present this demarcation is invalid) 14

Limited power saving options Includes lot of power saving features

GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS
DSP DSP…
 Powerful special purpose 8/16/32 bit microprocessors designed  A typical DSP incorporates the following key units
 Program Memory
specifically to meet the computational demands and power  For storing the program required by DSP to process the data
constraints of today's embedded audio, video, and  Data Memory
 Working memory for storing temporary variables and data/signal to be processed
communications applications
pp  Computational Engine
 2 to 3 times faster than the general purpose microprocessors in  Performs the signal processing in accordance with the stored program memory
signal processing applications  I/O Unit
 Acts as an interface between the outside world and DSP
 DSPs implement algorithms in hardware which speeds up the  Responsible
espo s b e for
o cap
capturing
u g ssignals
g a s to
o be p
processed
ocessed aand
d de
delivering
e g thee p
processed
ocessed ssignals
g as
execution
 Audio video signal processing, telecommunication and multimedia applications
 Whereas general purpose processors implement the algorithm in
are typical examples where DSP is employed
software and the speed
p of execution depends
p primarilyy on the clock
p
for the processors  Employs a large amount of real‐time calculations with operations involving
 DSP can be viewed as a microchip designed for performing high  Sum of products (SOP) calculation, convolution, fast Fourier transform (FFT), discrete
speed
p computational
p operations
p for ‘addition’,, ‘subtraction’,, Fourier transform (DFT)
15 16
‘multiplication’ and ‘division’
 GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS
APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR (ASIP) ARCHITECTURAL CLASSIFICATION
 Processors with architecture and instruction set optimized
p  GP Purpose and Domain Specific Processor could be
to specific domain/application requirements like Network classified based on various processor design options
processing, Automotive, Telecom, media applications,
digital signal processing,
processing control applications etc.
etc
 Fill the architectural spectrum between General Purpose  Based on the Design Philosophy of Instruction Set
Processors and Application Specific Integrated Circuits Architecture
(ASICs)  Reduced Instruction Set Computing (RISC)
 The need for an ASIP arises when the traditional general
 Complex Instruction Set Computing (CISC)
purpose
p p processor are unable to meet the increasingg
p
application needs
 ASIPs incorporate a processor and on‐chip peripherals,  Based on Memory System architecture
demanded by the application requirement,
requirement program and 17
 Harvard 18
data memory  Princeton /Von Neumann/

GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS
RISC VS. CISC PROCESSOR/CONTROLLER HARVARD VS. VON NEUMANN ARCHITECTURE
RISC CISC
 Von‐Neumann/Princeton Architecture
Lesser number of instructions Greater number of instructions
 Shares a single common bus for fetching both instructions and data
Instruction Pipelining and increased execution speed Generally no instruction pipelining feature  Program instructions and data are stored in a common main memory
Orthogonal instruction set (Allows each instruction to Non‐orthogonal instruction set (All instructions are not  First fetch an instruction and then fetch the data to support the instruction
operate on any register and use any addressing mode) allowed to operate on any register and use any
from code memory
addressing mode. It is instruction‐specific)
 Two separate fetches slows down the controller’s operation
Operations are performed on registers only, the only Operations are performed on registers or memory
memory operations are load and store depending on the instruction  Harvard Architecture
A large number of registers are available Limited number of general purpose registers  Have separate data bus and instruction bus
Programmer needs to write more code to execute a task Instructions are like macros in C language. A  Allows the data transfer and program fetching to occur simultaneously on
since the instructions are simpler ones programmer can achieve the desired functionality with both buses
a single instruction which in turn provides the effect of  The data memory can be read and written while the program memory is being
using more simpler single instructions in RISC accessed
Single, fixed length instructions Variable length instructions  These separated data memory and code memory buses allow one instruction
Less silicon usage and pin count More silicon usage since more additional decoder logic to execute while the next instruction is fetched (“Pre‐fetching”)
is required to implement the complex instruction
decoding.
19 20
With Harvard architecture Can be Harvard or Von Neumann
Example: ARM Family, PIC, MIPS Example: 8086, 8051, Motorola 68k Series
 GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSORS
HARVARD VS. VON NEUMANN ARCHITECTURE HARVARD VS. VON NEUMANN ARCHITECTURE…
Harvard Architecture Von-Neumann Architecture
Separate buses for instruction and data Single shared bus for instruction and data
fetching fetching
Easier to pipeline,
pipeline so high Low performance compared to Harvard
performance can be achieved architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self modifying codes
Since data memory and program Since data memory and program
memory are stored physically in memory are stored physically in the
different locations, no chances for same chip, chances for accidental
accidental corruption of program corruption of program memory
memory
21 S
Separate
t buses
b f
for i t ti
instruction and
d data
d t Si l shared
Single h d bus
b for
f instruction
i t ti and
d data
d t22
fetching fetching

PROCESSOR/CORE PROCESSOR/CORE
ASICS ASICS…
 A micro chip designed to perform a specific or unique application  Fabrication of ASICs requires a non‐refundable initial investment
 Used as replacement to conventional general purpose logic chips (Non Recurring Engineering (NRE) charges) for the process
 Integrates several functions into a single chip and thereby technology and configuration expenses
reduces the system
y development
p cost  If the Non‐Recurringg Engineering
g g Charges
g ((NRE)) is born byy a third
 As a single chip, ASIC consumes very small area in the total party and the Application Specific Integrated Circuit (ASIC) is
system and thereby helps in the design of smaller systems with made openly available in the market,
high capabilities /functionalities  The ASIC is referred as Application
pp Specific
p Standard Product(ASSP)
( )
 Mostly proprietary  The ASSP is marketed to multiple customers just as a general‐
 Its fabrication could be either of purpose product, but to a smaller number of customers since it is
 Pre‐fabricated for
o a spec
specificc app
application
cat o
 For a special application  Example
 Custom fabricated
 The ADE7760 Energy Meter ASIC developed by Analog Devices for
 Using the components from a re‐usable “building block” library of components
for a particular customer application Energy metering applications
23 24
 PROCESSOR/CORE PROCESSOR/CORE
PROGRAMMABLE LOGIC DEVICES (PLDS) PROGRAMMABLE LOGIC DEVICES (PLDS)…
 Logic devices provides specific functions, including device to device  With PLDS
interfacing, data communication, signal processing, data display, timing  Designers can use inexpensive software tools to quickly develop,
& control operations, and almost every other function a system must simulate, and test their logic designs
perform  The design can be quickly programmed into a device, and immediately
testedd in a live
l circuit
 Logic devices can be broadly classified into  Advantage of PLDs
 Fixed logic device  No NRE cost
 Programmable logic device  Final design completed much faster than custom/fixed logic device
 During the design phase it is possible to change the circuitry as often
 Circuits in fixed logic devices are permanent, they perform one function as needed, until the design operates as expected
or set of functions once manufactured,
manufactured they cannot be changed  As it is based on re
re‐writable
writable memory technology
 Programmable Logic devices can be re‐configured to perform any  Once the design complete, it can go immediately into production
number of functions at any time  Two major types of PLDs
 Offer customers a wide range g of logic
g capacity,
p y, features,, speed,
p , and  Field Programmable Gate Arrays (FPGA)
25  Complex Programmable Logic Device (CPLD) 26
voltage characteristics

PROCESSOR/CORE PROCESSOR/CORE
COMMERCIAL OFF-THE-SHELF COMPONENTS COMMERCIAL OFF-THE-SHELF COMPONENTS
(COTS) (COTS)…
 Such products are those which are used “as‐is”  The majorj advantage g of usingg COTS
 Designed in such a way to provide easy integration and  Readily available in the market
interoperability with existing system components  Cheap and a developer can cut down his/her development
 Mayy be developed
p around GPP or ASIP or ASIC or ASSP or PLD time to a great extent
 Example : Control unit of Remote Controlled Toy Car  No need to design the module yourself and write the
firmware
 Everything will be readily supplied by the COTs manufacturer
 Disadvantage of COTS
 No operational and manufacturing standards
 Components from different manufacturers many not be
i
interoperable
bl
 Compatibility issues
 Might restricts the end‐user to stick to a particular vendor

 Manufacturer may withdraw the product or discontinue the

27 28
production of the COTs at any time
 ENDIANESS COMPONENTS OF ES HARDWARE
BIG-ENDIAN VS. LITTLE-ENDIAN MEMORY
 Endianness specifies the order in which the data is stored in the memory by  An important part of an ES
processor operations in a multi byte system (Processors
( whose word size is
greater than one byte)
 Can be either Program Storage Memory (ROM) or Data
 Little‐endian means the lower‐order byte of the data is stored in memory at the memory (RAM)
lowest address, and the higher‐order byte at the highest address. (The little  Program
g Storage
g Memoryy ((ROM))
end comes first.) For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0  Stores the program instructions
will be stored in the memory as shown below – Left Figure
 Retains its contents even after the power to it is turned off
 Big‐endian means the higher‐order byte of the data is stored in memory at the
lowest address, and the lower
lower‐order
order byte at the highest address. (The big end  It is generally known as Non‐volatile storage memory
comes first.) For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be  Depending on the fabrication, erasing and programming
stored in the memory as shown below – Right Figure techniques they are classified as

29 30

MEMORY MEMORY
PROGRAM STORAGE MEMORY PROGRAM STORAGE MEMORY…
 Masked ROM  Electrically Erasable Programmable Read Only Memory (EEPROM)
 One‐time programmable (OTP) memory/ Can't be reprogrammed  Can be erased and reprogrammed in‐circuit
 Factory programmed (Mask‐Programmed)  Provides greater flexibility for system design
 Low cost for high volume production  Capacity is limited when compared with the standard ROM (A few kilobytes)
 E h cellll is
Each i a single
i l transistor
t it
 FLASH
 Programmable Read Only Memory (PROM)  Takes advantages of both EPROM and EEPROM
 Nott pre‐programmed
N d by
b the
th manufacturer
f t  Stores information in an array of floating gate MOSFET transistors
 End user is responsible for Programming these devices  All the contents on large block can be erased

 Erasable Programmable Read Only Memory ( EPROM)  Non‐volatile RAM NVRAM

 Gives the flexibility to re‐program the same chip  RAM with a battery backup
 EPROM stores the bit information by charging the floating gate of an  Contains static RAM based memory and a minute battery for providing
FET(field
( effect)) supply to the memory in the absence of external power supply
31 32
 It has an optical port, exposing this port to UV photons will erase the data
 MEMORY MEMORY
DATA MEMORY/READ-WRITE MEMORY(RAM) DATA MEMORY/READ-WRITE MEMORY(RAM)
 Workingg memoryy of the controller/processor
/p  Dynamic RAM ( DRAM)
 Stores data in the form of charge high density and low cost
 Controller/processor can read from it and write to it  Need to be refreshed periodically

 Volatile, when the power is turned off

 Static RAM ( SRAM)
 All the contents are destroyed  Stores data in the form of voltage made up of flip‐flops

 RAM is a direct access memory  The fastest form of RAM available

 We can access the desired memory location directly without

 NVRAM Non
Non‐volatile
volatile RAM
the
h need d for
f traversing through
h h the
h entire memory locations
l to  Random access memory with battery backup
reach the desired memory position  The memory and battery are packed together in a single package

 Random Access of memory location

33 34

COMPONENTS OF ES HARDWARE COMPONENTS OF ES HARDWARE

SENSOR AND ACTUATOR SENSOR

 Embedded system
y is in constant interaction with the real world A transducer
a sduce dedevice
ce that
a de
detects
ec s p
physical,
ys ca , cchemical,
e ca , oor
 Controlling/monitoring functions executed by the embedded environmental changes (such as temperature, light,
system is achieved in accordance with the changes happening to motion, or pressure) and converts them into an
the Real World electrical
l i l signal
i l for
f processing
i
 The changes in the system environment or variables are detected  Convertsenergy from one form to another for any
by the sensors connected to the input port of the embedded measurement or control purpose
system  Sensorsacts as input device
 If the embedded system is designed for any controlling purpose,  Example
the system
y will p
produce some changes g in controllingg variable to  Soil moisture sensor,
sensor Ultrasonic sensor,
sensor Temperature sensor
bring the controlled variable to the desired value
 Achieved through an actuator connected to the out port of the
embedded system
35 36
 COMPONENTS OF ES HARDWARE COMPONENTS OF ES HARDWARE
ACTUATOR THE I/O SUBSYSTEM
A form
o o of transducer
a sduce dedevice
ce ((mechanical
ec a ca o or eelectrical)
ec ca )  Facilitates the interaction of the embedded system with external world
 The interaction happens through the sensors and actuators connected
which converts signals to corresponding physical to the Input and output ports, respectively of the embedded system
action (motion)
 Acts
A as an output device
d i  The
h sensors may not be b directly
d l interfaced
f d to theh Input ports, instead
d
they may be interfaced through signal conditioning and translating
 Different types of actuators
systems like Analogue to Digital Converter (ADC), Optocoupler etc.
 Electric,, Pneumatic,, Hydraulic,
y , Magnetic
g
 Example  Sample I/O Devices
 DC motor, servo motor, Stepper motor  Light Emitting Diode (LED), Seven segment display, Optocoupler, Stepper
Motor, Relay, Piezo Buzzer, Push Button Switch, Keyboard, Programmable
Peripheral Interface (PPI)

37 38

COMPONENTS OF ES HARDWARE COMPONENTS OF ES HARDWARE

THE I/O SUBSYSTEM COMMUNICATION INTERFACE
 Opto coupler
 A solid state device to isolate two parts of a circuit
 Essential for communicating with various
 Combines an LED and a photo‐transistor in a single housing (package) subsystems of the embedded system and with
 Stepper Motor
 An electro mechanical device which generates discrete displacement (motion) the external world
in response to dc electrical signals
 Relay
 An electro mechanical device which acts as dynamic path selectors for signals  Can be viewed in two different perspectives
andd power
 Normally controlled using a relay driver circuit connected to the port pin of  Device/board level communication interface
the processor/controller  Onboard Communication Interface
 Piezo Buzzer
 A piezoelectric device for generating audio indications in embedded  Product
P d l l communication
level i i interface
i f
applications  External Communication Interface
 Push Button Switch
 An input device,
device used for generating a momentary pulse 39 40
 Programmable Peripheral Interface (PPI)
 Used for extending the I/O capabilities of processors/controllers
 COMMUNICATION INTERFACE ONBOARD COMMUNICATION INTERFACE
ONBOARD COMMUNICATION INTERFACE I2C BUS
 Pronounced ‘I square C’, a synchronous half duplex two wire serial
 The communication channel which i t f
interface b
bus
 The two bus lines are called Serial Clock (SCL) and Serial Data (SDA)
interconnects the various components (ICs and  SCL line is responsible for generating synchronization clock pulses
 SDA is responsible for transmitting the serial data across devices
other p
peripherals)
p ) within an embedded p
product  I2C
C iss a sshared
a ed bus syste
system to which
c many
a y number
u be o
of I2CC de
devices
ces ca
can be
connected
 Devices connected to the I2C bus can act as either “Master” device or
“Slave” device
 Examples of onboard communication interfaces  The Master device is responsible for controlling the communication by
initiating/terminating data transfer, sending data and generating
 I2C (Inter Integrated Circuit) Bus necessary synchronization clock pulses
 SPI (Serial Peripheral Interface) Bus  Slave devices wait for the commands from the master and respond
upon receiving the commands
 UART(Universal Asynchronous Receiver Transmitter)  M t and
Master d Slave
Sl d i
devices can actt as either
ith transmitter
t itt or receiver,
i
supports multi masters on the same bus
 1‐Wires Interface  Read about the Mechanics of Data Transfer

 Parallel Interface
41 42

ONBOARD COMMUNICATION INTERFACE ONBOARD COMMUNICATION INTERFACE

SPI BUS SPI BUS…
 A synchronous full duplex four wire serial interface bus  The master device is responsible for generating the clock signal
 A single master multi slave system  Master device selects the required slave device by asserting the corresponding slave
 Possible to have a system where more than one SPI device devices slave select signal “LOW”
can be master, provided only one master device is active at  The data out line (MISO) of all the slave devices when not selected floats at high
any given point of time impedance state
 Used to send data between microcontrollers and small  The serial data transmission through SPI Bus is fully configurable
peripherals such as shift registers, sensors, and SD  SPI devices contain certain set of registers for holding these configurations
cards  The Serial Peripheral Control Register holds the various configuration parameters like
master/slave selection for the device, baud rate selection for communication, clock signal
 Requires four signal lines for communication
control etc.
 Master Out Slave In (MOSI)
 The status register holds the status of various conditions for transmission and reception.
 Signal line carrying the data from master to slave device
 Master In Slave Out (MISO)  SPI works on the principle of “Shift Register‟
 Signal
g line carrying
y g the data from slave to master device  The master and slave devices contain a special shift register for the data to transmit or receive
 The size of the shift register is device dependent, normally it is a multiple of 8
 Serial Clock (SCLK)
 Signal line carrying the clock signals  During transmission from the master to slave, the data in the master’s shift register is
 Slave Select (SS) shifted out to the MOSI pin and it enters the shift register of the slave device through
 Signal
g line for slave device select the MOSI pin of the slave device
43 44
 ONBOARD COMMUNICATION INTERFACE ONBOARD COMMUNICATION INTERFACE
SPI VS. I2C BUS UART
I2C SPI  An asynchronous form of serial data transmission
Speed limit varies from 100kbps, 400kbps, 1mbps, More than 1mbps, 10mbps to 100mbps can be  Doesn’t require a clock signal to synchronize the transmitting
3.4mbps depending on the version achieved
end and receiving end for transmission
Half duplex synchronous protocol Full duplex synchronous protocol
 The start and stop p of communication is indicated through g
Support Multi master configuration Multi master configuration is not possible inserting special bits in the data stream
Acknowledgement at each transfer No acknowledgement  While sending a byte of data, a start bit is added first and a
Requires Two Pins only SDA
SDA, SCL Requires separate MISO,
MISO MOSI,
MOSI CLK and CS signal stop bit is added at the end of the bit stream
for each slave  The least significant bit of the data byte follows the ‘start’ bit
Addition of new device on the bus is easy Addition of new device on the bus is not much easy
as I2C

More overhead (due to start, stop, ack) Less overhead

Noise sensitivity high Less noise sensitivity

45 46

ONBOARD COMMUNICATION INTERFACE ONBOARD COMMUNICATION INTERFACE

1-WIRE INTERFACE PARALLEL INTERFACE
 An asynchronous half‐duplex communication protocol, that  A method of conveying multiple binary digits (bits) simultaneously
provides
id low‐speed
l d data,
d signaling,
i li and
d power over a single
i l  The on‐board parallel interface is normally used for communicating with
conductor called DQ peripheral devices which are memory mapped to the host of the system
 Follows the master‐slave communication model
 The communication through the parallel bus is controlled by the control
 Similar in concept to I²C, but with lower data rates and longer
range signal interface between the device and the host
 Typically used to communicate with small inexpensive devices (Microprocessor/controller)
such as digital thermometers and weather instruments  The device normally contains a device select line (Chip Select) and the
 There is always one master in overall charge, which initiates device becomes active only when this line is asserted by the host processor
activity
ti it on the
th bus
b  A parallel
As ll l communication
i i isi host
h processor initiated,
i i i d If a device
d i wants to
 Protocols are built into the software to detect collisions initiate the communication, it can inform the same to the processor
 After a collision, the master retries the required communication
 Many devices can share the same bus. Each device on the bus through interrupts
has a unique 64‐bit serial number  The interrupt line of the device is connected to the interrupt line of the processor
and the corresponding interrupt is enabled in the host processor
 It allows power to be sent along the signal wire as well

 Read Mechanics of data transmission

47 48
 COMMUNICATION INTERFACE EXTERNAL COMMUNICATION INTERFACE
EXTERNAL COMMUNICATION INTERFACE RS-232C
 Responsible for data transfer between the embedded system and other devices A legacy,
egacy, full
u dup
duplex,
e , wired,
ed, asy
asynchronous
c o ous seserial
a
or modules
 As some embedded systems may be a part of a large distributed system communication interface
 Based on the medium of transmission can be of  Extends the UART communication signals for
 Wired or wireless
 Based on the mode of transfer can be of externall data
d communication
i i
 Serial or parallel
 Define various handshaking and control signals for
 Wired communication interface communication, apart from the “Transmit”
Transmit and
 Transfer information over a wired network
 Example
“Receive” signal lines for data communication
 RS‐232 C/ RS‐422/ RS‐485, USB, IEEE 1394 (Firewire)  Supports two different types of connectors, namely
 Wireless communication interface
 DB‐9 ‐ 9‐Pin connector
 Transmit information over a distance without help of wires, cables or any other forms
of electrical conductors  DB‐25 ‐ 25‐Pin connector
 Example
 Infrared,
Infrared Bluetooth,
Bluetooth Wi‐Fi,
Wi Fi Zigbee,
Zigbee GPRS (General Packet Radio Service)
49 50

EXTERNAL COMMUNICATION INTERFACE EXTERNAL COMMUNICATION INTERFACE

RS-232C… IEEE 1394 (FIREWIRE)
 The devices involved in RS‐232 communication are called ‘Data Terminal  Wired high speed serial bus for data communication
Equipment (DTE)’ and ‘Data Communication Equipment (DCE)’  Isochronous high speed serial communication bus
 Supports baud rates up to 20Kbps (Upper limit 19.2 Kbps)  Also known as High Performance Serial Bus (HPSB)
 The commonly used baud rates by devices are 300bps, 1200bps, 2400bps, 9600bps,  The 1394 standard supports a data rate of 400 to 3200Mbits/second
11.52Kbpsp and 19.2Kbps
p
 9600 is the popular baud rate setting used for PC communication
 The interface cable supports 3 types of connectors,
connectors namely; 4‐pin
4 pin
 The maximum operating distance is 50 feet at the highest supported baud rate connector, 6‐pin connector (alpha connector) and 9 pin connector (beta
connector).
 Supports only point
point‐to‐point
to point communication and not suitable for multimulti‐drop
drop  The 6 and 9 p
pin connectors carryy p
power in the range
g of 24 to 30V
communication  A popular communication interface for connecting embedded devices like
 Uses single ended data transfer technique for signal transmission and thereby Digital Camera, Camcorder, Scanners/ Printers to desktop computers for
more susceptible to noise and it greatly reduces the operating distance data transfer and storage

 was the most popular communication interface during the olden days, the
advent of other communication techniques like Bluetooth, USB, Firewire, etc are
pushing down RS
RS‐232
232 from the scenes
51 52
 EXTERNAL COMMUNICATION INTERFACE COMPONENTS OF ES HARDWARE
WIRELESS SUPERVISORY AND SUPPORT CIRCUITS
 Infrared(IrDA)  Refer to the components,
components circuits,
circuits ICs which are
 Bluetooth (BT) necessary for the proper functioning of the
 Wi‐Fi
embedded system
 Zigbee
 Example: Watchdog timer, Reset circuit, Brown‐
 GPRS, 3G, 4G, 5G
out p
protection circuit,, Clock Oscillator circuit,, RTC

 Some controllers or SoCs integrate g these

components within a single IC and doesn’t
require
q such components
p externallyy connected to
53 54
the chip for proper functioning

SUPERVISORY AND SUPPORT CIRCUITS SUPERVISORY AND SUPPORT CIRCUITS

RESET CIRCUIT RESET CIRCUIT…
 Reset circuit is essential to ensure that the device is not operating  Figure
gu e be o illustrates
below us a es a resistor
es s o capac
capacitor
o ((RC)) based
at a voltage level where the device is not guaranteed to operate, passive reset circuit for active high and low
during system power ON
configurations
 The reset signal
g brings
g the internal registers
g and the different
hardware systems of the processor/controller to a known state  The
Th reset pulse
l width
id h can be
b adjusted
dj d by
b changing
h i the h
and starts the firmware execution from the reset vector resistance value R and capacitance value C
 The reset signal can be either active high or active low
 The reset signal to the processor can be applied at power ON
 Through an external passive reset circuit comprising a Capacitor and
Resistor or
 Through a standard Reset IC
 Some microprocessors/controllers contain built‐in internal reset
circuitryy and theyy don’t require
q external reset circuitryy
55 56
 SUPERVISORY AND SUPPORT CIRCUITS SUPERVISORY AND SUPPORT CIRCUITS
OSCILLATOR AND CLOCK CIRCUIT REAL TIME CLOCK (RTC)
 The instruction execution of a microprocessor/controller occurs in sync with a  A system component responsible for keeping track of time
clock signal  RTC holds
h ld information
i f ti like
lik currentt time
ti (I hours,
(In h minutes
i t and d seconds)
d ) in
i 12 hour/24
h /24 hour
h
format, date, month, year, day of the week, etc
 An oscillator unit of the embedded system is responsible for generating the  Supplies timing reference to the system
precise clock for the processor  Intended to function even in the absence of power
 Certain processors/controllers integrate a built
built‐in
in oscillator unit and simply  Available in the form of Integrated Circuits
require an external ceramic resonator/quartz crystal for producing the  The RTC chip contains a microchip for holding the time and date related information and backup
necessary clock signals battery cell for functioning in the absence of power, in a single IC package
 The RTC chip is interfaced to the processor or controller of the embedded system
 Certain devices may not contain a built‐in oscillator unit and require the clock
pulses
l to be
b generated d and
d supplied
li d externally
ll  For Operating System based embedded devices, a timing reference is essential for synchronizing
 Quartz crystal Oscillators are available in the form chips and they can be used for the operations of the OS kernel
generating the clock pulses in such a cases.  The RTC can interrupt the OS kernel by asserting the interrupt line of the processor/controller to
which the RTC interrupt line is connected
 Figure
g illustrates the usage
g of q
quartz crystal/ceramic
y resonator and external
 The
Th kernel
k l can perform
f necessary operations
ti lik system
like t d t time
date ti updating,
d ti managing
i software
ft
oscillator chip for clock generation timers etc when an RTC timer tick interrupt occurs.
 The RTC can be configured to interrupt the processor at predefine intervals or to interrupt the
processor when the RTC register reaches a specified value (used as alarm interrupt)

57 58

SUPERVISORY AND SUPPORT CIRCUITS SUPERVISORY AND SUPPORT CIRCUITS

WATCHDOG TIMER WATCHDOG TIMER…
 A hardware timer for monitoring the firmware execution and reset the system  Most of the processors implement watchdog as a built‐in component and
processor/ microcontroller when the program execution hangs up provides status register to control the watchdog timer (like enabling and
 The watchdog timer increments/decrements a free running counter with each disabling watchdog functioning) and watchdog timer register for writing the
clock pulse and generates a reset signal to reset the processor if the count count value
reaches zero/ the highest count value  If the processor/controller doesn
doesn’tt contain a built in watchdog timer,
timer it can be
implemented using an external watchdog timer IC circuit
 When in the enabled state, the firmware can write a zero (for up counting  The external watchdog timer uses hardware logic for enabling/disabling, resetting
watchdog implementation) to it before starting the execution of a piece of code the watchdog count, etc instead of the firmware based ‘writing’ to the status and
( b
(subroutine
i or portioni off code
d which
hi h is
i susceptible
ibl to execution
i hang
h up)) and
d watchdog
t hd timer
ti register
it
the watchdog will start counting  In modern systems running on embedded operating systems, the watchdog
 If the firmware execution doesn’t complete due to malfunctioning, within the time can be implemented in such a way that when a watchdog timeout occurs,
required by the watchdog to reach the maximum count, the counter will generate an interrupt is generated instead of resetting the processor. The interrupt
a reset pulse and this will reset the processor (if it is connected to the reset line of handler for this handles the situation in an appropriate fashion
the processor)
 If the firmware execution completes before the expiration of the watchdog timer
you can reset the count by writing a 0 (for an up counting watchdog timer) to the
watchdog timer register 59 60
 SUPERVISORY AND SUPPORT CIRCUITS INTERRUPT CONTROLLER
BROWN-OUT PROTECTION CIRCUIT INTERRUPTS
 Prevents the processor/controller from unexpected program  Real Time Embedded System design requires that I/O devices
execution behavior when the supply voltage to the receive servicing in an efficient manner
processor/controller falls below a recommended operating
 This requires the use of the concept of Interrupts
voltage
 Essential for battery powered devices since there are greater
chances for the battery voltage to drop below the required  Interrupt
threshold  Signal to the processor emitted by hardware or software indicating an
event that needs immediate attention
 A brown‐out
brown out protection circuit holds the processor/controller in
 When a processor receives an interrupt signal, it completes the execution
reset state, when the operating voltage falls below the threshold,
of the current instruction and starts the execution of an Interrupt Service
until it rises above the threshold voltage
Routine (ISR) or Interrupt Handler
 Certain processors/controllers support built in brown‐out  TTakes
k a specified
ifi d action
ti d
depending
di on the
th priority
i it and
d
protection circuit which monitors the supply voltage internally importance of the entity generating the signal.
 If the processor/controller doesn’t integrate a built‐in brown‐out
protection circuit,
circuit it can be implemented using external passive  I t
Interrupts
t could
ld be
b classified
l ifi d using
i different
diff t criteria
it i
61 62
circuits or supervisor ICs as shown in the figure

INTERRUPT CONTROLLER INTERRUPT CONTROLLER

INTERRUPTS… INTERRUPTS…
 Based on the source  Based on the servicing of the interrupts
 Hardware Interrupts ‐ Caused by the connected devices  Fixed interrupt
 Software Interrupts ‐ Interrupts deliberately introduced by  Address of the ISR built into microprocessor, cannot be changed
 Either ISR stored at address or a jump to actual ISR stored if not enough bytes
software instructions to ggenerate user defined exceptions
p available
 Trap ‐ These are interrupts used by the processor to detect any
exception such as divide by zero  Vectored interrupt
 Peripheral must provide the address of the ISR
 Common when microprocessor has multiple peripherals connected by a system
 Based on enabling and disabling bus
 Maskable
 Programmer
g can set bit that causes p
processor to ignore
g interrupt
p
 This is important when the processor is executing a time‐critical code
 C
Compromise
i between
b t fi d and
fixed d vectored
t d interrupts
i t t
 One interrupt pin
 Non‐maskable
 Table in memory holding ISR addresses (maybe 256 words)
 a separate interrupt pin that can’t be masked
 Peripheral doesn’t provide ISR address, but rather index into table
 Typically reserved for drastic situations,
situations like power failure requiring immediate
63  Fewer bits are sent by the peripheral 64
backup of data to non‐volatile memory
 Can move ISR location without changing peripheral
 ELEMENTS OF AN EMBEDDED SYSTEM
INTERRUPT CONTROLLER EMBEDDED FIRMWARE
 Approgrammable
g peripheral
p p that manages
g the interrupt
p requests
q  The control algorithm (Program instructions) and or the configuration settings
that an embedded system developer dumps into the code (Program) memory of
from other peripherals to the CPU the embedded system
 Enables/disables the interrupt requests and selects the interrupt priority  Responsible for controlling the various peripherals of the embedded hardware
 E t d the
Extends th CPU scope for f multiple
lti l interrupts
i t t byb multiplexing
lti l i and generating response in accordance with the functional requirements of the
product
interrupts from peripherals  Imparts intelligence to an Embedded system

 Th product
The d starts functioning
f i i properlyl once the
h intelligence
i lli i
imparted
d to the
h
 When an interrupt is triggered, the CPU gets notified with the product by embedding the firmware in the hardware
interrupt number, which is used to execute the  The product will continue serving the assigned task till hardware breakdown
p
occurs or a corruption in embedded firmware
respective interrupt service routine (ISR) on the CPU
 In case of hardware breakdown, the damaged component may need to be
replaced and for firmware corruptions the firmware should be re‐loaded, to
 Example: Intel PIC ‐ 8259 bring back the embedded product to the normal functioning
65 66

ELEMENTS OF AN EMBEDDED SYSTEM

EMBEDDED FIRMWARE…
 The embedded firmware can be developed using various methods
 Write the program in high level languages like Embedded C/C++ using an Integrated
Development Environment
 Write the program in Assembly Language using the Instructions supported by your
application’s target processor/controller

 The embedded firmware is usually stored in a permanent memory (ROM) and it


is non alterable by end users

The different approaches available for the design and implementation of the
End of Chapter 3
embedded firmware will be the focus of the upcoming chapter

67 68