Program : B.

Tech
Subject Name: Network Analysis
Subject Code: EC-305
Semester: 3rd
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UNIT 2

Network topology, Concept of Network graph, Tree, tree branches and links, cut set and tie set schedules. Network
Theorems – Thevenin, Norton, Superposition, Reciprocity, Compensation, Maximum power transfer and Millmans
theorems, problems with controlled sources. This type of simplified picture is called a graph. A graph consists of a
set of dots, called vertices, and a set of edges connecting pairs of vertices. While we drew our original graph to
correspond with the picture we had, there is nothing particularly important about the layout when we analyze a
graph. Both of these graphs are equivalent to the one drawn above.

Definitions
Vertex. A vertex is a dot in the graph where edges meet. A vertex could represent an intersection of streets, a land
ass, o a ge e al lo atio , like o k o s hool . Note that e ti es o l o u he a dot is e pli itl pla ed, ot
whenever two edges cross. Imagine a freeway overpass – the freeway and side street cross, but it is not possible to
change from the side street to the freeway at that point, so there is no intersection and no vertex would be placed.

Edges. Edges connect pairs of vertices. An edge can represent a physical connection between locations, like a
street, or simply that a route connecting the two locations exists, like an airline flight.

Loop. A loop is a special type of edge that connects a vertex to itself. Loops are not used much in street network
graphs.

Degree of a vertex. The degree of a vertex is the number of edges meeting at that vertex. It is possible for a vertex
to have a degree of zero or larger.

Degree 0 Degree 1 Degree 2 Degree 3 Degree 4

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Path. A path is a sequence of vertices using the edges. Usually we are interested in a path between two vertices.
For example, a path from vertex A to vertex M is shown below. It is one of many possible paths in this graph.

A B C D

E F G H

J K L M

Circuit. A circuit is a path that begins and ends at the same vertex. A circuit starting and ending at vertex A is shown
below.

A B C D

F G H
E K M

J L
Connected graph. A graph is connected if there is a path from any vertex to any other vertex. Every graph drawn so
far has been connected. The graph below is disconnected; there is no way to get from the vertices on the left to the
vertices on the right.

Weights. Depending upon the problem being solved, sometimes weights are assigned to the edges. The weights
could represent the distance between two locations, the travel time, or the travel cost. It is important to note that
the distance between vertices in a graph does not necessarily correspond to the weight of an edge.

Shortest Path
Whe ou isit a e site like Google Maps o MapQuest a d ask fo di e tio s f o ho e to ou Au t’s house i
Pasadena, you are usually looking for a shortest path between the two locations. These computer applications use
representations of the street maps as graphs, with estimated driving times as edge weights.

While often it is possible to find a shortest path on a small graph by guess-and-check, our goal in this chapter is to
develop methods to solve complex problems in a systematic way by following algorithms. An algorithm is a step-by-
step p o edu e fo sol i g a p o le . Dijkst a’s p o ou ed dike-stra) algorithm will find the shortest path
between two vertices.

Terms and definitions

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The description of networks in terms of their geometry is referred to as network topology. The adequacy of a set of
equations for analyzing a network is more easily determined topologically than algebraically.

Graph (or linear graph): A network graph is a network in which all nodes and loops are retained but its branches are
represented by lines. The voltage sources are replaced by short circuits and current sources are replaced by open
circuits. (Sources without internal impedances or admittances can also be treated in the same way because they can
be shifted to other branches by E-shift and/or I-shift operations.)

Branch: A line segment replacing one or more network elements that are connected in series or parallel.

Node: Interconnection of two or more branches. It is a terminal of a branch. Usually interconnections of three or
more branches are nodes.

Path: A set of branches that may be traversed in an order without passing through the same node more than once.

Loop: Any closed contour selected in a graph.

Mesh: A loop which does not contain any other loop within it.

Planar graph: A graph which may be drawn on a plane surface in such a way that no branch passes over any other
branch.

Non-planar graph: Any graph which is not planar.

Oriented graph: When a direction to each branch of a graph is assigned, the resulting graph is called an oriented
graph or a directed graph.

Connected graph: A graph is connected if and only if there is a path between every pair of nodes.

Sub graph: Any subset of branches of the graph.

Tree: A connected sub-graph containing all nodes of a graph but no closed path. i.e. it is a set of branches of graph
which contains no loop but connects every node to every other node not necessarily directly. A number of different
trees can be drawn for a given graph.

Link: A branch of the graph which does not belong to the particular tree under consideration. The links form a sub-
graph not necessarily connected and is called the co-tree.

Tree compliment: Totality of links i.e. Co-tree.

Independent loop: The addition of each link to a tree, one at a time, results one closed path called,an independent
loop. Such a loop contains only one link and other tree branches. Obviously, the number of such independent loops
equals the number of links.

Tie set: A set of branches contained in a loop such that each loop contains one link and the remainder are tree
branches.

Tree branch voltages: The branch voltages may be separated in to tree branch voltages and link voltages. The tree
branches connect all the nodes. Therefore if the tree branch voltages are forced to be zero, then all the node
potentials become coincident and hence all branch voltages are forced to be zero. As the act of setting only the tree
branch voltages to zero forces all voltages in the network to be zero, it must be possible to express all the link
voltages uniquely in terms of tree branch voltages. Thus tree branch form an independent set of equations.

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Cut set: A set of elements of the graph that dissociates it into two main portions of a network such that replacing
any one element will destroy this property. It is a set of branches that if removed divides a connected graph in to
two connected sub-graphs. Each cut set contains one tree branch and the remaining being links.

Fig. below shows a typical network with its graph, oriented graph, a tree, co-tree and a non-planar graph.

Matrix representation of a graph

For a given oriented graph, there are several representative matrices. They are extremely important
in the analytical studies of a graph, particularly in the computer aided analysis and synthesis of
large scale networks.

Incidence Matrix An
It is also known as augmented incidence matrix. The element node incidence matrix A indicates
in a connected graph, the incidence of elements to nodes. It is an N × B matrix with elements of
An = (akj)

akj = 1, when the branch bj is incident to and oriented away from the kth node.
= -1, when the branch bj is incident to and oriented towards the kth node.
= 0, when the branch bj is not incident to the kth node.
As each branch of the graph is incident to exactly two nodes,
∑akj = fo j = , , , · · · B.

That is, each column of An has exactly two non zero elements, one being +1 and the other -1. Sum of elements of
any column is zero. The columns of An are lineraly dependent. The rank of the matrix is less than N. Significance of
the incidence matrix lies in the fact that it translates all the geometrical features in the graph into an algebraic
expression. Using the incidence matrix, we can write KCL as An iB = 0, where iB = branch current vector. But these
equations are not linearly independent. The rank of the matrix A is N - 1. This property of An is used to define
another matrix called reduced incidence matrix or bus incidence matrix. For the oriented graph shown in Fig. below
the incidence matrix is as follows:

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Reduced incidence matrix

Any node of a connected graph can be selected as a reference node. Then the voltages of the other nodes (referred
to as buses) can be measured with respect to the assigned reference. The matrix obtained from An by deleting the
row corresponding to the reference node is the elementbus incident matrix A and is called bus incidence matrix with
dimension (N - 1) × B. A is rectangular and therefore singular. In An, the sum of all elements in each column is zero.
This leads to an important conclusion that if one row is not known in A, it can be found so that sum of elements of
each column must be zero.

From A, we have A iB = 0, which represents a set of linearly independent equations and there are N - 1 independent
node equations.

For the graph shown in Fig 2.3 shown above with d selected as the reference node, the reduced incidence matrix is

Note that the sum of elements of each column in A need not be zero. Note that if branch current vector,

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Then A iB = 0 representing a set of independent node equations.

Another important property of A is that determinant AAT gives the number of possible trees of the network. If A =
[At : Ai] where At and Ai are sub-matrices of A such that At contains only twigs, then det At is either + 1 or -1. To
verify the property that det AAT gives the number of all possible trees, consider the reduced incidence matrix A of
the example considered. That is,

Fig. shown below shows all possible trees corresponding to the matrix A.

To verify the property that the determinant of sub matrix At of A = At ; Ai is +1 or -1. For tree [2, 3, 4]

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For another tree [2, 4, 5]

Loop equations and fundamental loop matrix (Tie-set Matrix)

In this matrix, the loop orientation is to be the same as the corresponding link direction. In order to construct this
matrix, the following procedure is to be followed.
1. Draw the oriented graph of the network. Choose a tree.
2. Each link forms an independent loop. The direction of this loop is same as that of the corresponding link. Choose
each link in turn.
3. Prepare the tie-set matrix with elements biJ, where biJ = 1 bJ when branch i in loop _ and is directed in the same
direction as the loop current.
= -1 when branch bJ is in loop i and is directed in the opposite direction as the loop
current.
= 0 when branch bJ is not in loop i.
Tie-set matrix is an b x I matrix.

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Then MVb gives the following independent loop equations:

Looking column wise, we can express branch currents in terms of loop currents. This is done by the following matrix
equation.

Cut-set matrix and node pair potentials

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A cut-set of a graph is a set of branches whose removal, cuts the connected graph into two parts such that the
replacement of any one branch of the cut-set renders the two parts connected. For example, two separated graphs
are obtained for the graph by selecting the cut-set consisting of branches [1, 2, 5, 6]. These seperated graphs are as
shown in Just as a systematic method exists for the selection of a set of independent loop current variables, a similar
process exists for the selection of a set of independent node pair potential variables.

It is already known that the cut set is a minimal set of branches of the graph, removal of which divides the graph in
to two connected sub-graphs. Then it separates the nodes of the graph in to two groups, each being one of the two
sub-graphs. Each branch of the tie-set has one of its terminals incident at a node on one sub-graph. Selecting the
orientation of the cut set same as that of the tree branch of the cut set, the cut set matrix is constructed row-wise
taking one cut set at a time. Without link currents, the network is inactive. In the same way, without node pair
voltages the network is active. This is because when one twig voltage is made active with all other twig voltages are
zero, there is a set of branches which becomes active. This set is called cut-set. This set is obtained by cutting the
graph by a line which cuts one twig and some links. The algebraic sum of these branch currents is zero. Making one
twig voltage active in turn, we get entire set of node equations.

This matrix has current values,

qiJ = 1, if branch J is in the cut-set with orientation same as that of tree branch.
= -1, if branch J is in the cut-set with orientation opposite to that of tree branch.
= 0, if branch J is not in the cut-set.
and dimension is ( N – 1 ) x B

Q. Refer the circuit shown in Fig. below Draw the graph, one tree and its co-tree.

ANS:

there are four nodes (N = 4) and seven branches (B = 7). The graph is then drawn and appears as shown in Fig. . It
may be noted that node d represented in the graph (Fig.) represents both the nodes d and e of Fig. 2. shows one tree

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of graph shown in Fig. . The tree is made up of branches 2, 5 and 6. The co-tree for the tree of Fig. 2.7 is shown in Fig.
. The co-tree has L = B - N +1 = 7 - 4+1 = 4 links.

Graph

Tree

Cotree

Q. Refer the network shown in Fig. Obtain the corresponding incidence matrix.

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ANS:

The network shown in Fig. I has five nodes and eight branches. The corresponding graphappears as shown in Fig. II

Q. For the incidence matrix shown below, draw the graph.

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ANS:

Q. Draw the graph of a netwrok of whose the incidence matrix is as shown below.

ANS:

Q. For the given cut-set matrix, draw the oriented graph

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ANS:

Therefore the graph is

Dual Networks

Two electrical circuits are duals if the mesh equations that characterize one of them have the same mathematical
form as the nodal equations that characterize the other. Let us consider the series Ra - La - Ca network excited by a
voltage source va as shown in Fig. and the parallel Gb - Cb - Lb network fed by a current source ib as shown in Fig.

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Superposition theorem

The principle of superposition is applicable only for linear systems. The concept of superposition can be explained
mathematically by the following response and excitation principle :

The quantity to the left of the arrow indicates the excitation and to the right, the system response. Thus, we can
state that a device, if excited by a current i1 will produce a response v1. Similarly, an excitation i2 will cause a
response v2. Then if we use an excitation i1 + i2, we will find a response v1 + v2.

The principle of superposition has the ability to reduce a complicated problem to several easier problems each
containing only a single independent source.

Superposition theorem states that,

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In any linear circuit containing multiple independent sources, the current or voltage at any point in the network
may be calculated as algebraic sum of the individual contributions of each source acting alone.

When determining the contribution due to a particular independent source, we disable all the remaining
independent sources. That is, all the remaining voltage sources are made zero by replacing them with short circuits,
and all remaining current sources are made zero by replacing them with open circuits. Also, it is important to note
that if a dependent source is present, it must remain active (unaltered) during the process of superposition.

Q. Fi d the urre t i the 6 Ω resistor usi g the pri iple of superpositio for the ir uit

ANS:

The e i ’s theore

The ai o je ti e of The e i ’s theo e is to edu e so e po tio of a i uit to a e ui ale t source and a single
element. This reduced equivalent circuit connected to the remaining part of the circuit will allow us to find the
desi ed u e t o oltage. The e i ’s theo e is ased o i uit e ui ale e. A i uit e ui ale t to a othe i uit
exhibits identical characteristics at identical terminals.

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The The e i ’s theore ay e stated as follo s:

A linear two–terminal circuit can be replaced by an equivalent circuit consisting of a voltage source Vt in series
with a resistor Rt, Where Vt is the open–circuit voltage at the terminals and Rt is the input or equivalent resistance
at the terminals when the independent sources are turned off or Rt is the ratio of open–circuit voltage to the
short–circuit current at the terminal pair.

Norto ’s theore

Norto ’s theore states that a li ear two-terminal network can be replaced by an equivalent circuit consisting of
a current source iN in parallel with resistor RN, where iN is the short-circuit current through the terminals and RN
is the input or equivalent resistance at the terminals when the independent sources are turned off. If one does not
wish to turn off the independent sources, then RNis the ratio of open circuit voltage to short–circuit current at the
terminal pair.

Maximum Power Transfer Theorem

In circuit analysis, we are some times interestedin determining the maximum power that a circuit can supply to the
load. Consider the linear circuit A as shown in Fig.

Circuit A is replaced by its Thevenin equivalent circuit as seen from a and b

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The maximum power transfer theorem states that the maximum power delivered by a source represented by its
Thevenin equivalent circuit is attained when the load RLis equal to the Thevenin resistance RT,

A simple circuit as shown in is considered to the concept of equivalent circuit and it is always possible to view even a
very complicated circuit in terms of much simpler equivalent source and load circuits. Subsequently the reduction of
computational complexity that involves in solving the current through a branch for different values of load resistance
( RL ) is also discussed. In many applications, a network may contain a variable component or element while other
elements in the circuit are kept constant. If the solution for current ( I ) or voltage ( V ) or power ( P ) in any
component of network is desired, in such cases the whole circuit need to be analyzed each time with the change in
component value. In order to avoid such repeated computation, it is desirable to introduce a method that will not
have to be repeated for each value of variable component. Such tedious computation burden can be avoided
provided the fixed part of such networks could be converted into a very simple equivalent circuit that represents
either in the form of practical voltage sou e k o as The e i ’s oltage sou e VTh = ag itude of oltage
sou e , RTh = i te al esista e of the sou e o i the fo of p a ti al u e t sou e k o as No to ’s u e t
source ( I N = magnitude of current source , RN = int ernal resis tan ce of current source ). Intrue sense, this
conversion will considerably simplify the analysis while the load resistance changes. Although the conversion
technique accomplishes the same goal, it has certain advantages over the techniques that we have learnt in earlier
lessons.

The Transient Response of RC Circuits

The Transient Response (also known as the Natural Response) is the way the circuit responds to energies stored
in storage elements, such as capacitors and inductors. If a capacitor has energy stored within it, then that energy
can be dissipated/absorbed by a resistor. How that energy is dissipated is the Transient Response.

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n this circuit, there is a pulse, a resistor, and a capacitor. Assume here that the pulse goes from 10V down to 0V
att=0.
Assume also that the circuit is in Steady State at t=0-. This implies that the capacitor is 'open' at t=0-. In order for KVL
to be true at t=0- then the capacitor voltage must be 10V at t=0-. This is because there is no current in the circuit,
therefore the voltage across the resistor is zero.

Vc(0-) = Vc(0+) = 10V

Note that since the Transient Response is the circuit's response toenergies stored in storage elements, we will 'kill'
the pulse source. This leaves us with a simple Resitor-Capacitor circuit with an initial 10V on the capacitor at t=0+.

Applying KCL to an RC circuit:

Cdv/dt + V/R = 0
dv/dt + V/(RC) = 0
∫d /V = ∫-1/(RC) dt
ln V = -t/(RC) + K
ln V(t=0) = K
ln Vo = K ←Vo is the voltage on the cap at t=0+.

lnV - ln Vo = -t/(RC)
ln (V/Vo) = -t/(RC)
V/Vo = e-t/(RC)
V(t) = Vo e-t/(RC) ←Vo = 10V in this example.

Note that the speed at which the capacitor discharges from 10V to 0V is determined by the product R×C

When t=RC, the voltage on the capacitor is Vo/e or 37% of it's initial value. We call RC the time constant and the
s ol is τ

Fo a RC i uit, τ=RC

I this pa ti ula i uit τ = RC = Ω×1mF = 0.1 seconds

This means it takes 0.1 seconds for the capacitor to discharge from 10V down to 3.7V.

Here is the sa e i uit as that a o e, e ept that the esisto alue is dou led. This ea s that τ is also dou led.
τ = RC = Ω×1mF = 0.2 seconds
This circuit is twice as slow as the last circuit.

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The Transient Response of RL Circuits

The Transient Response (also known as the Natural Response) is the way the circuit responds to energies stored
in storage elements, such as capacitors and inductors. If an inductor has energy stored within it, then that energy
can be dissipated/absorbed by a resistor. How that energy is dissipated is the Transient Response.

In this circuit, there is a pulse, a resistor, and an inductor. Assume here that the pulse goes from -10V to 0V at t=0.

Assume also that the circuit is in Steady State at t=0-. This implies that the inductor is a 'short' at t=0-. In order for
KCL to be true at t=0- the inductor current must be -1A at t=0-.

IL(0-) = IL(0+) = -1A

Consider the circuit at t=0+, the voltage across the pulse is zero but since I L(0+) = -1A then VR = -10V. Therefore for
KVL to be true VL = +10V.
Therefore VL = +10V is the initial voltage across the inductor.

Note that since the Transient Response is the circuit's response to energies stored in storage elements, we will 'kill'
the pulse source. This leaves us with a simple Resitor-Inductor circuit with an initial -10A going through the inductor
at t=0+.

Applying KVL to an RL circuit:

iR + Ldi/dt = 0
iR/L + di/dt = 0
-iR/L = di/dt
-R/L dt = di/i
∫-R/L dt = ∫di/i
-Rt/L + K = ln i
K = ln i(t=0)
K = ln io
-Rt/L = ln i - K
-Rt/L = ln i - ln io
-Rt/L = ln(i/io)

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i/io = e-Rt/L
i(t) = ioe-Rt/L ←io in this case is -1A

Since the plot on the right is for voltage we will find VL using VL = Ldi/dt
VL = (1H) d[ioe-Rt/L]/dt = (1H) (-10) ioe-Rt/L
VL = -10 e-Rt/L

When t=L/R, the voltage on the inductor is Vo/e or 37% of it's initial value. We call L/R the time constant and again
the s ol is τ

Fo a RL i uit, τ=L/R

I this pa ti ula i uit τ = L/R = H/ Ω = . se o ds

This means it takes 0.1 seconds for the inductor to go from 10V down to 3.7V.

The Complete Response

The Complete Response is the circuit's response to both an independent source as well as energies stored in the
circuit.
A circuit driven by an independent source is said to have a forcing function.
Vcomplete response = Vnatural + Vforced

Here is an RC Circuit with a Forcing Function:

Assume the source is a pulse which goes from0V to 10V at t=0.

If we assume steady state at t=0-, then there is no initial energystored in the circuit.

Intuitively we know that the capacitor is going tocharge up to 10V. When the capacitor gets to 10V then the circuit is
again at steady state.

The pulse is forcing the capacitor to 10V, thus the 10V on the capacitor is called the forced response.

The time it takes the capacitor to charge up to 10V is determined by the time constant. The response of getting to
10V is the transient response.

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Now we will find the Complete Response for V across the capacitor. This equation will match the curve shown at the
right.

From the last section we know that the transient response for an RC circuit is:
V(t) = Vo e-t/(RC) = A e-t/(RC) Note that A is just some constant.

We also know from inspection that eventually the capacitor will charge up to 10V. Now putting
the transient and forced responses together we get:

Vcomplete = A e-t/(RC) + Vforced

Vcomplete = A e-t/(RC) + 10V

Now we need to find A such that the equation equals Vo at t=0. In other words, the equation must satisfy the initial
condition.

V(t=0) = 0, therefore:
0 = A e0 + 10V = A + 10V
A = -10V

Vcomplete = -10e-t/(RC) + 10V

Vcomplete = -10e-10t + 10V

Note that when t>>0, Vcomplete = 10V. This intuitively means that when the transient response is gone the
forced response still remains.

In this circuit, the capacitor DOES NOT start at 0V. In other words the capacitor has a non-zero initial
condition of 5V:

Note that the left switch closes at the same time the right switch opens. Intuitively we can see that the
capacitor is going to start at 5V and then charge up to 15V. For t<0 the 5V source is the forcing function
and for t>0 the 15V source is the forcing function.

Since this is an RC circuit with a forcing function, the response takes the following form:
Vcomplete=Ae-t/(RC)+Vforced
By inspection we know that Vforced = 15V
Vcomplete = A e-t/(RC) + 15V
Now we need to find A such that the entire equation satisfies the value of V at t=0.
V(t=0) = 5V = A e0 + 15V
A = -10V
Vcomplete = -10e-t/(RC) + 15 V
Vcomplete = -10e-10t + 15 V

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Now let's find the voltage across the resistor for the RL circuit to the right.

Note that the pulse goes from 5V to 15V at t=0. Assume that the circuit is in steady state at t=0-.
At steady state inductors look like 'shorts' therefore the voltage across the resistor must be equal to the
pulse voltage of 5V at t=0-.

At t=0+ the voltage across the resistor is still 5V

Since the current in the inductor is continuous from 0- to 0+, and the current in the resistor is the same as the
current in the inductor, and the voltage across the resistor is determined by its current, then we can say that if the
resistor's current is continuous then the resistor's voltage must also be continuous.

At t>>0 the voltage across the resistor is 15V.

For t>0 we eventually reach steady state (as the transient response dies away), so we know that at t>>0 the inductor
will look like a 'short'. Therefore the voltage across the resistor will equal the voltage of the pulse.
Therefore we have both the initial condition and the forced response for the voltage across the resistor:
Vo = 5V
Vforced = 15V

Analysis Steps for finding the Complete Response of RC and RL Circuits

Use these Steps when finding the Complete Response for a 1st-order Circuit:

Step 1: First examine the switch to see if it is opening or closing and at what time.

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Step 2: Next draw the circuit right before the switch moves. You will probably assume steady state at this time but
not always. The problem needs to tell you to assume steady state.

Step 3: Find all voltages and currents that can not change instantaneously when the switch moves. In other words,
Find voltages across all capacitors and currents through all inductors!

Step 4: Now draw the circuit right after the switch moves. Label the circuit with all the capacitor voltages and
inductor currents you found in step 3.

Step 5: Now you are ready to find your initial condition(s). Analyze the circuit to find the initial condition(s) of what it
is your solving for.

Step 6: Ne t ou ill fi d the t a sie t/ atu al epo se, o τ. To do this 'kill' all fo i g fu tio s. Make all oltage
sources 'shorts' and all current sources 'opens'. Remember that the transient response is the circuit's response to
energies stored in storage elements, so we need to remove forcing functions to find this. Recall that every voltage
a d u e t ill ha e the sa e τ alue. You o ha e Ae-t/τ for what your solving for.

Step 7: Now we need to find the forced response. The forced response is the state of the circuit after the switch has
moved AND after the transient response has died-off. To find the forced response assume Steady State, i,e, t>>>0.
Find the final resting value (forced response - VF) of whatever it is you are solving for.

Step 8: You should now have an equation which looks like v(t) = Ae -t/τ + VF or i(t) = Ae-t/τ + IF. To find the unknown
'A' you will apply the initial condition to this equation. Usually the initial condition is the value at t=0, so you will plug
in t=0 to get the following: I.C. = A + VF or I.C. = A + IF You can now solve for A.

Step 9: Plugging the value of A into: v(t) = Ae-t/τ + VF, you now know the voltage for all time greater than t=0
(assuming that the switch moved at t=0).

Step 10: Using your equation for v(t) or i(t), you can find other things (voltages, currents, power, etc.) using KVL,
KCL, and Ohm's Law.

Network Analysis, ECE, CDGI, Indore Page 23

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