2023 International Conference on IC Design and Technology (ICICDT)

2023 International Conference on IC Design and Technology (ICICDT)

Design of 1-5 GHz Two-Stage Noise-Canceling

Low-Noise Amplifier with gm-boosting Technique
for Spin Wave Detection Circuit
Zhenyu Cheng∗, Zunsong Yang†, Yuyang Zhu∗, Md Shamim Sarker‡, Hiroyasu Yamahara‡, Munetoshi Seki∗‡,
2023 International Conference on IC Design and Technology (ICICDT) | 979-8-3503-1931-6/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICICDT59917.2023.10332416

Hitoshi Tabata∗‡, Tetsuya Iizuka∗†

∗
Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo 113-0032, Japan
†
Systems Design Lab., School of Engineering, The University of Tokyo, Tokyo 113-0032, Japan
‡
Department of Bioengineering, The University of Tokyo, Tokyo, 113-8656, Japan

Abstract—This work presents a two-stage low-noise

amplifier (LNA) for spin wave detection. Since spin wave
detection must be performed under strong magnetic field, no
on-chip inductors should be used in the circuit for avoiding
unexpected electromagnetic coupling. The first stage employs
noise-canceling and gm-boosting to provide preferable noise
figure, wideband input matching and low power consumption.
The second stage is a fully differential cascode amplifier for
further voltage gain. The prototype is implemented in 65nm
CMOS technology and consumes 8.3 mA from 1 V supply.
Fig. 1. Schematic representation of fabricated device and the measurement
Without any on-chip inductor, the proposed two-stage LNA
systems. The PNA monitor shows typical interference behavior[1].
including the output buffer achieves 30.6 dB maximum gain,
3.4–5.4 dB noise figure, and better than -10 dB input matching
within the frequency range of 1-5 GHz based on post-layout
simulation results.

Keywords—low-noise amplifier (LNA); wideband; noise-

canceling; gm-boosting; inductorless; spin wave detection;
lock-in amplifier (LIA)

I. INTRODUCTION
The angular momentum of electrons is transmitted as
waves, allowing information to be transmitted and controlled
without transporting electrons physically. Consequently, zero Fig. 2. Diagram of a typical lock-in amplifier (LIA).
heat is generated. Based on this property, spin is expected to
be applied to next-generation ultra-low power consumption
computers that can transmit and control information without
heat loss[1]. Specifically, we aim to develop a brain-type
(neuromorphic) element that can function at room
temperature, induce spin fluctuations on magnetic thin films
made of garnet (magnetic optical material), and electrically Fig. 3. Proposed LNA in front of LIA.
detect spin angular momentum (spin wave) by spin-orbit
interaction. These achievements will be applicable to
(1)
reservoir computing by spin wave calculation, spiking
neurons, etc[1]. For manipulation and utilization of spin (2)
waves, we develop a device to measure the amplitude and
phase of a spin wave, which is expected to be small enough LIA enables the measurement of amplitude and phase of
and implemented on chip for future large-scale integrations. RF input. Since the RF signal from the DUT can be as weak
This measurement can be performed by lock-in amplifier as -90 dBm, an LNA is needed to guarantee preferable signal-
(LIA). As shown in Fig. 2, an LIA is composed of 2 mixers to-noise ratio (SNR), or the weak input signal being measured
with LO signals that have 90-degree phase difference. LIA can easily be buried in noise and hard to be detected. As
converts RF signal to DC outputs with which the amplitude shown in Fig. 3, we apply a single-to-differential LNA before
and phase can be calculated by equations (1) and (2). the LIA for detection of extremely weak input.

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 II. TECHNIQUES REVIEW
The LNA and LIA are implemented without inductors to
avoid unwanted electromagnetic coupling since the spin
wave detection must be performed under strong magnetic
field. There are mainly 2 techniques adopted in the first stage.
A. Noise-canceling
In [2], A CG-CS structured LNA which enables the
cancellation of thermal noise from CG transistor was proposed.
As shown in Fig. 4, the noise generated by CG transistor M1
can be canceled when CG and CS stage has the same gain.
Fig. 4. An example of CG-CS noise-canceling LNA[2].
B. gm-boosting
As shown in Fig. 5, gm-boosting applies an inversely
amplified voltage to the gate of CG transistor, making the
effective gm of CG transistor larger by a factor of 1+A (where
A is the amplification of inverting amplifier), enabling input
matching to be realized with smaller DC current[3]. This
makes it popular with low voltage and low power applications.
(3) Fig. 5. General example of gm-boosting[3].

III. CIRCUIT IMPLEMENTATION

As shown in Fig. 6, the proposed LNA has 2 stages. The
first stage determines the noise figure (NF) and input matching.
The second stage is differential amplifier for further voltage
gain. The outputs of second stage are connected to a voltage
buffer for 50Ω output matching.
A. Noise-canceling and gm-boosting stage.
In CG amplifier, input matching is determined by gm of
CG transistor, which is approximated by 1/gmCG. While with
gm-boosting, as equation (3) implies, the effective gm of CG
transistor will get larger. Matching condition should be
rewritten as:

(4) Fig. 6. Schematic of the proposed LNA.

The first stage of Fig. 6 is a gm-boosting LNA with pMOS Noise factor of the first stage can be calculated as:
FET M3 in its CS stage[4]. This pMOS amplifies the input
without consuming extra DC current, improving gain of CS
stage. By adding pMOS in CS stage, the needed gm of M2 (9)
becomes smaller. Thus, DC current and size of M2 can be
reduced and the voltage headroom of vout+ can also be widen.
The feedback amplification of CS stage AVM is determined by
B. Fully differential cascode amplifier.
transistors M3, M4 and M5:
The second stage in Fig. 6 is a fully differential amplifier
(5) with cascode transistors M9 and M10. This amplifier is
applied for larger overall voltage gain. Cascode structure
With equations (4) and (5), impedance matching condition contributes to better bandwidth by reducing parasitic
can be expressed as: capacitance caused by Miller effect through gate and drain
(6) of transistors M6 and M7.
C. Output voltage buffer.
Noise cancellation is achieved when CG and CS stage show
equal gain, which gives the canceling condition: There are two versions of buffers in use. The first buffer
(7) is flipped voltage follower (FVF), as shown in Fig. 7. As
shown in Fig. 8, the second buffer is called voltage combiner.
Then the total gain of the first stage is:
It avoids unnecessary voltage loss by combining differential
(8) outputs to be single-ended, providing extra gain[6].

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 Fig. 7. Flipped voltage follower (FVF).

Fig. 10. Input reflection (S11) vs frequency.

Fig. 8. Voltage combiner.

Fig. 9. Layout of the

proposed LNA.

IV. SIMULATION RESULTS

The proposed LNA is implemented with TSMC 65nm Fig. 11. Power gain (S21) vs frequency.
technology, whose layout is shown in Fig. 9 (with the FVF
as a buffer). All the following results are obtained from post-
layout simulations. All simulations are done respectively
with 2 different buffers (FVF and voltage combiner).
A. Input Reflection (S11).
S11 versus frequency is shown in Fig. 10. As input
matching is mainly associated with the first stage, S11 with
FVF and voltage combiner have almost no difference. Within
the target frequency range of 1-5 GHz, S11 is always better
than -10 dB.
B. Power Gain (S21).
S21 is shown in Fig. 11. The result with voltage
combiner is several dB better than that with the FVF. Within Fig. 12. Output reflection (S22) vs frequency.
the target frequency range, the proposed LNA with voltage
combiner offers the best gain over 30 dB, which is large
compared with previously reported works.
C. Output Reflection (S22).
S22 versus frequency is shown in Fig. 12. Voltage
combiner gives better than -15 dB output matching with the
target frequency range. It is revealed that both in gain and
output matching voltage combiner performs better than FVF.
D. Noise Figure
NF versus frequency is shown in Fig. 13. Because NF
is dominated mainly by the first stage, the 2 curves almost
overlap with each other. The best value is 3.4 dB at 900 MHz
and the worst value is 5.4 dB at 5 GHz. Fig. 13. Noise figure vs frequency.

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 TABLE 1 COMPARISON WITH PREVIOUSLY PUBLISHED INDUCTORLESS LNAs

*: Post-layout simulation results obtained with FVF as a buffer.

**: Post-layout simulation results obtained with voltage combiner as a buffer.

E. Performance Comparison REFERENCES

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