1

Design of an Ultra-Wideband Low-Noise Amplifier

for Spin Wave Readout Circuitry in 65 nm CMOS
Technology
Christian Meier1 , Eugen Egel1 , György Csaba2 , Stephan Breitkreutz-von Gamm1
1 Institute
for Technical Electronics, Technical University of Munich, Munich, Germany
2 Center for Nano Science and Technology, University of Notre Dame (NDnano), Notre Dame, IN, USA

Abstract—We introduce a new approach to measure spin waves characterizes its properties concerning the topology, conver-
on-chip and describe the design of an ultra-wideband Low- sion gain, Noise Figure (NF), power consumption and required
Noise Amplifier (LNA) implemented in a readout circuitry for chip area. Sec. IV summarizes this paper.
characterization of the spin wave devices. The LNA shows a gain
of 22.6 dB in the frequency range between 9.7 GHz and 43.3 GHz.
The minimum Noise Figure (NF) is 5.3 dB at 22.75 GHz. Simu- II. O N -C HIP R EADOUT C IRCUITRY FOR S PIN WAVES
lations were performed with 65 nm CMOS technology node in
Cadence Virtuoso. Estimated power consumption and chip area The structure of the readout circuitry for spin wave devices
are 41.62 mW and 0.172 mm2 , respectively. is depicted in Fig. 1. First of all, the spin waves induce a signal
Index Terms—Low-Noise Amplifier (LNA), ultra-wideband,
with an amplitude of 10 µV to 100 µV and a frequency in the
microwave devices, spectrum analyzer, on-chip oscilloscope, spin- range of 10 GHz to 50 GHz in the antenna. Such antennas can
wave readout. be realized on the surface of a magnetic materials, e.g. Yttrium
Iron Garnet (YIG) film [5]. The equivalent circuit model of
the antenna is shown in Fig. 2. The values for the equivalent
I. I NTRODUCTION serial resistance R and inductance L were calculated with
PIN wave-based devices are promising candidates for the approach described in [6]. The main part of the noise
S beyond-CMOS computing. As already shown in [1]- [4],
spin waves can perform Boolean and non-Boolean data pro-
comes from the thermal noise caused by antenna resistance.
In order to estimate the magnitude of thermal agitation of
cessing and provide a low-power solution for highly demanded magnetic moments, we performed micro-magnetic simulation
image processing tasks. The oscillation frequency of the spin using OOMMF with the thetavolver module [7], [8]. The
waves is in the range from 10 GHz to 50 GHz and currently simulation results show the magnetic noise equivalent to an
they are detected by external network analyzers or Spin Hall R ≈ 10−3 Ω, i.e. it can be neglected compared to the resistance
Effect (SHE) devices [5]. However, on-chip detection of the of the antenna. In accordance with the high frequency of the
spin waves is still missing for practical applications due to spin waves, the loop antenna requires an area of approximately
the integration challenge of the whole system. We propose 1 µm2 . [5]
on-chip loop antennas as integrated sensor, since they provide
a scalable, low resistive and contactless sensing, compared 0.1 - 1 mV > 100 mV
10 - 50 GHz < 100 MHz
to other sensors like Giant Magnetoresistance (GMR) or 10 - 100 µV 0.1 - 1 mV
Tunnel Magnetoresistance (TMR) devices. The realization of 10 - 50 GHz < 100 MHz
Antenna
the readout circuitry together with the spin wave devices on a Mixer
single chip would provide a low-cost system characterizing the RF
LNA
RF IF
OpAmp ADC
frequency, amplitude and phase difference of the spin waves.
One of the challenges of the proposed detection system is LO
the realization of the interface between the spin wave device VCNRL
and the electrical circuitry. The second intricacy is to design
the ultra-wideband high frequency readout CMOS components VCO

such as LNA, mixer and Voltage Controlled Oscillator (VCO)

Fig. 1. Block diagram of the on-chip readout circuitry for spin waves with
due to the relatively high frequency of the generated spin operating amplitude and frequency ranges of a propagated signal.
waves ranging from 10 GHz to 50 GHz. [5]
This paper is organized as follows. Sec. II introduces the In the second step, the signal received by the antenna is
overview of the on-chip readout circuitry for spin wave devices amplified by the LNA. A direct amplification by a traditional
and describes the general idea behind their characterization. Operational Amplifier (OpAmp) is not possible due to the
Sec. III details the proposed ultra-wideband LNA design and poles coming at high frequencies (1 GHz to 10 GHz) from
978-1-5090-2586-2/16/$31.00 2016 IEEE

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 2

R=50Ω L=25pH
TABLE I
D IMENSIONING OF THE LNA TRANSISTORS .

Transistor Length x Width x Fingers x Multiplier

T1 65 nm x 2.7 µm x 5 x 5
Noise
T2 65 nm x 2.7 µm x 5 x 5
T3 65 nm x 2.8 µm x 3 x 1
T4 65 nm x 2.4 µm x 3 x 4
T5 65 nm x 2.4 µm x 3 x 4
Fig. 2. Equivalent circuit model of the loop antenna build on a YIG film. T6 65 nm x 2.2 µm x 3 x 3
T7 65 nm x 2.2 µm x 3 x 3

parasitic capacitances of transistors. A relative high gain of

22.6 dB in the bandwidth of 9.7 GHz to 43.3 GHz was achieved
design published in [10]. However, to our knowledge no ultra-
for the LNA. The circuit was simulated in Cadence Virtuoso
wideband LNA design was published yet with a considerable
with 65 nm technology node and is described more closely in
conversion gain of at least 20 dB in the frequency span from
Sec. III.
10 GHz to 40 GHz. Figure 4 depicts the conversion gains of
Subsequently, the Radio Frequency (RF) signal is provided each stage and whole gain of the LNA in black. The aforemen-
to a mixer generating an Intermediate Frequency (IF) signal by tioned bandwidth of 9.7 GHz to 43.3 GHz corresponds to the
multiplying the RF and a Local Oscillator (LO) signal in the corner frequencies at 3 dB decrease of the achieved 22.6 dB.
time domain. The high frequency components, coming from Parameters of the LNA transistors are listed in Tab. I.
the convolution of the RF and LO signals in the frequency
domain can be filtered out by the OpAmp with a Low Stage I Stage II Stage III
Pass (LP) characteristic or by an additional LP filter inserted
between the mixer and the OpAmp. A possible realization of
R4 R5
an ultra-wideband 9 GHz to 50 GHz mixer in 0.13 µm CMOS T3
L2

C C,FB OUT
technology was already published in [9] and can be adapted R1
L3 L5
R2
to this work and CMOS technology. Similar to [9], we expect R3
T5 T7
the power and the area consumption of the mixer in the region T2

of 97 mW and 0.25 mm2 , respectively. IN

C C,1
L1
T1
C C,2
T4
C C,3
L4
T6

The LO signal is generated by a VCO. The VCO is a R B,1

R B,2
R B,3

V B,1 V B,2 V B,3

tunable frequency generator which frequency is controlled
by a DC voltage at the input. As shown in [12], the VCO VB,1 = 700 mV R1 = 25 Ω VB,1 = 700 mV R4 = 50.1 Ω VB,1 = 700 mV R5 = 30 Ω
can also be controlled digitally. Such a digitally controlled L1 = 670 pH R2 = 120 Ω L3 = 4.2 nH RB,2 = 20 kΩ L4 = 830 pH RB,3 = 20 kΩ
L2 = 600 pH R3 = 26 Ω CC,2 = 700 fF L5 = 1.41 nH
VCO consumes 3 mW of power and requires 0.02 mm2 of chip CC,1 = 700 fF RB,1 = 20 kΩ CC,3 = 700 fF
CC,FB = 10 pF
space. In order to cover a wider frequency range more than
one VCO, designed and optimized for different frequencies, Fig. 3. Schematic of the proposed multi-stage LNA design. Different
can be used. resonance frequencies of the individual stages constitute an overall flat gain
Before the measured signal is converted to the digital response.
domain by the Analog-to-Digital Converter (ADC), it has
to be amplified by the OpAmp to reasonably high voltages 30
from 100 mV to 300 mV. To achieve these voltage values 25 Stage I
an OpAmp with an amplification of approximately 60 dB 20
Stage II
Magnitude [dB]

Stage III
to 70 dB is required. First simulations have shown that the 15 Total (s 21)
power consumption and the required chip area of the OpAmp 10
compared to the LNA, mixer and VCO are negligibly small. 5
Finally, the measured and digitized spin wave signal can be 0
analyzed and information about the frequency, amplitude and -5
phase differences of the spin waves can be extracted. -10
-15
-20
III. D ESIGN OF THE L OW-N OISE A MPLIFIER 109 1010 1011
Frequency [Hz]
In order to achieve a flat gain over a wide bandwidth, a
multi-stage design with inductive peaking techniques has been Fig. 4. Conversion gain (s-parameter s21 ) of the overall LNA and its three
developed. Multi-stage amplifiers are based on the idea that constituting stages in the frequency range from 1 GHz to 100 GHz.
different stages with different resonant frequencies in a series
configuration form a flat transfer characteristic. Here, we are The challenge with multi-stage amplifiers is to carefully set
working with a three stages LNA (see Fig. 3) based on a the different resonance frequencies of the individual stages

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 3

and simultaneously optimize noise behavior, gain, power con- factor of 0.8 and 0.55 for the intermediate stage and the output
sumption, chip area and stability. stage, respectively. As already mentioned earlier, varying the
The input stage of the designed LNA has a gain peak load resistors R4 and R5 changes the bandwidth and gain but
around 30 GHz and is also responsible for sufficient matching also moves the center frequency of the RLC-tank of Stage II
of the impedance of the LNA input and the loop antenna. The and Stage III.
intermediate stage peak is at approximately 10 GHz and has a Further extension of the overall LNA could be possible for
high gain and broad bandwidth. Since the first and the second achieving a higher bandwidth and better gain performance.
stages have very small or even negative contributions of gain At the upper end of the frequency spectrum, area and power
in the frequency range starting from 40 GHz to 50 GHz, a third consumption drops significantly but more stages are required
stage compensates for this effect. The output stage peaks at to cover a certain piece of the spectrum compared to the lower
approximately 45 GHz and has a much lower gain. High gain end of the frequency range. Also noise increases at higher
at high frequencies is difficult to achieve since up-scaling of frequencies considerably.
transistors leads to increased parasitic capacitances.
C. Noise Figure Analysis
A. Input Stage Having a low noise figure (NF) is a key specification of our
A shunt-series-peaking amplifier is the basis for the input LNA design. An in-depth investigation of the antenna loop
stage. This is a widespread design since it offers a good model showed that the magnetic noise can be neglected and
balance between input matching, gain and noise performance. only the thermal noise caused by the series resistance of the
In the first stage a coupling capacitance CC,1 blocks existing antenna is to be considered. Simulations of the LNA showed a
DC components from the signal source. The amplifier core minimal NF of 5.3 dB at 22.75 GHz and values under 8 dB up
consists of the common source configuration of transistor to 40 GHz. The noise behaviour over frequency can be seen in
T1 and the cascode configuration of T2 . The insertion of Fig. 5 together with the transfer gain of the LNA. A dedicated
the inductor L1 is the so-called series peaking technique spot-noise analysis was performed at certain frequencies in
that compensates for the parasitic gate capacitances of T1 . It order to identify the biggest noise contributors of the amplifier
increases not only the bandwidth of the LNA but also improves stages. This revealed - as expected - that the first stage is
gain and noise figure at high frequencies, without increasing critical in the LNA design and contributes most to the NF.
power consumption. Adjusting the value of R1 changes the Q- The top 4 noise sources at 11 GHz are in descending order:
factor of the resonance circuit at the output of the first stage transistor T4 , the loop antenna, transistor T1 and resistor R1 .
and therefore also the corresponding bandwidth and gain. The Together those four components make up for over 85.25 % of
inductor of this output resonance tank is L2 and it introduces the total NF at 11 GHz.
the so called shunt-peaking technique. This also optimizes At 43 GHz, the top 5 noise sources (79.49 % of the total NF)
gain, bandwidth and noise of the LNA without significantly are in descending order: transistors T1 , resistor R2 , the antenna
increasing power consumption. However, those two inductors loop, T2 and T4 . While relative change in noise contribution
take up a considerable amount of space on the chip and area varies, absolute values for noise contribution increase for
requirements have been analyzed as detailed later. all transistors with increasing frequencies. The increasingly
Active feedback in the first stage allows for wideband predominating resistive noise at high frequencies can explain
matching of the input impedance but reduces gain and in- the steep rise of the NF beginning at 30 GHz.
creases the noise figure. It consists of the transistor T3 in
25
a source-follower configuration. The first stage is especially
Noise Figure
critical in the overall design since it significantly contributes Gain (S )
Magnitude [dB]

20 21
to the noise figure of the whole amplifier. Careful adjusting the
parameters of this first stage and keeping in mind the stability
15
of the feedback loop is crucial.
10
B. Intermediate and Output Stages
Stage II & III of the LNA are structurally similar but have 5
different resonance frequencies. Also stage II works without
series peaking and thus saves considerable chip area. They 0
109 1010 1011
both make use of a center-tapped coil at the drain of the
cascode transistors which not only has desirable gain and Frequency [Hz]
bandwidth benefits, but is also possible to integrate on chip as a Fig. 5. Noise figure and gain of the LNA in the frequency range from 1 GHz
single coil. The amplifier configuration of the intermediate and to 100 GHz.
output stage is the same cascoded common source amplifier
as in the input stage with a similar inductive and resistive
load. All bulk terminals of the transistors were connected to D. Power Consumption
ground. In simulation, L4 and L6 were realized by connecting In order to be competitive with existing CMOS based
to inductances in series and coupling them with a magnetic computation systems, spin-waves devices, too, have to be

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 4

designed with minimal power consumption in mind. Even TABLE II

though the RF read-out circuitry is an auxiliary part of the E STIMATION OF THE LNA CHIP AREA .
spin-wave device, it may consume a significant portion of
power. Therefore, early in the simulation phase an emphasis Component Type Area [mm2 ] Percentage
was placed on checking power consumption and minimizing Active Area 2.53 · 10−5 0.015 %
it as far as possible. Capacitors 2.00 · 10−2 11.630 %
There are many trade-offs involved with dissipation power Resistors 3.52 · 10−5 0.020 %
minimization. For example, an increase in amplifier gain can Inductors 1.52 · 10−1 88.334 %
be achieved with an increased MOSFET transconductance, Total Area 1.72 · 10−1 100 %
which in turn, is linked to an increased power dissipation.
Power analysis for the used 65 nm CMOS technology has
IV. C ONCLUSION
shown a total power consumption of 41.62 mW at a supply
voltage of 1.2 V. A breakdown of this values reveals that Preliminary circuit simulations show that the spin-wave
38.7 % of total power was consumed by the first stage of characterization with the proposed CMOS-integrated on-chip
the LNA. The second stage consumes 12.8 % of the total oscilloscope is possible. The proposed technique could offer
power, which is equivalent to 5.32 mW. Lastly, the third stage a low power and low cost alternative for currently used spin-
consumes 48.5 % of the total power or 20.2 mW. The increased wave detecting systems. By using the spin wave devices at
power requirement of the last stage can be traced back to the a certain frequency, i.e. for on-chip computing, the readout
resistive termination at the output. circuitry can be designed and optimized even further, conse-
These differences in power consumption between the dif- quently consuming less power and area.
ferent stages are primarily explained by the transistor size The ultra-wideband LNA, as a crucial part of the readout
and consequently the resulting bias current. For instance, the circuitry for spin wave devices has been described and its
transistor size in the first stage is high since gain losses of the significant properties has been analyzed. The conversion gain
active feedback have to be compensated and a high gain in of 22.6 dB and bandwidth of 9.7 GHz to 43.3 GHz has been
the very first stage is crucial for noise figure optimization. In achieved. The estimated power consumption and area of the
the last stage however, a high resonance frequency is linked to LNA are equal 41.62 mW and 0.172 mm2 , respectively. In
small transistor sizes (and therefore low power consumption) addition, it is important to mention that proposed LNA can
in order to minimize parasitic capacitances. easily be used for other applications.

ACKNOWLEDGMENT
E. Chip Area Estimation The authors thank to C. Yilmaz, S. Kiesel, M. Fulde,
L. Heiß, M. Becherer, J. Russer and G. Ziemys from TUM
One of main amplifier target specifications is a minimal chip and A. Papp from ND for fruitful discussions.
area consumption. Even though no actual chip was produced
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