Finite State Machine Design Procedure

Overview

° Design of systems that input flip flops and

combinational logic
° Specifications start with a word description
° Create a state table to indicate next states
° Convert next states and outputs to output and flip flop
input equations
• Reduce logic expressions using truth tables

° Draw resulting circuits.

Lots of opportunities for interesting design

Concept of the State Machine
Computer Hardware = Datapath + Control

Qualifiers
Registers FSM generating sequences
Combinational Functional of control signals Instructs
Units (e.g., ALU) Busses datapath what to do next
Control

Control

State

Qualifiers Control
and Signal
Inputs Outputs

Datapath
Designing Finite State Machines

° Specify the problem with words

(Q. Problem: Design a circuit that detects three
consecutive 1 inputs)
° Assign binary values to states
° Develop a state table
° Use K-maps to simplify expressions
° Flip flop input equations and output equations
° Create appropriate logic diagram
° Should include combinational logic and flip
flops
Example: Detect 3 Consecutive 1 inputs

0
State S0 : zero 1s detected
State S1 : one 1 detected
State S2 : two 1s detected
State S3 : three 1s detected

° Note that each state has 2 output arrows

° Two bits needed to encode state
 State Table for Sequence Detector

Present Next ° Sequence of outputs, inputs,

State Input State Output and flip flop states enumerated
A B x A B y in state table
0 0 0 0 0 0 ° Present state indicates current
0 0 1 0 1 0 value of flip flops
0 1 0 0 0 0
0 1 1 1 0 0
° Next state indicates state after
next rising clock edge
1 0 0 0 0 0
1 0 1 1 1 0 ° Output is output value on
1 1 0 0 0 1 current clock edge
1 1 1 1 1 1

° S0 = 00 ° S2 = 10
° S1 = 01 ° S3 = 11
Finding Expressions for Next State and Output Value

° Create K-map directly from state table (3 columns = 3 K-maps)

° Minimize K-maps to find SOP representations
° Separate circuit for each next state and output value
 Circuit for Consecutive 1s Detector

° Note location of state

flip flops
° Output value (y) is
function of state
° This is a Moore
machine.
 Concept of the State Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Res e t
P re se nt S tate Input Nex t Sta te Output
E v en 0 E v en 0
E v en 0 E v en 1 Odd 0
Odd 0 Odd 1
[0] Odd 1 E v en 1

Symbolic State Transition Table

1 1
Present State Input Next State Output
0 0 0 0
Odd 0 1 1 0
[1] 1 0 1 1
0 1 1 0 1

State Diagram Encoded State Transition Table

° Note: Present state and output are the same value

° Moore machine
Concept of the State Machine
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS

NS
Input
D Q
CLK PS/Output
Q
R
\Reset
D FF Implementation

Input 1 0 0 1 1 0 1 0 1 1 1 0

Clk

Output 1 1 1 0 1 1 0 0 1 0 1 1

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

 Mealy and Moore Machines

Solution 1: (Mealy) Solution 2: (Moore)

0/0 0
Reset Even
Even Input [0] Output
O/P is dependent
1/0 1/1
on current state and 1 1
Input
Output input in Mealy
Transition Odd Odd
[1]
Output is
Arc dependent only
0 on current state
0/1
Mealy Machine: Output is associated with
the state transition Moore Machine: Output is associated
- Appears before the state transition is with the state
completed (by the next clock pulse). -Appears after the state transition
takes place.
 Vending Machine FSM

Step 1. Specify the problem

 Deliver package of gum after 15 cents deposited

 Single coin slot for dimes, nickels

 No change

 Design the FSM using combinational logic and flip flops

N
Coin Vending
D Open Gum
Sensor Machine Release
Reset FSM Mechanism

Clk
 Vending Machine FSM

State Diagram

R eset Present Inputs Next Output

0¢
State D N State Open
0¢ 0 0 0¢ 0
N
0 1 5¢ 0
5¢
D
1 0 10¢ 0
1 1 X X
N 5¢ 0 0 5¢ 0
10¢ 0 1 10¢ 0
D 1 0 15¢ 0
N ,D
1 1 X X
10¢ 0 0 10¢ 0
15¢
0 1 15¢ 0
[ open]
1 0 15¢ 0
1 1 X X
15¢ X X 15¢ 1
Reuse states
whenever possible
Symbolic State Table
 Vending Machine FSM

State Encoding How many flip-flops are needed?

PresentState Inputs Next State Output

Q1 Q0 D N D1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X
 Vending Machine FSM

Determine F/F implementation

Q1 Q1 Q1
Q1 Q0 Q1 Q0 Q1 Q0
DN DN DN

N N N
D D D

Q0 Q0 Q0
K-map for D1 K-map for D0 K-map for Open
 Minimized Implementation

Q1
D D1 Q1
D Q
Q0 CLK Q̄ 1
R Q
N Reset OPEN
N
Q̄ 0
Q0
D0
N̄ Q0
D Q
Q1 CLK
R Q Q̄ 0
N
Reset
Q1
D

Vending machine FSM implementation based on D flip-flops(Moore).

State Assignment Problem

Q. Design a clock synchronous sequential circuit with

two inputs A, B and a single output Z that is 1 if:
– A had the same value at each of the two
previous clock ticks, or
– B has been 1 since the last time that the
first condition was true.
– Otherwise, output should be 0.
State Assignment Example (cont.)

A: 0 1 0 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0
B: 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
Z: 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0
• State definitions:
– INIT: initial state
– A0: A had 10 but not 00 on
the previous clock ticks.
– A1: A had 01 but not 11 on
the previous clock ticks.
– OK0: A had 00, or when OK B=1 and
last A=0
– OK1: A had 11, or when OK B=1 and
last A=1
How to choose the best state
assignment?
• Formal way: try all assignments!
– To much work, not practical.

• Guidelines for reasonable state assignments:

– Choose an initial state into which the machine can easily be
forced at reset (00…0 or 11…1).
– Minimize the number of state variables that change on each
transition.
– Maximize the number of state variables that don’t change in a
group of related states.
– Exploit symmetries in the problem specifications.
– Don’t limit the choice of coded states to the first m n-bit
integers.
– Decompose the set of state variables into individual bits or
fields, where each bit or field has a well-defined meaning wrt
the input effects or output behavior.
– Consider using more than the minimum number of state
variables to make, a decomposed assignment, possible.
Ex: Decomposed State Assignment

State Q1Q2Q3
• Easy to force reset state
INIT 000 • When Q1=1
• Q2 indicates an OK state
A0 100 • Q3 indicates the previous
value of A
A1 101

OK0 110

OK1 111
Ex: One-hot State Assignment

State Q1—Q5 Q1—Q4

(almost one-hot)
•One bit to each state
•Simple structure
INIT 00001 0000 •Requires more than
minimum number of
A0 00010 0001
FFs.
A1 00100 0010

OK0 01000 0100

OK1 10000 1000

Note on unused states

• Minimal Risk:
– Consider getting one of the unused (or illegal) states (can
be hardware failure, design error, etc).
– Identify unused states, create next-state transitions to
initial, idle or a safe state.

• Minimal Cost:
– Assumes the machine never enters to the unused states.
– In the next-state table unused states can be marked as
don’t cares.
– Simplifies excitation logic, but may create problems.
State Minimization

• Should minimize the cost of the final sequential

clocked circuit (scct) either by
– Reducing the number of gates, or
– Reducing the number of FFs
• One possible way for this minimization is
– Elimination of equivalent states.
• Equivalent states:
– If it is impossible to distinguish them by
observing the current and future outputs
of the machine.
 • Example on equivalent states:

• E≡G Present Next State Output

• F≡D State X=0 X=1 X=0 X=1
A A B 0 0
Present
State
Next State Output B C D 0 0
X=0 X=1 X=0 X=1
C A D 0 0
A A B 0 0 D E F 0 1
B C D 0 0 E A F 0 1
C A D 0 0 F G F 0 1
D E D 0 1 G A F 0 1
E A D 0 1
Row Matching Example

State Transition Table

NS output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
Row Matching Example

NS output
PS x=0 x=1 x=0 x=1
Reduced State Transition Diagram
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1

NS output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
 Summary

° Finite state machines form the basis of many digital

systems
° Designs often start from clear specifications
° Develop state diagram and state table
° Optimize using combinational design techniques
° Mealy or Moore implementations possible
• Can model approach using HDL.