EXPERIMENT – 1

VERIFICATION OF LOGIC GATES USING VERILOG HDL

Aim: Verification of logic gates using verilog HDL
Components required: DSCH Tool
1.AND gate

VERILOG CODE:
module logicgate (A,B,F);
input A,B;
output F;
and and1 (F,A,B);
endmodule

NAND gate:

VERILOG CODE:
module logicgate (A,B,F);
input A,B;
output F;
nand nand1 (F,A,B);
endmodule
OR Gate:

VERILOG CODE:
module logicgate (A,B,F);
input A,B;
output F;
or or1 (F,A,B);
endmodule
NOR gate

VERILOG CODE:
module logicgate (A,B,F);
input A,B;
output F;
nor nor1 (F,A,B);
endmodule
EX-OR gate

VERILOG CODE:
module logicgate (A,B,F);
input A,B;
output F;
xor xor1 (F,A,B);
endmodule
EX-NOR gate

Verilog code:

module logicgate (A,B,F);

input A,B;
output F;
Procedure:

0. Open the DSCH software.

1. Drag the components on work place,
2. Apply various input combinations and observe output for each one.
3. Verify the truth table for each input/ output combination.
4. Repeat the process for all other logic gates.

Result: Verified the Logic Gates using TTL IC’s on DSCH

 EXPERIMENT – 2

LED CONTROL USING UNIVERSAL GATES

AIM: To control given LED sequence using NAND and NOR gates

Apparatus:

S. Description of Item Quantity

No
1. IC 7400 03
2. IC 7402 02
3. Digital Trainer Kit 01
4. Bread Board 01
Truth Table

A B LED1 LED2
0 0 1 0
0 1 0 1
1 0 0 0
1 1 1 1

Circuit Implementation Using NAND Gate

Circuit Implementation Using NOR Gate

Theory: NAND and NOR gates are known as universal logic gates. We can implement
any logic by using these universal logic gates. A logic circuit is designed to control LED’s
using NAND and NOR logic gates.

Procedure:

a) Connections are made as per the circuit diagram I

b) By applyingthe inputs, the LED outputs are observed and the operation is verified with the
help of truth table.

Precautions:
1. Connections must be tight on the bread board.

2. Identify the pins of the IC properly.

3. Take care while removing and inserting the IC on bread board.

Result:
1. Understand the concept of universal gates
2. Identify the replacement of universal gates instead of basic gates
3. LED on and off controlling using universal gates
 EXPERIMENT – 3

COMBINATIONAL CIRCUIT BASED CAR SECURITY SYSTEM

Aim: To Design a combinational circuit that check the following conditions to start the car engine
Otherwise blow horn if any one condition fails

Unlock the doors

Whether the seat belt is fasten or not whether the doors
are properly closed or not

Apparatus:

Logic Gates

No of 3-input AND gates No of 2-input AND gates No of 2- input OR No of Inverters

gates
1 2 1 2

Principle of Operation:

It is used to provide the security and safety to the passengers travelling in the car. When
a driver step into the car first it checks whether all the doors are properly closed or not if the
doors are closed then it checks for seatbelt is fasten or not all the conditions are satisfied then
the engine will start otherwise buzzer will blown.

Block diagram:
Truth Table:
Inputs Outputs
Key Cardoors Seatbelt Buzzer Engine
0 X X 0 0
1 0 0 1 0
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1

K-Maps:

Logic Diagram:
Procedure:

Connect the circuit as per the logic diagram

Connect all the inputs of the circuit to the toggle switches Connect all the
outputs of the circuit to the LEDs.
Apply the inputs as per the truth table
Observe and tabulate the output of the circuit

Result: Student is able to design a car security system using logic gates
 EXPERIMENT – 4:

PARTICIPANT SELECTION IN COMPETITION USING MULTIPLEXER

Aim: Participant selection in competitions.

Two judges of the Indian Idol competition need the help of digital logic to display
whether the participant must stay or leave the competition without displaying their votes. The
selection criteria are as follows.

1) At least one judge should vote positively.

2) Same type of votes cancels each other.
3) If the participant stays, green LED should glow.
4) If the participant leaves, red LED should glow.

Components Required: LED’s (Green and Red), MUX IC, NI Multisim with MyDAQ

Theory:

1. There will be 4 possibilities based on the voting of two judges (say A & B).
2. If the 2 judges vote positively or negatively for the participant, then the participant
should leave the competition i.e., if 00 or 11 then output should be zero.
3. If both the judges vote compliment to each other, then the participant stays in the
competition i.e., if 01 or 10 then output should be one.
4. Since one of the combinations will occur at a time based on the voting we can
switch the output using a multiplexer.
5. The circuit diagram is shown below for the given conditions.

Circuit Diagram:
Truth Table:

A B Decision Mux Output LED Status

0 0 Leaves 0 RED ON
0 1 Stays 1 GREEN ON
1 0 Stays 1 GREEN ON
1 1 Leaves 0 RED ON

Procedure:

1. Construct the multiplexer using the basic gates as shown in Fig 2

2. Connect the componentson the bread board as per given circuit diagram (Fig 1).
3. Give Power Supply and the inputs using Kit
4. Change the selection lines and observe the output for each combination.

Observation:

1. What happens if both the judges vote positively for the participant?
2. Does both LEDs glow at the same time for any combination?
3. Can we implement the digital logic for the given problem using universal gates other
than MUX
 EXPERIMENT – 5

RANDOM NUMBER GENERATOR FOR GAMING USING D- FLIPFLOP

Aim: To generate random number for gaming, using D-flipflops.

Components Required: -

S.No Component Name Quantity

1 IC 7474 1

2 IC 7486 1

3 Breadboard 1

4 LEDs 4

5 Connecting Wires Required number

Theory:
1. Circuit counts through 24-1 different non-zero bit patterns.
2. Left most bit determines shift or more complex operation
3. Can build a similar circuit with any number of FFs, may need more xor gates.
4. In general, with n flip-flops, 2n-1 different non-zero bit patterns.

Circuit Diagram:
Block Diagram:

Procedure:
1. Let us consider the initial input data is “ 0001”;
2. D1,D2,D3 and D4 are input lines of corresponding flipflops.
3. Similarly q1,q2,q3 and q4 are output lines of corresponding
flipflops. 4. D1=q4, D2=q1^q4
D3=q2
D4=q3

S.No No.of.Clock Pulse 4-bit output Decimal Equivalent

1 1 0001 1
2 2 0010 2
3 3 0100 4
4 4 1000 8
5 5 0011 3
6 6 0110 6
7 7 1100 12
8 8 1011 11
9 9 0101 5
10 10 1010 10
11 11 0111 7

12 12 1110 14
13 13 1111 15
14 14 1101 13
 15 15 1001 9
16 16 0001 1

Schematic In NI-Multisim:

Result:
1) From this Design, we had understand the concept of flipflops and its Applications.
2) Understood the concept of LFSR and its uses.
DSCH Installation procedure

http://csit-sun.pub.ro/courses/vlsi/Carte_VLSI/intrage.insa-tlse.fr/_etienne/Microwind/index.html

1. Verification of logic gates using verilog HDL

2. Design and verification of full adder using verilog HDL
3. Design and verification of 3-bit odd parity generator using verilog HDL
4. Verification of flip flops using verilog HDL
5. Design and verification of 3-bit synchronous counter using verilog HDL
 EXPERIMENT – 6
DESIGN AND VERIFICATION OF FULL ADDER USING VERILOG HDL

Aim: To Design and verification of full adder using verilog HDL

Components required: DSCH Tool

TRUTH TABLE
module FULL ADDER (A,B,C,SUM,CARRY);
input A,B,C;
output SUM,CARRY;
and and1 (w1,A,B);
xor xor1 (w2,A,B);
and and2 (w3,w1,C);
xor xor2 (SUM,w1,C);
or or1 (CARRY,w1,w3);
endmodule
EXPERIMENT – 7
DESIGN AND VERIFICATION OF 3-BIT ODD PARITY GENERATOR USING VERILOG HDL

Aim: To design and verification of 3-bit odd parity generator using verilog HDL
Components required: DSCH Tool
module oddparitygenerator (A,B,C,Pe,b3,b2,b1);
input A,B,C;
output Pe,b3,b2,b1;
xor xor1 (w1,A,B);
xnor xnor2 (Pe,w1,C);
buf buf1 (b1,A);
buf buf2 (b2,B);
buf buf3 (b2,C);
endmodule

module oddparitygenerator (A,B,C,Po,b3,b2,b1);

input A,B,C;
output Pe,b3,b2,b1;
xor xor1 (w1,A,B);
xor xor2
(Po,w1,C); buf
buf1 (b1,A); buf
buf2 (b2,B); buf
buf3 (b2,C);
endmodule
 EXPERIMENT – 8
VERIFICATION OF FLIP FLOPS USING VERILOG HDL

Aim: Verification of flip flops using verilog HDL

Components required: DSCH Tool

SR-Flip-Flop

D-Flip flop
JK-Flip flop

T-Flop flop
Verilog codes for Flip flops
 EXPERIMENT – 9
DESIGN AND VERIFICATION OF 3-BIT SYNCHRONOUS COUNTER USING VERILOG HDL

Aim: To design and verification of 3-bit synchronous counter using verilog HDL
Components required: DSCH Tool

Circuit diagram:

Truth table