MC68HC908QY4 MC68HC908QT4 MC68HC908QY

MC68HC908QT2 MC68HC908QY1 MC68HC908QT

Data Sheet

M68HC08
Microcontrollers

MC68HC908QY4/D
Rev. 5 07/2005
freescale.com
 MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT
MC68HC908QY1 MC68HC908QT1
Data Sheet

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed co

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash®
technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.

The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 3)
Date Revision
Level
September, N/A
2002

December,
0.1
2002
January, 0.2
2003
HC908QY4 MC68HC908QT4 MC68HC908QY2
HC908QT2 MC68HC908QY1 MC68HC908QT1
eet

rollers

QY4/D
05
m
 908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2
908QY1 MC68HC908QT1

up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To

the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash®
sed from SST.
miconductor, Inc., 2005. All rights reserved.

revision history table summarizes changes contained in this document. For your
the page number designators have been linked to the appropriate location.
story (Sheet 1 of 3)
Description Page
Number(s)
Initial release N/A

1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list. 19
Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages. 21
Figure 2-1. Memory Map — Clarified illegal address and unimplemented memory. 27

Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for Port 27
A Data Register (PTA) and Data Direction Register A (DDRA).
Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard interrupt 118
and ADC conversion complete interrupt.
Chapter 13 System Integration Module (SIM) — Removed reference to break status 113
register as it is duplicated in break module.
11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming — Clarified
oscillator trim option ordering information and what to expect with untrimmed 92
device.
Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation corrected. 98
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) — Diagram 150
updated for clarity.
Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7, 99
DDRA7, and DDRA6.
Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7. 100
Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for 101
DDRA7 and DDRA6.
Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1 103
Chapter 9 Keyboard Interrupt Module (KBI) — Section reworked after deletion of 83
auto wakeup for clarity.
Chapter 4 Auto Wakeup Module (AWU) — New section added for clarity. 49
Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation. 87
Chapter 16 Electrical Specifications — Extensive changes made to electrical 169
specifications.
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case outline 177
drawing for DFN package.
Chapter 17 Ordering Information and Mechanical Specifications — Added ordering 185
information for DFN package.
4.2 Features — Corrected third bulleted item. 49
Revision History (Sheet 2 of 3)
Date Revision
Level

August,
1.0
2003

October,
2.0
2003

January,
2004
3.0
story (Sheet 2 of 3)
Description Page
Number(s)
Reformatted to meet latest M68HC08 documentation standards N/A
Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt 20
module and TCLK pin designator.
Figure 1-2. MCU Pin Assignments — Added TCLK pin designator. 21
Table 1-2. Pin Functions — Added TCLK pin description. 22
Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to add 23
TCLK.
Figure 2-1. Memory Map — Corrected names for the IRQ status and control 26
register (INTSCR) bits 3–0.
3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock 47
prescaler bits.
4.3 Functional Description — Updated periodic wakeup request values. 51
Figure 6-1. COP Block Diagram — Reworked for clarity 59
Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF, ACK, 77–79
and IMASK
Chapter 14 Timer Interface Module (TIM) — Added TCLK function. 131–139
15.3 Monitor Module (MON) — Updated with additional data. 147
Chapter 16 Electrical Specifications — Updated with additional data. 169–173
Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented areas
from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available. Also corrected 27
$FFBF designation from unimplemented to reserved.
Figure 6-1. COP Block Diagram — Reworked for clarity 59
6.3.2 STOP Instruction — Added subsection 60
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity. 111
Table 13-2. Reset Recovery Timing — Replaced previous table with new 112
information.
Chapter 14 Timer Interface Module (TIM) — Updated with additional data. 131
Figure 15-3. Break I/O Register Summary — Corrected bit designators for the 143
BRKAR register
15.3 Monitor Module (MON) — Clarified seventh bullet. 147
Table 17-1. MC Order Numbers — Corrected temperature and package 175
designators.
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal Oscillator 32
Trim Value at $FFC0.
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for 38
clarity.
Revision History (Sheet 3 of 3)
Date Revision
Level

November,
4.0
2004

July, 2005 5.0

List of Chapters
Chapter 1 General Description 17
Chapter 2 Memory 25
Chapter 3 Analog-to-Digital Converter (ADC) 41
Chapter 4 Auto Wakeup Module (AWU) 49
Chapter 5 Configuration Register (CONFIG) 53
Chapter 6 Computer Operating Properly (COP) 57
Chapter 7 Central Processor Unit (CPU) 61
Chapter 8 External Interrupt (IRQ) 73
Chapter 9 Keyboard Interrupt Module (KBI) 79
Chapter 10 Low-Voltage Inhibit (LVI) 85
Chapter 11 Oscillator Module (OSC) 89
Chapter 12 Input/Output Ports (PORTS) 97
Chapter 13 System Integration Module (SIM) 103
Chapter 14 Timer Interface Module (TIM) 119
Chapter 15 Development Support 133
Chapter 16 Electrical Specifications 149
Chapter 17 Ordering Information and Mechanical Specifications 165

Table of Contents
Chapter 1 General Description
1.1 Introduction
1.2 Features
1.3 MCU Block Diagram 1
1.4 Pin Assignments 1
1.5 Pin Functions 2
1.6 Pin Function Priority
Chapter 2 Memory
2.1 Introduction
2.2 Unimplemented Memory Locations
2.3 Reserved Memory Locations 2
2.4 Input/Output (I/O) Section
2.5 Random-Access Memory (RAM) 32
2.6 FLASH Memory (FLASH) 3
2.6.1 FLASH Control Register 3
2.6.2 FLASH Page Erase Operation 34
2.6.3 FLASH Mass Erase Operation 3
2.6.4 FLASH Program Operation 3
2.6.5 FLASH Protection 3
2.6.6 FLASH Block Protect Register 3
2.6.7 Wait Mode
2.6.8 Stop Mode
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction
3.2 Features
3.3 Functional Description
3.3.1 ADC Port I/O Pins 4
3.3.2 Voltage Conversion
3.3.3 Conversion Time
3.3.4 Continuous Conversion
3.3.5 Accuracy and Precision
3.4 Interrupts
3.5 Low-Power Modes 4
3.5.1 Wait Mode
3.5.2 Stop Mode
3.6 Input/Output Signals
3.7 Input/Output Registers
3.7.1 ADC Status and Control Register 4
3.7.2 ADC Data Register
3.7.3 ADC Input Clock Register 4
Chapter 4
Auto Wakeup Module (AWU)
4.1 Introduction
4.2 Features
4.3 Functional Description
4.4 Wait Mode
4.5 Stop Mode
4.6 Input/Output Registers
4.6.1 Port A I/O Register 5
4.6.2 Keyboard Status and Control Register
4.6.3 Keyboard Interrupt Enable Register
Chapter 5 Configuration Register (CONFIG)
5.1 Introduction
5.2 Functional Description
Chapter 6
Computer Operating Properly (COP)
6.1 Introduction
6.2 Functional Description
6.3 I/O Signals
6.3.1 BUSCLKX4 5
6.3.2 STOP Instruction 5
6.3.3 COPCTL Write 5
6.3.4 Power-On Reset 5
6.3.5 Internal Reset
6.3.6 COPD (COP Disable) 5
6.3.7 COPRS (COP Rate Select) 59
6.4 COP Control Register 5
6.5 Interrupts
6.6 Monitor Mode
6.7 Low-Power Modes 5
6.7.1 Wait Mode
6.7.2 Stop Mode
6.8 COP Module During Break Mode 5
Central Processor Unit (CPU)
7.1 Introduction
7.2 Features
7.3 CPU Registers 6
7.3.1 Accumulator
7.3.2 Index Register
7.3.3 Stack Pointer
7.3.4 Program Counter
7.3.5 Condition Code Register 6
7.4 Arithmetic/Logic Unit (ALU)
7.5 Low-Power Modes 6
7.5.1 Wait Mode
7.5.2 Stop Mode
7.6 CPU During Break Interrupts 6
7.7 Instruction Set Summary
7.8 Opcode Map
Chapter 8 External Interrupt (IRQ)
8.1 Introduction
8.2 Features
8.3 Functional Description
8.3.1 MODE = 1 7
8.3.2 MODE = 0 7
8.4 Interrupts
8.5 Low-Power Modes 7
8.5.1 Wait Mode
8.5.2 Stop Mode
8.6 IRQ Module During Break Interrupts 7
8.7 I/O Signals
8.7.1 IRQ Input Pins (IRQ) 7
8.8 Registers
Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction
9.2 Features
9.3 Functional Description
9.3.1 Keyboard Operation
9.3.2 Keyboard Initialization
9.4 Wait Mode
9.5 Stop Mode
9.6 Keyboard Module During Break Interrupts
9.7 Input/Output Registers
9.7.1 Keyboard Status and Control Register
9.7.2 Keyboard Interrupt Enable Register
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
10.2 Features
10.3 Functional Description
10.3.1 Polled LVI Operation 8
10.3.2 Forced Reset Operation 8
10.3.3 Voltage Hysteresis Protection
10.3.4 LVI Trip Selection
10.4 LVI Status Register 8
10.5 LVI Interrupts
10.6 Low-Power Modes 8
10.6.1 Wait Mode
10.6.2 Stop Mode
Chapter 11 Oscillator Module (OSC)
11.1 Introduction
11.2 Features
11.3 Functional Description
11.3.1 Internal Oscillator
11.3.1.1 Internal Oscillator Trimming
11.3.1.2 Internal to External Clock Switching 9
11.3.2 External Oscillator
11.3.3 XTAL Oscillator 9
11.3.4 RC Oscillator 9
11.4 Oscillator Module Signals
11.4.1 Crystal Amplifier Input Pin (OSC1) 9
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) 94
11.4.3 Oscillator Enable Signal (SIMOSCEN) 9
11.4.4 XTAL Oscillator Clock (XTALCLK) 94
11.4.5 RC Oscillator Clock (RCCLK) 9
11.4.6 Internal Oscillator Clock (INTCLK) 9
11.4.7 Oscillator Out 2 (BUSCLKX4) 9
11.4.8 Oscillator Out (BUSCLKX2) 9
11.5 Low Power Modes 9
11.5.1 Wait Mode
11.5.2 Stop Mode
11.6 Oscillator During Break Mode 9
11.7 CONFIG2 Options 9
11.8 Input/Output (I/O) Registers
11.8.1 Oscillator Status Register
11.8.2 Oscillator Trim Register (OSCTRIM) 9
Input/Output Ports (PORTS)
12.1 Introduction
12.2 Port A
12.2.1 Port A Data Register 9
12.2.2 Data Direction Register A
12.2.3 Port A Input Pullup Enable Register 9
12.3 Port B 1
12.3.1 Port B Data Register 10
12.3.2 Data Direction Register B 1
12.3.3 Port B Input Pullup Enable Register 10
Chapter 13
System Integration Module (SIM)
13.1 Introduction 1
13.2 RST and IRQ Pins Initialization 10
13.3 SIM Bus Clock Control and Generation 10
13.3.1 Bus Timing 1
13.3.2 Clock Start-Up from POR 10
13.3.3 Clocks in Stop Mode and Wait Mode 10
13.4 Reset and System Initialization 1
13.4.1 External Pin Reset 10
13.4.2 Active Resets from Internal Sources 1
13.4.2.1 Power-On Reset 10
13.4.2.2 Computer Operating Properly (COP) Reset 10
13.4.2.3 Illegal Opcode Reset 10
13.4.2.4 Illegal Address Reset 10
13.4.2.5 Low-Voltage Inhibit (LVI) Reset 10
13.5 SIM Counter 10
13.5.1 SIM Counter During Power-On Reset 10
13.5.2 SIM Counter During Stop Mode Recovery 10
13.5.3 SIM Counter and Reset States 10
13.6 Exception Control 1
13.6.1 Interrupts 1
13.6.1.1 Hardware Interrupts 1
13.6.1.2 SWI Instruction 11
13.6.2 Interrupt Status Registers 1
13.6.2.1 Interrupt Status Register 1 1
13.6.2.2 Interrupt Status Register 2 1
13.6.2.3 Interrupt Status Register 3 1
13.6.3 Reset 1
13.6.4 Break Interrupts 1
13.6.5 Status Flag Protection in Break Mode 11
13.7 Low-Power Modes 11
13.7.1 Wait Mode 1
13.7.2 Stop Mode 1
13.6.2 Interrupt Status Registers 1
13.6.2.1 Interrupt Status Register 1 1
13.6.2.2 Interrupt Status Register 2 1
13.6.2.3 Interrupt Status Register 3 1
13.6.3 Reset 1
13.6.4 Break Interrupts 1
13.6.5 Status Flag Protection in Break Mode 11
13.7 Low-Power Modes 11
13.7.1 Wait Mode 1
13.7.2 Stop Mode 1

13.8 SIM Registers 1

13.8.1 SIM Reset Status Register 11
13.8.2 Break Flag Control Register 11
Chapter 14
Timer Interface Module (TIM)
14.1 Introduction 1
14.2 Features 1
14.3 Pin Name Conventions 11
14.4 Functional Description 1
14.4.1 TIM Counter Prescaler 12
14.4.2 Input Capture 1
14.4.3 Output Compare 1
14.4.3.1 Unbuffered Output Compare 12
14.4.3.2 Buffered Output Compare 1
14.4.4 Pulse Width Modulation (PWM) 12
14.4.4.1 Unbuffered PWM Signal Generation 12
14.4.4.2 Buffered PWM Signal Generation 12
14.4.4.3 PWM Initialization 12
14.5 Interrupts 1
14.6 Wait Mode 1
14.7 TIM During Break Interrupts 1
14.8 Input/Output Signals 1
14.8.1 TIM Clock Pin (PTA2/TCLK) 126
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1) 126
14.9 Input/Output Registers 1
14.9.1 TIM Status and Control Register 12
14.9.2 TIM Counter Registers 12
14.9.3 TIM Counter Modulo Registers 12
14.9.4 TIM Channel Status and Control Registers 12
14.9.5 TIM Channel Registers 13
Chapter 15 Development Support
15.1 Introduction 1
15.2 Break Module (BRK) 13
15.2.1 Functional Description 1
15.2.1.1 Flag Protection During Break Interrupts 13
15.2.1.2 TIM During Break Interrupts 13
15.2.1.3 COP During Break Interrupts 13
15.2.2 Break Module Registers 13
15.2.2.1 Break Status and Control Register 13
15.2.2.2 Break Address Registers 13
15.2.2.3 Break Auxiliary Register 13
15.2.2.4 Break Status Register 13
15.2 Break Module (BRK) 13
15.2.1 Functional Description 1
15.2.1.1 Flag Protection During Break Interrupts 13
15.2.1.2 TIM During Break Interrupts 13
15.2.1.3 COP During Break Interrupts 13
15.2.2 Break Module Registers 13
15.2.2.1 Break Status and Control Register 13
15.2.2.2 Break Address Registers 13
15.2.2.3 Break Auxiliary Register 13
15.2.2.4 Break Status Register 13
15.2.2.5 Break Flag Control Register 13
15.2.3 Low-Power Modes 13

15.3 Monitor Module (MON) 1

15.3.1 Functional Description 1
15.3.1.1 Normal Monitor Mode 14
15.3.1.2 Forced Monitor Mode 14
15.3.1.3 Monitor Vectors 1
15.3.1.4 Data Format 1
15.3.1.5 Break Signal 14
15.3.1.6 Baud Rate 14
15.3.1.7 Commands 14
15.3.2 Security 1
Chapter 16 Electrical Specifications
16.1 Introduction 1
16.2 Absolute Maximum Ratings 14
16.3 Functional Operating Range 15
16.4 Thermal Characteristics 1
16.5 5-V DC Electrical Characteristics 15
16.6 Typical 5-V Output Drive Characteristics 15
16.7 5-V Control Timing 1
16.8 5-V Oscillator Characteristics 1
16.9 3-V DC Electrical Characteristics 15
16.10 Typical 3.0-V Output Drive Characteristics 15
16.11 3-V Control Timing 1
16.12 3-V Oscillator Characteristics 1
16.13 Supply Current Characteristics 15
16.14 Analog-to-Digital Converter Characteristics 1
16.15 Timer Interface Module Characteristics 16
16.16 Memory Characteristics 16
Chapter 17
Ordering Information and Mechanical Specifications
17.1 Introduction 1
17.2 MC Order Numbers 16
17.3 Package Dimensions 16
story (Sheet 3 of 3)
Description Page
Number(s)
Reformatted to meet current documentation standards Throughout
6.3.1 BUSCLKX4 — Clarified description of BUSCLKX4 58
Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary: Reworked definitions for STOP instructionAdded WAIT instruc
7071

13.8.1 SIM Reset Status Register — Clarified SRSR flag setting 117
14.9.1 TIM Status and Control Register — Added information to TSTOP note 127
16.8 5-V Oscillator Characteristics — Added values for deviation from trimmed 155
inernal oscillator
16.12 3-V Oscillator Characteristics — Added values for deviation from trimmed 158
inernal oscillator
Figure 5-2. Configuration Register 1 (CONFIG1) — Clarified bit definitions for 54
COPRS.
Chapter 8 External Interrupt (IRQ) — Reworked for clarification. 73
11.3.4 RC Oscillator — Improved RC oscillator wording. 93
12.1 Introduction — Added note pertaining to non-bonded port pins. 97
17.3 Package Dimensions — Updated package information. 165

hapters
neral Description 17
mory 25
alog-to-Digital Converter (ADC) 41
to Wakeup Module (AWU) 49
nfiguration Register (CONFIG) 53
mputer Operating Properly (COP) 57
ntral Processor Unit (CPU) 61
ernal Interrupt (IRQ) 73
yboard Interrupt Module (KBI) 79
ow-Voltage Inhibit (LVI) 85
scillator Module (OSC) 89
put/Output Ports (PORTS) 97
ystem Integration Module (SIM) 103
mer Interface Module (TIM) 119
evelopment Support 133
ectrical Specifications 149
rdering Information and Mechanical Specifications 165

Contents
eral Description
ction 17
s 17
ock Diagram 19
gnments 19
ctions 22
ction Priority 23
mory
ction 25
emented Memory Locations 25
ed Memory Locations 25
utput (I/O) Section 27
m-Access Memory (RAM) 32
Memory (FLASH) 33
SH Control Register 33
SH Page Erase Operation 34
SH Mass Erase Operation 35
SH Program Operation 35
SH Protection 36
SH Block Protect Register 38
t Mode 39
p Mode 39

tal Converter (ADC)

ction 41
s 41
nal Description 41
C Port I/O Pins 41
age Conversion 44
version Time 44
tinuous Conversion 44
uracy and Precision 44
pts 44
wer Modes 44
t Mode 44
p Mode 45
 utput Signals 45
utput Registers 45
C Status and Control Register 45
C Data Register 47
C Input Clock Register 47

Module (AWU)
ction 49
s 49
nal Description 49
ode 50
ode 50
utput Registers 51
A I/O Register 51
board Status and Control Register 51
board Interrupt Enable Register 52
figuration Register (CONFIG)
ction 53
nal Description 53

rating Properly (COP)

ction 57
nal Description 57
als 58
SCLKX4 58
OP Instruction 58
PCTL Write 58
er-On Reset 58
rnal Reset 58
PD (COP Disable) 58
PRS (COP Rate Select) 59
ntrol Register 59
pts 59
Mode 59
wer Modes 59
t Mode 59
p Mode 59
dule During Break Mode 59
 sor Unit (CPU)
ction 61
s 61
gisters 61
umulator 62
ex Register 62
ck Pointer 63
gram Counter 63
dition Code Register 64
etic/Logic Unit (ALU) 65
wer Modes 65
t Mode 65
p Mode 65
ring Break Interrupts 65
ion Set Summary 66
Map 71
rnal Interrupt (IRQ)
ction 73
s 73
nal Description 73
DE = 1 75
DE = 0 75
pts 76
wer Modes 76
t Mode 76
p Mode 76
dule During Break Interrupts 76
als 76
Input Pins (IRQ) 77
rs 77

rupt Module (KBI)

ction 79
s 79
nal Description 79
board Operation 79
board Initialization 82
ode 82
ode 82
rd Module During Break Interrupts 82
utput Registers 83
board Status and Control Register 83
board Interrupt Enable Register 84

hibit (LVI)
ction 85
s 85
nal Description 85
ed LVI Operation 86
ced Reset Operation 86
age Hysteresis Protection 86
Trip Selection 86
us Register 87
rrupts 87
wer Modes 87
t Mode 87
p Mode 87
cillator Module (OSC)
ction 89
s 89
nal Description 89
rnal Oscillator 90
ternal Oscillator Trimming 91
ternal to External Clock Switching 91
ernal Oscillator 91
L Oscillator 92
Oscillator 93
or Module Signals 93
stal Amplifier Input Pin (OSC1) 93
stal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) 94
illator Enable Signal (SIMOSCEN) 94
L Oscillator Clock (XTALCLK) 94
Oscillator Clock (RCCLK) 94
rnal Oscillator Clock (INTCLK) 94
illator Out 2 (BUSCLKX4) 94
illator Out (BUSCLKX2) 94
wer Modes 95
t Mode 95
p Mode 95
or During Break Mode 95
2 Options 95
utput (I/O) Registers 95
illator Status Register 96
illator Trim Register (OSCTRIM) 96
orts (PORTS)
ction 97
97
A Data Register 98
a Direction Register A 98
A Input Pullup Enable Register 99
100
B Data Register 100
a Direction Register B 101
B Input Pullup Enable Register 102

ation Module (SIM)

ction 103
d IRQ Pins Initialization 104
s Clock Control and Generation 104
Timing 105
ck Start-Up from POR 105
cks in Stop Mode and Wait Mode 105
nd System Initialization 105
ernal Pin Reset 106
ve Resets from Internal Sources 106
ower-On Reset 107
omputer Operating Properly (COP) Reset 108
egal Opcode Reset 108
egal Address Reset 108
ow-Voltage Inhibit (LVI) Reset 108
unter 108
Counter During Power-On Reset 108
Counter During Stop Mode Recovery 109
Counter and Reset States 109
on Control 109
rrupts 109
ardware Interrupts 111
WI Instruction 112
rrupt Status Registers 112
terrupt Status Register 1 113
terrupt Status Register 2 113
terrupt Status Register 3 113
et 114
ak Interrupts 114
tus Flag Protection in Break Mode 114
wer Modes 114
t Mode 114
p Mode 115
 rrupt Status Registers 112
terrupt Status Register 1 113
terrupt Status Register 2 113
terrupt Status Register 3 113
et 114
ak Interrupts 114
tus Flag Protection in Break Mode 114
wer Modes 114
t Mode 114
p Mode 115

gisters 116
Reset Status Register 117
ak Flag Control Register 118

e Module (TIM)
ction 119
s 119
me Conventions 119
nal Description 121
Counter Prescaler 122
ut Capture 122
put Compare 122
nbuffered Output Compare 122
uffered Output Compare 122
se Width Modulation (PWM) 123
nbuffered PWM Signal Generation 124
uffered PWM Signal Generation 124
WM Initialization 125
pts 125
ode 126
ing Break Interrupts 126
utput Signals 126
Clock Pin (PTA2/TCLK) 126
Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1) 126
utput Registers 126
Status and Control Register 127
Counter Registers 128
Counter Modulo Registers 129
Channel Status and Control Registers 129
Channel Registers 132
velopment Support
ction 133
Module (BRK) 133
ctional Description 133
ag Protection During Break Interrupts 135
M During Break Interrupts 135
OP During Break Interrupts 135
ak Module Registers 135
reak Status and Control Register 136
reak Address Registers 136
reak Auxiliary Register 137
reak Status Register 137
Module (BRK) 133
ctional Description 133
ag Protection During Break Interrupts 135
M During Break Interrupts 135
OP During Break Interrupts 135
ak Module Registers 135
reak Status and Control Register 136
reak Address Registers 136
reak Auxiliary Register 137
reak Status Register 137
reak Flag Control Register 138
-Power Modes 138

Module (MON) 138

ctional Description 139
ormal Monitor Mode 142
orced Monitor Mode 143
onitor Vectors 143
ata Format 144
reak Signal 144
aud Rate 144
ommands 144
urity 148
ctrical Specifications
ction 149
e Maximum Ratings 149
nal Operating Range 150
l Characteristics 150
Electrical Characteristics 151
5-V Output Drive Characteristics 152
ntrol Timing 153
illator Characteristics 154
Electrical Characteristics 155
3.0-V Output Drive Characteristics 156
ntrol Timing 157
illator Characteristics 158
Current Characteristics 159
to-Digital Converter Characteristics 161
nterface Module Characteristics 162
y Characteristics 163

mation and Mechanical Specifications

ction 165
er Numbers 165
e Dimensions 165
Chapter 1
General Description
1.1 Introduction
The MC68HC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) wi
Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor u
(CPU08) and are available with a variety of modules, memory sizes and types, and package type
Table 1-1. Summary of Device Variations

Device FLASH Analog-to-Digital Pin Count

Memory Size Converter
MC68HC908QT1 1536 bytes — 8 pins
MC68HC908QT2 1536 bytes 4 ch, 8 bit 8 pins
MC68HC908QT4 4096 bytes 4 ch, 8 bit 8 pins
MC68HC908QY1 1536 bytes — 16 pins
MC68HC908QY2 1536 bytes 4 ch, 8 bit 16 pins
MC68HC908QY4 4096 bytes 4 ch, 8 bit 16 pins

1.2 Features
Features include:
• High-performance M68HC08 CPU core
• Fully upward-compatible object code with M68HC05 Family
• 5-V and 3-V operating voltages (VDD)
• 8-MHz internal bus operation at 5 V, 4-MHz at 3 V
• Trimmable internal oscillator
– 3.2 MHz internal bus operation
– 8-bit trim capability allows 0.4% accuracy(1)
– ± 25% untrimmed
• Auto wakeup from STOP capability
• Configuration (CONFIG) register for MCU configuration options, including:
– Low-voltage inhibit (LVI) trip point
• In-system FLASH programming
• FLASH security(2)

1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming.
2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult
unauthorized users.
• On-chip in-application programmable FLASH memory (with internal program/erase voltage
generation)
– MC68HC908QY4 and MC68HC908QT4 — 4096 bytes
– MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and MC68HC908QT1 — 1536 bytes
• 128 bytes of on-chip random-access memory (RAM)
• 2-channel, 16-bit timer interface module (TIM)
• 4-channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY2, MC68HC908QY4,
MC68HC908QT2, and MC68HC908QT4
• 5 or 13 bidirectional input/output (I/O) lines and one input only:
– Six shared with keyboard interrupt function and ADC
– Two shared with timer channels
– One shared with external interrupt (IRQ)
– Eight extra I/O lines on 16-pin package only
– High current sink/source capability on all port pins
– Selectable pullups on all ports, selectable on an individual bit basis
– Three-state ability on all port pins
• 6-bit keyboard interrupt with wakeup feature (KBI)
• Low-voltage inhibit (LVI) module features:
– Software selectable trip point in CONFIG register
• System protection features:
– Computer operating properly (COP) watchdog
– Low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose inp
• Master asynchronous reset pin (RST) shared with general-purpose input/output (I/O) pin
• Power-on reset
• Internal pullups on IRQ and RST to reduce external components
• Memory mapped I/O registers
• Power saving stop and wait modes
• MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 are available in these packages:
– 16-pin plastic dual in-line package (PDIP)
– 16-pin small outline integrated circuit (SOIC) package
– 16-pin thin shrink small outline package (TSSOP)
• MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in these packages:
– 8-pin PDIP
– 8-pin SOIC
– 8-pin dual flat no lead (DFN) package

MCU Block Di
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8  8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support

1.3 MCU Block DiagramFigure 1-1 shows the structure of the MC68HC908QY4.

1.4 Pin AssignmentsThe MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in 8-pin packages and the MC68HC90
 ce M68HC08 Family of 8-bit
ction Set Computer (CISC) with a
M68HC08 central processor unit
and types, and package types.

uding:

fter trimming.
ading or copying the FLASH difficult for
al program/erase voltage

08QT1 — 1536 bytes

QY2, MC68HC908QY4,

red with general-purpose input pin

input/output (I/O) pin

able in these packages:

able in these packages:

MCU Block Diagram

e in 8-pin packages and the MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 in 16-pin packages. Figure 1-2 shows the pin assignment for th
 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

CLOCK GENERATOR
(OSCILLATOR)
DDRA
PTA

M68HC08 CPU

SYSTEM INTEGRATION
MODULE

SINGLE INTERRUPT
MODULE

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

DDRB
PTB

BREAK MODULE

POWER-ON RESET
MODULE

MC68HC908QY4 AND MC68HC908QT4

4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH

KEYBOARD INTERRUPT
MODULE
 8-BIT ADC

16-BIT TIMER
MODULE

128 BYTES RAM

COP MODULE

POWER SUPPLY

MONITOR ROM

RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 1-1. Block Diagram
1/AD1/TCH1/KBI1
K PTA3/RST/KBI3
4/OSC2/AD2/KBI4
5/OSC1/AD3/KBI5

B1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

 RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
able on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 1-1. Block Diagram

VD
D

VSS
 Pin Assignme
1 8
2 7
3 6
4 5

V
DD V
SS PTA0/TCH0/KBI0 V
DD 1 8
V
SS PTA0/AD0/TCH0/K
PTA5/OSC1/KBI PTA1/TCH1/KBI1 PTA5/OSC1/AD3/KBI
2 7 PTA1/AD1/TCH1/KBI1
5 PTA2/IRQ/KBI2/TCLK 5 3 6 PTA2/IRQ/KBI2/TCLK
PTA4/OSC2/KBI PTA4/OSC2/AD2/KBI
4 5
4 4
PTA3/RST/KBI3 PTA3/RST/KBI3

8-PIN ASSIGNMENT 8-PIN ASSIGNMENT

1
MC68HC908QT1 16
PDIP/SOIC 1 1
MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC
2 15 2 6
V
DD V
SS PTB0 PTB1 V
DD V
SS
3 14 3 1
PTB7 PTB6 PTA0/TCH0/KBI0 PTB7 PTB6 PTB0 PTB1
4 13 4 5
PTA5/OSC1/KBI5 PTA1/TCH1/KBI1 PTB2 PTA5/OSC1/AD3/KBI5 PTA0/AD0/TCH0/KBI0
5 12 5 1
PTA4/OSC2/KBI4 PTB3 PTA4/OSC2/AD2/KBI4 PTA1/AD1/TCH1/KBI1
6 11 6 4
PTB5 PTB4 PTA2/IRQ/KBI2/TCLK PTB5 PTB4 PTB3
7 10 7 1
PTA3/RST/KBI3 PTA3/RST/KBI3 PTA2/IRQ/KBI2/TCLK
8 9 8 3
1
2
1
1
1
0
9

16-PIN
ASSIGNMENT 16-PIN ASSIGNMENT
MC68HC908QY1 PDIP/SOIC MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC
1 16
2 15
3 14
4 13
5 12
6 11
7 10
8 9

1 16
2 15
3 14
4 13
5 12
6 11
7 10
8 9

PTA0/TCH0/KBI0 P PTA0/AD0/TCH0/KBI0 P
PTB1 PTB0 T PTB1 PTB0 T
V
SS VDD A V
SS VDD A
PTB7 PTB6 16- 1 PTB7 PTB6 1
PTA5/OSC1/KBI5 PI / PTA5/OSC1/AD3/KBI5 16- /
N T PIN A
AS C AS D
SI H SI 1
GN 1 GN /
ME / ME T
NT K NT C
MC68HC908QY1 TSSOP
MC68HC908QY2 AND MC68HC908QY4 TSSOP

PTA0/TCH0/KBI0 1 8 PTA1/TCH1/KBI1 PTA0/AD0/TCH0/KBI0 1

 V
SS 2 7 PTA2/IRQ/KBI2/TCLK V
SS 2
V
DD 3 6 PTA3/RST/KBI3 V
DD 3
PTA5/OSC1/KB15 4 5 PTA4/OSC2/KBI4 PTA5//OSC1/AD3/KB15 4

8-PIN ASSIGNMENT 8-PIN ASSIGNMENT MC68HC908QT2 AND MC68HC908QT4 DFN

MC68HC908QT1 DFN Figure 1-2. MCU Pin Assignments
 Pin Assignments

V
SS PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK

8QT4 PDIP/SOIC
V
SS
PTB0 PTB1
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1 PTB2
PTB3
PTA2/IRQ/KBI2/TCLK

08QY4 PDIP/SOIC

8 PTA1/AD1/TCH1/KBI1
7 PTA2/IRQ/KBI2/TCLK
6 PTA3/RST/KBI3
5 PTA4/OSC2/AD2/KBI4
 1.5 Pin FunctionsTable 1-2 provides a description of the pin functions.Table 1-2. Pin Functions

Pin Name Description

V
DD Power supply
V
SS Power supply ground

PTA0 — General purpose I/O port

AD0 — A/D channel 0 input
PTA0
TCH0 — Timer Channel 0 I/O
KBI0 — Keyboard interrupt input 0
PTA1 — General purpose I/O port
AD1 — A/D channel 1 input
PTA1
TCH1 — Timer Channel 1 I/O
KBI1 — Keyboard interrupt input 1
PTA2 — General purpose input-only port
IRQ — External interrupt with programmable pullup and Schmitt trigger input
PTA2
KBI2 — Keyboard interrupt input 2
TCLK — Timer clock input
PTA3 PTA3 — General purpose I/O port
RST — Reset input, active low with internal pullup and Schmitt trigger
KBI3 — Keyboard interrupt input 3
PTA4 — General purpose I/O port
OSC2 —XTAL oscillator output (XTAL option only)
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
PTA4
AD2 — A/D channel 2 input
KBI4 — Keyboard interrupt input 4
PTA5 — General purpose I/O port
OSC1 — XTAL, RC, or external oscillator input
PTA5
AD3 — A/D channel 3 input
KBI5 — Keyboard interrupt input 5
PTB[0:7](1) 8 general-purpose I/O ports

1. The PTB pins are not available on the 8-pin packages (see note in 12.1 Introduction).
Functions

Input/Output

Power

Power

Input/Output
Input
Input/Output
Input
Input/Output
Input
Input/Output
Input
Input
Input
Input
Input
Input/Output
Input
Input
Input/Output
Output
Output
Input
Input
Input/Output
Input
Input
Input
Input/Output
 Pin Function Priority
1.6 Pin Function Priority
Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin.NOTEUpon reset all pins come up as input ports re

Pin Name Highest-to-Lowest Priority Sequence

PTA0 AD0  TCH0  KBI0  PTA0

PTA1 AD1 TCH1  KBI1  PTA1

PTA2 IRQ  KBI2  TCLK  PTA2

PTA3 RST  KBI3  PTA3

PTA4 OSC2  AD2  KBI4  PTA4

PTA5 OSC1  AD3  KBI5  PTA5

Chapter 2 Memory

2.1 IntroductionThe central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, incl

2.2 Unimplemented Memory LocationsAccessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2

2.3 Reserved Memory LocationsAccessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in reg
 Pin Function Priority

Upon reset all pins come up as input ports regardless of the priority table.Table 1-3. Function Priority in Shared Pins

The memory map, shown in Figure 2-1, includes:• 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4• 1536 bytes of user FLAS

table effects on MCU operation. In Figure 2-1 and in register figures in this document, unimplemented locations are shaded.

on MCU operation. In Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.
$0000

$003F
$0040

$007F
$0080

$00FF
$0100

$27FF
$2800

$2DFF
$2E00

$EDFF
$EE00

$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D

$FE0F
$FE10

$FFAF
$FFB0

$FFBD
$FFBE
$FFBF
$FFC0
$FFC1
$FFC2

$FFCF
$FFD0

$FFFF

I/O REGISTERS 64 BYTES

Note 1.
Attempts to execute code from addresses in this range will
generate an illegal address reset.
 RESERVED(1) 64 BYTES

RAM 128 BYTES Note 1.

Attempts to execute code from addresses in this range will
generate an illegal address reset.
UNIMPLEMENTED(1) 9984 BYTES

AUXILIARY ROM 1536 BYTES

UNIMPLEMENTED(1) 49152 BYTES UNIMPLEMENTED 51712 BYTES

FLASH MEMORY MC68HC908QT4 AND

MC68HC908QY4 FLASH MEMORY 1536 BYTES
4096 BYTES

BREAK STATUS REGISTER (BSR) MC68HC908QT1, MC68HC908QT2, MC68HC908QY1, and MC68HC908QY2

RESET STATUS REGISTER (SRSR) Memory Map
BREAK AUXILIARY REGISTER (BRKAR)
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
INTERRUPT STATUS REGISTER 3 (INT3)
RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)
FLASH CONTROL REGISTER (FLCR)
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOWREGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
LVISR
RESERVED FOR FLASH TEST 3 BYTES

MONITOR ROM 416 BYTES

FLASH 14 BYTES

FLASH BLOCK PROTECT REGISTER (FLBPR)

RESERVED FLASH
INTERNAL OSCILLATOR TRIM VALUE
RESERVED FLASH
FLASH 14 BYTES

USER VECTORS 48 BYTES

Figure 2-1. Memory Map

2.4 Input/Output (I/O) SectionAddresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Addition
es in this range will
es in this range will

$2E00

$F7FF
$F800

$FDFF

Y1, and MC68HC908QY2

and data registers. Additional I/O registers have these addresses:• $FE00 — Break status register, BSR• $FE01 — Reset status register, SRSR• $F
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
R AWUL PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

$0000 Port A Data Register(PTA)See

Read:page 98.Port B Data Register(PTB)See page 100.
$0001 Write:
Reset: Unaffected by reset
Read:
Write:
Reset: Unaffected by reset

PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

$0002 Unimplemented

$0003 Unimplemented
R R DDRA5 DDRA4 DDRA3 0 DDRA1 DDRA0

Read:
Write:
Reset: 0 0 0 0 0
Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3
Write:
Reset: 0 0 0 0 0
= R =
$0004 Data Direction Register A(DDRA)See page 98.Data DirectionUnimplemente Reserved
Register B(DDRB)See page 101.Figure 2-2. Control, Status, and D
$0005 d
 1 Bit 0

0 0 0
DDRB2 DDRB1 DDRB0

0 0 0
U=
Unaffected
igure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
 Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0006 Unimplemented UnimplementedPort A Input Pullup Enable Register (PTAPUE)See page 99.Port B Input Pullup Enable Register

$000A
$000B
$000C
$000D

$0019

OSC2EN 0 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Read:
Write:
Reset: 0 0 0 0 0
Read: PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3
Write:
Reset: 0 0 0 0 0

0 0 0 0 KEYF 0 IMASKK MODEK

ACKK
$001A Keyboard Status and ControlRead:
Register (KBSCR)See page 83.Keyboard Interrupt Enable Register (KBIER)See page 84.
$001B Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0

0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

$001C Unimplemented
0 0 0 0 IRQF 0 IMASK MODE
ACK
$001D IRQ Status and Control Register
Read: (INTSCR) See page 77.Configuration Register 2(CONFIG2)(1)See page 53.
$001E Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0 (2)
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN

COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD

$001F Configuration Register 1 Read:

$0020 (CONFIG1)(1) Write:
$0021 See page 54. Reset: 0 0 0 0 0 (2) 0 0 0
TIM Status and Control 1. One-time writable register after each reset.
Register (TSC) See page 2. LVI5OR3 reset to 0 by a power-on reset (POR) only.
127.
TIM Counter Register
High
(TCNTH)
See page 128.

TOF TOIE TSTOP 0 0 PS2 PS1 PS0

0 TRST
Read:
Write:
Reset: 0 0 1 0 0
Read: Bit 15 Bit 14 Bi t 13 Bit 12 Bit 11
Write:
Reset: 0 0 0 0 0
= R =
Unimplemente Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
d
 1 Bit 0

B Input Pullup Enable Register (PTBPUE) See page 102.Unimplemented

0 0 0
PTBPUE2 PTBPUE1 PTBPUE0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0 (2)
0 0 0

0 0 0
Bit 10 B it 9 Bit 8

0 0 0
U=
Unaffected
f 5)
 Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0022 TIM Counter Register Low(TCNTL)See

Read: page 128.TIM Counter Modulo Register High (TMODH)See page 129.TIM Counter Mo
$0023 Write:
$0024 Reset: 0 0 0 0 0 0 0 0
$0025 Read:
$0026 Write:
$0027 Reset: 1 1 1 1 1 1 1 1
$0028 Read:
$0029 Write:
$002A Reset: 1 1 1 1 1 1 1 1
$002B Read:
 Write:
$0035 Reset: 0 0 0 0 0 0 0 0
$0036 Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 0 0 0 0 0 0 0 0

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CH1F CH1IE 0 MS1A ELS1B ELS1A TOV1 CH1MAX

0
 Read:
Write:
Reset: 0 0 0 0 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
Write:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

R R R R R R ECGON ECGST

$0037 Unimplemented Read:

TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0

$0038 Oscillator Trim Register(OSCTRIM)See

Read: page 96.
Write:
Reset: 1 0 0 0 0 0 0 0

R
= Unimplemented = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
 1 Bit 0

0 0 0

1 1 1

1 1 1

0 0 0

eset

eset
eset

eset

0 0 0
 0 0 0
Bit 10 Bit 9 Bit 8

0 0 0

U = Unaffected
f 5)
 Addr. Register Name Bit 7 6 5 4 3
$0039 Unimplemented

$003B

COCO AIEN ADCO CH4 CH3 CH2 CH1 CH0

R
$003C ADC Status and ControlRead:
Register (ADSCR) See page 45.
Write:
Reset: 0 0 0 1 1 1 1 1

$003D Unimplemented
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$003E ADC Data Register Read:

$003F (ADR) Write:
$FE00 See page 47. Reset: Indeterminate after reset
$FE01 ADC Input Clock
$FE02 Register
$FE03 (ADICLK)
$FE04 See page 47.
$FE05 Break Status Register
$FE06 (BSR)
See page 137.
SIM Reset Status
Register
(SRSR)
See page 117.
Break Auxiliary Register
(BRKAR) See page 137.
Break Flag Control
Register (BFCR) See
page 138.
Interrupt Status
Register 1
(INT1)
See page 77.
Interrupt Status
Register 2
(INT2)
See page 77.
Interrupt Status
Register 3
(INT3)
See page 77.

ADIV2 ADIV1 ADIV0 0 0 0 0 0

Read:
Write:
Reset: 0 0 0 0 0
Read:
Write:
 Reset:
1. Writing a 0 clears SBSW.

Read: POR PIN COP ILOP ILAD

Write:
POR: 1 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0
Read: BCFE R R R R
Write:
Reset: 0
Read: 0 IF5 IF4 IF3 0
Write: R R R R R
Reset: 0 0 0 0 0
Read: IF14 0 0 0 0
Write: R R R R R
Reset: 0 0 0 0 0
Read: 0 0 0 0 0
Write: R R R R R
Reset: 0 0 0 0 0
R R R R R R SBSW R
See note
0 0 0 0 0 0 1
0 BDCOP

R R R R R R R R
$FE07 Reserved

R
= Unimplemented = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
 2 1 Bit 0

1 1 1

eset

0 0 0
 0

MODRST LVI 0

0 0 0

0 0 0
R R R

IF1 0 0
R R R
0 0 0
0 0 0
R R R
0 0 0
0 0 IF15
R R R
0 0 0

U = Unaffected
f 5)
 Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 HVEN MASS ERASE PGM

$FE08 FLASH Control Register(FLCR)See

Read: page 33.Break Address High Register (BRKH) See page 136.Break Address low Register (B
$FE09 Write:
$FE0A Reset: 0 0 0 0 0 0 0 0
$FE0B Read:
$FE0C Write:
$FE0D Reset: 0 0 0 0 0 0 0 0
 Read:
$FE0F Write:
$FFBE Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Unaffected by reset

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BRKE BRKA 0 0 0 0 0 0

LVIOUT 0 0 0 0 0 0 R

R R R R R R R R

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

R R R R R R R R
$FFBF Reserved
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0

$FFC0 Internal Oscillator Trim Read:

Value (Optional) Write:
$FFC1 Reserved Reset: Unaffected by reset
 R R R R R R R R
LOWBYTE OF RESET VECTOR
WRITING CLEARS COP COUNTER (ANY VALUE)
$FFFF COP Control Register(COPCTL)See
Read: page 59.
Write:
Reset: Unaffected by reset

R
= Unimplemented = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
 3 2 1 Bit 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

Unaffected by reset

Unaffected by reset
Unaffected by reset

= Reserved U = Unaffected
gisters (Sheet 5 of 5)
 Table 2-1. Vect or Addresses
.

Vector Priority Vector Address Vector

Lowest IF15 $FFDE ADC conversion complete vector (high)
Highest
$FFDF ADC conversion complete vector (low)
IF14 $FFE0 Keyboard vector (high)
$FFE1 Keyboard vector (low)
IF13 — Not used

IF6

IF5 $FFF2 TIM overflow vector (high)

$FFF3 TIM overflow vector (low)
IF4 $FFF4 TIM Channel 1 vector (high)
$FFF5 TIM Channel 1 vector (low)
IF3 $FFF6 TIM Channel 0 vector (high)
$FFF7 TIM Channel 0 vector (low)
IF2 — Not used
IF1 $FFFA IRQ vector (high)
$FFFB IRQ vector (low)
— $FFFC SWI vector (high)
$FFFD SWI vector (low)
— $FFFE Reset vector (high)
$FFFF Reset vector (low)

2.5 Random-Access Memory (RAM)

Addresses $0080–$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bi
stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save th
contents of the CPU registers.

NOTE
For M6805, M146805, and M68HC05 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack po
decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during th
interrupt stacking operation.
2.6 FLASH Memory (FLASH)
This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be
programmed, and erased from a single external supply. The program and erase operations are enable
through the use of an internal charge pump.
The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user ve
The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH
memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operation
facilitated through control bits in the FLASH control register (FLCR). Details for these operations appea
later in this section. The address ranges for the user memory and vectors are:
• $EE00 – $FDFF; user memory, 4096 bytes: MC68HC908QY4 and MC68HC908QT4
• $F800 – $FDFF; user memory, 1536 bytes: MC68HC908QY2, MC68HC908QT2, MC68HC908QY1 an
MC68HC908QT1
• $FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE
An erased bit reads as a 1 and a programmed bit reads as a 0. A security feature prevents viewing of the FLASH co
(1)

2.6.1 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase operations.
Address: $FE08
Bit 7 6 5 4 3 2 1 Bit 0
RAM is programmable. The 16-bit
y space.

five bytes of the stack to save the

d.
the return address. The stack pointer

RAM during a subroutine or during the

mory. The FLASH memory can be read,
and erase operations are enabled

n additional 48 bytes for user vectors.

and the maximum size of FLASH
w). Program and erase operations are
etails for these operations appear
tors are:
MC68HC908QT4
8HC908QT2, MC68HC908QY1 and

re prevents viewing of the FLASH contents.

operations.
 0 0 0 0 HVEN MASS ERASE PGM

Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or e
operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for program or er
followed.
1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge
pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass erase operation selected
0 = Mass erase operation unselected

1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficu
unauthorized users.
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit s
that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE b
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.6.2 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive byt
starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also
forms a page. Any FLASH memory page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block to be erased.
4. Wait for a time, tNVS (minimum 10 s).
5. Set the HVEN bit.
6. Wait for a time, tErase (minimum 1 ms or 4 ms).
7. Clear the ERASE bit.
8. Wait for a time, tNVH (minimum 5 s).
9. Clear the HVEN bit.
10. After time, tRCV (typical 1 s), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memo
While these operations must be performed in the order as shown, but other unrelated operations
may occur between the steps.

CAUTION
A page erase of the vector page will erase the internal oscillator trim value at $FFC0.
In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specificat
get improved long-term reliability. Any application can use this 4 ms page erase specification. Howeve
applications where a FLASH location will be erased and reprogrammed less than 1000 times, and
speed is important, use the 1 ms page erase specification to get a shorter cycle time.

2.6.3 FLASH Mass Erase Operation

Use the following procedure to erase the entire FLASH memory to read as a 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address(1) within the FLASH memory address range.
4. Wait for a time, tNVS (minimum 10 s).
5. Set the HVEN bit.
6. Wait for a time, tMErase (minimum 4 ms).
7. Clear the ERASE and MASS bits.
NOTE
Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF).
8. Wait for a time, tNVHL (minimum 100 s).
9. Clear the HVEN bit.
10. After time, tRCV (typical 1 s), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memo
While these operations must be performed in the order as shown, but other unrelated operations may occur between
steps.

CAUTIONA mass erase will erase the internal oscillator trim value at $FFC0.2.6.4 FLASH Program OperationProgramming of the FLASH

1. When in monitor mode, with security sequence failed (see 15.3.2 Security), write to the FLASH block protect register in
of any FLASH address.
2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing P
must not exceed the maximum programming time, tPROG maximum.
8. Wait for time, tPROG (minimum 30 s).
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
10. Clear the PGM bit(1).
11. Wait for time, tNVH (minimum 5 s).
12. Clear the HVEN bit.
13. After time, tRCV (typical 1 s), the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between steps 5–12, when the HVEN bit is set. Since this
register is located at a
valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memo
While these operations must be performed in the order shown, other unrelated operations may occur between the st
Do not exceed tPROG maximum, see 16.16
Memory Characteristics.
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the targe
application, provision is made to protect blocks of memory from unintentional erase or program opera
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). T
FLBPR determines the range of the FLASH memory which is to be protected. The range of the protecte
area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). W
the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
operations.

NOTE
In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or
ERASE bit and before asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are sh
in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass e
is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erase
programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also
allows entry from reset into the monitor mode.
0 0

to the memory for either program or erase

the proper sequence for program or erase is

gh voltage disabled to array and charge

ation.

is to make reading or copying the FLASH difficult for

 ERASE is interlocked with the PGM bit such
e.

on. PGM is interlocked with the ERASE bit

e time.

. A page consists of 64 consecutive bytes

48-byte user interrupt vectors area also

trol register.

ange of the block to be erased.

d in read mode again.

code being executed from the FLASH memory.

her unrelated operations

ue at $FFC0.
les, use the 4 ms page erase specification to
4 ms page erase specification. However, in
ammed less than 1000 times, and
et a shorter cycle time.

ry to read as a 1:
ntrol register.

memory address range.

not equal $FF).

d in read mode again.

code being executed from the FLASH memory.

her unrelated operations may occur between the

ASH Program OperationProgramming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX

ity), write to the FLASH block protect register instead

e last FLASH address programmed to clearing PGM bit,

are programmed.

d in read mode again.

s 5–12, when the HVEN bit is set. Since this

s written while HVEN is set.

til all data is programmed.

code being executed from the FLASH memory.

related operations may occur between the steps.

ogram the FLASH memory in the target

m unintentional erase or program operations
FLASH block protect register (FLBPR). The
be protected. The range of the protected
ottom of the FLASH memory ($FFFF). When
ERASE or PROGRAM

gister must be read after setting the PGM or

y is protected from being programmed and

y is accessible for program and erase.
of memory. The address ranges are shown
ammed with a value other than
of FLASH memory is prohibited. Mass erase
qual $FF). The FLBPR itself can be erased or
IRQ pin. This voltage also
 Algorithm for Programming 1

a Row (32 Bytes) of FLASH Memory

READ THE FLASH BLOCK PROTECT
REGISTER

2
WRITE ANY DATA TOANY FLASH ADDRESS
WITHIN THE ROWADDRESS RANGE
DESIRED
3
WAIT FOR A TIME, tNVS

4
SET HVEN BIT

5
WAIT FOR A TIME, tPGS
7
6
WRITE DATA TOTHE FLASH ADDRESS TO
BE PROGRAMMED

8
WAIT FOR A TIME, tPROG

10
11
NOTES: COMPLETED 12

9 PROGRAMMIN
The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programm
to clearing PGM bitG(step
THIS 7 to step 10) 13
ROW?
must not exceed the maximum programming time, tPROG max.
This row program algorithm assumes the row/s to be programmed are initially erased.
N

CLEAR PGM BIT

WAIT FOR A TIME, tNVH

CLEAR HVEN BIT

WAIT FOR A TIME, tRCV

Figure 2-4. FLASH Programming Flowchart

ming 1 SET PGM BIT
ASH Memory

12
Y
FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed
p 7 to step 10) 13

aximum programming time, tPROG max.

thm assumes the row/s to be programmed are initially erased.

END OF PROGRAMMING

Figure 2-4. FLASH Programming Flowchart

2.6.6 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore c
only be written during a programming sequence of the FLASH memory. The value in this register
determines the starting address of the protected range within the FLASH memory.
Address: $FFBE
Bit 7 6 5 4 3 2 1 Bit 0
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Read:Write:Reset: Unaffected by reset. Initial value fromfactory is 1.Write to this register is by a programming seque

16-BIT MEMORY ADDRESS

START ADDRESS OF FLASH 1BLOCK PROTECT FLBPR 0 0 0 0 0
1 VALUE 0
Figure 2-6. FLASH Block Protect Start Address
Table 2-2. Examples of Protect Start Address
BPR[7:0] Start of Address of Protect Range
$00–$B8 The entire FLASH memory is protected.
$B9 (1011 1001) $EE40 (1110 1110 0100 0000)
$BA (1011 1010) $EE80 (1110 1110 1000 0000)
$BB (1011 1011) $EEC0 (1110 1110 1100 0000)
$BC (1011 1100) $EF00 (1110 1111 0000 0000)
and so on...
$DE (1101 1110) $F780 (1111 0111 1000 0000)
$DF (1101 1111) $F7C0 (1111 0111 1100 0000)
$FE (1111 1110) $FF80 (1111 1111 1000 0000)
FLBPR, OSCTRIM, and vectors are protected
$FF The entire FLASH memory is not protected.
2.6.7 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the FL
or the operation will discontinue and the FLASH will be on standby mode.
2.6.8 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the FL
or the operation will discontinue and the FLASH will be on standby mode
NOTE
Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are
inactive and the current consumption of the FLASH is at a minimum.

Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-to
digital converter. The ADC module is only available on the MC68HC908QY2, MC68HC908QT2,
MC68HC908QY4, and MC68HC908QT4.

3.2 Features
Features of the ADC module include:
• 4 channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock frequency
3.3 Functional DescriptionFour ADC channels are available for sampling external sources at pins PTA0, PTA1, PTA4, and PTA5. An ana
 FLASH memory, and therefore can
y. The value in this register
ASH memory.

Bit 0

te to this register is by a programming sequence to the FLASH memory.Figure 2-5. FLASH Block Protect Register (FLBPR)BPR[7:0] — FLASH Protec

0 0 0 0

ddress
ddress
s not affect the operation of the
ce the CPU is inactive.
ram or erase operation on the FLASH,
ode.

s not affect the operation of the

ce the CPU is inactive.
ram or erase operation on the FLASH,
ode

rnal control signals to the FLASH are

C is an 8-bit, 4-channel analog-to-

908QY2, MC68HC908QT2,
pins PTA0, PTA1, PTA4, and PTA5. An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC voltage i
 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

CLOCK GENERATOR
(OSCILLATOR)
DDRA
PTA

M68HC08 CPU

SYSTEM INTEGRATION
MODULE

SINGLE INTERRUPT
MODULE

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

DDRB
PTB

BREAK MODULE

POWER-ON RESET
MODULE

MC68HC908QY4 AND MC68HC908QT4

4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH

KEYBOARD INTERRUPT
MODULE
 8-BIT ADC

16-BIT TIMER
MODULE

128 BYTES RAM

COP MODULE

POWER SUPPLY

MONITOR ROM

RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 3-1. Block Diagram Highlighting ADC Block and Pins
TA1/AD1/TCH1/KBI1
CLK PTA3/RST/KBI3
TA4/OSC2/AD2/KBI4
TA5/OSC1/AD3/KBI5

PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

 RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
able on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 3-1. Block Diagram Highlighting ADC Block and Pins

VD
D

VSS
 DATA Functional Descrip
BUS
INTERNAL
DDRAx READ
DDRA

DISABL
WRITE E
PTAx
DDRA
RESET
ADCx
WRITE
PTA

READ
PTA

DISABL
E
ADC
ADC DATA REGISTER CHANNEL x

ADC

CONVERSION A CH[4:0]
COMPLETE D
C

V
O
ADC CLOCK
L
AIEN COCO T
A
CHANNEL SELECT
(1 OF 4 CHANNELS)

INTERRUPT
LOGIC

CLOCK
GENERATOR

BUS CLOCK

ADIV[2:0]
Figure 3-2. ADC Block Diagram
 3.3.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the in
voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line lin
conversion. All other input voltages will result in $FF if greater than V DD and $00 if less than VSS.
NOTE
Input voltage should not exceed the analog supply voltages.
3.3.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on
first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC inte
clock is selected to run at 1 MHz, then one conversion will take 16 s to complete. With a 1-MHz AD
internal clock the maximum sample rate is 62.5 kHz.
16 ADC Clock Cycles

Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time  Bus Frequency
3.3.4 Continuous Conversion
In the continuous conversion mode (ADCO = 1), the ADC continuously converts the selected channe
filling the ADC data register (ADR) with new data after each conversion. Data from the previous
conversion will be overwritten whether that data has been read or not. Conversions will continue unt
the ADCO bit is cleared. The COCO bit (ADSCR, $003C) is set after each conversion and will stay set
the next read of the ADC data register.
When a conversion is in process and the ADSCR is written, the current conversion data should be
discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.

3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a central processor unit (CPU)
interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO
not used as a conversion complete flag when interrupts are enabled.

3.5 Low-Power Modes

The following subsections describe the ADC in low-power modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the
can bring the microcontroller unit (MCU) out of wait mode. If the ADC is not required to bring the MC
out of wait mode, power down the ADC by setting the CH[4:0] bits in ADSCR to 1s before executing t
WAIT instruction.

Input/Output Signals
3.5.2 Stop Mode
 Functional Description

ADCx

CHANNEL x
F (full scale). If the input
are a straight-line linear
$00 if less than VSS.

arts a conversion on the

DSCR. If the ADC internal
ete. With a 1-MHz ADC

the selected channel

om the previous
ons will continue until
ion and will stay set until

on data should be

cessor unit (CPU)

it is at 0. The COCO bit is

upt request from the ADC

uired to bring the MCU
1s before executing the
 The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is abo
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before using ADC data after exiting stop mode.
3.6 Input/Output Signals
The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC m

3.7 Input/Output Registers

These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
3.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register (ADSCR). When
conversion is in process and the ADSCR is written, the current conversion data should be discarded to
prevent an incorrect reading.

Address: $003C
Bit 7 6 5 4 3 2 1 Bit 0
COCO AIEN ADCO CH4 CH3 CH2 CH1 CH0
R
Read:
Write:
Reset: 0 0 0 1 1 1 1 1
= Reserved
Figure 3-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. CO
will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It alwa
reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR register, always have a 0 in the COCO b
position.

R
ruction. Any pending conversion is aborted.
w one conversion cycle to stabilize the
e.

ort A.
of the four ADC channels to the ADC module.

us and control register (ADSCR). When a

conversion data should be discarded to

1 Bit 0

1 1

is set at the end of each conversion. COCO

eset clears this bit.
t set at the end of a conversion. It always

bled (AIEN = 1)

SCR register, always have a 0 in the COCO bit

AIEN — ADC Interrupt Enable BitWhen this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cle

CH4 CH3 CH2 CH1 CH0 ADC Input Select

Channel
0 0 0 0 0 ADC0 PTA0
0 0 0 0 1 ADC1 PTA1
0 0 0 1 0 ADC2 PTA4
0 0 0 1 1 ADC3 PTA5
0 0 1 0 0 — Unused(1)
     —
1 1 0 1 0 —
1 1 0 1 1 — Reserved
1 1 1 0 0 — Unused
1 1 1 0 1 — (2)
V
DDA
1 1 1 1 0 — (2)
V
SSA
1 1 1 1 1 — ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes, as specified in the table, are used to ve
the operation of the ADC converter both in produc- tion test and for user applications.
d at the end of an ADC conversion. The interrupt signal is cleared when ADR is read or ADSCR is written. Reset clears the AIEN bit.1 = ADC interrupt e

ulting ADC conversion will be unknown.

erence nodes, as specified in the table, are used to verify
duc- tion test and for user applications.
Input/Output Registers
3.7.2 ADC Data Register

One 8-bit result register is provided. This register is updated each time an ADC conversion complete
Address: $003E
Bit 7 6 5 4 3 2 1 Bit 0
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Read:
Write:
Reset: Indeterminate after reset
= Unimplemented
Figure 3-4. ADC Data Register (ADR)
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.

Address: $003F
Bit 7 6 5 4 3 2 1 Bit 0
ADIV2 ADIV1 ADIV0 0 0 0 0 0

Read:Write:Reset: 0 0 0 0 0 0 0 0= UnimplementedFigure 3-5. ADC Input

Table 3-2. ADC Clock Divide Ratio

ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 Bus clock ÷ 1
0 0 1 Bus clock ÷ 2
0 1 0 Bus clock ÷ 4
0 1 1 Bus clock ÷ 8
1 X X Bus clock ÷ 16
X = don’t care

Chapter 4
Auto Wakeup Module (AWU)
 4.1 IntroductionThis section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wak

4.2 Features
Features of the auto wakeup module include:
• One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt v
and keyboard interrupt mask bit
• Exit from low-power stop mode without external signals
• Selectable timeout periods
• Dedicated low-power internal oscillator separate from the main system clock sources

4.3 Functional DescriptionThe function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (M
each time an ADC conversion completes.

1 Bit 0

1 Bit 0

0 0= UnimplementedFigure 3-5. ADC Input Clock Register (ADICLK)ADIV2–ADIV0 — ADC Clock Prescaler BitsADIV2, ADIV1, and ADI

de Ratio
generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the AWU.

sharing the same keyboard interrupt vector

e main system clock sources

ic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, wit
 COPRS (FROM CONFIG1) V
DD TO
PTA
REA
D,
D
BIT Q
6
AW
E
UL
AW R
UIRE
Q
TO
AUTOWUGEN KBI

SHORT 1 = DIV
29
0 = DIV
INT RC OSC OVERFLOW
214
CLK RST

EN 32
kHz

CLRLOGIC
CLEAR

CLK
RST

RESET

(CGMXCLK) BUSCLKX4 R
E
S
I E
S T
T A
O C
P K
K
RESET
AWUIE
Figure 4-1. Auto Wakeup Interrupt Request Generation LogicThe auto wakeup RC oscillator is highly dependent on operating voltage and te

4.4 Wait Mode

The AWU module remains inactive in wait mode.

4.5 Stop Mode

When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activat
automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control
register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters
start from ‘0’ each time stop mode is entered.
hly dependent on operating voltage and temperature. This feature is not recommended for use as a time-keeping function.The wakeup request is latched to

pt enable register) it is activated

e keyboard status and control
top mode. The AWU counters
 Input/Output Registers
4.6 Input/Output Registers
The AWU shares registers with the keyboard interrupt (KBI) module and the port A I/O module. The
following I/O registers control and monitor operation of the AWU:
• Port A data register (PTA)
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
4.6.1 Port A I/O Register
The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in add
to the data latches for port A.

Address: $0000
Bit 7 6 5 4 3 2 1 Bit 0
0 AWUL PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

Read:
Write:
Reset: 0 0 Unaffected by reset
= Unimplemented
Figure 4-2. Port A Data Register (PTA)

AWUL — Auto Wakeup Latch

This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup req
signal is generated internally. There is no PTA6 port or any of the associated bits such as PTA6 data
direction or pullup bits.
1 = Auto wakeup interrupt request is pending
0 = Auto wakeup interrupt request is not pending
NOTE
PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 12.
Port A Data Register.
4.6.2 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
• Flags keyboard/auto wakeup interrupt requests
• Acknowledges keyboard/auto wakeup interrupt requests
• Masks keyboard/auto wakeup interrupt requests

Address: $001A
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 KEYF 0 IMASKK MODEK
ACKK
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 4-3. Keyboard Status and Control Register (KBSCR)
 Input/Output Registers

module and the port A I/O module. The

WU:

ate of the AWU interrupt request, in addition

1 Bit 0

Unaffected by reset

ster (PTA)

interrupt request latch. The wakeup request

he associated bits such as PTA6 data

e. To see a description of these bits, see 12.2.1

1 Bit 0

0 0 0 0

ol Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears
KEYF bit.
1 = Keyboard/auto wakeup interrupt pending
0 = No keyboard/auto wakeup interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto
wakeup logic. ACKK always reads as 0.Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard/auto wakeup interrupt requests masked
0 = Keyboard/auto wakeup interrupt requests not masked
NOTE
MODEK is not used in conjuction with the auto wakeup feature. To see a description of this bit, see 9.7.1 Keyboard
Status and Control Register.
4.6.3 Keyboard Interrupt Enable Register
The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a
keyboard/auto wakeup interrupt input.

Address: $001B
Bit 7 6 5 4 3 2
Read:
Write:
Reset: 0 0 0 0 0 0
= Unimplemented
0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

Figure 4-4. Keyboard Interrupt Enable Register (KBIER) AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears
AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE
KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 9
Keyboard Interrupt Enable Register.
uto wakeup. Reset clears the

equest on port A and auto

pt mask from generating

this bit, see 9.7.1 Keyboard

wakeup to operate as a

1 Bit 0

0 0

nterrupt Enable Bit

requests. Reset clears

escription of these bits, see 9.7.2

 Chapter 5
Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registe
enable or disable the following options:
• Stop mode recovery time (32  BUSCLKX4 cycles or 4096  BUSCLKX4 cycles)
• STOP instruction
• Computer operating properly module (COP)
• COP reset period (COPRS): 8176  BUSCLKX4 or 262,128  BUSCLKX4
• Low-voltage inhibit (LVI) enable and trip voltage selection
• OSC option selection
• IRQ pin
• RST pin
• Auto wakeup timeout period

5.2 Functional Description

The configuration registers are used in the initialization of various options. The configuration register
be written once after each reset. Most of the configuration register bits are cleared during reset. Sinc
various options affect the operation of the microcontroller unit (MCU) it is recommended that this reg
be written immediately after reset. The configuration registers are located at $001E and $001F, and
be read at anytime.

NOTEThe CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined

Address: $001E

Bit 7 6 5 4 3 2
Read: IRQPUD IRQEN R OSCOPT1 OSCOPT0 R
Write:

Reset: 0 0 0 0 0 0
POR: 0 0 0 0 0 0
R = U=
Reserved Unaffected
Figure 5-1. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin 0 = Interrupt request function inactive in pin
OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option
(0, 0) Internal oscillator
(0, 1) External oscillator
(1, 0) External RC oscillator
(1, 1) External XTAL oscillator
RSTEN — RST Pin Function Selection
1 = Reset function active in pin 0 = Reset function inactive in pin
The configuration registers

cycles)

he configuration registers can

cleared during reset. Since the
commended that this register
t $001E and $001F, and may

registers default to predetermined settings as shown in Figure 5-1 and Figure 5-2.

1 Bit 0
R RSTEN

0 U
0 0
ctive in pin
NOTE
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected.

Address: $001F

Bit 7 6 5 4 3 2
Read: LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC
COPRS
Write:
Reset: 0 0 0 0 U 0
POR: 0 0 0 0 0 0
U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1) COPRS (Out of STOP Mode) — COP Reset Period Selection
1 = COP reset short cycle = 8176  BUSCLKX4
0 = COP reset long cycle = 262,128  BUSCLKX4
COPRS (In STOP Mode) — Auto Wakeup Period Selection Bit
1 = Auto wakeup short cycle = 512  INTRCOSC
0 = Auto wakeup long cycle = 16,384  INTRCOSC
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. R
clears LVISTOP.
1 = LVI enabled during stop mode 0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled 0 = LVI module resets enabled

Functional Desc
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit

LVI5OR3 selects the voltage operating mode of the LVI module. The voltage mode selected for the
should match the operating VDD for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
NOTE
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSC
cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4 cycles
gives a delay longer than the LVI enable time for these startup scenarios. There is no period where th
MCU is not protected from a low-power condition. However, when using the short stop recovery
configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to avoid a p
in startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled 0 = COP module enabled
it unaffected.

1 Bit 0
STOP COPD

0 0
0 0

OP Reset Period Selection Bit

erate during stop mode. Reset

Functional Description

module power enabled

ge mode selected for the LVI

the modes.
 bit unaffected.

es instead of a 4096 BUSCLKX4

h 4096 BUSCLKX4 cycles)

ere is no period where the
short stop recovery
turn on time to avoid a period
 Chapter 6
Computer Operating Properly (COP)
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a res
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP rese
clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
configuration 1 (CONFIG1) register.

6.2 Functional Description

RESET CIRCUIT
BUSCLKX4
12-BIT SIM COUNTER
RESET STATUS REGISTER
C
STOP INSTRUCTION L
INTERNAL RESET SOURCES E
A
COPCTL WRITE
R
COP CLOCK
6-BIT COP COUNTER
COPEN (FROM SIM) COP DISABLE (COPD C
FROM CONFIG1) O
RESET COPCTL WRITE P

C
COP RATE SELECT (COPRS O
FROM CONFIG1) U
N
T
Figure 6-1.
COP Block Diagram
E
R
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SI
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset a
262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscill
gives a COP timeout period of 20.48 ms. Writing any value to location $FFFF before an overflow occur
prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum t
before the first COP counter overflow.
A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32  BUSCLKX4
cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register.
NOTE
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine
keep the COP from generating a reset even while the main program is not working properly.
6.3 I/O SignalsThe following paragraphs describe the signals shown in Figure 6-1.6.3.1 BUSCLKX4BUSCLKX4 is the oscillator output si

COP Control Register

6.3.7 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1

6.4 COP Control Register

The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing
value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF retur
the low byte of the reset vector.

Address: $FFFF
Bit 7 6 5 4 3 2 1 Bit 0
LOWBYTE OF RESET VECTOR
CLEAR COP COUNTER
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
 6.5 Interrupts
The COP does not generate CPU interrupt requests.

6.6 Monitor Mode

The COP is disabled in monitor mode when VTST is present on the IRQ pin.
6.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodica
clear the COP counter.
6.7.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after ent
or exiting stop mode.

6.8 COP Module During Break Mode

The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxi
register (BRKAR).

Chapter 7
Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version o
M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a descrip
of the CPU instruction set, addressing modes, and architecture.
7.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes

7.3 CPU Registers

Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
ee-running counter that generates a reset if
from runaway code. Prevent a COP reset by
e disabled through the COPD bit in the

ram
he 12-bit system integration module (SIM)
and generates an asynchronous reset after
the COP rate select bit, COPRS, in
flow option, the internal 12.8-MHz oscillator
ocation $FFFF before an overflow occurs
12–5 of the SIM counter.

iting stop mode to guarantee the maximum time

CONFIG1 register) for 32  BUSCLKX4

See 13.8.1 SIM Reset Status Register.

rupt subroutine. Such an interrupt subroutine could

not working properly.
 1 BUSCLKX4BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the internal oscillator frequency, the crystal frequency, or th

(COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register (CONFIG).

F and overlaps the reset vector. Writing any

out period. Reading location $FFFF returns

1 Bit 0

Unaffected by reset
er (COPCTL)
he IRQ pin.

nsumption standby modes.

a COP reset during wait mode, periodically

rs the SIM counter. Service the COP

sure a full COP timeout period after entering

de when BDCOP bit is set in break auxiliary

fully object-code-compatible version of the

umber CPU08RM/AD) contains a description
.
ily

tions

tor
ructions

tion for extension of addressing range

t part of the memory map.

 7 0 ACCUMULATOR (A) INDEX REGISTER (H:X) STACK POINTER (S
15 0 PROGRAM COUNTER (PC)
15 0 CONDITION CODE REGISTER (CCR)
15 0
7 0

V 1 1 H I N Z
H X C

CARRY/BORROWFLAG ZERO FLAG

NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOWFLAG
Figure 7-1. CPU Registers

7.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands
and the results of arithmetic/logic operations.
Bit 7 6 5 4 3 2 1 Bit 0

Read:
Write:
Reset: Unaffected by reset
Figure 7-2. Accumulator (A)

7.3.2 Index Register

The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byt
of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.

Bit 15
14 13 12 11 10 9 8 7 6 5 4 3 2

Read:
Write:

Reset: 0 0 0 0 0 0 0 0 X X X X X X
X = Indeterminate
Figure 7-3. Index Register (H:X)
ER (H:X) STACK POINTER (SP)

tor to hold operands

e. H is the upper byte

ex register.
r to determine the

Bit
1 0

X X
CPU Registers
7.3.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location on the stack. Durin
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as
data is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as
index register to access data on the stack. The CPU uses the contents of the stack pointer to determin
the conditional address of the operand.

Bit 15
14 13 12 11 10 9 8 7 6 5 4 3 2

Read:
Write:

Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Figure 7-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the
out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM location
7.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand t
be fetched.
Normally, the program counter automatically increments to the next sequential memory location ever
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF
The vector address is the address of the first instruction to be executed after exiting the reset state.

Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read: Write:

Reset: Loaded with vector from$FFFE and $FFFF

Figure 7-5. Program Counter (PC)
 on the stack. During a
n sets the least
nter decrements as

er can function as an
pointer to determine

Bit
1 0

1 1

ry (RAM). Moving the SP

t only to RAM locations.

uction or operand to

emory location every

oad the program

at $FFFE and $FFFF.

ng the reset state.

it
0

F
 7.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results o
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe t
functions of the condition code register.
Bit 7 6 5 4 3 2 1 Bit 0

V 1 1 H I N Z C

Read:
Write:
Reset: X 1 1 X 1 X X X
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)

V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instruc
BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ad
without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automati
after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled

NOTE
To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the
interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interru
mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result

Arithmetic/Logic Unit (ALU)

Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produ
result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit tes
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7

7.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.

7.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
7.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. Afte
from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.

7.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the
to normal operation if the break interrupt has been deasserted.

7.7 Instruction Set SummaryTable 7-1 provides a summary of the M68HC08 instruction set.Table 7-1. Instruction Set Summary (Sheet 1
and five flags that indicate the results of the
1. The following paragraphs describe the

Bit 0

1 X X X

gister (CCR)

rflow occurs. The signed branch instructions

accumulator bits 3 and 4 during an add-

alf-carry flag is required for
nstruction uses the states of the H and C

re disabled. CPU interrupts are enabled

urs, the interrupt mask is set automatically
interrupt vector is fetched.

ister (H) is not stacked automatically. If the

ck H using the PSHH and PULH instructions.
s serviced first.
from the stack and restores the interrupt
and can be cleared only by the clear

ogic operation, or data manipulation

c operation, or data manipulation produces a

n produces a carry out of bit 7 of the

w. Some instructions — such as bit test and
flag.

by the instruction set.

CPU08RM/AD) for a description of the
architecture of the CPU.

nsumption standby modes.

ister, enabling interrupts. After exit from

eset, the I bit is set.

ister, enabling external interrupts. After exit

After exit by reset, the I bit is set.

he oscillator stabilization delay.

ak interrupt by:

FEFC:$FEFD in monitor mode

ction in progress. If the break address
he break interrupt begins immediately.
ends the break interrupt and returns the MCU
d.

ction set.Table 7-1. Instruction Set Summary (Sheet 1 of 6)

 Source Form Operation Description Effect on

Address
CCR
V I N Z C
H
ADC #opr ADC opr ⭥ ⭥ ⭥ ⭥ ⭥ IMM DIR
ADC opr ADC EXT IX2
opr,X ADC opr,X IX1 IX
ADC ,X SP1 SP2
ADC opr,SP ADC Add with Carry A  (A) + (M) + (C) –
opr,SP

ADD #opr ADD ⭥ ⭥ ⭥ ⭥ ⭥ IMM DIR

opr ADD opr ADD EXT IX2
opr,X ADD opr,X IX1 IX
ADD ,X SP1 SP2
ADD opr,SP ADD Add without Carry A  (A) + (M) –
opr,SP

AIS #opr Add Immediate Value (Signed) to SP SP  (SP) + (16 « M) – – – – – – IMM

AIX #opr Add Immediate Value (Signed) to H:X  (H:X) + (16 « M) – – – – – – IMM
H:X
AND #opr AND opr ⭥ ⭥ IMM DIR
AND opr AND EXT IX2
opr,X AND opr,X IX1 IX
AND ,X SP1 SP2
AND opr,SP AND Logical AND A  (A) & (M) 0 – – –
opr,SP

ASL opr ASLA Arithmetic Shift Left (Same as LSL) DIR INH
ASLX INH IX1
ASL opr,X ASL ,X IX SP1
ASL opr,SP ⭥ – – ⭥ ⭥ ⭥
C 0
b7 b0

ASR opr ASRA C DIR INH

ASRX b7 b0 INH IX1
ASR opr,X ASR IX SP1
opr,X ASR opr,SP Arithmetic Shift Right ⭥ – – ⭥ ⭥ ⭥

BCC rel Branch if Carry Bit Clear PC  (PC) + 2 + rel ? (C) = 0 – – – – – – REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
BCLR n, opr Clear Bit n in M Mn  0 – – – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

BCS rel Branch if Carry Bit Set (Same as PC  (PC) + 2 + rel ? (C) = 1 – – – – – – REL
BEQ rel BLO)
Branch if Equal PC  (PC) + 2 + rel ? (Z) = 1 – – – – – – REL
BGE opr Branch if Greater Than or Equal To PC  (PC) + 2 + rel ? (N  V   – – – – – – REL
(Signed Operands)
BGT opr Branch if Greater Than (Signed PC  (PC) + 2 + rel ? (Z) | (N  V   – – – – – – REL
Operands)
BHCC rel Branch if Half Carry Bit Clear PC  (PC) + 2 + rel ? (H) = 0 – – – – – – REL
BHCS rel Branch if Half Carry Bit Set PC  (PC) + 2 + rel ? (H) = 1 – – – – – – REL
BHI rel Branch if Higher PC  (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL
 Operand
Opcode

Cycles
A9 B9 ii dd 2
C9 D9 hh ll 3
E9 F9 ee ff ff 4
9EE9 ff 4
9ED9 ee ff 3
2
4
5

AB BB ii dd 2
CB DB hh ll 3
EB FB ee ff ff 4
9EEB ff 4
9EDB ee ff 3
2
4
5

A7 ii 2
AF ii 2
A4 B4 ii dd 2
C4 D4 hh ll 3
E4 F4 ee ff ff 4
9EE4 ff 4
9ED4 ee ff 3
2
4
5

38 dd 4
48 ff ff 1
58 1
68 4
78 3
9E68 5

37 dd 4
47 ff ff 1
57 1
67 4
77 3
9E67 5

24 rr 3
11 dd dd 4
13 dd dd 4
15 dd dd 4
17 dd dd 4
19 4
1B 4
1D 4
1F 4

25 rr 3
27 rr 3
90 rr 3

92 rr 3

28 rr 3
29 rr 3
22 rr 3
 Source Form Operation Description Effect on

Address
CCR
V I N Z C
H
BHS rel Branch if Higher or Same (Same as PC  (PC) + 2 + rel ? (C) = 0 – – – – – – REL
BCC)
BIH rel Branch if IRQ Pin High PC  (PC) + 2 + rel ? IRQ = 1 – – – – –
– REL
BIL rel Branch if IRQ Pin Low PC  (PC) + 2 + rel ? IRQ = 0 – – – – –
– REL
BIT #opr IMM
BIT opr DIR
BIT opr EXT
BIT opr,X BIT opr,X Bit Test (A) & (M) 0 – – ⭥ ⭥ – IX2 IX1

BIT ,X IX
BIT opr,SP SP1
BIT opr,SP SP2
BLE opr Branch if Less Than or Equal To PC  (PC) + 2 + rel ? (Z) | (N  V  1 – – – – – – REL
(Signed Operands)
BLO rel Branch if Lower (Same as BCS) PC  (PC) + 2 + rel ? (C) = 1 – – – – – – REL
BLS rel Branch if Lower or Same PC  (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL
BLT opr Branch if Less Than (Signed PC  (PC) + 2 + rel ? (N  V 1 – – – – – – REL
Operands)
BMC rel Branch if Interrupt Mask Clear PC  (PC) + 2 + rel ? (I) = 0 – – – – – – REL
BMI rel Branch if Minus PC  (PC) + 2 + rel ? (N) = 1 – – – – – – REL
BMS rel Branch if Interrupt Mask Set PC  (PC) + 2 + rel ? (I) = 1 – – – – – – REL
BNE rel Branch if Not Equal PC  (PC) + 2 + rel ? (Z) = 0 – – – – – – REL
BPL rel Branch if Plus PC  (PC) + 2 + rel ? (N) = 0 – – – – – – REL
BRA rel Branch Always PC  (PC) + 2 + rel – – – – – – REL
⭥ DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
BRCLR n,opr,rel Branch if Bit n in M Clear PC  (PC) + 3 + rel ? (Mn) = 0 – – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

BRN rel Branch Never PC  (PC) + 2 – – – – – – REL

⭥ DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
BRSET n,opr,rel Branch if Bit n in M Set PC  (PC) + 3 + rel ? (Mn) = 1 – – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
BSET n,opr Set Bit n in M Mn  1 – – – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

BSR rel Branch to Subroutine PC  (PC) + 2; push (PCL) SP  (SP) – 1; – – – – – – REL

push (PCH) SP  (SP) – 1
PC  (PC) + rel
CBEQ opr,rel Compare and Branch if Equal PC  (PC) + 3 + rel ? (A) – (M) = $00 – – – – – – DIR IMM
CBEQA #opr,rel PC  (PC) + 3 + rel ? (A) – (M) = $00 IMM
CBEQX #opr,rel PC  (PC) + 3 + rel ? (X) – (M) = $00 IX1+ IX+
CBEQ opr,X+,rel PC  (PC) + 3 + rel ? (A) – (M) = $00 SP1
CBEQ X+,rel PC  (PC) + 2 + rel ? (A) – (M) = $00
CBEQ opr,SP,rel PC  (PC) + 4 + rel ? (A) – (M) = $00

CLC Clear Carry Bit C0 – – – – – 0 INH

CLI Clear Interrupt Mask I0 – – 0 – – – INH
CLR opr M  $00 DIR
CLRA A  $00 INH
CLRX X  $00 INH
– – 0 1 – INH
CLRH Clear H  $00 0
CLR opr,X M  $00 IX1
CLR ,X M  $00 IX
CLR opr,SP M  $00 SP1
CMP #opr IMM
CMP opr DIR
CMP opr EXT
CMP opr,X CMP Compare A with M (A) – (M) ⭥ – – ⭥ ⭥ ⭥ IX2 IX1
opr,X
CMP ,X IX
CMP opr,SP SP1
CMP opr,SP SP2
COM opr M  (M) = $FF – (M) DIR
COMA A  (A) = $FF – (M) INH
COMX Complement (One’s Complement) X  (X) = $FF – (M) 0 – – ⭥ ⭥ 1 INH IX1
COM opr,X M  (M) = $FF – (M)
COM ,X M  (M) = $FF – (M) IX
COM opr,SP M  (M) = $FF – (M) SP1
CPHX #opr CPHX Compare H:X with M (H:X) – (M:M + 1) ⭥ – – ⭥ ⭥ ⭥ IMM DIR
opr
CPX #opr IMM
CPX opr DIR
CPX opr EXT
CPX ,X Compare X with M (X) – (M) ⭥ – – ⭥ ⭥ ⭥ IX2 IX1
CPX opr,X
CPX opr,X IX
CPX opr,SP SP1
CPX opr,SP SP2
DAA Decimal Adjust A (A)10 U – – ⭥ ⭥ ⭥ INH
DBNZ opr,rel A  (A) – 1 or M  (M) – 1 or X  (X) – 1 DIR INH
DBNZA rel DBNZX PC  (PC) + 3 + rel ? (result)  0 PC  INH IX1
rel DBNZ opr,X,rel (PC) + 2 + rel ? (result)  0 PC  (PC) + 2 IX SP1
DBNZ X,rel DBNZ Decrement and Branch if Not Zero + rel ? (result)  0 PC  (PC) + 3 + rel ? – – – – – –
opr,SP,rel (result)  0 PC  (PC) + 2 + rel ? (result)
 0 PC  (PC) + 4 + rel ? (result)  0

DEC opr M  (M) – 1 DIR

DECA A  (A) – 1 INH
DECX Decrement X  (X) – 1 ⭥ – – ⭥ ⭥ – INH IX1
DEC opr,X M  (M) – 1
DEC ,X M  (M) – 1 IX
DEC opr,SP M  (M) – 1 SP1
DIV Divide A  (H:A)/(X) – – – – ⭥ ⭥ INH
H  Remainder
EOR #opr IMM
EOR opr DIR
EOR opr EXT
EOR opr,X EOR Exclusive OR M with A A  (A  M) 0 – – ⭥ ⭥ – IX2 IX1
opr,X
EOR ,X IX
EOR opr,SP SP1
EOR opr,SP SP2
INC opr M  (M) + 1 DIR
INCA A  (A) + 1 INH
INCX Increment X  (X) + 1 M  (M) + 1 ⭥ – – ⭥ ⭥ – INH IX1
INC opr,X
INC ,X M  (M) + 1 IX
INC opr,SP M  (M) + 1 SP1
 Operand
Opcode

Cycles
24 rr 3

2F rr 3
2E rr 3
A5 ii 2
B5 dd 3
C5 hh ll 4
D5 ee ff ff 4
E5 3
F5 2
9EE5 ff 4
9ED5 ee ff 5
93 rr 3

25 rr 3
23 rr 3
91 rr 3
2C rr 3
2B rr 3
2D rr 3
26 rr 3
2A rr 3
20 rr 3
01 dd rr 5
03 dd rr 5
05 dd rr 5
07 dd rr 5
09 dd rr 5
0B dd rr 5
0D dd rr 5
0F dd rr 5

21 rr 3
00 dd rr 5
02 dd rr 5
04 dd rr 5
06 dd rr 5
08 dd rr 5
0A dd rr 5
0C dd rr 5
0E dd rr 5

10 dd dd 4
12 dd dd 4
14 dd dd 4
16 dd dd 4
18 4
1A 4
1C 4
1E 4

AD rr 4
31 dd rr ii 5
41 rr 4
51 ii rr ff 4
61 rr rr 5
71 ff rr 4
9E61 6

98 1
9A 2
3F dd 3
4F 1
5F 1
8C
1
6F ff 3
7F 2
9E6F ff 4
A1 ii 2
B1 dd 3
C1 hh ll 4
D1 ee ff ff 4
E1 3
F1 2
9EE1 ff 4
9ED1 ee ff 5
33 dd 4
43 1
53 ff 1
63 4
73 3
9E+63 ff 5
65 ii ii+1 3
75 dd 4
A3 ii 2
B3 dd 3
C3 hh ll 4
D3 ee ff ff 4
E3 3
F3 2
9EE3 ff 4
9ED3 ee ff 5
72 2
3B dd rr 5
4B rr 3
5B rr 3
6B ff rr rr 5
7B ff rr 4
9E6B 6

3A dd 4
4A 1
5A ff 1
6A 4
7A 3
9E6A ff 5
52 7

A8 ii 2
B8 dd 3
C8 hh ll 4
 D8 ee ff ff 4
E8 3
F8 2
9EE8 ff 4
9ED8 ee ff 5
3C dd 4
4C 1
5C ff 1
6C 4
7C 3
9E6C ff 5
 Source Form Operation Description Effect on

Address
CCR
V I N Z C
H
JMP opr JMP opr Jump PC  Jump Address – – – – – – DIR EXT
JMP opr,X JMP IX2 IX1
opr,X JMP ,X IX

JSR opr JSR opr JSR Jump to Subroutine PC  (PC) + n (n = 1, 2, or 3) Push – – – – – – DIR EXT
opr,X JSR opr,X (PCL); SP  (SP) – 1 IX2 IX1
JSR ,X Push (PCH); SP  (SP) – 1 IX
PC  Unconditional Address

LDA #opr LDA opr ⭥ ⭥ IMM DIR

LDA opr LDA opr,X EXT IX2
LDA opr,X LDA ,X IX1 IX
LDA opr,SP LDA SP1 SP2
opr,SP Load A from M A  (M) 0 – – –

LDHX #opr LDHX Load H:X from M H:X  M:M + 1 0 – – ⭥ ⭥ – IMM DIR
opr
LDX #opr LDX opr ⭥ ⭥ IMM DIR
LDX opr LDX opr,X EXT IX2
LDX opr,X LDX ,X IX1 IX
LDX opr,SP LDX SP1 SP2
opr,SP Load X from M X  (M) 0 – – –

LSL opr LSLA LSLX Logical Shift Left (Same as ASL) DIR INH
LSL opr,X LSL ,X INH IX1
LSL opr,SP IX SP1
⭥ – – ⭥ ⭥ ⭥
C 0
b7
b0

LSR opr LSRA DIR INH

LSRX INH IX1
LSR opr,X LSR ,X IX SP1
LSR opr,SP Logical Shift Right ⭥ – – 0 ⭥ ⭥
0 C
b7 b0

MOV opr,opr MOV Move (M)

Destination  (M)
Source H:X  (H:X) + 1 0 – – ⭥ ⭥ – DD DIX+
opr,X+ MOV (IX+D, DIX+) IMD
#opr,opr MOV IX+D
X+,opr

MUL Unsigned multiply X:A  (X)  (A) – 0 – –

– 0 INH
NEG opr NEGA M  –(M) = $00 – (M) DIR INH
NEGX A  –(A) = $00 – (A) INH IX1
NEG opr,X NEG ,X X  –(X) = $00 – (X) IX SP1
NEG opr,SP Negate (Two’s Complement) M  –(M) = $00 – (M) ⭥ – – ⭥ ⭥ ⭥
M  –(M) = $00 – (M)

NOP No Operation None – – – – – – INH

NSA Nibble Swap A A  (A[3:0]:A[7:4]) – – – – – – INH
ORA #opr ORA opr ⭥ ⭥ IMM DIR
ORA opr ORA EXT IX2
opr,X ORA opr,X IX1 IX
ORA ,X SP1 SP2
ORA opr,SP ORA Inclusive OR A and M A  (A) | (M) 0 – – –
opr,SP

PSHA Push A onto Stack Push (A); SP  (SP) – 1 – – – – – – INH

PSHH Push H onto Stack Push (H); SP  (SP) – 1 – – – – – – INH
PSHX Push X onto Stack Push (X); SP  (SP) – 1 – – – – – – INH
 Operand
Opcode

Cycles
BC dd hh 2
CC ll ee ff 3
DC ff 4
EC 3
FC 2

BD dd hh 4
CD ll ee ff 5
DD ff 6
ED 5
FD 4

A6 B6 ii dd 2
C6 D6 hh ll 3
E6 F6 ee ff ff 4
9EE6 ff 4
9ED6 ee ff 3
2
4
5

45 ii jj dd 3
55 4
AE BE ii dd 2
CE DE hh ll 3
EE FE ee ff ff 4
9EEE ff 4
9EDE ee ff 3
2
4
5

38 dd 4
48 ff ff 1
58 1
68 4
78 3
9E68 5

34 dd 4
44 ff ff 1
54 1
64 4
74 3
9E64 5

4E dd dd 5
5E dd 4
6E ii dd 4
7E dd 4

42 5
30 dd 4
40 ff ff 1
50 1
60 4
70 3
9E60 5

9D 1
62 3
AA BA ii dd 2
CA DA hh ll 3
EA FA ee ff ff 4
9EEA ff 4
9EDA ee ff 3
2
4
5

87 2
8B 2
89 2
 Source Form Operation Description Effect on

Address
CCR
V I N Z C
H
PULA Pull A from Stack SP  (SP + 1); Pull A – – – – –– INH
PULH Pull H from Stack SP  (SP + 1); Pull H – – – – –– INH
PULX Pull X from Stack SP  (SP + 1); Pull X – – – – –– INH
ROL opr ROLA DIR INH
ROLX INH IX1
ROL opr,X ROL ,X IX SP1
ROL opr,SP Rotate Left through Carry ⭥ – – ⭥ ⭥ ⭥
C
b7 b0

ROR opr RORA DIR INH

RORX INH IX1
ROR opr,X ROR ,X IX SP1
ROR opr,SP Rotate Right through Carry ⭥ – – ⭥ ⭥ ⭥
C
b7
b0

RSP Reset Stack Pointer SP  $FF – – – – – – INH

RTI Return from Interrupt SP  (SP) + 1; Pull (CCR) SP  (SP) + 1; ⭥ ⭥ ⭥ ⭥ ⭥ ⭥ INH
Pull (A) SP  (SP) + 1; Pull (X) SP  (SP)
+ 1; Pull (PCH) SP  (SP) + 1; Pull (PCL)

RTS Return from Subroutine SP  SP + 1 Pull PCH) SP  SP + – – – – – – INH

1; Pull (PCL)
SBC #opr SBC opr ⭥ ⭥ ⭥ ⭥ IMM DIR
SBC opr SBC opr,X EXT IX2
SBC opr,X SBC ,X IX1 IX
SBC opr,SP SBC SP1 SP2
opr,SP Subtract with Carry A  (A) – (M) – (C) – –

SEC Set Carry Bit C1 – – – – – 1 INH

SEI Set Interrupt Mask I1 – – 1 – – – INH
STA opr STA opr Store A in M M  (A) 0 – – ⭥ ⭥ – DIR EXT
STA opr,X STA IX2 IX1
opr,X STA ,X IX SP1
STA opr,SP STA SP2
opr,SP

STHX opr Store H:X in M (M:M + 1)  (H:X) 0 – – ⭥ ⭥ – DIR

STOP Enable Interrupts, Stop Processing, I  0; Stop Processing – – 0 – – – INH
Refer to MCU Documentation
STX opr STX opr Store X in M M  (X) 0 – – ⭥ ⭥ – DIR EXT
STX opr,X STX IX2 IX1
opr,X STX ,X IX SP1
STX opr,SP STX SP2
opr,SP

SUB #opr SUB opr ⭥ ⭥ ⭥ ⭥ IMM DIR

SUB opr SUB opr,X EXT IX2
SUB opr,X SUB ,X IX1 IX
SUB opr,SP SUB SP1 SP2
opr,SP Subtract A  (A) – (M) – –
 Operand
Opcode

Cycles
86 2
8A 2
88 2
39 dd 4
49 ff ff 1
59 1
69 4
79 3
9E69 5

36 dd 4
46 ff ff 1
56 1
66 4
76 3
9E66 5

9C 1
80 7

81 4

A2 B2 ii dd 2
C2 D2 hh ll 3
E2 F2 ee ff ff 4
9EE2 ff 4
9ED2 ee ff 3
2
4
5

99 1
9B 2
B7 C7 dd hh 3
D7 E7 ll ee ff 4
F7 ff 4
9EE7 ff 3
9ED7 ee ff 2
4
5

35 dd 4
8E 1

BF CF dd hh 3
DF EF ll ee ff 4
FF ff 4
9EEF ff 3
9EDF ee ff 2
4
5

A0 B0 ii dd 2
C0 D0 hh ll 3
E0 F0 ee ff ff 4
9EE0 ff 4
9ED0 ee ff 3
2
4
5
 Source Form Operation Description Effect on

Address
CCR
V I N Z C
H
PC  (PC) + 1; Push (PCL) SP  (SP) – 1;
Push (PCH)
SP  (SP) – 1; Push (X)
SWI Software Interrupt SP  (SP) – 1; Push (A) – – 1 – – – INH
SP  (SP) – 1; Push (CCR) SP  (SP) – 1; I
1
PCH  Interrupt Vector High Byte PCL 
TAP Transfer A to CCR InterruptCCR
Vector Low Byte
 (A) ⭥ ⭥ ⭥ ⭥ ⭥ ⭥ INH
TAX Transfer A to X X  (A) – – – – –
– INH
TPA Transfer CCR to A A  (CCR) – – – – –
– INH
TST opr DIR
TSTA INH
TSTX Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – ⭥ ⭥ – INH IX1
TST opr,X
TST ,X IX
TST opr,SP SP1
TSX Transfer SP to H:X H:X  (SP) + 1 – – – – – – INH
TXA Transfer X to A A  (X) – – – – – – INH
TXS Transfer H:X to SP (SP)  (H:X) – 1 – – – – – – INH
WAIT Enable Interrupts; Wait for Interrupt I bit  0; Inhibit CPU clocking until – – 0 – – – INH
interrupted
A Accumulator n Any bitC Carry/borrow bit
 Operand
Opcode

Cycles
83 9

84 2
97 1
85 1
3D dd 3
4D 1
5D ff 1
6D 3
7D 2
9E6D ff 4
95 2
9F 1
94 2
8F 1

/borrow bit opr Operand (one or two bytes)CCR Condition code register
 Table 7-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Reg
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR
MSB 0 1 2 3 4 5 6 9E+6 7 8 9 A B
LSB

0 5 4 3 41 1 4 5 37 3 2 3
BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG NEG RTI BGE SUB SUB
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR
1 5 4 3 5 4 4 5 6 4 4 3 2 3
BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ RTS BLT CMP CMP
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 4 SP1 2 IX+ 1 INH 2 REL 2 IMM 2 DIR
2 5 4 3 57 3 2 3 2 3
BRSET1 BSET1 BHI MUL DIV NSA DAA BGT SBC SBC
3 DIR 2 DIR 2 REL 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR
3 5 4 3 41 1 45 39 3 2 3
BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI BLE CPX CPX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR
 4 5 4 3 4 1 1 45 32 2 2 3
BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR LSR TAP TXS AND AND
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR
5 5 4 3 4 3 4 3 4 1 2 2 3
BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR
6 5 4 3 41 1 45 32 2 3
BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA LDA LDA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 IMM 2 DIR
7 5 4 3 41 1 45 32 1 2 3
BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX AIS STA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR
8 5 4 3 4 1 1 45 32 1 2 3
BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL LSL PULX CLC EOR EOR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR
9 5 4 3 41 1 45 32 12 3
BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR
A 5 4 3 41 1 45 32 2 2 3
BRSET5 BSET5 BPL DEC DECA DECX DEC DEC DEC PULH CLI ORA ORA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR
B 5 4 3 5 3 3 5 6 4 2 2 2 3
BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ DBNZ PSHH SEI ADD ADD
3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 4 SP1 2 IX 1 INH 1 INH 2 IMM 2 DIR
C 5 4 3 4 1 1 45 31 1 2
BRSET6 BSET6 BMC INC INCA INCX INC INC INC CLRH RSP JMP
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 DIR
D 5 4 3 3 11 34 2 14 4
BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST TST NOP BSR JSR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 DIR
E 5 4 3 5 44 41 * 2 3
BRSET7 BSET7 BIL MOV MOV MOV MOV STOP LDX LDX
3 DIR 2 DIR 2 REL 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR
F 5 4 3 3 1 1 34 2 11 2 3
BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR CLR WAIT TXA AIX STX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR
MSB 0
LSB

0 5
BRSET0
3 DIR
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM H
Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR i
Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT g
Extended IX2 Indexed, 16-Bit Offset Post Increment Low Byte of Opcode in Hexadecimal h
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment B
*Pre-byte for stack pointer indexed instructions y
Chapter 8
External Interrupt (IRQ)
8.1 Introduction
The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and keyboard interr
a maskable interrupt input

8.2 Features
Features of the IRQ module include the following:
• External interrupt pin, IRQ
• IRQ interrupt control bits
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Selectable internal pullup resistor
8.3 Functional Description
IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordi
disables the IRQ function and PTA2 will assume the other shared functionalities. A one enables
A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request
the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until o
actions occurs:
• IRQ vector fetch — An IRQ vector fetch automatically generates an interrupt acknowledge
the IRQ latch.
• Software clear — Software can clear the IRQ latch by writing a 1 to the ACK bit in the interr
control register (INTSCR).
• Reset — A reset automatically clears the IRQ latch.
The external interrupt pin is falling-edge-triggered out of reset and is software-configurable to
edge or falling-edge and low-level triggered. The MODE bit in INTSCR controls the triggering se
pin.
 Register/Memory
EXT IX2 SP2 IX1 SP1 IX
C D 9ED E 9EE F

4 45 34 2
SUB SUB SUB SUB SUB SUB
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
CMP CMP CMP CMP CMP CMP
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
SBC SBC SBC SBC SBC SBC
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
CPX CPX CPX CPX CPX CPX
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
 4 45 34 2
AND AND AND AND AND AND
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 3 4 2
BIT BIT BIT BIT BIT BIT
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
LDA LDA LDA LDA LDA LDA
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
STA STA STA STA STA STA
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
EOR EOR EOR EOR EOR EOR
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
ADC ADC ADC ADC ADC ADC
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
ORA ORA ORA ORA ORA ORA
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
ADD ADD ADD ADD ADD ADD
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
3 4 3 2
JMP JMP JMP JMP
3 EXT 3 IX2 2 IX1 1 IX
5 6 5 4
JSR JSR JSR JSR
3 EXT 3 IX2 2 IX1 1 IX
4 45 34 2
LDX LDX LDX LDX LDX LDX
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
4 45 34 2
STX STX STX STX STX STX
3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX

H
i
g
h

B
y

and keyboard interrupt (KBI), provides

2) IRQEN bit accordingly. A zero
ties. A one enables the IRQ function.
PU interrupt request. Figure 8-2 shows

h remains set until one of the following

rrupt acknowledge signal that clears

ACK bit in the interrupt status and

are-configurable to be either falling-

ols the triggering sensitivity of the IRQ
 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

CLOCK GENERATOR
(OSCILLATOR)
DDRA
PTA

M68HC08 CPU

SYSTEM INTEGRATION
MODULE

SINGLE INTERRUPT
MODULE

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

DDRB
PTB

BREAK MODULE

POWER-ON RESET
MODULE

MC68HC908QY4 AND MC68HC908QT4

4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH

KEYBOARD INTERRUPT
MODULE
 8-BIT ADC

16-BIT TIMER
MODULE

128 BYTES RAM

COP MODULE

POWER SUPPLY

MONITOR ROM

RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Intr
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 8-1. Block Diagram Highlighting IRQ Block and Pins

When set, the IMASK bit in INTSCR masks the IRQ interrupt request. A latched interrupt request is not
presented to the interrupt priority logic unless IMASK is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including the IRQ interrupt r
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch, sof
clears the IRQ latch.
 /KBI0 PTA1/AD1/TCH1/KBI1
Q/KBI2/TCLK PTA3/RST/KBI3
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

B0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

 RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 8-1. Block Diagram Highlighting IRQ Block and Pins

bit in INTSCR masks the IRQ interrupt request. A latched interrupt request is not
errupt priority logic unless IMASK is clear.

n the condition code register (CCR) masks all interrupt requests, including the IRQ interrupt request.
IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch, software clear, or reset
VD
D

VSS
 Functio

RESET
DD

VECTOR
FETCH
DECODE
R V

D
D
I

E
IR
R
QF
N

IRQ

IRQP
UD

D CLR Q
CK
IRQ
LATCH

SYNCHRO-
NIZER

MODE
HIGH
VOLTAGE
DETECT

Figure 8-2. IRQ Module Block Diagram

8.3.1 MODE = 1
If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set
both of the following actions must occur to clear the IRQ interrupt request:
• Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active
• IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signa
latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK in INTSCR. The ACK
applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to ACK prior to le
service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequ
the IRQ pin. A falling edge that occurs after writing to ACK latches another interrupt request. If the IRQ
is clear, the CPU loads the program counter with the IRQ vector address.
The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any o
request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and the MODE c
clearing the interrupt even if the pin stays low.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
8.3.2 MODE = 0
If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetc
immediately clears the IRQ latch.
The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMA
it useful in applications where polling is preferred.
NOTE
When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interr

IMASK
ACK
8.4 Interrupts
The following IRQ source can generate interrupt requests:
• Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ
interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests.
 8.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt
the MCU out of wait mode.
8.5.2 Stop Mode
The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt
the MCU out of stop mode.

8.6 IRQ Module During Break InterruptsThe system integration module (SIM) controls whether status bits in other modules can

8.7 I/O Signals

The IRQ module shares its pin with the keyboard interrupt, input/output ports, and timer inter

NOTE
When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL instructions can be used to read the log
pin. If the IRQ function is disabled, these instructions will behave as if the IRQ pin is a logic 1, regardless of the actu
Conversely, when the IRQ function is enabled, bit 2 of the port A data register will always read a 0.
When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt r
pullup resistor to VDD is connected to the IRQ pin; this can be disabled by setting
the IRQPUD bit in the CONFIG2 register ($001E).
Functional Description

TO CPU FOR BIL/BIH

INSTRUCTIONS
IRQ INTERRUPT
REQUEST

TO MODE SELECT LOGIC

sitive. With MODE set,

quest remains active.

t acknowledge signal to clear the IRQ
in INTSCR. The ACK bit is useful in
ing to ACK prior to leaving an interrupt
es not affect subsequent transitions on
upt request. If the IRQ mask bit, IMASK,

el may occur in any order. The interrupt

atch and the MODE control bit, thereby

ar, an IRQ vector fetch or software clear

s not affected by IMASK, which makes

pt requests in the interrupt routine.

ed based on the IRQ mode. The IRQ

ests.
standby modes.

enables IRQ interrupt requests to bring

enables IRQ interrupt requests to bring

us bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits

ports, and timer interface modules.

be used to read the logic level on the IRQ

, regardless of the actual level on the pin.
ad a 0.
quests in the interrupt routine. An internal
Registers
8.7.1 IRQ Input Pins (IRQ)

The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pu
device.
8.8 RegistersThe IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. See Chapter 5 Con

Address: $001D
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 IRQF 0 IMASK MODE
ACK
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 8-3. IRQ Status and Control Register (INTSCR)

IRQF — IRQ Flag

This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled 0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling ed

Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides six independently maskable external interrupts,
via the PTA0–PTA5 pins.
 9.2 Features
Features of the keyboard interrupt module include:
• Six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboa
• Software configurable pullup device if input pin is configured as input port bit
• Programmable edge-only or edge and level interrupt sensitivity
• Exit from low-power modes

9.3 Functional DescriptionThe keyboard interrupt module controls the enabling/disabling of interrupt functions on the six port A p
ce. The IRQ pin contains an internal pullup

itors operation of the IRQ module. See Chapter 5 Configuration Register (CONFIG).The INTSCR has the following functions:• Shows the state of the

2 1 Bit 0

d:
e:
0 0 0 0
mented
Control Register (INTSCR)

pending.

K always reads as 0.

pt request.
uest enabled

he IRQ pin.
s 0 = IRQ interrupt request on falling edges only

endently maskable external interrupts, which are accessible

d interrupt enable bits and one keyboard interrupt mask
configured as input port bit
pt sensitivity

ng/disabling of interrupt functions on the six port A pins. These six pins can be enabled/disabled independently of each other. Refer to Figure 9-2.9.3.1 K
 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

CLOCK GENERATOR
(OSCILLATOR)

M68HC08 CPU

SYSTEM INTEGRATION
MODULE

SINGLE INTERRUPT
MODULE

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

DDRB
PTB

BREAK MODULE

POWER-ON RESET
MODULE

MC68HC908QY4 AND MC68HC908QT4

4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH

KEYBOARD INTERRUPT
MODULE

8-BIT ADC

16-BIT TIMER
MODULE

128 BYTES RAM

 COP MODULE

POWER SUPPLY

MONITOR ROM

RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 9-1. Block Diagram Highlighting KBI Block and Pins
TCH0/KBI0 PTA1/AD1/TCH1/KBI1
RST/KBI3 PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

 RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 9-1. Block Diagram Highlighting KBI Block and Pins

VD
D

VSS
INTERNAL BUS Functi
ACKK
RESET
VECTOR FETCH
DECODER

K
E
KBIE0 Y
KBI0 V B
O
.
D
D A KEYF
R
. D
SYNCHRONIZ
TO PULLUP ENABLE . I ER
KBI5 N
TO PULLUP ENABLE T
E
R IMASK
R K
U
P
T
R
E
Q
U
DCLR Q E
CK S
T

KEYBOARD
INTERRUPT FF

MODEK

KBIE5
AWUIREQ
(1)
1. For AWUGEN logic refer to Figure 4-1. Auto Wakeup Interrupt Request Generation Logic.
Figure 9-2. Keyboard Interrupt Block Diagram
If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and low-level sens
the following actions must occur to clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signa
interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to t
keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll t
interrupt inputs and require software to clear the keyboard interrupt request. Writing to the A
leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting
affect subsequent transitions on the keyboard interrupt inputs. A falling edge that occurs afte
ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clea
processor unit (CPU) loads the program counter with the vector address at locations $FFE0 an
$FFE1.
• Return of all enabled keyboard interrupt inputs to logic 1 — As long as any enabled keybo
is at logic 0, the keyboard interrupt remains set. The auto wakeup interrupt input, AWUIREQ,
by writing to ACKK bit in KBSCR or reset.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to log
any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only. With MODE
fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request
keyboard interrupt input stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) whic
in applications where polling is preferred.

To determine the logic level on a keyboard interrupt pin, use the data direction register to con
pin as an input and then read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overr
direction register. However, the data direction register bit must be a 0 for software to read the pin.
9.3.2 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. There
interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable registe
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin
signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends
load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction
2. Write 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable registe

9.4 Wait Mode

The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard s
register enables keyboard interrupt requests to bring the MCU out of wait mode.

9.5 Stop Mode

The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard s
register enables keyboard interrupt requests to bring the MCU out of stop mode.

9.6 Keyboard Module During Break Interrupts

The system integration module (SIM) controls whether the keyboard interrupt latch can be cle
break state. The BCFE bit in the break flag control register (BFCR) enables software to clear st
the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to th
latch is cleared during the break state, it remains cleared when the MCU exits the break state

Input/Output Registers
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state)
keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state h
 Functional Description

Request Generation Logic.

 and low-level sensitive, and both of

acknowledge signal to clear the

l by writing a 1 to the ACKK bit in the
plications that poll the keyboard
est. Writing to the ACKK bit prior to
ue to noise. Setting ACKK does not
ge that occurs after writing to the
bit, IMASKK, is clear, the central
locations $FFE0 and

any enabled keyboard interrupt pin

t input, AWUIREQ, will be cleared only

nterrupt pins to logic 1 may occur in

e only. With MODEK clear, a vector

he interrupt request even if a

n be used to see if a pending

sk bit (IMASKK) which makes it useful

ction register to configure the

n to be an input, overriding the data
pin.

each a logic 1. Therefore a false

d control register.
rupt enable register.
alse interrupts.

er enabling the pin. An interrupt

delay that depends on the external

n the data direction register A.

rupt enable register.

t in the keyboard status and control

mode.

it in the keyboard status and control

mode.

upt latch can be cleared during the

software to clear status bits during

rrupt, write a 1 to the BCFE bit. If a

xits the break state.

0 (its default state), writing to the

ng the break state has no effect.
 9.7 Input/Output Registers
The following I/O registers control and monitor operation of the keyboard interrupt module:
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
9.7.1 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity

Address: $001A
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 KEYF 0 IMASKK MODEK
ACKK
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-3. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Rese
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard interrupt request on port A and auto wak
always reads as 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from gen
requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A a
Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
on of the keyboard interrupt module:
SCR)

2 1 Bit 0

0 0 0

) Bits 7–4 — Not used

ending on port A or auto wakeup. Reset clears the KEYF bit.

terrupt request on port A and auto wakeup logic. ACKK

the keyboard interrupt mask from generating interrupt

ASKK bit.

the keyboard interrupt pins on port A and auto wakeup.

ow levels
 9.7.2 Keyboard Interrupt Enable Register
The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or a
operate as a keyboard interrupt input.
Address: $001B
Bit 7 6 5 4 3 2 1 Bit 0
0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

Read:Write:Reset: 0 0 0 0 0 0 0 0= UnimplementedFigure 9-4. Keyboard I

enables or disables each port A pin or auto wakeup to

2 1 Bit 0

0 0= UnimplementedFigure 9-4. Keyboard Interrupt Enable Register (KBIER)KBIE5–KBIE0 — Port A Keyboard Interrupt Enable BitsEach of
 Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the
a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
10.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Selectable LVI trip voltage
• Programmable stop mode operation

10.3 Functional DescriptionFigure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVI5OR3, and LVIRST

V
DD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIPWRD
LOWVDD DETECTOR FROM CONFIG
FROM CONFIG VDD > LVITRIP = 0 VDD  LVITRIP = 1
Figure 10-1. LVI Module Block Diagram

LVIOUT
LVI5OR3

The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comp
Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V DD voltage. Clearing th
bit, LVIRSTD, enables the LVI module to generate a reset when V DD falls below a voltage,
 LVIRSTD

VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode
or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be configured for 5-V oper
LVI5OR3 bit enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual t
specified in 16.5 5-V DC Electrical Characteristics and 16.9 3-V
DC Electrical Characteristics.
NOTEAfter a power-on reset, the LVI’s default mode of operation is 3 volts. If a 5-V system is used, the user must set the LVI5OR3 bit to ra
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (V TRIPF [5 V] or VTRIPF [3 V]) ma
See 16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical
Characteristics for the actual trip point voltages.
monitors the voltage on the V DD pin and can force
VTRIPF.

LVIPWRD, LVI5OR3, and LVIRSTD are user selectable options found in the configuration register (CONFIG1). See Chapter 5 Configuration Register (C

LVI RESET

eference circuit and comparator.

tor V DD voltage. Clearing the LVI reset disable
ls below a voltage,
VI to operate in stop mode. Setting the LVI 5-V
be configured for 5-V operation. Clearing the
3-V operation. The actual trip thresholds are

user must set the LVI5OR3 bit to raise the trip point to 5-V operation.If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset while
int (V TRIPF [5 V] or VTRIPF [3 V]) may be lower than this.
 LVI Status R
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level whi
LVI resets have been disabled.
Address: $FE0C
Bit 7 6 5 4 3 2 1 Bit 0
LVIOUT 0 0 0 0 0 0 R

Read:
Write:
Reset: 0 0 0 0 0 0 0 0

R
= Unimplemented = Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared when VDD voltage rises above V

V
DD LVIOUT
V
DD >V
TRIPR 0
V
DD V
TRIPF 1
V
TRIPF V
DD V
TRIPR Previous value

10.5 LVI Interrupts

The LVI module does not generate interrupt requests.

10.6 Low-Power Modes

The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the confi
set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI modul
reset and bring the MCU out of stop mode.

Chapter 11
Oscillator Module (OSC)
11.1 Introduction
The oscillator module is used to provide a stable clock source for the microcontroller system an
module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used b
integration module (SIM) and the computer operating properly module (COP). The BUSCLKX2 c
two in the SIM to be used as the bus clock for the microcontroller.
Therefore the bus frequency will be one fourth of the BUSCLKX4 frequency.

11.2 Features
The oscillator has these four clock source options available:
1. Internal oscillator: An internally generated, fixed frequency clock, trimmable to ±5%.This
out of reset.
2. External oscillator: An external clock that can be driven directly into OSC1.
3. External RC: A built-in oscillator module (RC oscillator) that requires an external R connec
capacitor is internal to the chip.
4. External crystal: A built-in oscillator module (XTAL oscillator) that requires an external cry
resonator.

11.3 Functional Description

The oscillator contains these major subsystems:
• Internal oscillator circuit
• Internal or external clock switch control
• External clock circuit
• External crystal circuit
• External RC clock circuit
 LVI Status Register

e was detected below the VTRIPF level while

2 1 Bit 0

0 0 0 0

= Reserved

oltage and is cleared when VDD voltage rises above VTRIPR. The difference in these threshold levels results in a hysteresis that prevents oscillation into

wer-consumption standby modes.

e. If enabled to generate resets, the LVI module can

cleared and the LVISTOP bit in the configuration register is

abled to generate resets, the LVI module can generate a
 ource for the microcontroller system and bus. The oscillator
SCLKX4. The BUSCLKX4 clock is used by the system
roperly module (COP). The BUSCLKX2 clock is divided by
controller.
USCLKX4 frequency.

able:
requency clock, trimmable to ±5%.This is the default option

driven directly into OSC1.

ator) that requires an external R connection only. The

oscillator) that requires an external crystal or ceramic-

 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

CLOCK GENERATOR
(OSCILLATOR)
DDRA
PTA

M68HC08 CPU

SYSTEM INTEGRATION
MODULE

SINGLE INTERRUPT
MODULE

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

DDRB
PTB

BREAK MODULE

POWER-ON RESET
MODULE

MC68HC908QY4 AND MC68HC908QT4

4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH

KEYBOARD INTERRUPT
MODULE
 8-BIT ADC

16-BIT TIMER
MODULE

128 BYTES RAM

COP MODULE

POWER SUPPLY

MONITOR ROM

RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Intro
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1

Figure 11-1. Block Diagram Highlighting OSC Block and Pins11.3.1 Internal OscillatorThe internal oscillator circuit is designed for use wit
Functional Description
11.3.1.1 Internal Oscillator Trimming
The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing
increases the clock period. Trimming allows the internal clock frequency to be set to
12.8 MHz ± 5%.
All devices are programmed with a trim value in a reserved FLASH location, $FFC0. This value can be
FLASH to the OSCTRIM register ($0038) during reset initialization.
Reset loads OSCTRIM with a default value of $80.
WARNING
Bulk FLASH erasure will set location $FFC0 to $FF and the factory programmed value will be lost.
11.3.1.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the followin
1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal oscilla
(OSC2) as an output and drive high for several cycles. This may help the crystal circuit start more rob
2. Set CONFIG2 bits OSCOPT[1:0] according to . The oscillator module control logic will then set OSC
clock input and, if the external crystal option is selected, OSC2 will also be set as the clock output.
3. Create a software delay to wait the stabilization time needed for the selected clock source (crysta
recommended by the component manufacturer. A good rule of thumb for crystal oscillators is to wait
crystal frequency, i.e., for a 4-MHz crystal, wait approximately 1 msec.
4. After the manufacturer’s recommended delay has elapsed, the ECGON bit in the OSC status regis
needs to be set by the user software.
5. After ECGON set is detected, the OSC module checks for oscillator activity by waiting two externa
6. The OSC module then switches to the external clock. Logic provides a glitch free transition.
7. The OSC module first sets the ECGST bit in the OSCSTAT register and then stops the internal osci

NOTE
Once transition to the external clock is done, the internal oscillator will only be reactivated with reset. No post-switch
implemented (clock does not switch back to internal if external clock dies).
11.3.2 External Oscillator
The external clock option is designed for use when a clock signal is available in the application to prov
to the microcontroller. The OSC1 pin is enabled as an input by the oscillator module. The clock signal
create BUSCLKX4 and also divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4.So the OSC2EN bit in the port A pullup en
clear to enable PTA4 I/O functions on the pin
11.3.3 XTAL OscillatorThe XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide a
/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4
1/AD3/KBI5

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

Pins have internal (about 30K Ohms) pull up
High current sink and source capability
Pins have programmable keyboard interrupt and pull up
Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
available on the MC68HC908QY1 and MC68HC908QT1

Highlighting OSC Block and Pins11.3.1 Internal OscillatorThe internal oscillator circuit is designed for use with no external components to provide a clo
 VD
D

VSS

llator Trimming
egister, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing OSCTRIM value
period. Trimming allows the internal clock frequency to be set to

ammed with a trim value in a reserved FLASH location, $FFC0. This value can be copied from the
IM register ($0038) during reset initialization.
M with a default value of $80.

will set location $FFC0 to $FF and the factory programmed value will be lost.
xternal Clock Switching
source (external OSC, RC, or XTAL) is desired, the user must perform the following steps:
stal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal oscillator, set PTA4
and drive high for several cycles. This may help the crystal circuit start more robustly.
s OSCOPT[1:0] according to . The oscillator module control logic will then set OSC1 as an external
e external crystal option is selected, OSC2 will also be set as the clock output.
re delay to wait the stabilization time needed for the selected clock source (crystal, resonator, RC) as
e component manufacturer. A good rule of thumb for crystal oscillators is to wait 4096 cycles of the
e., for a 4-MHz crystal, wait approximately 1 msec.
acturer’s recommended delay has elapsed, the ECGON bit in the OSC status register (OSCSTAT)
he user software.
t is detected, the OSC module checks for oscillator activity by waiting two external clock rising edges.
e then switches to the external clock. Logic provides a glitch free transition.
e first sets the ECGST bit in the OSCSTAT register and then stops the internal oscillator.

xternal clock is done, the internal oscillator will only be reactivated with reset. No post-switch clock monitor feature is
es not switch back to internal if external clock dies).
illator
ption is designed for use when a clock signal is available in the application to provide a clock source
er. The OSC1 pin is enabled as an input by the oscillator module. The clock signal is used directly to
d also divided by two to create BUSCLKX2.
the OSC2 pin cannot output BUSCLKX4.So the OSC2EN bit in the port A pullup enable register will be
I/O functions on the pin
scillatorThe XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In this configura
NOTE
The series resistor (R ) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required
S

operation,
especially
FROM
with high frequency crystals. Refer to the crystal manufacturer’s data for more information.
SIM
BUSCLKX2

÷2

SIMOSCEN

Note 1.RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. See Chapter 16 Electrical Specifica
MCU

OSC1
NOTE
The series resistor (R ) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ran
S

operation,
especially with high frequency crystals.TORefer to the crystal
TO
manufacturer’s data for more information.
SIM SIM
BUSCLK
X4

XTALCL
K
SIMOSCEN

Note 1.RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. See Chapter 16 Electrical Specifications for com
MCU

OSC1
OSC
2

RS(1)
RB

X1

C1 C2
Oscillator Module Signals
11.3.4 RC Oscillator

The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with a tolerance within 25

OSCRCOPT
FROM SIM TO SIM TOSIM
INTCLK 0
1 BUSCLKX4 BUSCLKX2
÷2

SIMOSCEN EXTERNAL RC
EN RCCLK
OSCILLATOR

1
0
PTA4
I/O PTA4

OSC2EN
MCU
OSC1 PTA4/BUSCLKX4 (OSC2)
V
DD
R
EXT

See Chapter 16 Electrical Specifications for component value requirements.Figure 11-3. RC Oscillator External Conne

11.4 Oscillator Module Signals

The following paragraphs describe the signals that are inputs to and outputs from the oscillato
11.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC oscillator
external clock source.
For the internal oscillator configuration, the OSC1 pin can assume other functions according t
Priority in Shared Pins.
 11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4)
For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier o
For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bi
For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions accord
Function Priority in Shared Pins, or the output of the oscillator clock (BUSCLKX4).
Table 11-1. OSC2 Pin Function
ovide a clock source with a tolerance within 25% of the expected frequency. See Figure 11-3.The capacitor (C) for the RC oscillator is internal to the MCU

nts.Figure 11-3. RC Oscillator External Connections

s to and outputs from the oscillator module.

ifier, an input to the RC oscillator circuit, or an

sume other functions according to Table 1-3. Function

OSC2/PTA4/BUSCLKX4)
stal oscillator inverting amplifier output.
PTA4 I/O function. The OSC2EN bit has no effect.
can assume other functions according to Table 1-3.
f the oscillator clock (BUSCLKX4).
Function
 Option OSC2 Pin Function
XTAL oscillator Inverting OSC1
External clock PTA4 I/O
Internal oscillator or Controlled by OSC2EN bit in PTAPUE register OSC2EN
RC oscillator = 0: PTA4 I/O
OSC2EN = 1: BUSCLKX4 output
11.4.3 Oscillator Enable Signal (SIMOSCEN)The SIMOSCEN signal comes from the system integration module (SIM) and enabl
gnal comes from the system integration module (SIM) and enables/disables either the XTAL oscillator circuit, the RC oscillator, or the internal oscillator.
Low Power Modes
again in the SIM and results in the internal bus frequency being one fourth of either the XTALCLK, RCC
frequency.

11.5 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
11.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue
module.
11.5.2 Stop Mode
The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCL

11.6 Oscillator During Break Mode

The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device enters the break

11.7 CONFIG2 OptionsTwo CONFIG2 register options affect the operation of the oscillator module: OSCOPT1 and OSCOPT0. All CONF

OSCOPT1 OSCOPT0 Oscillator Modes

0 0 Internal oscillator
0 1 External oscillator
1 0 External RC
1 1 External crystal

11.8 Input/Output (I/O) Registers

The oscillator module contains these two registers:
1. Oscillator status register (OSCSTAT)
2. Oscillator trim register (OSCTRIM)
ency being one fourth of either the XTALCLK, RCCLK, or INTCLK

U in low-power consumption standby modes.

cillator logic. BUSCLKX2 and BUSCLKX4 continue to drive to the SIM

LCLK, the RCCLK, or INTCLK output, hence BUSCLKX2 and BUSCLKX4.

and BUSCLKX4 when the device enters the break state.

tion of the oscillator module: OSCOPT1 and OSCOPT0. All CONFIG2 register bits will have a default configuration. Refer to Chapter 5 Configuration R

isters:
 11.8.1 Oscillator Status Register
The oscillator status register (OSCSTAT) contains the bits for switching from internal to extern

Address: $0036

Bit 7 6 5 4 3 2 1 Bit 0
R R R R R R ECGON ECGST

Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Reserved = Unimplemented
Figure 11-4. Oscillator Status Register (OSCSTAT)
ECGON — External Clock Generator On Bit
This read/write bit enables external clock generator, so that the switching process can be initiated. Th
during reset. This bit is ignored in monitor mode with the internal oscillator bypassed, PTM or CTM mo
1 = External clock generator enabled 0 = External clock generator disabled
ECGST — External Clock Status Bit
This read-only bit indicates whether or not an external clock source is engaged to drive the system clo
1 = An external clock source engaged
0 = An external clock source disengaged
11.8.2 Oscillator Trim Register (OSCTRIM)

Address: $0038

Bit 7 6 5 4 3 2 1 Bit 0
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0

Read:
Write:
Reset: 1 0 0 0 0 0 0 0
Figure 11-5. Oscillator Trim Register (OSCTRIM)
TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the internal oscillator. By meas
the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine
(decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimm
period for TRIM = $80). The trimmed frequency is guaranteed not to vary by more than ±5% over the
of temperature and
voltage. The reset value is $80, which sets the frequency to 12.8 MHz (3.2 MHz bus speed) ±25%.

Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction
The MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 have five bidirectional input-output (I/O)
only pin. The MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4 have thirteen bidirectional pins
pin. All I/O pins are programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either V or V . Although the I/O ports do not require term
DD SS

operation, termination reduces excess current consumption and the possibility of electrostatic damage.
8-pin devices have non-bonded pins. These pins should be configured either as outputs driving low or high, or as inp
enabled. Configuring these non-bonded pins in this manner will prevent any excess current consumption caused by

12.2 Port APort A is a 6-bit special function port that shares all six of its pins with the keyboard interrupt (KBI) module (see Chapter 9 Keyb

PTA2 is input only.

When the IRQ function is enabled in the configuration register 2 (CONFIG2), bit 2 of the port
will always read a 0. In this case, the BIH and BIL instructions can be used to read the logic l
When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic
2 of PTA will
read the actual logic level on the pin.
its for switching from internal to external clock sources.

2 1 Bit 0

0 0

e switching process can be initiated. This bit is forced low

nal oscillator bypassed, PTM or CTM mode.
ator disabled

urce is engaged to drive the system clock.

2 1 Bit 0

0 0

used by the internal oscillator. By measuring the period of

quency of the internal clock can be fine tuned. Increasing
d by approximately 0.2% of the untrimmed period (the
not to vary by more than ±5% over the full specified range

.8 MHz (3.2 MHz bus speed) ±25%.

ave five bidirectional input-output (I/O) pins and one input
08QY4 have thirteen bidirectional pins and one input only

V . Although the I/O ports do not require termination for proper

SS

sibility of electrostatic damage.

either as outputs driving low or high, or as inputs with internal pullups
any excess current consumption caused by floating inputs.

keyboard interrupt (KBI) module (see Chapter 9 Keyboard Interrupt Module (KBI)). Each port A pin also has a software configurable pullup device if the

ation register 2 (CONFIG2), bit 2 of the port A data register (PTA)

L instructions can be used to read the logic level on the PTA2 pin.
tions will behave as if the PTA2 pin is a logic 1. However, reading bit
 12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
Address: $0000

Bit 7 6 5 4 3 2 1 Bit 0
R AWUL PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

Read:
Write:
Reset: Unaffected by reset
Additional Functions:

KBI5 KBI4 KBI3 KBI2 KBI1 KBI0

R

= Reserved = Unimplemented
Figure 12-1. Port A Data Register (PTA)
PTA[5:0] — Port A Data Bits

These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit i

Address: $0004

Bit 7 6 5 4 3 2 1 Bit 0
R R DDRA5 DDRA4 DDRA3 0 DDRA1 DDRA0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Reserved = Unimplemented
Figure 12-2. Data Direction Register A (DDRA) DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from

R
 each of the six port A pins.

2 1 Bit 0

reset

rt A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data.AWUL — Auto Wakeup Latch Data B

2 1 Bit 0
 0 0

irection Register A Bits

s DDRA[5:0], configuring all port A pins

onding port A pin configured as input

e changing data direction register A bits from 0 to 1.

Port A
Figure 12-3 shows the port AREAD
I/O DDRA
logic.
($0004)
PTAPUE
DDRAx WRITE DDRA x
($0004)
RESET
PTAx
WRITE PTA
($0000) P
TO KEYBOARD INTERRUPT CIRCUIT
Figure 12-3. Port A I/O Circuit
NOTE READ PTA
($0000)
Figure 12-3 does not apply to PTA2
When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading ad
the voltage level on the pin. The data latch can always be written, regardless of the state of its data d
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for ea
pins. Each bit is individually configurable and requires the corresponding data direction register, DDRA
as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRAx
output.

Address: $000B

Bit 7 6 5 4 3 2 1 Bit 0
OSC2EN PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 12-4. Port A Input Pullup Enable Register (PTAPUE)
OSC2EN — Enable PTA4 on OSC2 Pin
This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is s
no effect for the XTAL or external oscillator options.
1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions
 PTAPUE
x

30
k

PTAx

ta latch. When DDRAx is a 0, reading address $0000 reads

en, regardless of the state of its data direction bit.

tware configurable pullup device for each if the six port A

esponding data direction register, DDRAx, to be configured
disabled when its corresponding DDRAx bit is configured as

2 1 Bit 0

0 0

nal oscillator or RC oscillator option is selected. This bit has

LKX4)
and pullup functions
PTAPUE[5:0] — Port A Input Pullup Enable BitsThese read/write bits are software programmable to enable pullup devices on port A pins. 1

PTAPUE DDRA PTA I/O Pin Mode Accesses to DDRA Accesses to PTA
Bit Bit Bit
Read/Write Read
1 0 X(1) Input, VDD (2)
DDRA5–DDRA0 Pin

0 0 X Input, Hi-Z(4) DDRA5–DDRA0 Pin

X 1 X Output DDRA5–DDRA0 PTA5–PTA0
1. X = don’t care
2. I/O pin pulled to VDD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2

12.3 Port B
Port B is an 8-bit general purpose I/O port. Port B is only available on the MC68HC908QY1, MC
MC68HC908QY4.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.

Address: $0001

Bit 7 6 5 4 3 2 1 Bit 0
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

Read:
Write:
Reset: Unaffected by reset
Figure 12-5. Port B Data Register (PTB)

PTB[7:0] — Port B Data Bits

These read/write bits are software programmable. Data direction of each port B pin is under t
corresponding bit in data direction register B. Reset has no effect on port B data.
e pullup devices on port A pins. 1 = Corresponding port A pin configured to have internal pull if its DDRA bit is set to 00 = Pullup device is disconnected

Accesses to PTA
Write
PTA5–PTA0(3)

PTA5–PTA0(3)
PTA5–PTA0(5)

the MC68HC908QY1, MC68HC908QY2, and

ght port B pins.

Bit 0

ed by reset
B)

ach port B pin is under the control of the

port B data.
Port B
12.3.2 Data Direction Register B

Data direction register B (DDRB) determines whether each port B pin is an input or an output.
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the outp
Address: $0005

Bit 7 6 5 4 3 2 1 Bit 0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 12-6. Data Direction Register B (DDRB) DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 12-7 shows the port B I/O logic.

READ DDRB
($0005)
DDRBx PTBPUE
WRITE DDRB x
($0005)
RESET
PTBx
WRITE PTB
($0001) PTB
Figure 12-7. Port B I/O CircuitWhen DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading address

READ PTB
($0001)

DDRB PTB I/O Pin Mode Accesses to DDRB Accesses to PTB

Bit Bit
Read/Write Read Write
0 X(1) Input, Hi-Z (2)
DDRB7–DDRB0 Pin PTB7–PTB0(3)
1 X Output DDRB7–DDRB0 Pin PTB7–PTB0
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.

12.3.3 Port B Input Pullup Enable Register

The port B input pullup enable register (PTBPUE) contains a software configurable pullup devi
eight port B pins. Each bit is individually configurable and requires the corresponding data dir
DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRBx bit is configured as output.
ort B pin is an input or an output. Writing a 1
g port B pin; a 0 disables the output buffer.

1 Bit 0

0
n Register B Bits
B[7:0], configuring all port B pins

g port B pin configured as input

B I/O logic.

30
k

PTBx
latch. When DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its da

t.

oftware configurable pullup device for each of the

uires the corresponding data direction register,
tically and dynamically disabled
 Address: $000C

Bit 7 6 5 4 3 2 1 Bit 0
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0

Read:Write:Reset: 0 0 0 0 0 0 0 0Figure 12-8. Port B Input Pullup Enable

PTBPUE DDRB PTB I/O Pin Mode Accesses to DDRB Accesses to PTB
Bit Bit Bit
Read/Write Read
1 0 X(1) Input, VDD(2) DDRB7–DDRB0 Pin

0 0 X Input, Hi-Z(4) DDRB7–DDRB0 Pin

X 1 X Output DDRB7–DDRB0 PTB7–PTB0

1. X = don’t care
2. I/O pin pulled to VDD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
 Bit 0

12-8. Port B Input Pullup Enable Register (PTBPUE) PTBPUE[7:0] — Port B Input Pullup Enable BitsThese read/write bits are software programmable t

Accesses to PTB
Write
PTB7–PTB0(3)

PTB7–PTB0(3)

PTB7–PTB0
 Chapter 13
System Integration Module (SIM)
13.1 IntroductionThis section describes the system integration module (SIM), which supports up to 24 external and/or internal in

Table 13-1. Signal Name Conventions

Signal Name
BUSCLKX4
BUSCLKX2

Address bus
Data bus
PORRST
IRST
R/W
hapter 13
ystem Integration Module (SIM)
IntroductionThis section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the c

Table 13-1. Signal Name Conventions

Description
Buffered clock from the internal, RC or XTAL oscillator circuit.
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to generate the
internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
ernal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is
 MODULE STOP MODULE WAIT
CPU STOP (FROM CPU) CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
STOP/
WAIT
CONTRO
L

SIM
COUNTER
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)

INTERNAL PULL-UP VDD INTERN

AL
CLOCK
S
ILLEGA
L
CLOCK
OPCOD
CONTRO
E
L
(FROM
CPU)
ILLEGA
L
ADDRE
SS
(FROM
ADDRE
SS MAP
DECOD
ERS)
COP
TIMEO
UT
(FROM
COP
MODUL
E) LVI

MASTER
RESET
CONTROL

RESET

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

RESET PIN
LOGIC
INTERRUPT CONTROL AND
PRIORITY DECODE

13.2 RST and IRQ Pins InitializationRST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ function
13.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MC
are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-2.
 MODULE STOP MODULE WAIT
CPU STOP (FROM CPU) CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
STOP/
WAIT
CONTRO
L

BUSCLKX4 (FROM OSCILLATOR)

BUSCLKX2 (FROM OSCILLATOR)


2

CLOCK
CLOCK
CONTRO
GENERATORS
L

ationRST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be activated by programing CONFIG2 accordingl
 k Control and Generation
or provides system clock signals for the CPU and peripherals on the MCU. The system clocks
n incoming clock, BUSCLKX2, as shown in Figure 13-2.
 SIM COUNT
2
SIM

FROM OSCILLATOR
FROM OSCILLATOR
BUSCLKX2

ER
BUS CLOCK
GENERATORS
Figure 13-2. SIM Clock Signals
13.3.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four
13.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are
an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The IBUS c
completion of the time out.
13.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM c
peripheral clocks do not become active until after the stop delay time out. This time out is sele
BUSCLKX4 cycles. See 13.7.2 Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other m
wait mode subsection of each module to see if the module is active or inactive in wait mode. So
programmed to be active in wait mode.

13.4 Reset and System Initialization

The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
(IRST). IRST causes all registers to be returned to their default values and all modules to be ret
states.
An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external reset does not
sets a corresponding bit in the SIM reset status register (SRSR). See 13.8 SIM Registers.
13.4.1 External Pin ResetThe RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all pr
 BUSCLKX4

BUSCLKX2

quency is the oscillator frequency (BUSCLKX4) divided by four.

generates a reset, the clocks to the CPU and peripherals are inactive and held in
4096 BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon

Wait Mode
nterrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter. The CPU and
active until after the stop delay time out. This time out is selectable as 4096 or 32
p Mode.
inactive. The SIM also produces two sets of clocks for other modules. Refer to the
dule to see if the module is active or inactive in wait mode. Some modules can be
mode.

alization
:
)

module (COP)
LVI)

ector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal
o be returned to their default values and all modules to be returned to their reset

ounter (see 13.5 SIM Counter), but an external reset does not. Each of the resets
M reset status register (SRSR). See 13.8 SIM Registers.
s include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set a
 BUSCLKX2
ADDRESS BUS
RST Figure 13-3. External Reset Timing

PC VECT H VECT
L

13.4.2 Active Resets from Internal Sources

The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in
CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is
activity on the RST pin.
NOTEFor POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles during which the SIM forces the RST pin low. The interna

IRST
RST
BUSCLKX4 ADDRESS
BUS

32CYCLES 32CYCLES
Figure 13-4. Internal Reset Timing
VECTOR HIGH

RSTPULLEDLOWBYMCU
SCLKX2
RESS BUS
ernal Reset Timing

VECT H VECT
L

nput after a POR. Setting the RSTEN bit in the

tion. This section assumes the RSTEN bit is set when describing

during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 13-4.The

32CYCLES
Reset Timing
 ILLEGAL ADDRESS RST ILLEGAL OPCODE RST
COPRST INTERN
POR LVI AL
RESET

Figure 13-5. Sources of Internal Reset

Table 13-2. Reset Recovery Timing
Reset Recovery Type Actual Number of Cycles

POR/LVI 4163 (4096 + 64 + 3)

All others 67 (64 + 3)

13.4.2.1 Power-On ResetWhen power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate t

OSC1
PORRST
BUSCLKX4 40 32 32
BUSCLKX2 96 CY CY
RST CY CL CL
CL ES ES
ES

ADDRESS BUS
Figure 13-6. POR Recovery
13.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter cause
and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RS
internal reset sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF
counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least eve
cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to
maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set
register (BRKAR).
13.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets th
SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction
opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all inter
13.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifie
fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and re
A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down
all internal reset sources. See Figure 2-1. Memory Map for memory ranges.
13.4.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The L
reset status register (SRSR) is set, and the external reset pin (RST) is held low while the
SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4 c
CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM
down the (RST) pin for all internal reset sources.

13.5 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to al
time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves a
the computer operating properly module (COP). The SIM counter uses 12 stages for counting,
13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. Th
clocked by the falling edge of BUSCLKX4.
13.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR ci
signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state
13.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM count
interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the norma
BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications using canned oscil
require long start-up times from stop mode. External crystal applications should use the full sto
that is, with SSREC cleared in the configuration register 1 (CONFIG1).
13.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 13.7.2 Stop Mode for details.) The SIM cou
running after all reset states. See 13.4.2 Active Resets from Internal Sources for counter contro
reset recovery sequences.

13.6 Exception ControlNormal sequential program execution can be changed in three different ways:1. Interruptsa. Maskable h
Sources of Internal Reset
Reset Recovery Timing

the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-

$FFF $FFF
E F

3-6. POR Recovery

 signal. The overflow of the COP counter causes an internal reset
ster (SRSR). The SIM actively pulls down the RST pin for all

lue to location $FFFF. Writing to location $FFFF clears the COP

SIM counter output, which occurs at least every 4080 BUSCLKX4
be serviced as soon as possible out of reset to guarantee the
ut.
rupt with monitor mode when BDCOP bit is set in break auxiliary

illegal instructions. An illegal instruction sets the ILOP bit in the

set.
egister is 0, the SIM treats the STOP instruction as an illegal
SIM actively pulls down the RST pin for all internal reset sources.

nerates an illegal address reset. The SIM verifies that the CPU is
t in the SIM reset status register (SRSR) and resetting the MCU.
ot generate a reset. The SIM actively pulls down the RST pin for
ry Map for memory ranges.

DD voltage falls to the LVI trip voltage VTRIPF. The LVI bit in the SIM
nal reset pin (RST) is held low while the
fter VDD rises above VTRIPR. Sixty-four BUSCLKX4 cycles later, the
low the reset vector sequence to occur. The SIM actively pulls

module (POR) and in stop mode recovery to allow the oscillator

us (IBUS) clocks. The SIM counter also serves as a prescaler for
. The SIM counter uses 12 stages for counting, followed by a
s and supplies the clock for the COP module. The SIM counter is

er applied to the MCU. At power-on, the POR circuit asserts the

ables the oscillator to drive the bus clock state machine.
y
very. The STOP instruction clears the SIM counter. After an
te of the short stop recovery bit, SSREC, in the configuration
n the stop recovery is reduced from the normal delay of 4096
This is ideal for applications using canned oscillators that do not
ernal crystal applications should use the full stop recovery time,
register 1 (CONFIG1).

see 13.7.2 Stop Mode for details.) The SIM counter is free-
Resets from Internal Sources for counter control and internal

be changed in three different ways:1. Interruptsa. Maskable hardware CPU interruptsb. Non-maskable software interrupt instruction (SWI)2. Reset
(AS MANY INTERRUPTS AS EX
STACK CPU REGISTERS SET I BIT
LOAD PC WITH INTERRUPT VECTOR

FETCH NEXT
INSTRUCTION

UNSTACK CPU REGISTERS

EXECUTE INSTRUCTION

Figure 13-7. Interrupt Processing

Figure 13-7. Interrupt Processing
 FROMRESE
T

YES
BREAIKBINTTSEER
TR?UPT?
NO

YES
I BIT
SET?

NO

IRQ YES
INTERRUPT?

NO

TIMER YES
INTERRUPT?

NO

IST ON
CHIP)

SWI YES
INSTRUCTION
?
NO

RTI YES
INSTRUCTION
?
NO
 MODULE INTERRUPT

I BIT
ADDRESS BUS DUMM SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L
Y DUMMY STARTADDR
PC – 1[7:0] PC –
DATA BUS
1[15:8] X
Figure 13-8. Interrupt Entry
MODULE
INTERRUPT
I BIT

ADDRESS BUS SP – 4

DATA BUS CCR

R/W
Figure 13-9. Interrupt Recovery
13.6.1.1 Hardware Interrupts

A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins
the current instruction. When the current instruction is complete, the SIM checks all pending hardware
interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrup
the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interr
Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt is pending
original interrupt service routine, the pending interrupt is serviced before the LDA instruction is execu
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions. How
the INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If th
routine modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.

R/
W
 SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L
STARTADDR
1[7:0] PC – A CCR V DATA H V DATA L
OPCODE
Figure 13-8. Interrupt Entry

SP – 3 SP – 2 SP – 1 SP PC PC + 1

A X PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND

current instruction. Processing of a hardware interrupt begins after completion of

nt instruction is complete, the SIM checks all pending hardware interrupts. If
the condition code register), and if the corresponding interrupt enable bit is set,
sing; otherwise, the next instruction is fetched and executed.
t the end of an instruction execution, the highest priority interrupt is serviced first.
ens when two interrupts are pending. If an interrupt is pending upon exit from the
ending interrupt is serviced before the LDA instruction is executed.
the INT1 and INT2 return-from-interrupt (RTI) instructions. However, in the case of
nt operation.

mily, the H register is not pushed on the stack during interrupt entry. If the interrupt service
dexed addressing mode, software
t prior to exiting the routine.
 CLI
#$FF

INT
LDA BACKGROUND ROUTINE
1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
INT2 INTERRUPT SERVICE ROUTINE
PULH RTI

Figure 13-10. Interrupt Recognition Example

INT
13.6.1.2 SWI
2 Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition

Table 13-3. Interrupt Sources

INT Vector Address
Priority Source Flag Mask(1) Register
Flag
Highest Reset — — — $FFFE–$FFFF
Lowest
SWI instruction — — — $FFFC–$FFFD
IRQ pin IRQF IMASK IF1 $FFFA–$FFFB
Timer channel 0 interrupt CH0F CH0IE IF3 $FFF6–$FFF7
Timer channel 1 interrupt CH1F CH1IE IF4 $FFF4–$FFF5
Timer overflow interrupt TOF TOIE IF5 $FFF2–$FFF3
Keyboard interrupt KEYF IMASKK IF14 $FFE0–$FFE1
ADC conversion complete interrupt COCO AIEN IF15 $FFDE–$FFDF
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI inst

RTI
PSHH
13.6.2.1 Interrupt Status Register 1
Address: $FE04
Bit 7 6 5 4 3 2 1 Bit 0
 BACKGROUND ROUTINE

RUPT SERVICE ROUTINE

he interrupt mask (I bit) in the condition code register.NOTEA software interrupt pushes PC onto the stack. A software interrupt doesnot push PC – 1, as a

es

terrupt sources except the SWI instruction.

0
 0 IF5 IF4 IF3 0 IF1 0 0
R R R R R R R R
Read:Write:Reset: 0 0 0 0 0 0 0 0= ReservedFigure 13-11. Interru

R
IF14 0 0 0 0 0 0 0
R R R R R R R R
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Reserved
Figure 13-12. Interrupt Status Register 2 (INT2)

R
IF14 — Interrupt FlagsThis flag indicates the presence of interrupt requests from the sources shown in Table 13-3.1 = Interrupt req

Address: $FE06
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 0 0 0 IF15
R R R R R R R R
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Reserved
Figure 13-13. Interrupt Status Register 3 (INT3)

R
IF15 — Interrupt FlagsThese flags indicate the presence of interrupt requests from the sources shown in Table 13-3.1 = Interrupt re

13.6.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
13.6.4 Break Interrupts
The break module can stop normal program flow at a software programmable break point by a
interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break
the SWI vector location. Refer to the break interrupt subsection of each module to see how eac
by the break state.
13.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break
select whether flags are protected from being cleared by properly initializing the break clear fla
in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. T
registers to be freely read and written during break mode without losing status flag information
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag rem
when break mode is exited. Status flags with a two-step clearing mechanism — for example, a
followed by the read or write of another — are protected, even when the first step is accomplis
break mode. Upon leaving break mode, execution of the second step will clear the flag as norm

13.7 Low-Power ModesExecuting the WAIT or STOP instruction puts the MCU in a low power- consumption mode for standby s

ADDRESS BUS WAIT WAIT ADDR SAM

DATA BUS ADDR PREVIOUS + 1 NEXT E
R/W DATA OPCODE
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 13-14. Wait Mode Entry Timing
 A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interru

32 32
CYCLE CYCLE
S S
ADDRESS BUS $6E0B $6E0 $6E0C RSTVCTH
$00FE RSTVCTL
$00FD
DATA BUS $A6 B $A $00FF
$0 $0 $00FC
$6
EXITSTOPWAIT $A6 6 1 B E
$A6 $A6 $A6
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 13-15. Wait Recovery from Interrupt
ADDRESS BUS
DATA BUS
RST
BUSCLKX4
Figure 13-16. Wait Recovery from Internal Reset
13.7.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request
cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery t
Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the C
Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1).
recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32. This is ideal f
oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by clearing the SSREC bit.

The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the r
0 0 0= ReservedFigure 13-11. Interrupt Status Register 1 (INT1) IF1 and IF3–IF5 — Interrupt FlagsThese flags indicate the presence of i

d:
e:
0 0 0 0
rved
atus Register 2 (INT2)

om the sources shown in Table 13-3.1 = Interrupt request present0 = No interrupt request presentBit 0–6 — Always read 013.6.2.3 Interrupt Status Regis

2 1 Bit 0

d:
e:
0 0 0 0
rved
atus Register 3 (INT3)
 from the sources shown in Table 13-3.1 = Interrupt request present0 = No interrupt request presentBit 1–7 — Always read 0

and cannot be arbitrated.

ftware programmable break point by asserting its break

.) The SIM puts the CPU into the break state by forcing it to
section of each module to see how each module is affected

modules can be cleared during break mode. The user can

y properly initializing the break clear flag enable bit (BCFE)

l not be cleared while in break mode. This protection allows

de without losing status flag information.
Once cleared in break mode, a flag remains cleared even
clearing mechanism — for example, a read of one register
d, even when the first step is accomplished prior to entering
second step will clear the flag as normal.

CU in a low power- consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is de

SAM
SAM E SAM
E E
WAIT opcode, depending on the last instruction.
ode Entry Timing
 upt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, th

RSTVCTH
$00FE RSTVCTL
$00FD
$00FC

CPU interrupt OR break interrupt

overy from Interrupt

ocks are disabled. An interrupt request from a module can

egins after the selected stop recovery time has elapsed.

USCLKX4) in stop mode, stopping the CPU and peripherals.

he configuration register 1 (CONFIG1). If SSREC is set, stop
CLKX4 cycles down to 32. This is ideal for the internal
which do

earing the SSREC bit.

eginning of stop recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and Figure 13-18 shows the stop mode r
 CPUSTOP
ADDRESS BUS STOP STOP ADDR
ADDR PREVIOUS + 1 NEXT
DATA BUS
DATA OPCODE
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 13-17. Stop Mode Entry Timing

STOP RECOVERY PERIOD

BUSCLKX4
INTERRUPT STOP +1
ADDRESS BUS STOP + 2
STOP + 2
Figure 13-18. Stop Mode Recovery from Interrupt
13.8 SIM RegistersThe SIM has three memory mapped registers. Table 13-4 shows the mapping of these registers.Table 13-4

Address Register Access Mode

$FE00 BSR User
$FE01 SRSR User
$FE03 BFCR User
 SAM SAM
NEXT E SAM E SAM
OPCODE
R/W E E
and data or the STOP opcode, depending on the last instruction.
13-17. Stop Mode Entry Timing

STOP RECOVERY PERIOD

STOP + 2 SP SP – SP – SP –
STOP + 2 1 2 3
Stop Mode Recovery from Interrupt
registers. Table 13-4 shows the mapping of these registers.Table 13-4. SIM Registers
 13.8.1 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the register. A
set the individual flag bits but do not clear the register. More than one reset source can be flag
depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time
Address: $FE01

Bit 7 6 5 4 3 2 1 Bit 0
POR PIN COP ILOP ILAD MODRST LVI 0

Read:
Write:
POR: 1 0 0 0 0 0 0 0
= Unimplemented
Figure 13-19. SIM Reset Status Register (SRSR) POR — Power-On Reset Bit
1 = Last reset caused by POR circuit 0 = Read of SRSR
PIN — External Reset Bit 1 = Last reset caused by external reset pin (RS
of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter 0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented address
1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF a
VTST
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset Bit
1 = Last reset caused by LVI circuit 0 = POR or read of SRSR
f the last reset. The status register will automatically clear
nd clears all other bits in the register. All other reset sources
More than one reset source can be flagged at any time
or external
if the power supply has a slow rise time.

2 1 Bit 0

0 0

wer-On Reset Bit

t reset caused by external reset pin (RST) 0 = POR or read

of SRSR

ead of SRSR
opcode from an unimplemented address)
l address 0 = POR or read of SRSR

or locations $FFFE and $FFFF are $FF after POR while IRQ 

SRSR
 13.8.2 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits whil
break state.
Address: $FE03

Bit 7 6 5 4 3 2 1 Bit 0
BCFE R R R R R R R

Read:
Write:
Reset: 0
= Reserved
Figure 13-20. Break Flag Control Register (BFCR)

R
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the
state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
les software to clear status bits while the MCU is in a

2 1 Bit 0

0
d
trol Register (BFCR)

accessing status registers while the MCU is in a break

E bit must be set.
 Chapter 14
Timer Interface Module (TIM)
14.1 IntroductionThis section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a timing

14.2 Features
Features of the TIM include the following:
• Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse width modulation (PWM) signal generation
• Programmable TIM clock input
– 7-frequency internal bus clock prescaler selection
– External TIM clock input
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits

14.3 Pin Name ConventionsThe TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are lis

TCH0 TCH1 TCLK

PTA0/TCH0 PTA1/TCH1 PTA2/TCLK

odule (TIM)
es the timer interface module (TIM). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width

the following:
ut compare channels
e, or any-edge input capture trigger
put compare action
d pulse width modulation (PWM) signal generation
k input
s clock prescaler selection

o up-count operation
on overflow
eset bits

input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are listed in Table 14-1. The generic pin name appear in the text that
 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

CLOCK GENERATOR
(OSCILLATOR)
DDRA
PTA

M68HC08 CPU

SYSTEM INTEGRATION
MODULE

SINGLE INTERRUPT
MODULE

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

DDRB
PTB

BREAK MODULE

POWER-ON RESET
MODULE

MC68HC908QY4 AND MC68HC908QT4

4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH

KEYBOARD INTERRUPT
MODULE
 8-BIT ADC

16-BIT TIMER
MODULE

128 BYTES RAM

COP MODULE

POWER SUPPLY

MONITOR ROM

RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Intro
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1

Figure 14-1. Block Diagram Highlighting TIM Block and Pins

/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4
1/AD3/KBI5

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

Pins have internal (about 30K Ohms) pull up
High current sink and source capability
Pins have programmable keyboard interrupt and pull up
Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
available on the MC68HC908QY1 and MC68HC908QT1

Figure 14-1. Block Diagram Highlighting TIM Block and Pins

VD
D

VSS
 14.4 Functional DescriptionFigure 14-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM cou

PRESCALER SELECT

PS2 PS1 PS0

PTA2/IRQ/KBI2/TCLK
PRESCALER

INTERNAL BUS CLOCK

TSTOP
TRST
TOF INTERRUPT
LOGIC
TOIE

TOV0 PORT
LOGIC
CH0MAX

CH0F
INTERRUPT
LOGIC
A CH0IE
MS0B
TOV1 PORT
LOGIC
CH1MAX

CH1F
INTERRUPT
LOGIC
A CH1IE
16-BIT COMPARATOR
TMODH:TMODL
ELS0B ELS0A

16-BIT COMPARATOR
TCH0H:TCH0L
16-BIT LATCH
ELS1B ELS1A
 TCH1
Figure 14-2. TIM Block Diagram

16-BIT COMPARATOR
TCH1H:TCH1L
16-BIT LATCH

16-BIT
COUNTER

CHANNEL
0

CHANNEL
1
14.4.1 TIM Counter Prescaler
The TIM clock source is one of the seven prescaler outputs or the TIM clock pin, TCLK. The pres
seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM statu
register (TSC) select the TIM clock source.
14.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occur
edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM cou
channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captur
TIM central processor unit (CPU) interrupt requests.
14.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable
and frequency. When the counter reaches the value in the registers of an output compare chan
set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests
14.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 1
Compare. The pulses are unbuffered because changing the output compare value requires writ
over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could
operation for up to two counter overflow periods. For example, writing a new value before the c
old value but after the counter reaches the new value prevents any compare during that count
Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may
to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on
• When changing to a smaller value, enable channel x output compare interrupts and write t
output compare interrupt routine. The output compare interrupt occurs at the end of the curren
pulse. The interrupt routine has until the end of the counter overflow period to write the new va
• When changing to a larger output compare value, enable TIM overflow interrupts and write
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current c
period. Writing a larger value in an output compare interrupt routine (at the end of the current
two output compares to occur in the same counter overflow period.
14.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appe
pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and ch
compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously con
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1)
2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-c

TCLK

TCH0
 TCH1
Figure 14-2. TIM Block Diagram

MS
0

MS
1
r
the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates
ernal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control
lock source.

n, the TIM can capture the time at which an external event occurs. When an active
nput capture channel, the TIM latches the contents of the TIM counter into the TIM
xL. The polarity of the active edge is programmable. Input captures can generate
U) interrupt requests.

tion, the TIM can generate a periodic pulse with a programmable polarity, duration,
nter reaches the value in the registers of an output compare channel, the TIM can
el pin. Output compares can generate TIM CPU interrupt requests.
mpare
can generate unbuffered output compare pulses as described in 14.4.3 Output
uffered because changing the output compare value requires writing the new value
n the TIM channel registers.
e TIM channel registers to change an output compare value could cause incorrect
er overflow periods. For example, writing a new value before the counter reaches the
r reaches the new value prevents any compare during that counter overflow period.
errupt routine to write a new, smaller output compare value may cause the compare
ss the new value before it is written.
synchronize unbuffered changes in the output compare value on channel x:
ler value, enable channel x output compare interrupts and write the new value in the
ine. The output compare interrupt occurs at the end of the current output compare
as until the end of the counter overflow period to write the new value.
r output compare value, enable TIM overflow interrupts and write the new value in
tine. The TIM overflow interrupt occurs at the end of the current counter overflow
in an output compare interrupt routine (at the end of the current pulse) could cause
in the same counter overflow period.
are
d to form a buffered output compare channel whose output appears on the TCH0
of the linked pair alternately control the output.
annel 0 status and control register (TSC0) links channel 0 and channel 1. The output
nnel 0 registers initially controls the output on the TCH0 pin.
egisters enables the TIM channel 1 registers to synchronously control the
s. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status a

OVERFLOW OVERFLOW OVERFLOW

PERIOD

PULSE
WIDTH

POLARITY = 1 TCHx
(ELSxA = 0) TCHx
POLARITY = 0
(ELSxA = 1)

OUTPUT COMPARE OUTPUT COMPARE

Figure 14-3. PWM Period and Pulse Width

14.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 14.4.4 Pulse Width
The pulses are unbuffered because changing the pulse width requires writing the new pulse width val
value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incor
up to two PWM periods. For example, writing a new value before the counter reaches the old value bu
reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the c
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write th
output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse
routine has until the end of the PWM period to write the new value.
• When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a la
output compare interrupt routine (at the end of the current pulse) could cause two output compares t
PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output comp
0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise
compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larg
14.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 p
registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1
registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enab
1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each
overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. T
monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. W
is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.

NOTE
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Us
track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel r
as generating
unbuffered PWM signals.
14.4.4.3 PWM InitializationTo ensure correct operation when generating unbuffered or buffered PWM signals, use the following initializati

14.5 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo va
the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM ov
requests. TOF and TOIE are in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output com
channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt ena
Channel x TIM CPU interrupt requests are enabled when CHxIE =1. CHxF and CHxIE are in the
status and control register.
14.6 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode.
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM register
by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mod
If TIM functions are not required during wait mode, reduce power consumption by stopping the
executing the WAIT instruction.
14.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be clea
state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bit
state. See 13.8.2 Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a sta
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its defa
can read and write I/O registers during the break state without affecting status bits. Some statu
step read/write clearing procedure. If software does the first step on such a bit before the brea
change during the break state as long as BCFE is at 0. After the break, doing the second step c
14.8 Input/Output Signals
Port A shares three of its pins with the TIM. Two TIM channel I/O pins are PTA0/TCH0 and PTA1/
alternate clock source is PTA2/TCLK.
14.8.1 TIM Clock Pin (PTA2/TCLK)
PTA2/TCLK is an external clock input that can be the clock source for the TIM counter instead of
internal bus clock. Select the PTA2/TCLK input by writing 1s to the three prescaler select bits, P
TIM Status and Control Register.) When the PTA2/TCLK pin is the TIM clock input, it is an input r
pin initialization.
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1)
Each channel I/O pin is programmable independently as an input capture pin or an output comp
can be configured as a buffered output compare or buffered PWM pin.
14.9 Input/Output Registers
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
tion, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpos

OVERFLOW

OUTPUT COMPARE

dth
ed in 14.4.4 Pulse Width Modulation (PWM).
the new pulse width value over the old

value could cause incorrect operation for

eaches the old value but after the counter

h value may cause the compare to be

se width on channel x:
e interrupts and write the new value in the
end of the current pulse. The interrupt

d write the new value in the TIM overflow

WM period. Writing a larger value in an
two output compares to occur in the same

e. Toggling on output compare prevents reliable

nt of software error or noise. Toggling on output
e width to a new, much larger value.

appears on the TCH0 pin. The TIM channel

channel 0 and channel 1. The TIM channel 0

hannel 1 registers enables the TIM channel
xt PWM period. At each subsequent
e ones written to last. TSC0 controls and
ister (TSC1) is unused. While the MS0B bit

ctive channel registers. User software should

iting to the active channel registers is the same
als, use the following initialization procedure:1. In the TIM status and control register (TSC):a. Stop the TIM counter by setting the TIM stop bit, TST

r reaches the modulo value programmed in

it, TOIE, enables TIM overflow CPU interrupt

ut capture or output compare occurs on

channel x interrupt enable bit, CHxIE.
xF and CHxIE are in the TIM channel x
mode.
t mode the TIM registers are not accessible
the MCU out of wait mode.
mption by stopping the TIM before

er modules can be cleared during the break

tware to clear status bits during the break

to the BCFE bit. If a status bit is cleared

k state.
With BCFE at 0 (its default state), software
g status bits. Some status bits have a two-
ch a bit before the break, the bit cannot
doing the second step clears the status bit.

e PTA0/TCH0 and PTA1/TCH1 and an

TIM counter instead of the prescaled

e prescaler select bits, PS[2–0]. (See 14.9.1
ock input, it is an input regardless of port

re pin or an output compare pin. PTA0/TCH0

 14.9.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $0020
Bit 7 6 5 4 3 2 1 Bit 0

TOF TOIE TSTOP 0 0 PS2 PS1 PS0

0 TRST
Read:
Write:
Reset: 0 0 1 0 0 0 0 0
= Unimplemented
Figure 14-4. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the T
registers. Clear TOF by reading the TIM status and control register when TOF is set and then wr
another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF ha
Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clea
Writing a 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears
1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets
stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active

NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. When the TSTOP bit is
configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared.
When using TSTOP to stop the timer counter, see if any timer flags are set. If a timer flag is set, it must be cleared b
clearing the flag, then setting TSTOP again.
 wing:

1 Bit 0

0 0

TIM Overflow Flag Bit

the modulo value programmed in the TIM counter modulo
ol register when TOF is set and then writing a 0 to TOF. If
ce is complete, then writing 0 to TOF has no effect.
inadvertent clearing of TOF. Reset clears the TOF bit.

the TOF bit becomes set. Reset clears the TOIE bit.
terrupts disabled

mes when TSTOP is cleared. Reset sets the TSTOP bit,

P bit.

ed to exit wait mode. When the TSTOP bit is set and the timer is
the TSTOP bit is cleared.
set. If a timer flag is set, it must be cleared by clearing TSTOP, then
 TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no e
registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter
reads as a 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTESetting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000.PS[2:0] — Prescaler Select BitsThese re

PS2 PS1 PS0 TIM Clock Source

0 0 0 Internal bus clock ÷ 1
0 0 1 Internal bus clock ÷ 2
0 1 0 Internal bus clock ÷ 4
0 1 1 Internal bus clock ÷ 8
1 0 0 Internal bus clock ÷ 16
1 0 1 Internal bus clock ÷ 32
1 1 0 Internal bus clock ÷ 64
1 1 1 PTA2/TCLK
14.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counte
byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH d
latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset
the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break in
TCNTL retains the value latched during the break.

Address: $0021 TCNTH

Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

0 0 0 0 0 0 0 0
$0022 TCNTL
Bit 7 6 5 4 3 2 1 Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 0 0 0
= Unimplemented
Read: Write:
Reset:

Address:
 Read: Write:
Reset:

Figure 14-5. TIM Counter Registers (TCNTH:TCNTL)

14.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TI
the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts
(TMODL) is written. Reset sets the TIM counter modulo registers.
he TIM prescaler. Setting TRST has no effect on any other
ed automatically after the TIM counter is reset and always

lue of $0000.PS[2:0] — Prescaler Select BitsThese read/write bits select either the PTA2/TCLK pin or one of the seven prescaler outputs as the input to th

ow bytes of the value in the TIM counter. Reading the high

a buffer. Subsequent reads of TCNTH do not affect the
counter registers. Setting the TIM reset bit (TRST) also clears

by reading TCNTL before exiting the break interrupt. Otherwise,

egisters (TCNTH:TCNTL)

value for the TIM counter. When the TIM counter reaches
and the TIM counter resumes counting from $0000 at the
bits the TOF bit and overflow interrupts until the low byte
egisters.
 Address: $0023 TMODH
Bit 7 6 5 4 3 2

Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Write:
Reset: 1 1 1 1 1 1

Address: $0024 TMODL

Bit 7 6
5 4 3 2
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Write:
Reset: 1 1 1 1 1 1
Figure 14-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
14.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
 1 Bit 0

Bit 9 Bit 8

1 1

1 Bit 0
Bit 1 Bit 0

1 1

trigger
 Address: $0025 TSC0
Bit 7 6 5 4 3 2

Read:
Write:
Reset: 0 0 0 0 0 0
Address: $0028 TSC1
Bit 7 6
5 4 3 2
Read:
Write:
Reset: 0 0 0 0 0 0
CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
0
CH1F CH1IE 0 MS1A ELS1B ELS1A TOV1 CH1MAX
0

= Unimplemented
Figure 14-7. TIM Channel Status and Control Registers (TSC0:TSC1)
CHxF — Channel x Flag BitWhen channel x is an input capture channel, this read/write bit is set when an active edge occurs on t

When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 14-3). Reset clears the MSxA
 1 Bit 0

0 0

1 Bit 0

0 0

egisters (TSC0:TSC1)
set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registe

Table 14-3). Reset clears the MSxA bit.1 = Initial output level low0 = Initial output level high
 NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM st
(TSC).
Table 14-3. Mode, Edge, and Level Selection

MSxB MSxA ELSxB ELSxA Mode

X 0 0 0 Output preset
X 1 0 0
0 0 0 1 Input capture
0 0 1 0
0 0 1 1
0 1 0 0 Output compare
or PWM
0 1 0 1
0 1 1 0
0 1 1 1
1 X 0 1 Buffered output
compare or
1 X 1 0
buffered PWM
1 X 1 1
ELSxB and ELSxA — Edge/Level Select BitsWhen channel x is an input capture channel, these read/write bits control the active e

NOTE
After initially enabling a TIM channel register for input capture operation and selecting the edge sensitivity, clear CHx
erroneous edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channe
TIM counter overflows. When channel x is an input capture channel, TOVx has no effect Reset clears t
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the s

CHxMAX — Channel x Maximum Duty Cycle Bit

When the TOVx bit is at a 1, setting the CHxMAX bit forces the duty cycle of buffered and unb
to 100%. As Figure 14-8 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is clea
 NOTE
he MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ble 14-3. Mode, Edge, and Level Selection

Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
n channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x.When channel x is an output compare cha

nput capture operation and selecting the edge sensitivity, clear CHxF to ignore any

nel, this read/write bit controls the behavior of the channel x output when the
n input capture channel, TOVx has no effect Reset clears the TOVx bit.
verflow.
ounter overflow.

precedence over a channel x output compare if both occur at the same time.

y Cycle Bit
the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals
CHxMAX bit takes effect in the cycle after it is set
100% duty cycle level until the cycle after CHxMAX is cleared.
 OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
TCHx PERIO
DOUTPUT OUTPUT OUTPUT OUTPUT COMPARE
CHxMAX COMPARE COMPARE COMPARE

Figure 14-8. CHxMAX Latency

14.9.5 TIM Channel Registers

These read/write registers contain the captured TIM counter value of the input capture functio
compare value of the output compare function. The state of the TIM channel registers after re
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registe
input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA  0:0), writing to the high byte of the TIM channel x reg
inhibits output compares until the low byte (TCHxL) is written.

Address: $0026 TCH0H

Bit 7 6 5 4 3 2

Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Write:
Reset: Indeterminate after
Address: $0027 TCH0L reset

Bit 7 6 5 4 3 2
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Write:
Reset: Indeterminate after
Address: $0029 TCH1H reset

Bit 7 6 5 4 3 2
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Write:
Reset: Indeterminate after
Address: $02A TCH1L reset

Bit 7 6 5 4 3 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Read:
Write:
Reset: Indeterminate after reset
Figure 14-9. TIM Channel Registers (TCH0H/L:TCH1H/L)

Chapter 15 Development Support

15.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the moni
methods.
15.2 Break Module (BRK)The break module can generate a break interrupt that stops normal program flow at a defined address to
FLOW OVERFLOW

OUTPUT COMPARE

f the input capture function or the output

channel registers after reset is unknown.
the TIM channel x registers (TCHxH) inhibits

e of the TIM channel x registers (TCHxH)

1 Bit 0

Bit 9 Bit 8

1 Bit 0
Bit 1 Bit 0

1 Bit 0
Bit 9 Bit 8

1 Bit 0

ate after reset

L:TCH1H/L)

mory (MON), and the monitor mode entry

ogram flow at a defined address to enter a background program.Features include:• Accessible input/output (I/O) registers during the break Interrupt•
 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

CLOCK GENERATOR
(OSCILLATOR)
DDRA
PTA

M68HC08 CPU

SYSTEM INTEGRATION
MODULE

SINGLE INTERRUPT
MODULE

PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

DDRB
PTB

BREAK MODULE

POWER-ON RESET
MODULE

MC68HC908QY4 AND MC68HC908QT4

4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH

KEYBOARD INTERRUPT
MODULE
 8-BIT ADC

16-BIT TIMER
MODULE

128 BYTES RAM

COP MODULE

POWER SUPPLY

MONITOR ROM

RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Intro
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 15-1. Block Diagram Highlighting BRK and MON Blocks

ADDRESS BUS[15:8]
BREAK ADDR
8-BIT
8-BIT BREAK
ADDR

ESS REGISTER HIGH

COMPARATOR CONTROL

COMPARATOR
ESS REGISTER LOW

BKPT (TOSIM)
ADDRESS BUS[7:0]
Figure 15-2. Break Module Block Diagram
 ADDRESS BUS[15:0]

When the internal address bus matches the value written in the break address registers or whe
1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is
after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is
break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next in
executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break inte
generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode. When software does not change the bre
the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrup
the internal address bus matches the value written in the break address registers.
15.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
13.8.2 Break Flag Control Register and the Break Interrupts subsection for each module.
15.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxili
(BRKAR).
15.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (BSR)
• Break flag control register (BFCR)
PTA1/AD1/TCH1/KBI1
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5

TB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7

 RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
ilable on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 15-1. Block Diagram Highlighting BRK and MON Blocks

ADDRESS BUS[15:8]

BKPT (TOSIM)
ADDRESS BUS[7:0]
Figure 15-2. Break Module Block Diagram
 VD
D

VSS

ADDRESS BUS[15:0]

ddress bus matches the value written in the break address registers or when software writes a
the break status and control register, the CPU starts a break interrupt by:
ruction register with the SWI instruction
gram counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
timing is:
ddress is placed at the address of the instruction opcode, the instruction is not executed until
he break interrupt routine.
ddress is placed at an address of an instruction operand, the instruction is executed before the

writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is

address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be
usly.
 ced at the address of the instruction opcode. When software does not change the break address and clears
nterrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when
es the value written in the break address registers.
ing Break Interrupts
dule (SIM) controls whether or not module status bits can be cleared during the break state.
flag control register (BFCR) enables software to clear status bits during the break state. See
Register and the Break Interrupts subsection for each module.
terrupts
timer counter.
nterrupts
a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register

sters
d monitor operation of the break module:
ol register (BRKSCR)
high (BRKH)
low (BRKL)
BSR)
ster (BFCR)
 15.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits
Address: $FE0B

Bit 7 6 5 4 3 2 1

Read:
Write:
Reset: 0 0 0 0 0 0 0
= Unimplemented
BRKE BRKA 0 0 0 0 0 0

Figure 15-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a
bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match 0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to
break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset clears th
1 = Break address match
0 = No break address match
15.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired bre
Reset clears the break address registers.

Address: $FE09

Bit 7 6 5 4 3 2
Read: Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 15
Write:
Reset: 0 0 0 0 0 0
Figure 15-4. Break Address Register High (BRKH)
Address: $FE0A

Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 15-5. Break Address Register Low (BRKL)
ule enable and status bits.

1 Bit 0

0 0

Enable Bit
Clear BRKE by writing a 0 to

ch occurs. Writing a 1 to BRKA generates a

k routine. Reset clears the BRKA bit.

w bytes of the desired breakpoint address.

1 Bit 0
Bit 9 Bit 8

0 0
(BRKH)

Bit 0

0 0 0
(BRKL)
 15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP w
state of break interrupt with monitor mode.
Address: $FE02

Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 0 0 0 BDCOP

Read:
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 15-6. Break Auxiliary Register (BRKAR)
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt 0 = COP enabled during break interrupt
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode
used in emulation mode.

Address: $FE00
Bit 7 6 5 4 3 2 1 Bit 0
R R R R R R SBSW R
Note (1)

Read:
Write:
Reset: 0
= Reserved 1. Writing a 0 clears SBSW.
Figure 15-7. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address o
subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt

R
t enables software to disable the COP while the MCU is in a

2 1 Bit 0

0 0

eset clears the BDCOP bit.

ng break interrupt

a break caused an exit from wait mode. This register is only

2 1 Bit 0

he user can modify the return address on the stack by

 15.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits whil
break state.
Address: $FE03

Bit 7 6 5 4 3 2 1 Bit 0
BCFE R R R R R R R

Read:
Write:
Reset: 0
= Reserved
Figure 15-8. Break Flag Control Register (BFCR)

R
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the
state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
15.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If ena
module will remain enabled in wait and stop modes. However, since the internal address bus d
these modes, a break interrupt will never be triggered.

15.3 Monitor Module (MON)

This subsection describes the monitor module (MON) and the monitor mode entry methods. T
debugging and programming of the microcontroller unit (MCU) through a single-wire interface
computer. Monitor mode entry can be achieved without use of the higher test voltage, V TST, as
long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requiremen
in-circuit programming.
Features include:
• Normal user-mode pin functionality on most pins
• One pin dedicated to serial communication between MCU and host computer
• Standard non-return-to-zero (NRZ) communication with host computer
• Execution of code in random-access memory (RAM) or FLASH
• FLASH memory security feature(1)
• FLASH memory programming interface
• Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz
• Simple internal oscillator mode of operation (no external clock or high voltage)
• Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF co
$FF)
• Standard monitor mode entry if high voltage is applied to IRQ

1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH
unauthorized users.
15.3.1 Functional DescriptionFigure 15-9 shows a simplified diagram of monitor mode entry.The monitor module receives and exe
nables software to clear status bits while the MCU is in a

2 1 Bit 0

d:
e:
0
rved
ontrol Register (BFCR)

by accessing status registers while the MCU is in a break

FE bit must be set.

er- consumption standby modes. If enabled, the break

wever, since the internal address bus does not increment in

nd the monitor mode entry methods. The monitor allows

it (MCU) through a single-wire interface with a host
t use of the higher test voltage, V TST, as
hus reducing the hardware requirements for

en MCU and host computer

with host computer
M) or FLASH

internal frequency of 2.4576 MHz

ternal clock or high voltage)
set vector is blank ($FFFE and $FFFF contain

plied to IRQ

rategy is to make reading or copying the FLASH difficult for

nitor mode entry.The monitor module receives and executes commands from a host computer. Figure 15-10, Figure 15-11, and Figure 15-12 show exampl
 POR RESET
NO
IRQ
PTA0 = 1, NO RESET VECTOR
BLANK?
YES
NOR USER
IS R PO
EXE MONITO
YES
DOES

ESET YES
R?

N
O

RESET OCCUR?

CONDITIONSFROM Table 15-1

FORCED MONITOR
MODE

MAL MODE

NORMAL MONITOR
MODE

INVALID USER
MODE
HOST SENDS
8 SECURITY BYTES
 DISABLE FLASH

ENABLE FLASH

MONITOR MODE ENTRY

DEBUGGING AND FLASH PROGRAMMING (IF FLASH

IS ENABLED)

CUTE
R CODE

NO
Figure 15-9. Simplified Monitor Mode Entry Flowchart
 ARE ALL
YES N
SECURITY
O
BYTES
CORRECT?

CONDITIONSFROM Table 15-1

 DEBUGGING AND FLASH PROGRAMMING (IF FLASH
IS ENABLED)

Figure 15-9. Simplified Monitor Mode Entry Flowchart

 V
DD

Figure 15-10. Monitor Mode Circuit (External Clock, with High Voltage)
10
k* VDD

3 C1– 15 1 F RST (PTA3)

+ 4 MAX2
C2+ V+ 2 + 0.1 F
OSC110 k*
9.8304 MHz
DD V
IRQ (PTA2)
5 32
C2– V
V–D 6 74HC125
CLOCK 10 k
1 D 1 F (PTA5)
1 +

+ 6 + VTST
1 1 F C1+ 1
FDB9 F
3 1 1
C1– 5 + F 1 10
k PTA k*
4
V 2 IRQ 1
1 2 + C2+ 7 + 10 6VD 5 (PTA2)
F V– 6 9 74HC125 D PTA0
3 5 8 1 F 2 3 4 9.1
C2– + 10 V
DB9 5 1 k
74HC125
PTA4 1 6 5 PTA
2 7 0 74HC125
3 8 9 4 * Value not critical 0
2 3
Figure 15-11.
1 Monitor Mode Circuit (External Clock, No High
VSSVoltage)
5
N.C RST
. (PTA3) * Value
VD not
critical
D

MAX2
VD
32
D
1 1 9.8304 MHz
+ C1+ 6 + CLOCK OSC1
1 1 (PTA5)
F F

N.C. RST VDD

(PTA3)

MAX2 Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage)
VD N.C OSC1
32
D . (PTA5)
 MAX2
VD N.C OSC1
32 can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM b
Simple monitor commands
1 D . (PTA5)
1
+ C1+ 6 +
1
1 F
F IRQ PTA
3 1 1
(PTA2) 1
5 + F
C1–
10 k*
4
V+ 2 VDD PTA
+ C2+ 4
1 V– 6
F 5 C2 1 F
– + 10
DB k
74HC125
29 7 1 6 5 PTA VSS
0 74HC1
9 0
3 8 2 25 4
3
5 1
* Value not
critical

Table 15-1. Monitor Mode Signal Requirements and Options

 V
DD

h High Voltage)
V
DD
0.1 F

IRQ (PTA2) PTA1 N.C.

PTA4 N.C.

VD
D

10
k*

PTA0 V
SS
10
k*

o High Voltage)

* Value
VD not
critical
D

VD
D

0 .1 F
o High Voltage)
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host com

N.C
.

N.C
.

nd Options
 IRQ RST Reset Serial Mode Communication Speed
(PTA2) (PTA3) Vector Communi- Selection
cation
Mode COP
PTA0 PTA1 PTA4 External Bus Baud
Clock Frequency Rate
Normal V
TST V
DD X 1 1 0 Disabled 9.8304 2.4576 9600
Monitor MHz MHz
Forced V
DD X $FFFF 1 X X Disabled 9.8304 2.4576 9600
Monitor (blank) MHz MHz
V
SS X $FFFF 1 X X Disabled X 3.2 MHz 9600
(blank) (Trimmed)
User X X Not X X X Enabled X X X
$FFFF
MON08 V
TST [6] RST COM [8] MOD0 MOD1 OSC1
Function [4] — [12] [10] — [13] — —
[Pin No.]
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscil
frequency / 256 and baud rate using internal oscillator is bus frequency / 335.
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.

NC 1 2 GND
NC 3 4 RST
NC 5 6 IRQ
NC 7 8 PTA0
NC 9 10 PTA4
NC 11 12 PTA1
OSC1 13 14 NC
V
DD 15 16 NC

The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latc
values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 15.3.2 Security)
bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is r
command.
15.3.1.1 Normal Monitor Mode
RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is
pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in monitor mod
functions will be determined by the settings in the configuration registers (see
Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH an
will read the IRQ pin state only if IRQEN is set in the CONFIG2 register.

If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied
15.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then startup port pin requirements and c
(PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
NOTEIf the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR
 Comments

Provide external
clock at OSC1.
Provide external
clock at OSC1.
Internal clock is
active.

d rate using external oscillator is bus

ctor.

e monitor mode is latched, the

(see 15.3.2 Security). After the security

, indicating that it is ready to receive a

tively as long as VTST is applied to the IRQ

rating in monitor mode, but the pin
(see
VTST lowered, the BIH and BIL instructions

long as VTST is applied to IRQ.

in requirements and conditions,

performing in-circuit
he initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to
 Table 15-2. Mode Difference
Modes Functions
Reset Vector Reset Vector Break Vector Break Vector SWI SWI
High Low High Low Vector High Vector Low
User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
15.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data
and receive baud rates must be identical.
NEXT
START STAR
Figure 15-13. Monitor Data Format BIT 6
STO T BIT
BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 P
15.3.1.5 Break Signal
BIT 7 BIT

A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
Figure 15-14. Break Transaction
15.3.1.6 Baud Rate

The monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the approp

MISSING STOP
BIT 2-STOP BIT DELAY
BEFOREZERO ECHO

0 1 2 3 4 5 6 0 1 2 3 4 5 6
7 7
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-
of each command allows the host to send a break character to cancel the command. A delay of two bi
before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read c
after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
 e

-zero (NRZ) mark/space data format. Transmit

NEXT
STAR
T BIT

When the monitor receives a break signal,

hoes back the break signal.

nal oscillator and the state of the appropriate pins as shown in Table 15-1.Table 15-1 also lists the bus frequencies to achieve standard baud rates. The effe

ELAY
ECHO

2 3 4 5 6

pin for error checking. An 11-bit delay at the end

command. A delay of two bit times occurs
he data returned by a read command appears
 FROM HOST

Notes: 3 = Cancel command delay, 11 bit times

1 = Echo delay, 2 bit times 4 = Wait 1 bit time before sending next byte.
2 = Data return delay, 2 bit times

Figure 15-15. Read Transaction

FROM HOST

Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-16. Write Transaction

A brief description of each monitor mode command is given in Table 15-3 through Table 15-8.Table 15-3. READ (Read Mem

ADDRES ADDRESS ADDRESS

WRITE DATA
S HIGH HIGH
ADDRESS LO
WRITE 1 DATA
LOW W
3 ECHO 3 1 1 3 1
3

ADDRESS ADDRESS ADDRESS

REA REA HIGH
ADDRESS LO LO DAT
D D A
4 1 4 HIGH 4 W 1 W 3,
ECHO 1 2

Description Read byte from memory

Operand 2-byte address in high-byte:low-byte order
Data Returned Returns contents of specified address
Opcode $4A
Command Sequence
SENT TO MONITOR

READ READ
ADDRESS ADDRESS ADDRESS
ADDRESS DATA
HIGH HIGH LOW
LOW

RETUR
ECHO N
lay, 11 bit times
e sending next byte.

ion

mes
t byte.
ion

le 15-8.Table 15-3. READ (Read Memory) Command

2,
3

DAT
A
4
RETUR
N
 Table 15-4. WRITE (Write Memory) Command
Description Write byte to memory
Operand 2-byte address in high-byte:low-byte order; low byte followed by data
byte
Data Returned None
Opcode $49
Command Sequence
FROM HOST

WRITE WRITE ADDRESS ADDRESS ADDRESS ADDRESS DATA DATA HIGH HIGH LOW
LOW

ECHO
Table 15-5. IREAD (Indexed Read) Command
Description Read next 2 bytes in memory from last address accessed
Operand None
Data Returned Returns contents of next two addresses
Opcode $1A
Command Sequence
FROM HOST
IREAD IREAD DATA DATA
ECHO
RETURN

Table 15-6. IWRITE (Indexed Write) Command

Description Write to last address accessed + 1
Operand Single data byte
Data Returned None
Opcode $19
FROM HOST Command Sequence
IWRITE ECHO IWRITE DATA DATA

A sequence of IREAD or IWRITE commands can access a block of memory sequentially over th
memory map.
Command

Command

Command

memory sequentially over the full 64-Kbyte

 Table 15-7. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand None
Data Returned Returns incremented stack pointer value (SP + 1) in high-byte:low-byte
order
Opcode $0C
Command Sequence
FROMHOST
READSP READSP SP SP
HIGH LOW
ECHO
RETURN

Table 15-8. RUN (Run User Program) Command

Description Executes PULH and RTI instructions
Operand None
Data Returned None
Opcode $28
Command Sequence
FROM HOST
RUN RUN ECHO

The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN comm
to execute the PULH and RTI instructions. Before sending the RUN command, the host can mod
registers to prepare to run the host program. The READSP command returns the incremented s
SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.

SP
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP + 7

HIGH BYTE OF INDEX REGISTER

CONDITION CODE REGISTER
ACCUMULATOR
LOWBYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER
LOWBYTE OF PROGRAM COUNTER
 Figure 15-17. Stack Pointer at Monitor Mode Entry
15.3.2 SecurityA security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the sec
 er) Command

Command

monitor mode. The RUN command tells the MCU

command, the host can modify the stacked CPU
nd returns the incremented stack pointer value,
esses SP + 5 and SP + 6.
 Mode Entry
nitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD
V
DD
RST
FROM HOST
4096 + 32 CGMXCLK CYCLES
PA0

256 BUS
CYCLES
(MINIMUM) Notes:
FROM MCU 1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-18. Monitor Mode Entry Timing
XCLK CYCLES

1 4 1 1 2 4 1

Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-18. Monitor Mode Entry Timing
 Chapter 16
Electrical Specifications
16.1 Introduction
This section contains electrical and timing specifications.

16.2 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be expose
permanently damaging it.

NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical Characteristics for guaranteed operating

Characteristic(1) Symbol
Supply voltage V
DD

Input voltage V
IN

Mode entry voltage, IRQ pin V

TST

Maximum current per pin excluding PTA0–PTA5, VDD, and VSS I

Maximum current for pins PTA0–PTA5 I
PTA0—IPTA5

Storage temperature T
STG

Maximum current out of VSS I

MVSS

Maximum current into VDD I

MVDD

1. Voltages references to VSS.

NOTE

This device contains circuitry to protect the inputs against damage due to high static voltages
however, it is advised that normal precautions be taken to avoid application of any voltage hi
rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the range VSS  (VIN or VOUT) 
operation is enhanced if unused inputs are connected to an appropriate logic voltage level (fo
example, either VSS or VDD.)
s.

crocontroller unit (MCU) can be exposed without

s.
al Characteristics for guaranteed operating conditions.

Value Unit
–0.3 to +6.0 V
VSS –0.3 to VDD +0.3 V
VSS –0.3 to +9.1 V
±15 mA
±25 mA
–55 to +150 C
100 mA
100 mA
ences to VSS.
E

s against damage due to high static voltages or electric fields;

taken to avoid application of any voltage higher than maximum-
proper
constrained to the range VSS  (VIN or VOUT)  VDD. Reliability of
ected to an appropriate logic voltage level (for
 16.3 Functional Operating Range
Characteristic Symbol Value

TA – 40 to +125
Operating temperature range – 40 to +105
– 40 to +85
Operating voltage range V
DD 2.7 to 5.5

16.4 Thermal Characteristics

Characteristic Symbol Value
Thermal resistance 8-pin PDIP 105
8-pin SOIC 8-pin DFN 16-pin PDIP 16-pin SOIC 142
16-pin TSSOP 173

76
JA
90
133

I/O pin power dissipation P

I/O User determined
Power dissipation(1)
PD PD = (IDD x VDD)
+ PI/O = K/(TJ + 273°C)

Constant(2) K PD x (TA + 273°C)

+ PD2 x JA

Average junction temperature TJ TA + (PD x JA)

Maximum junction temperature T
JM 150
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD an
any value of TA.
 Unit Temp.
Code

MVC
°C

V —

Value Unit
105
142
173
76
90 °C/W
133

User determined W
PD = (IDD x VDD) W
PI/O = K/(TJ + 273°C)

PD x (TA + 273°C) W/°C

+ PD2 x JA

TA + (PD x JA) °C
150 °C

red PD. With this value of K, PD and TJ can be determined for

 5-V DC Electrical Charac
16.5 5-V DC Electrical Characteristics
Characteristic(1) Symbol Min Typ(2)

Output high voltage

ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins V
OH VDD–0.4 —
VDD–1.5 —
ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only VDD–0.8 —
Maximum combined IOH (all I/O pins) I
OHT — —
Output low voltage
ILoad = 1.6 mA, all I/O pins V
OL — —
ILoad = 10.0 mA, all I/O pins — —
ILoad = 15.0 mA, PTA0, PTA1, PTA3–PTA5 only — —
Maximum combined IOL (all I/O pins) I
OLT — —
Input high voltage PTA0–PTA5, PTB0–PTB7 V
IH 0.7 x VDD —

Input low voltage PTA0–PTA5, PTB0–PTB7 V

IL V
SS —

Input hysteresis V
HYS 0.06 x VDD —
DC injection current, all ports I
INJ –2 —
Total dc current injection (sum of all I/O) I
INJTOT –25 —
Ports Hi-Z leakage current I
IL –1 0.1
Capacitance Ports (as input) Ports (as input) C
IN COUT — —
— —

POR rearm voltage(3) V

POR 0 —
POR rise time ramp rate(4) R
POR 0.035 —
Monitor mode entry voltage V
TST VDD + 2.5 —
Pullup resistors(5) PTA0–PTA5, PTB0–PTB7 R
PU 16 26

Low-voltage inhibit reset, trip falling voltage V

TRIPF 3.90 4.20
Low-voltage inhibit reset, trip rising voltage V
TRIPR 4.00 4.30
Low-voltage inhibit reset/recover hysteresis V
HYS — 100
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until m
5. RPU is measured at VDD = 5.0 V.

16.6 Typical 5-V Output Drive Characteristics

Figure 16-1. Typical 5-Volt Output High Voltage versus Output High Curren
 2.0
1.5
1.0
0.5
0.0
0 5 10 15 20 25 30 35
IOL (mA)

5V PTA
5V PTB

Figure 16-2. Typical 5-Volt Output Low Voltage versus Output Low Current

2.
0

1.
5
5V PTA
1. 5V PTB
0

0.
5

0.
0 0 - -10 -15 -20 -25 -30
5 -35
IOH
(mA)
 5-V DC Electrical Characteristics

Max Unit

— V
—
—
50 mA

0.4 V
1.5
0.8
50 mA
V
DD V

0.3 x VDD V

— V
+2 mA
+25 mA
+1 A
12 pF
8

100 mV
— V/ms
9.1 V
36 k

4.50 V
4.60 V
— mV

C only.

will hold the part in reset until minimum VDD is reached.

versus Output High Current (25°C)

versus Output Low Current (25°C)

V PTA
V PTB
 5-V Control
16.7 5-V Control Timing
Characteristic(1) Symbol Min
Internal operating frequency f
OP (fBus) —
Internal clock period (1/fOP) t
cyc 125
RST input pulse width low t
RL 100
IRQ interrupt pulse width low (edge-triggered) t
ILIH 100
IRQ interrupt pulse period t
ILIL Note(2)
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
2. The minimum period is the number of cyclestRit takes to execute the interrupt service routine plus 1 tcyc.
L

RST
t
ILIL
t
ILIH

IRQ
Figure 16-3. RST and IRQ Timing
 5-V Control Timing

Max Unit
8 MHz
— ns
— ns
— ns
— t
cyc

% VDD and 70% VSS, unless otherwise noted.

t service routine plus 1 tcyc.

ming
 16.8 5-V Oscillator Characteristics
Characteristic Symbol Min Typ
Internal oscillator frequency (1) f
INTCLK — 12.8
Deviation from trimmed Internal oscillator (2)(3)
—  0.4
12.8 MHz, fixed voltage, fixed temp — 2
12.8 MHz, VDD  10%, 0 to 70C ACCINT

12.8 MHz, VDD  10%, –40 to 125C — —

Crystal frequency, XTALCLK(1) f
OSCXCLK 1 —
External RC oscillator frequency, RCCLK (1) f
RCCLK 2 —
External clock reference frequency(1) (4) f
OSCXCLK dc —
Crystal load capacitance(5) CL — 20
Crystal fixed capacitance (3)
C1 — 2 x CL
Crystal tuning capacitance(3) C2 — 2 x CL
Feedback bias resistor RB 0.5 1
RC oscillator external resistor R
EXT See Figure 16-4
Crystal series damping resistor
f
OSCXCLK = 1 MHz f
OSCXCLK = 4 MHz
RS — 20
— 10
f
OSCXCLK = > 8 MHz
— 0
1. Bus frequency, fOP, is oscillator frequency divided by 4.
2. Deviation values assumes trimming @25°C and midpoint of voltage range
3. Values are based on characterization results, not tested in production.
4. No more than 10% duty cycle deviation from 50%.
5. Consult crystal vendor data sheet.

14
5 V 25°C
12
10
8
6
4
2
0
0 10 20 30 40 50 60
R (k)
EXT

Figure 16-4. RC versus Frequency (5 Volts @ 25°C)

 Max Unit
— MHz
— %
—

5

24 MHz
12 MHz
32 MHz
— pF
— —
— —
10 M
gure 16-4 —

— k
—
—

Volts @ 25°C)
 3-V DC Electrical Charac
16.9 3-V DC Electrical Characteristics
Characteristic(1) Symbol Min Typ(2)

Output high voltage

ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins V
OH VDD –0.3 —
VDD –1.0 —
ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only VDD –0.8 —
Maximum combined IOH (all I/O pins) I
OHT — —
Output low voltage
ILoad = 0.5 mA, all I/O pins V
OL — —
ILoad = 6.0 mA, all I/O pins — —
ILoad = 10.0 mA, PTA0, PTA1, PTA3–PTA5 only — —
Maximum combined IOL (all I/O pins) I
OLT — —
Input high voltage PTA0–PTA5, PTB0–PTB7 V
IH 0.7 x VDD —

Input low voltage PTA0–PTA5, PTB0–PTB7 V

IL V
SS —

Input hysteresis V
HYS 0.06 x VDD —
DC injection current, all ports I
INJ –2 —
Total dc current injection (sum of all I/O) I
INJTOT –25 —
Ports Hi-Z leakage current I
IL –1 0.1
Capacitance Ports (as input) Ports (as input) C
IN COUT — —
— —

POR rearm voltage(3) V

POR 0 —
POR rise time ramp rate(4) R
POR 0.035 —
Monitor mode entry voltage V
TST VDD + 2.5 —
Pullup resistors(5) PTA0–PTA5, PTB0–PTB7 R
PU 16 26

Low-voltage inhibit reset, trip falling voltage V

TRIPF 2.40 2.55
Low-voltage inhibit reset, trip rising voltage V
TRIPR 2.50 2.65
Low-voltage inhibit reset/recover hysteresis V
HYS — 60
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until m
5. RPU are measured at VDD = 3.0 V

16.10 Typical 3.0-V Output Drive Characteristics

 1.5
1.0
0.5
0.0
0 -5 -10 -15 -20
IOH (mA)

3V PTA
3V PTB

Figure 16-5. Typical 3-Volt Output High Voltage versus Output High Curren

1.5
1.0
0.5
0.0
0 5 10 15 20
IOL (mA)

3V PTA
3V PTB

Figure 16-6. Typical 3-Volt Output Low Voltage versus Output Low Current
 3-V DC Electrical Characteristics

Max Unit

— V
—
—
50 mA

0.3 V
1.0
0.8
50 mA
V
DD V

0.3 x VDD V

— V
+2 mA
+25 mA
+1 A
12 pF
8

100 mV
— V/ms
VDD + 4.0 V
36 k

2.70 V
2.80 V
— mV

5°C only.

VI will hold the part in reset until minimum VDD is reached.

ge versus Output High Current (25°C)

ge versus Output Low Current (25°C)

 3-V Control
16.11 3-V Control Timing
Characteristic(1) Symbol Min
Internal operating frequency f
OP (fBus) —
Internal clock period (1/fOP) t
cyc 250
RST input pulse width low t
RL 200
IRQ interrupt pulse width low (edge-triggered) t
ILIH 200
IRQ interrupt pulse period t
ILIL Note(2)
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwis
2. The minimum period is the number of cyclestRit takes to execute the interrupt service routine plus 1 tcyc.
L

RST
t
ILIL
t
ILIH

IRQ
Figure 16-7. RST and IRQ Timing
 3-V Control Timing

Max Unit
4 MHz
— ns
— ns
— ns
— t
cyc

% VDD and 70% VDD, unless otherwise noted.

t service routine plus 1 tcyc.

ming
 16.12 3-V Oscillator Characteristics
Characteristic Symbol Min Typ
Internal oscillator frequency (1) f
INTCLK — 12.8
Deviation from trimmed Internal oscillator (2)(3)
—  0.4
12.8 MHz, fixed voltage, fixed temp — 2
12.8 MHz, VDD  10%, 0 to 70C ACCINT

12.8 MHz, VDD  10%, –40 to 125C — —

Crystal frequency, XTALCLK(1) f
OSCXCLK 1 —
External RC oscillator frequency, RCCLK (1) f
RCCLK 2 —
External clock reference frequency(1) (4) f
OSCXCLK dc —
Crystal load capacitance(5) CL — 20
Crystal fixed capacitance (3)
C1 — 2 x CL
Crystal tuning capacitance(3) C2 — 2 x CL
Feedback bias resistor RB 0.5 1
RC oscillator external resistor R
EXT See Figure 16-8
Crystal series damping resistor
f
OSCXCLK = 1 MHz f
OSCXCLK = 4 MHz
RS — 10
— 5
f
OSCXCLK = > 8 MHz
— 0
1. Bus frequency, fOP, is oscillator frequency divided by 4.
2. Deviation values assumes trimming @25°C and midpoint of voltage range.
3. Values are based on characterization results, not tested in production.
4. No more than 10% duty cycle deviation from 50%
5. Consult crystal vendor data sheet

12
3 V 25°C
10
8
6
4
2
0
0 10 20 30 40 50 60
R (k)
EXT

Figure 16-8. RC versus Frequency (3 Volts @ 25°C)

 Max Unit
— MHz
— %
—

5

16 MHz
10 MHz
16 MHz
— pF
— —
— —
10 M
gure 16-8 —

— k
—
—

Volts @ 25°C)
 Supply Current Chara
16.13 Supply Current Characteristics
Bus Typ(2)

Characteristic(1) Voltage Frequency Symbol

(MHz)
Run Mode VDD supply current(3) 5.0 3.2 RIDD 6.0
3.0 3.2 2.5
Wait Mode VDD supply current(4) 5.0 3.2 WIDD 1.0
3.0 3.2 0.67
Stop Mode VDD supply current(5) 0.04
—
–40 to 85°C
—7
–40 to 105°C 5.0 SIDD 125
–40 to 125°C
25°C with auto wakeup enabled
Incremental current with LVI enabled at 25°C
Stop Mode VDD supply current(5) 0.02
—
–40 to 85°C
—5
–40 to 105°C 3.0 SIDD 100
–40 to 125°C
25°C with auto wakeup enabled
Incremental current with LVI enabled at 25°C
1. VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at 25°C only.
3. Run (operating) IDD measured using trimmed internal oscillator, ADC off, all other modules enabled. All pins confi
to 0.2 V from rail.
4. Wait IDD measured using trimmed internal oscillator, ADC off, all other modules enabled. All pins configured as in
from rail.
5. Stop IDD measured with all pins tied to 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configu
pullups enabled.
 Supply Current Characteristics

Max Unit

7.0 mA
3.2
1.5 mA
1.0 mA
1.0
2.0
5.0
— A
—

0.5
1.0
4.0
— A
—

odules enabled. All pins configured as inputs and tied

bled. All pins configured as inputs and tied to 0.2 V

pin versions, port B is configured as inputs with

 Figure 16-9. Typical 5-Volt Run Current versus Bus Frequency (25°C)

3
Crystal w/o ADC
2 Crystal w/ ADC

Internal Osc w/o

1 ADC
Internal Osc w/
ADC

0 1 2 3 4 5
Bus Frequency
(MHz)

4
Figure 16-10. Typical 3-Volt Run Current versus Bus Frequency (25°C)

14

12

10

0 1 2 3 4 5 6
Bus Frequency
(MHz)
olt Run Current versus Bus Frequency (25°C)

lt Run Current versus Bus Frequency (25°C)

Crystal w/o ADC

Crystal w/ ADC
Internal Osc w/o ADC
Internal Osc w/ ADC

7
 Analog-to-Digital Converter Characteristics
16.14 Analog-to-Digital Converter Characteristics

Characteristic Symbol Min Max Unit

Supply voltage V
DDAD 2.7 5.5 V
(VDD min) (VDD max)

Input voltages V
ADIN V
SS V
DD V

Resolution (1 LSB) RES 10.5 21.5 mV

Absolute accuracy E
TUE —  1.5 LSB
(Total unadjusted error)
ADC internal clock f
ADIC 0.5 1.048 MHz

Conversion range V
AIN V
SS V
DD V

Power-up time t
ADPU 16 — tADIC cycles
Conversion time t
ADC 16 17 tADIC cycles

Sample time(1) t
ADS 5 — tADIC cycles

Zero input reading(2) Z

ADI 00 01 Hex

Full-scale reading(3) F
ADI FE FF Hex

Input capacitance C
ADI — 8 pF

Input leakage(3) I
IL — ±1 A

ADC supply current VDD = 3 V I

ADAD Typical = 0.45 mA mA
VDD = 5 V Typical = 0.65

1. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source an
 Comments
—

Includes quantization

t = 1/f
ADIC ADIC,
tested only at 1 MHz

—
t = 1/f
ADIC ADIC

t = 1/f
ADIC ADIC

t = 1/f
ADIC ADIC

V =V
IN SS

V =V
IN DD

Not tested

Enabled Enabled

time during input sampling.

rate conversions.
equal to the product of R source and input current.
 16.15 Timer Interface Module Characteristics
Characteristic Symbol Min
Timer input capture pulse width t
TH, tTL 2

Timer input capture period t

TLTL Note(1)

Timer input clock pulse width t

TCL, tTCH tcyc + 5

1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
INPUT CAPTURE RISING t
TH t
TLTL
EDGE t
TH
INPUT CAPTURE FALLING
EDGE
INPUT CAPTURE

t
TLTL
t
TL

t
TLTL

t
TL

BOTH EDGES
t
TCH

TCLK
t
TCL
Figure 16-11. Timer Input Timing
 Max Unit
— t
cyc

— t
cyc

— ns

service routine plus 1 tcyc.

ng
 Memory Charac
16.16 Memory Characteristics
Characteristic Symbol Min Typ

RAM data retention voltage V

RDR 1.3 —

FLASH program bus clock frequency — 1 —

FLASH read bus clock frequency (1) 0 —

f
Read

FLASH page erase time t

Erase 0.9 1
<1 k cycles 3.6 4
>1 k cycles

FLASH mass erase time t

MErase 4 —

FLASH PGM/ERASE to HVEN setup time t

NVS 10 —

FLASH high-voltage hold time t

NVH 5 —

FLASH high-voltage hold time (mass erase) t

NVHL 100 —

FLASH program hold time t

PGS 5 —

FLASH program time t

PROG 30 —

FLASH return to read time (2) 1 —

t
RCV

FLASH cumulative program HV period tHV(3) — —

FLASH endurance(4) — 10 k 100 k

FLASH data retention time(5) — 15 100

1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump,
3. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satis
+ tPGS + (tPROG x 32)  tHV maximum.
4. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Ty
Endurance, please refer to Engineering Bulletin EB619.
5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature
using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618.
 Memory Characteristics

Max Unit

— V

— MHz

8M Hz

1.1 ms
5.5

— ms

— s

— s

— s

— s

40 s

— s

4 ms

— Cycles

— Years

e high voltage charge pump, by clearing HVEN to 0.

ore next erase. tHV must satisfy this condition: tNVS + tNVH

on how Freescale defines Typical

asured at high temperature and de-rated to 25°C

cal Data Retention, please
 Chapter 17
Ordering Information and Mechanical Specifications
17.1 Introduction
This section contains order numbers for the MC68HC908QY1, MC68HC908QY2, MC68HC908Q
MC68HC908QT2, and MC69HC908QT4. Dimensions are given for:
• 8-pin plastic dual in-line package (PDIP)
• 8-pin small outline integrated circuit (SOIC) package
• 8-pin dual flat no lead (DFN) package
• 16-pin PDIP
• 16-pin SOIC
• 16-pin thin shrink small outline package (TSSOP)

17.2 MC Order Numbers

Table 17-1. MC Order Numbers
MC Order Number ADC FLASH Memory Package
MC908QY1 — 1536 bytes 16-pins PDIP, SOIC,
MC908QY2 Yes 1536 bytes and TSSOP

MC908QY4 Yes 4096 bytes

MC908QT1 — 1536 bytes 8-pins PDIP, SOIC,
and DFN
MC908QT2 Yes 1536 bytes
MC908QT4 Yes 4096 bytes
Temperature and package designators: C = –40°C to +85°C
V = –40°C to +105°C M = –40°C to +125°C
P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit package (SOIC) DT = Thin shrink small outline package (TSSO
FQ = Dual flat no lead (DFN)

MC 9 0 8 QY 1 X X X E
Pb FREE
FAMILY
PACKAGE DESIGNATOR TEMPERATURE RANGE
Figure 17-1. Device Numbering System
17.3 Package Dimensions
Refer to the following pages for detailed package dimensions.
pecifications

MC68HC908QY2, MC68HC908QY4, MC68HC908QT1,

for:

umbers

Thin shrink small outline package (TSSOP)

XE
 5 .B240
. 260
4

.040
. 370

. 400

. 210
Id I N

0
0

SEAT I NO
PLANE .115
135

. 03 .022
. 05 .014
/.005
0

. 100
 @ FREESCALE SEM I CONDUCT OR, I NC. ALL R I CHTS MECHANICAL OUTLINE
RESERVED.
T I TLE: DOCUMENT N0: 98 ASB 42420B

CASE NUMBER: 626—06

8 LD PD I P
STANDARD: NON—JEDEC
’
 . 300
. 325

.115
135
 PR I NT VERS I 0N NOT TO SCALE

N0: 98 ASB 42420B REV: N

19 MAY 2005
NUMBER: 626—06

ARD: NON—JEDEC
 10’
MAX

@ FREESCALE SEM I CONDUCT OR, I NC. ALL R I

CHTS RESERVED.
UEGH*HICAL OUTLINE
98ASB42420B
.
008 626—06
NON-JEDEC
 98ASB42420B REV: N
19 MAY 2005
626—06
NON-JEDEC
 NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M — 1994.
2. ALL DIMENSIONS ARE IN INCHES.
3. 626—03 TO 626—06 OBSOLETE. NEW STANDARD 626—07. DIMENS
OF LEAD WHEN FORMED PARALLEL.

PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CONERS).

STYLE :

PIN 1. AC I N 5. GROUND
2. DC + I N 6. OUTPUT
3. DC — I N 7. AUX I LI ARY
4. AC I N 8. VCC
@ FREESCALE SEM I C0NDUC T0R, I NC. ALL R I MECHANICAL OUTLINE
CHTS RESERVED.

T I TLE: DOCUMENT N0: 98 ASB 42420B

8 LD PD I P CASE NUMBER: 626—06

STANDARD: NON—JEDEC
ME Y14.5M — 1994.

STANDARD 626—07. DIMENSION TO CENTER

SQUARE CONERS).

GROUND
OUTPUT
AUX I LI ARY
VCC

PR I NT VERS I 0N NOT TO SCALE

MENT N0: 98 ASB 42420B REV: N
19 MAY 2005
NUMBER: 626—06

ARD: NON—JEDEC
 UECHANICAL OUTLINES DOCUMENTNO:98
DICTIONARY
PAGE:

\/EPS I ONS ARE UNCONTROLLED EXCEPT WHEN STAMPED ” CONTROLLED

DO NOT SCALE TH I S DRAW I NG REV:
NOTES:
1. DIMENSIONS AND TOLERANCES PER ASME Y14.5—1994.
2. CONTROLLING DIMENSION: MILLIMETER.
DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT T
LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEDD 0.15mm PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR PROTRU SION SHALL BE 0.08m
EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CA
LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS
LEAD TO BE 0.46mm.
T I TLE: CASE NUMBER:968-02
8 LEAD MFP STANDARD:EIAJ
PACKAGE 6003
CODE:
 DOCUMENTNO:98ASH70107A
968
A

RE MEASURED AT THE PARTING

SIDE.

ON SHALL BE 0.08mm TOTAL IN

DITION. DAMBAR CANNOT BE
WEEN PROTRUSIONS AND ADJACENT
68-02

SHEET 3 OF 4
:
 MECHANICAL OUTMNES DOCUMENTNO: 98ARL10557D
DIC10NARY
PAGE: 1452
','’’'’’’’’’ ’’’’ ,, “y “- ' x '?,”” - ?’ ’” -’ ’,'’’'''’,'’’'''I “.’'*
””” “”” g¿. ,-„ ¿ '¿{ e\'@'
O FPEE SCALE SEMICONDUCTOR. INC. ALL RICH TS RESERVED.

DO NOT SCALE THIS DRAWING REV: A

ARE UNCON 7ROLLE D EXCEPT WHEN S7AMPED “CON TROLLED COPY” IN RED.

2X
TITLE: THERMALLY ENHANCED DUAL CASE NUMBER: 1452—01
FLAT NO LEAD PACKAGE (DFN) STANDARD: NON—JEDEC
8 TERMINAL, 0.8 PITCH (4 X 4 X 1)
PACKAGECODE: 6165
O: 98ARL10557D
452

REV: A

0.1
2X
C
X PIN 1

INDEX AREA
DETAIL G
M
1452—01
N—JEDEC
SHEET: 1 OF 5
 kIECHANICAL OUTMNES DOCUMENTNO: 98
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PAGE: 145
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ARE UNCONTROLLED EXCEPT WHEN STAMPED "CONTROLLED COPY" IN RED.

3.5
3.4
DETAIL M 0.1

PIN I INDEX
3.05
2.95 2.55
0.1 2.45
0.1
8X 0.5 _j DETAIL N
0.4 8X 035
0.25

0.1@ |C |A |
B
0.05 C
 1.0 1.00
0.8 0.75
0.05 C
(0.35)
0.05 c

0.00 (0.8)
SEATING PLANE
DETAIL G

TITLE: THERMALLY ENHANCED DUAL CASE NUMBER: 1452—01

FLAT NO LEAD PACKAGE (DFN) STANDARD: NON—JEDEC
8 TERMINAL, 0.8 PITCH (4 X 4 X 1)
PACKAGECODE: 6165
VIEW M —M
DOCUMENTNO: 98ARL10557D
PAGE: 1452
REV: A
 c

PLANE

R: 1452—01
ON—JEDEC
SHEET: 2 OF 5
 UECHANICAL OUTMNES DOCUMENTNO:
DIC10NARY
PAGE:
s-°.' ‹i° 2s’1? ' -°’‹'s’
O FPEESCALE SEMICONDUC TOR. INC. ALL RIGH TS RESERVED.
ARE UNCON 7ROLLE D EXCEPT WHEN S7AMPE D “CON TROLLED COPY” IN RED.

DO NOT SCALE THIS DRAWING REV:

0.3
0.2
0.3
0.2
0.4

DETAIL M
BACKSIDE PIN 1 INDEX
6X 0.8
DETAIL N

0.06
5
0.015
TITL THERMALLY ENHANCED DUAL CASE NUMBER: 1452—01
E: FLAT NO LEAD PACKAGE (DFN) STANDARD: NON—JEDEC
8 TERMINAL, 0.8 PITCH (4 X 4 X 1)
PACKAGECODE: 6165
DOCUMENTNO: 98ARL10557D
1452
A
1452—01
N—JEDEC
SHEE 3 OF 5
T:
 UECHANICAL OUTLINES DOCUMENT NO:98A
DICTIONARY
PAGE:

VERS IONS ARE UNCONTROLLED EXCEPT ¥/HEN STAMPED ”CONTROLLED

DO NOT SCALE TH I S DRAW I NG REV:

NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14. 5M-1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HP-VFDFP-N. COP
APPLIES TO LEADS AND DIE ATTACH PAD.
 :THERMALLY ENHANCED
TITLE
DUAL CASE NUMBER: 1452—01
FLAT NO LEAD PACKAGE ( DFN) STANDARD: NON—JEDEC
8 TERM I NAL, 0. 8 P I TCH( 4 X 4 X 1) PACKAGE 6165
CODE:
 DOCUMENT NO:98ARL10557D
1452
A

M-1994.
HP-VFDFP-N. COPLANARITY
1452—01
N—JEDEC
SHEE 4 OF 5
T:
 UECHANIGAL OUTLINES DOCUMENT NO:98A
DICTIONARY
P AGE: 751
DO NOT SCALE TH I S DRAW I NG REV: E
vERS I ONS ARE UNC 0N7ROLLED EXCEP 7 WHEN STAMPED ” C 0NTROLL ED

2. 65
8X 10. 55 2. 35
0. 25

10. 05 0. 10

0.2
5 16

16 0. 25 @
10. 14X
10. 1. 27
0. 635

45
15

7. 6 SEA1NG PLANE
7. 4 16X
0. 1
0. 75 X45”
0. 25
0. 32
0. 23
0. 4 7’
0’
SECTION A—A

T I TLE: CASE NUMBER:751G-05

16LD SO I C \\/B, 1. 27 PITCH STANDARD: JEDEC MS-0l3AA
CASE—OUTL I NE PACKAGE CODE: 2003
DOCUMENT NO:98ASB42567B
P AGE: 751G
REV: E

0. 25

0. 10

16X 0.49
0. 35
0. 25 @
14X
1. 27
0. 635

SEA1NG PLANE
1G-05
EC MS-0l3AA
SHEET: 1 OF 3
 UECHANICAL OUTLINES DOCUMENT N0:98A
DICTIONARY
PAGE:
DO NOT SCALE TH I S DRAW I NG REV:
VERS I ONS ARE UNCONTROLLED EXCEPT ¥/HEN STAMPED ”CONTROLLED

NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M—1994.
3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE
THE PLASTIC BODY.
THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOL
PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION
DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC B
THIS DIMENSION DOES NOT INCLUDE INTER—LEAD FLASH OR PROTRUSIONS. INTER—L
AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DET
THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY.
THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUS
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62 mm.
 T I TLE: P I TCH CASE NUMBER: 75 1 G—05
16LD SO I C W/B, 1. 27 STANDARD: JEDEC MS—0 13AA
CASE OUTL I NE PACKAGE CODE: 2003 SHEET:
DOCUMENT N0:98ASB42567B
751G
E

E BOTTOM OF THE LEADS EXIT

GATE BURRS. MOLD FLASH,

. THIS DIMENSION IS
EXIT THE PLASTIC BODY.
RUSIONS. INTER—LEAD FLASH
DIMENSION IS DETERMINED AT
BODY.
DAMBAR PROTRUSION
 1 G—05
C MS—0 13AA
SHEET: 2 OF 3
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