Chapter 5

gm/ID - Based Design

Ross Walker
ECE/CS 5720/6720 Fall 2017
University of Utah
Partly adapted from Stanford’s analog circuit
design sequence

Reading:
See ‘References’ at the end of this chapter for optional reading.

Outline

Review the three main figures of merit for transistors: gm/ID, T, gm/gds
– Transistor characteristics that are directly linked to circuit performance
See how the square law fails in practice
Discuss gm/ID-based design using lookup tables/charts
– Quantitative design methodology based on characterizing transistors
– Intuitive framework for exploring and optimizing circuit performance
• Transistor figures of merit become useful design variables
Design example using gm/ID methodology

Learning objectives
– Understand tradeoffs between speed, power efficiency, and gain
• In transistors, and in circuits
– Be able to use technology characterization tables/charts to size transistors
• Get practice in the design project
– Develop a systematic design methodology in the absence of simple
analytical models like the square law equation
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 2
 FOM #1: gm/ID as a Figure of Merit

“Transconductance efficiency” figure of merit for transistors

– Circuit performance often dictates the required gm
• e.g. gain of a common source stage: |Av| = gmRL

– gm/ID quantifies how much gm you get for the amount of bias current you invest
• i.e. gm/ID = 10S/A 10 S per 1 A

40
[V-1] Weak Inversion Blue curve: simulation
30
Square law: gm/ID = 2/VOV
gm/ID
20

Strong Inversion
10
Moderate Inversion
0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 3

Why Doesn’t the Square Law “Work”?

MOSFETs are complicated!

The IV-behavior in saturation can be roughly categorized according to
the channel’s inversion level: weak, moderate and strong inversion
The current is due to diffusion in weak inversion and mostly due to drift
in strong inversion; the transition is smooth and complicated
The classic square law model is based on an ideal drift model, and
applies only near the onset of strong inversion
– And even then, the predictions are inaccurate unless “short channel
effects” are taken into account

The bottom line is that there is no modeling expression that is simple

enough for hand analysis and sufficiently accurate to match real world
device behavior

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 4

 What are Cox (“KP”) and (“LAMBDA”) for our Technology?

.MODEL nmos6720 nmos

+acm = 3 hdif = 0.32e-6 LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ
+K1
= 1E-7
= 0.5916053
NCH
K2
= 2.3549E17
= 3.225139E-3
VTH0
K3
= 0.3618397
= 1E-3
The Spice model for an NMOS
+K3B
+DVT0W
= 2.3938862
= 0
W0
DVT1W
= 1E-7
= 0
NLX
DVT2W
= 1.776268E-7
= 0
device in our course technology is
+DVT0
+U0
= 1.3127368
= 256.74093
DVT1
UA
= 0.3876801
= -1.585658E-9
DVT2
UB
= 0.0238708
= 2.528203E-18
shown to the left
+UC = 5.182125E-11 VSAT = 1.003268E5 A0 = 1.981392
+AGS
+KETA
= 0.4347252
= -9.888408E-3
B0
A1
= 4.989266E-7
= 6.164533E-4
B1
A2
= 5E-6
= 0.9388917
This is a 110-parameter BSIM3v3
+RDSW
+WR
= 128.705483
= 1
PRWG
WINT
= 0.5
= 0
PRWB
LINT
= -0.2
= 1.617316E-8
model, quite complex even though
+XL
+DWB
= 0
= 9.111767E-9
XW
VOFF
= -1E-8
= -0.0854824
DWG = -5.383413E-9
NFACTOR = 2.2420572
180nm is a relatively old process
+CIT
+CDSCB
= 0
= 0
CDSC
ETA0
= 2.4E-4
= 2.981159E-3
CDSCD
ETAB
= 0
= 9.289544E-6
– More recent models may
+DSUB = 0.0159753
+PDIBLC2 = 2.543351E-3
PCLM = 0.7245546
PDIBLCB = -0.1
PDIBLC1 = 0.1568183
DROUT = 0.7445011
require even more parameters
+PSCBE1
+DELTA
= 8E10
= 0.01
PSCBE2
RSH
= 1.876443E-9
= 6.6
PVAG
MOBMOD
= 7.200284E-3
= 1
(e.g. PSP, BSIM6)
+PRT
+KT1L
= 0
= 0
UTE
KT2
= -1.5
= 0.022
KT1
UA1
= -0.11
= 4.31E-9
– KP and LAMBDA are
+UB1
+WL
= -7.61E-18
= 0
UC1
WLN
= -5.6E-11
= 1
AT
WW
= 3.3E4
= 0
nowhere to be found!
+WWN = 1 WWL = 0 LL = 0
+LLN
+LWL
= 1
= 0
LW
CAPMOD
= 0
= 2
LWN
XPART
= 1
= 1
The I-V characteristics of a modern
+CGDO
+CJ
= 4.91E-10
= 9.652028E-4
CGSO
PB
= 4.91E-10
= 0.8
CGBO
MJ
= 1E-12
= 0.3836899
MOSFET cannot be accurately
+CJSW
+CJSWG
= 2.326465E-10
= 3.3E-10
PBSW
PBSWG
= 0.8
= 0.8
MJSW
MJSWG
= 0.1253131
= 0.1253131
described by the square law
+CF = 0 PVTH0 = -7.714081E-4 PRDSW = -2.5827257
+PK2 = 9.619963E-4 WKETA = -1.060423E-4 LKETA = -5.373522E-3
+PU0 = 4.5760891 PUA = 1.469028E-14 PUB = 1.783193E-23
+PVSAT = 1.19774E3 PETA0 = 9.968409E-5 PKETA = -2.51194E-3
+nlev = 3 kf = 0.5e-25

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 5

Simulation (NMOS, 5/0.18 m, VDS=1.8V)

ID [mA] SQRT(ID [mA])

3.5 2

3 Square Law

1.5
2.5
SQRT(I D [mA])

2
ID [mA]

1
1.5

1
0.5
0.5

0 0
0 0.5 1 1.5 0 0.5 1 1.5
VGS [V] VGS [V]

Two observations
– The transistor does not abruptly turn off at some Vt
– The current is not perfectly quadratic with (VGS–Vt)
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 6
 gm/ID at Low VGS

40

NMOS6720
NMOS214
30 Square Law (2I /VOV
(2/V
D OV
))
BJT (q/kT)
gm/ID [S/A]
gm/ID [S/A]

20

10

0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
V [V]
VGS [V]
GS

The square law fails miserably at predicting gm/ID for low VGS

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 7

Currents on a Log Scale

0
10
NMOS6720
NMOS214
ID,IC [mA]
Square Law
-2
10 BJT
NPN214
ID, IC [mA]

~90mV/decade

-4 ~60mV/decade
10

-6
10

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

VGS, VBE [V]

What is Vt, anyway? The device does not turn off at all, but really
approaches an exponential IV law for low VGS
What determines the current at low VGS?
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 8
 Weak Inversion (Subthreshold) Operation

Before inversion occurs, the electrostatic field from the gate forward-
biases the source-side pn junction at the surface
Physics governed by a “gated diode” model

Potential at this point is higher than body/source potential forward bias

Cox
Cjs

D.L. Pulfrey, Understanding Modern Transistors and Diodes,

Cambridge University Press, 2010.

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 9

Resulting Diffusion Current

Here vth = kT/q is the

“thermal voltage”

The current grows exponentially with s

The current becomes independent of VDS for VDS > 3Vth (~78mV)

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 10

 Capacitive Divider

n is called “subthreshold factor” or “nonideality factor”

n 1.45 for an NMOS device in the ECE6720 technology
After including this relationship between s and VGS and after a few
additional manipulations, the final expression for the drain current
becomes:

where ID0 depends on technology (ID0 0.43 A for an NMOS device in

ECE6720 technology)

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 11

gm/ID
30
NMOS214
NMOS6720
25 Weak Inversion
Square Law
20
gm/ID [S/A]
ID [mA]

15

10

0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VGS [V]

We now have a better idea about the maximum possible gm/ID, but we still
do not know how to model the transition region between the two IV laws

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 12

 Moderate Inversion

In the transition region between weak and strong inversion, the drain
current consists of both drift and diffusion currents
One can show that the ratio of drift/diffusion current in moderate
inversion and beyond is approximately (VGS-Vt)/(kT/q)
This means that the square law equation (which assumes 100% drift
current) does not work unless the gate overdrive is several kT/q

Is there a simple expression that works for all three regions (weak,
moderate and strong inversion)?
– No, there is no closed-form expression that captures all modes of
operation as well as “short channel effects”
– This is why gm/ID-based design is very useful…

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 13

FOM #2: Transit Frequency

Transistor figure of merit that relates to circuit speed and efficiency
– The transit frequency of a transistor has "historically" been defined as
the frequency where the magnitude of the common source current
gain (|io/ii|) falls to unity
ii
io
(Biasing not shown)

Ignoring extrinsic capacitance and Cgb, and using the square law model:

We’ll use this improved definition for gm/ID-based design:

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 14

 Transit Frequency Interpretation

The transit frequency is only useful as a figure of merit in that it quantifies gm/Cgg
– Tells you how much Cgg you get for a given gm

It does not accurately predict up to which frequency you can use the device
– See slide 46 of Chapter 2

At a high level, Cgg affects circuit speed

– At a lower level, Cgs, Cgb, and Cgd affect a circuit’s bandwidth differently
• e.g. Miller effect in a common course stage, (1+|Av|)Cgd versus Cgs

We’ll see that Cgs/Cgg, Cgd/Cgg, etc. are fairly stable ratios
– Having a small Cgg means the individual components are small too

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 15

FOM #3: Intrinsic Gain

Transistor figure of merit related to the maximum gain a circuit can achieve

RL
Vout
Vin

Square law: } A very poor model

Intrinsic gain is typically related to circuit accuracy

– e.g. in feedback circuits, we use high open-loop gain to make an
accurate closed-loop gain
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 16
 Example: Intrinsic Gain and Active Loads

The gain of amplifiers with active loads is fundamentally linked to intrinsic gain

VDD

VBIAS

Vout
Vin

The ratio of gmp/gmn is usually designed to be low, for low noise

– Generally constrained by practical biasing (VDsat VOV)
is typically 2-4

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 17

How about VDsat?

VGS=0.9V
0.6
VDsat tells us how much voltage VDsat
VGS=0.8V
ID [mA]

we need across the channel to 0.4

operate in saturation VGS=0.7V
0.2
– “High gain region”
0
0 0.5 1 1.5
VDS [V]
40
It is important to note that VDsat 30
is not crisply defined in modern
gm/gds

devices 20
– gm/gds gradually increases
10
with VDS
0
0 0.5 1 1.5
VDS [V]

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 18

 Relationship Between VDsat and gm/ID

It turns out that 2/(gm/ID) is a reasonable first-order estimate for VDsat

Square Law Weak Inversion

2 Need about
ID K VGS Vt VGS Vt VDS
nVth Vth
3Vth for
ID ID0 e 1 e saturation
gm 2K VGS Vt

2 VGS Vt VDS
VGS Vt VOV VDsat ID0
gm / ID gm e nVth
1 e Vth
nVth
Consistent with the classical
first-order relationship 2
2nVth 3Vth
gm / ID

Corresponds well with the

required minimum VDS

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 19

Reality Check

0.6
ID [mA]

0.4

0.2 Computed
2/(gm/ID)
0 values
0 0.5 1
VDS [V]
40

30 The SPICE model data

gm/gds

confirms that 2/(gm/ID) is a

20
good estimate for the
10 minimum reasonable VDS

0
0 0.5 1
VDS [V]

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 20

 Summary: Transistor Figures of Merit for Design

Square Law

Transconductance efficiency gm 2
– Want large gm, for as little current
as possible
ID VOV

Transit frequency gm 3 VOV

– Want large gm, without large Cgg Cgg 2 L2

Intrinsic gain gm 2
– Want large gm, but no gds
gds VOV

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 21

Design Tradeoff: gm/ID and fT

40

30 gm/ID Moderate Inversion fT

gm/ID [S/A], f T [GHz]

20
Weak Inversion Strong Inversion

10

0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

W/L
Weak inversion: Large gm/ID (>20 S/A), but small fT
VDS
Strong inversion: Small gm/ID (<10 S/A), but large fT
VGS

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 22

 Product of gm/ID and fT

250

200
gm/ID f T [S/A GHz]

150 Moderate Inversion

100

50
Weak Inversion Strong Inversion

0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

Interestingly, the product of gm/ID and fT peaks in moderate inversion

– Peaks around gm/ID 10S/A in ECE6720 technology
Operating the transistor in moderate inversion makes sense when we
value speed and power efficiency equally
– This is just a heuristic, not always the case
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 23

Design in a Nutshell

ID

gm/ID

Choose length such that the circuit has ‘enough’ gain

Choose the inversion level according to the proper tradeoff between
speed (fT) and transconductance efficiency (gm/ID) for the given circuit
The inversion level is fully determined by the gate overdrive VOV
– But, VOV is not a very interesting parameter outside the square law
framework; not much can be computed from VOV
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 24
 Eliminating VOV

The inversion level is also fully defined once we pick gm/ID, so there is no
need to know VOV

ID 40

30

f T [GHz]
gm/ID 20

10

fT 0
5 10 15 20 25
gm/ID [S/A]

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 25

Outline

Review the three main figures of merit for transistors: gm/ID, T, gm/gds
– Transistor characteristics that are directly linked to circuit performance
See how the square law fails in practice
Discuss gm/ID-based design using lookup tables/charts
– Quantitative design methodology based on characterizing transistors
– Intuitive framework for exploring and optimizing circuit performance
• Transistor figures of merit become useful design variables
Design example using gm/ID methodology

Learning objectives
– Understand tradeoffs between speed, power efficiency, and gain
• In transistors, and in circuits
– Be able to use technology characterization tables/charts to size transistors
• Get practice in the design project
– Develop a systematic design methodology in the absence of simple
analytical models like the square law equation
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 26
 The Problem

Specifications

Square Law Hand Calculations

Circuit

Sim Models SPICE

Results

Since there is a disconnect between actual transistor behavior and the

simple square law model, any square-law driven design optimization will
be far off from SPICE results

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 27

Unfortunate Consequence

In the absence of a simple set of equations for hand analysis, many

designers tend to converge toward a “SPICE monkey” design methodology
– No hand calculations, play SPICE like a video game until the circuit
“somehow” meets the specifications
– Typically results in sub-optimal designs, uninformed design decisions,
circuit marginalities, etc.
Our goal
– Maintain a systematic design
methodology in the absence of a set
of useful compact MOS equations
Strategy
– Design using look-up tables or charts

[Courtesy Isaac Martinez]

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 28

 The Solution

Use pre-computed SPICE data in hand calculations

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 29

gm/ID-centric Technology Characterization

Tabulate the figures of merit considering gm/ID as an index, over a

reasonable range of gm/ID and channel lengths
– Transit frequency (fT)
– Intrinsic gain (gm/gds)

Also tabulate relative estimates of capacitances

– Cgd/Cgg and Cdd/Cgg

In order to compute device widths, we need one more table that links
gm/ID and current density ID/W

Note that all of these parameters are (to first order) independent of
device width

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 30

 Starting Point: Technology Characterization via DC Sweep

Obtain these tables through a DC sweep

simulation of the transistor models
– Measure transistor .op parameters at each
point of the sweep
• gm, ID, Cgg, gds, etc. W/L
– Repeat the sweep for different lengths
VDS
• 180nm, 200nm, ….. 3 m
– Generate charts, Matlab arrays, etc. VGS
Simple version: sweep VGS with VDS held fixed
at VDS =VDD/2
– The figures of merit and ID/W don’t vary
too much with VDS
Advanced version: sweep VDS and VBS also

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 31

HSPICE Example

* Example HSPICE netlist/simulation, techchar.sp

* Model file
.inc './models/ece6720.mod'
* Define 'width' and 'length' in a parameter file,
* along with 'gsmax' and 'gsstep'
.inc 'techchar_params.sp'

.param ds = 0.9
W/L
.param gs = 0.9
VDS
vdsn vdn 0 dc 'ds'
vgsn vgn 0 dc 'gs' VGS
mn vdn vgn 0 0 nmos6720 L='length' W='width'

.options dccap post brief accurate nomod

.dc gs 0 'gsmax' 'gsstep'

.probe n_id = par('i(mn)')

.probe n_gm = par('gmo(mn)')
.probe n_gds = par('gdso(mn)')
.probe n_cgg = par('cggbo(mn)')

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 32

 Example Matlab Wrapper
% Example Matlab wrapper

% HSPICE toolbox
addpath(‘./HSPICEToolBox')

% Parameters for HSPICE runs

VGS_step = 25e-3; VGS_max = 1.8;
VGS = 0:VGS_step:VGS_max;
W = 5e-6; L = [(0.18:0.02:0.5) (0.6:0.1:1.0) (1.2:0.2:3)]*1e-6;

% HSPICE simulation loop

for i = 1:length(L)
% write out circuit parameters and run HSPICE
fid = fopen('techchar_params.sp', 'w');
fprintf(fid,'*** simulation parameters **** %s\n', datestr(now));
fprintf(fid,'.param width = %d\n', W);
fprintf(fid,'.param length = %d\n', L(i));
fprintf(fid,'.param gsstep = %d\n', VGS_step);
fprintf(fid,'.param gsmax = %d\n', VGS_max);
fclose(fid);
system('/uusoc/facility/cad_common/Synopsys/hspice_G-2012.06-SP1/hspice/bin/hspice...
techchar.sp >! techchar.out');
%Read and store results
h = loadsig(techchar.sw0);
nch.GM(i,:) = evalsig(h, ‘n_gm’);
nch.ID(i,:) = evalsig(h, ‘n_id’);
nch.CGG(i,:) = evalsig(h, ‘n_cgg’);
nch.GDS(i,:) = evalsig(h, ‘n_gds’);
end

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 33

Intrinsic Gain Chart

L=0.5um

gm/gds [V/V]

L=0.18um

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 34

 Transit Frequency Chart

L=0.18um
fT [GHz]

L=0.5um

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 35

Current Density Chart

ID/W [A/m]
L=0.18um

L=0.5um

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 36

 VDS Dependence

VDS dependence
ID/W is relatively weak
[A/m]
Typically OK to
work with data
generated for
VDD/2

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 37

Handling Extrinsic Capacitances

NMOS, L=0.18um
1
Cdd/Cgg
Cgd/Cgg
0.8

0.60 Again, it’s usually

0.6 OK to work with
estimates taken at
VDS=VDD/2
0.4
0.24
0.2

0
0 0.5 1 1.5
VDS [V]

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 38

 Extrinsic Capacitances – Length Dependence

NMOS, gm/I D=10S/A, VDS=0.9V

0.8
Cgd/Cgg
0.7
Cdd/Cgg
0.6

0.5

0.4

0.3

0.2

0.1

0
0.2 0.25 0.3 0.35 0.4 0.45 0.5
L [ m]

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 39

Extrinsic Capacitances (PMOS) – Length Dependence

PMOS, gm/I D=10S/A, VDS=0.9V

0.8
Cgd/Cgg
0.7
Cdd/Cgg
0.6

0.5

0.4

0.3

0.2

0.1

0
0.2 0.25 0.3 0.35 0.4 0.45 0.5
L [ m]

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 40

 Key Question

How can we use all this data for systematic design?

Many options exist

– And you can invent your own, if you like

Method taught in ECE6720

– Look at the transistor in terms of width-independent figures of merit
that are intimately linked to design specifications and performance
• Rather than physical modeling parameters that do not directly
relate to circuit specs
– Think about the design tradeoffs in terms of the MOSFET’s inversion
level (bias point), using gm/ID as a proxy

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 41

A Generic Design Flow

1) Determine gm (from design objectives)

2) Pick L
Short channel high fT (high speed)
Long channel high intrinsic gain
3) Pick gm/ID
Large gm/ID low power, large signal swing (low VDSsat)
Small gm/ID high fT (high speed)
4) Determine ID (from gm and gm/ID)
5) Determine W (from ID/W)

Many other possibilities exist (depends on circuit specifics, design constraints

and objectives)

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 42

 Basic Design Example

Given specifications and

objectives
– 0.18 m technology
– Low frequency gain = -4
– RL=1k, CL=50fF, Rs=10k
– Maximize bandwidth while
keeping ITAIL 600 A
• Implies L=Lmin=0.18 m
– Determine device width
– Estimate dominant and non-
dominant pole

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 43

Small-Signal Half-Circuit Model

Cgd

Rs
+ +
vgs Cgs+Cgb gmvgs ro RL CL+Cdb vod
vid - -

Calculate gm and gm/ID

4 gm 4mS S
A v0 gmRL 4 gm 4mS 13.3
1k ID 300 A A

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 44

 Aside: Why can we Neglect ro?

A v0 gm RL || ro

4 gmRL || gmro

1 1 1
4 gmRL gmro

Even at L=Lmin= 0.18 m, we have gmro > 30

1 1
4 30
1 1 1 1
4 4 gmro gmRL

4 gmRL

ro is negligible in this design problem

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 45

Determine Cgg via fT Look-up

gm S
13.3
L=0.18um ID A
fT [GHz]
16.9 GHz

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 46

 Calculate Capacitance Values
Cgd

Rs
+ +
vgs Cgs+Cgb gmvgs RL CL+Cdb vod
vid - -

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 47

Zero and Pole Expressions

gmRL (1 sCgd / gm )
KCL analysis shows you: H(s)
1 b1s b2s2

gm
High frequency zero: z T negligible
Cgd

b1 Rs Cgs Cgd 1 A v0 RL (CL Cgd )

Denominator coefficients:
b2 Rs RL (CgsCL CgsCgd CLCgd )
(Cdb can be added to CL if significant)

1
Dominant pole approximation: p1
b1

b1
Non-dominant pole approximation: p2
b2

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 48

 Device Sizing

ID/W [A/m] 16.1 A/m gm S

L=0.18um 13.3
ID A

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 49

A Note on Current Density

Designing with current density charts in a normalized, width-independent

space works because
– Current density and gm/ID are independent of W
• ID/W ~ W/W
• gm/ID ~ W/W
– There is a one-to-one mapping from gm/ID to current density

2
gm 2 ID 1 1 2 1 1 gm
Square law: Cox VOV Cox
ID VOV W 2 L L 2 ID
gm ID 1 gm
General case: f VOV g VOV g f
ID W ID

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 50

 Circuit For SPICE Verification

ID 300 A
Device width W 18.6 m
ID 16.1A / m
W

Simulation circuit

50fF 1k 50fF
+ vodm -
+vidm/2
18.6/0.18
10k

-vidm/2
600 A
1V

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 51

Simulated DC Operating Point (Cadence/Spectre)

Good agreement with simulation!

Hand analysis: Simulation:
gm = 4 mS gm = 4.05 mS
Cdd = 22.6 fF Cdd = 24.63 fF
Cgg = 37.8 fF Cgg = 37.49 fF
Cgd = 9.0 fF Cgd = 8.97 fF

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 52

 Spectre dcOpInfo Capacitance Output Parameters

Corresponding Small Signal

Spectre dcOpInfo output parameter
Model Elements

cdd 24.6253f cdd Cgd + Cdb

cgg 37.4887f cgg Cgs + Cgd + Cgb
css 46.4128f css Cgs + Csb
cbb 39.4803f cbb Cgb + Csb+ Cdb
cgs -26.7941f cgs Cgs
cgd -8.9671f
cgd Cgd
Note: you can ignore the negative signs, they
are artifacts from the way Spectre computes
small signal capacitances, e.g. Cgs=dQg/dVs

See Cadence help/manuals for more parameters and details:

‘cdnshelp’ from the command prompt, then search for bsim3v3
and see the section “Operating-Point Parameters”

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 53

Simulated AC Response

20
Magnitude 215 MHz

[dB] 0 11.3 dB (3.7)

Magnitude [dB]

-20
4.8 GHz

-40

-60

-80 6 8 10 12
10 10 10 10
Frequency [Hz]

Calculated values: |Av0|=12 dB (4.0), fp1 = 200 MHz, fp2= 5.8 GHz

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 54

 Cadence Schematic

W, L, Rs, RL, CL, ID are setup as design variables in ADE L

Ideal baluns (from the ECE6720 library) are used to handle differential
and common mode conversion

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 55

Using Pole/Zero Analysis (pz)

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 56

 pz Analysis Results

Good agreement with simulation!

Simulation: Hand analysis:
fp1 215MHz fp1 200MHz (~7% error)
fp2 4.8GHz fp2 5.8GHz (~20% error)

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 57

Observations

The design is essentially right on target!

– Typical discrepancies are no more than 10-20%, due to V DS
dependencies, finite output resistance, etc.

We accomplished this by using pre-computed SPICE data in the design

process

Even if discrepancies are more significant, there’s always the possibility

to track down the root causes
– Hand calculations are based on parameters that also exist in SPICE,
e.g. gm/ID, fT, etc.
– Different from square law calculations using Cox, VOV, etc.
• Based on artificial parameters that do not exist or have no
significance in the SPICE model

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 58

 Comparison

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 59

Advanced Characterization

While variations due to VDS are fairly small for

most parameters, we can get better accuracy
by sweeping VDS as well
– Adds another dimension to the tables
• Harder to visualize
• Easy to deal with using Matlab lookup
functions instead of charts
GS
In many circuits VS VB
– e.g. a differential pair
SB DS
– Back-gate effect!
• Sweeping VSB generates
characterization data that captures this
effect as well

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 60

 Simulation Data in Matlab
% data stored in /home/ece6720/matlab
>> load 180n.mat
>> nch
nch =
ID: [4-D double]
VT: [4-D double] Four-dimensional arrays
GM: [4-D double]
GMB: [4-D double]
GDS: [4-D double]
CGG: [4-D double]
CGS: [4-D double]
CGD: [4-D double]
CGB: [4-D double]
CDD: [4-D double]
CSS: [4-D double]
INFO: 'Univ of Utah ECE6720 models,
180nm CMOS, BSIM3'
VGS: [73x1 double]
VDS: [73x1 double]
VSB: [11x1 double]
L: [32x1 double]
W: 5.0000e-06
NFING: 1
>> size(nch.ID)
ans =
32 73 73 11

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 61

Lookup Function in /home/ece6720/matlab

>> lookup(nch, 'ID', 'VGS', 0.5, 'VDS', 0.5)

ans =
8.4181e-06

>> help lookup

Rev. 20140731, Boris Murmann
The function "lookup" extracts a desired subset from the 4-dimensional simulation data
The function interpolates when the requested points lie off the simulation grid

There are three basic usage modes:

(1) Simple lookup of parameters at given (L, VGS, VDS, VSB)
(2) Lookup of arbitrary ratios of parameters, e.g. GM_ID, GM_CGG at given (L, VGS,
VDS, VSB)
(3) Cross-lookup of one ratio against another, e.g. GM_CGG for some GM_ID

In usage modes (1) and (2) the input parameters (L, VGS, VDS, VSB) can be
listed in any order and default to the following values when not specified:

L = min(data.L); (minimum length used in simulation)

VGS = data.VGS; (VGS vector used during simulation)
VDS = max(data.VDS)/2; (VDD/2)
VSB = 0;

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 62

 Matlab Design Script for the Diff Pair Example
clear all; close all;
load 180n.mat;

% Specs
Av0 = 4; RL = 1e3; CL = 50e-15; Rs = 10e3; ITAIL = 600e-6;

% Component calculations
gm = Av0/RL;
gm_id = gm/(ITAIL/2);
wT = lookup(nch, 'GM_CGG', 'GM_ID', gm_id);
cgd_cgg = lookup(nch, 'CGD_CGG', 'GM_ID', gm_id);
cdd_cgg = lookup(nch, 'CDD_CGG', 'GM_ID', gm_id);
cgg = gm/wT;
cgd = cgd_cgg*cgg;
cdd = cdd_cgg*cgg;
cdb = cdd - cgd;
cgs = cgg - cgd;

% Pole calculations
b1 = Rs*(cgs + cgd*(1+Av0))+RL*(CL+cgd);
b2 = Rs*RL*(cgs*CL + cgs*cgd + CL*cgd);
fp1 = 1/2/pi/b1
fp2 = 1/2/pi*b1/b2

% Device sizing
id_w = lookup(nch, 'ID_W', 'GM_ID', gm_id)
w = ITAIL/2 / id_w

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 63

lookup_examples.m
% Basic usage examples for function "lookup"
% Boris Murmann
% Stanford University
% Rev. 20140731
% Modified by Ross Walker, Univ of Utah, 8/1/2014
clear all; close all;

%Plot settings
font_size = 20; font_name = 'Arial'; linewidth = 1;

% Load data table

load 180n.mat;

% Plot drain characteristics for different VGS at minimum L (default)

vgs = 0:0.2:max(nch.VGS);
id = lookup(nch, 'ID', 'VGS', vgs, 'VDS', nch.VDS);
figure(1)
set(gca,'FontSize',font_size,'FontName',font_name);
plot(nch.VDS, id','LineWidth',linewidth)
xlabel('V_D_S [V]')
ylabel('I_D [A]')

% Plot fT against gm_ID for different L

gm_id = 5:0.1:20;
wt = lookup(nch, 'GM_CGG', 'GM_ID', gm_id, 'L', nch.L);
figure(2)

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 64

 An Example Optimization Flow
Complicated circuits have *many* degrees of freedom and objectives
– Usually we must make some heuristic choices up front
– Charts and lookup tables help you iterate through possible designs rapidly

1) Pick transistor lengths

2) Pick gm/ID bias points
Revise the
3) Determine transconductances
optimization
4) Determine bias currents (from gm and gm/ID) variables
5) Total power consumption = ???
- Room for improvement?
- Ready to verify?

6) Determine W (from ID/W)

7) Simulate the circuit: meets specs and estimated performance?
- If yes, then you’re done!
- If not, revise the design flow: correct mistakes, improve estimates, etc.
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 65

A Note on Tools
Modern IC design depends on *many* tools
– Schematic editors, simulators, layout editors, verification tools, etc…
– ‘Hand’ analysis tools
• MATLAB, Octave, MathCAD, Maple, Excel, etc…
• Technology characterization charts and lookup tables
– GUIs & graphics versus scripting

The designer uses the tools to design the circuit

– Tools don’t do the design for you
– Tools sometimes break, or are incompatible with each other
• Search/read the manuals, learn to use tools correctly
– Tips: ctrl + f, google, cdnshelp, CAD tutorial

Pick the right tool for the job

– Balance complexity, overhead, connection to the design objectives
• This can be a very personal choice
– Sometimes biting the bullet is better than fancy solutions
R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 66
 Chapter 5 Summary
Revisited the three figures of merit for transistors, in the context of design
– gm/ID, T, gm/gds
– Device characteristics that are directly linked to circuit performance
• Used as tradeoff ‘knobs’ or indices to balance power efficiency, speed, gain
• Powerful parameters to characterize a process technology

Saw how the square law breaks down in practice

– Weak/moderate/strong inversion, short channel effects

Discussed gm/ID-based design using charts and lookup tables

– Provides a systematic design/optimization methodology
• Accurately estimate capacitances, gain, power dissipation
• Minimize tweaking of W and L

Worked through a differential pair design example

– Good agreement between hand analysis and simulation
– This was a basic design exercise: nothing to optimize

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 67

Chapter 5 Learning Objectives

Learning objectives
– Understand tradeoffs between speed, power efficiency, and gain
• In transistors, and in circuits
– Be able to use technology characterization tables/charts to size transistors
• Get practice in the design project
– Develop a systematic design methodology in the absence of simple
analytical models like the square law equation

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 68

 References

F. Silveira et al. "A gm/ID based methodology for the design of CMOS
analog circuits and its application to the synthesis of a silicon-on-
insulator micropower OTA," IEEE J. Solid-State Circuits, Sep. 1996, pp.
1314-1319.
D. Foty, M. Bucher, D. Binkley, "Re-interpreting the MOS transistor via
the inversion coefficient and the continuum of gms/Id," Proc. Int. Conf. on
Electronics, Circuits and Systems, pp. 1179-1182, Sep. 2002.
B. E. Boser, "Analog Circuit Design with Submicron Transistors," IEEE
SSCS Meeting, Santa Clara Valley, May 19, 2005,
http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm
P. Jespers, The gm/ID Methodology, a sizing tool for low-voltage analog
CMOS Circuits, Springer, 2010.
T. Konishi, K. Inazu, J.G. Lee, M. Natsu, S. Masui, and B. Murmann,
“Optimization of High-Speed and Low-Power Operational
Transconductance Amplifier Using gm/ID Lookup Table Methodology,”
IEICE Trans. Electronics, Vol. E94-C, No.3, Mar. 2011.

R. Walker ECE/CS 5720/6720 Fall 2017 – Chapter 5 69