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CH5

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hussainfiras23
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Chapter 5

Synchronous Sequential Logic


By: Ahmed Noori
INTRODUCTION
• Hand-held devices, cell phones, navigation receivers, personal computers, digital
cameras, personal media players, and virtually all electronic consumer products
have the ability to send, receive, store, retrieve, and process information
represented in a binary format.

• The technology enabling and supporting these devices is critically dependent on


electronic components that can store information, i.e., have memory.

• Sequential circuits, however, act as storage elements and have memory.

• They can store, retain, and then retrieve information when needed at a later
time.
SEQUENTIAL CIRCUITS
• a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states .

• In contrast, the outputs of combinational logic depend


only on the present values of the inputs.
• There are two main types of sequential circuits,
and their classification is a function of the timing of
their signals.
• A synchronous sequential circuit is a system whose
behavior can be defined from the knowledge of its signals
at discrete instants of time.
• The behavior of an asynchronous sequential circuit
depends upon the input signals at any instant of time and
the order in which the inputs change.
SR Latch
STORAGE ELEMENTS: LATCHES
D Latch
STORAGE ELEMENTS: LATCHES
(Transparent Latch)
STORAGE ELEMENTS: FLIP-FLOPS
STORAGE ELEMENTS: FLIP- Edge-Triggered D
FLOPS Flip-Flop
STORAGE ELEMENTS: FLIP- Other Flip-Flops
FLOPS
STORAGE ELEMENTS: FLIP- Other Flip-Flops
FLOPS
STORAGE ELEMENTS: FLIP- Characteristic
FLOPS Tables
STORAGE ELEMENTS: FLIP- Characteristic
FLOPS Equations
STORAGE ELEMENTS: FLIP- Direct Inputs
FLOPS
ANALYSIS OF CLOCKED State Equations
SEQUENTIAL CIRCUITS
ANALYSIS OF CLOCKED State Table
SEQUENTIAL CIRCUITS
ANALYSIS OF CLOCKED State
SEQUENTIAL CIRCUITS Diagram
ANALYSIS OF CLOCKED State Diagram
SEQUENTIAL CIRCUITS
ANALYSIS OF CLOCKED Analysis with D
SEQUENTIAL CIRCUITS Flip-Flops
ANALYSIS OF CLOCKED Analysis with JK
SEQUENTIAL CIRCUITS Flip-Flops
ANALYSIS OF CLOCKED Analysis with JK
SEQUENTIAL CIRCUITS Flip-Flops
ANALYSIS OF CLOCKED Analysis with T
SEQUENTIAL CIRCUITS Flip-Flops
ANALYSIS OF CLOCKED Analysis with T
SEQUENTIAL CIRCUITS Flip-Flops
Mealy and Moore
ANALYSIS OF CLOCKED Models of Finite State
SEQUENTIAL CIRCUITS Machines
SYNTHESIZABLE HDL MODELS Behavioral
OF SEQUENTIAL CIRCUITS Modeling
SYNTHESIZABLE HDL MODELS Behavioral
OF SEQUENTIAL CIRCUITS Modeling
SYNTHESIZABLE HDL MODELS HDL Models of Flip-
OF SEQUENTIAL CIRCUITS Flops and Latches
SYNTHESIZABLE HDL MODELS HDL Models of Flip-
OF SEQUENTIAL CIRCUITS Flops and Latches
SYNTHESIZABLE
HDL MODELS
OF SEQUENTIAL
CIRCUITS

State diagram-
Based HDL Models
SYNTHESIZABLE HDL MODELS HDL Models of Flip-
OF SEQUENTIAL CIRCUITS Flops and Latches
Structural Description
SYNTHESIZABLE HDL MODELS of Clocked Sequential
OF SEQUENTIAL CIRCUITS Circuits
STATE REDUCTION AND State
ASSIGNMENT Reduction
STATE REDUCTION AND State
ASSIGNMENT Reduction
STATE REDUCTION AND State
ASSIGNMENT Reduction
STATE REDUCTION AND State
ASSIGNMENT Assignment
DESIGN PROCEDURE
Synthesis Using D
DESIGN PROCEDURE
Flip-Flops
Excitation
DESIGN PROCEDURE
Tables
Synthesis Using JK
DESIGN PROCEDURE
Flip-Flops
Synthesis Using T
DESIGN PROCEDURE
Flip-Flops

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