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stm32l4_system_debug

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6 views

stm32l4_system_debug

Uploaded by

judit112024
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Hello, and welcome to this presentation of the STM32

debug interface. It covers the debug capabilities offered


by STM32L4 devices.

1
The debug interface of STM32 products provides an
access to MCU internal resources.
This interface is used to program the MCU and debug
applications using basic debug features.
In addition to the basic debugging features, applications
benefit from the trace capability used to quickly identify
possible malfunctioning parts of the application and to
create coverage and profiling reports used for application
tests, optimizations and certifications.

2
The STM32L4 offers several basic debugging features
which are supported by all hardware and software debug
tool sets. Debugging hardware can interface with the
STM32L4 through the 5-wire standard JTAG interface or
the 2-wire serial wire debug port. The debugging toolset
can directly access the AHB access port, an AHB master
able to access all internal data buses, or directly read or
write to all registers and memories, including
programming the Flash memory.
The user can control the execution of the application
through breakpoints and code stepping. When the
program reaches a breakpoint, internal peripherals like
timers can be frozen in their current state or can be left
running.

3
The STM32L4 also supports more advanced debugging
features. These features require additional support by
the debugging toolset – both hardware and software, as
well as support on the MCU side for features requiring
additional pins like the embedded trace macrocell (ETM)
or the trace point unit interface (TPUI).

4
The Flash patch and breakpoint unit provides hardware
breakpoints for debugging the application or possibly
correcting software bugs in the code memory space. The
full implementation option offers two literal comparators
and six instruction comparators.

5
The embedded data watchpoint trigger provides four
comparators configurable as a hardware watchpoint,
ETM trigger, PC sampler or data address sampler. It
provides the necessary information for data tracing and
system profiling analysis, for which it embeds counters
for counting the number of clock cycles, load and store
operations, sleep cycles, clocks per instruction and also
information about interrupt overhead. It can also
generate reports about the application profile.

6
The instrumentation trace macrocell (ITM) supports printf
style debugging information for diagnostics. Packets can
be invoked by software – a direct write to the ITM or by
hardware – triggered from the data watchpoint trigger
(DWT).
It also provides a timestamp from the 21-bit counter.

7
The embedded trace macrocell (ETM) provides
information about the execution flow of the application by
tracing data through the DWT or ITM and tracing
instructions through the ETM. This information is then
sent to the debugger host for processing.
This information allows the debugger to completely
reconstruct the execution flow. It is very useful to quickly
identify bugs and also generate code coverage and
profiling reports, which are used for test purposes and
certifications.

8
The trace port interface unit formats information from the
on-chip trace units – ITM and ETM – and sends them to
the debugger host.
It supports Asynchronous mode with one pin used for
communication in Single-wire mode, or Synchronous
mode with up to 5 pins working in both JTAG and Single-
wire modes. Synchronous mode provides better data
throughput.
After a device reset, these pins are not assigned and
must be configured by the debugger host.

9
The STM32L4 supports flexible debug pin assignments.
After a reset, all five debug pins are assigned to the
debug interface. The application may reconfigure them
back for GPIO operation and release these pins for
application use.
Please note that these debug pins have internal pull-up
or pull-down resistors enabled after a reset to prevent
any uncontrolled IO levels on these pins.

10
The debug interface operates in all low-power modes.
For Sleep, Stop and Standby modes, related bits must
be configured in the DBGMCU_CR register in order to
prevent the clock and regulators from stopping when
entering a low-power mode.
For more technical details, visit the infocenter.arm.com
website.

12

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