International Journal of Innovative Research in Computer Science and Technology (IJIRCST)

ISSN(Online): 2347-5552, Volume-12, Issue-3, May 2024

https://doi.org/10.55524/ijircst.2024.12.3.6
Article ID IJIRD-1289, Pages 28-31
www.ijircst.org

Implementation of a Fully Automatic Four-way Traffic Light

Controller Using Verilog
Dr. P.A. Nageswara Rao1, Mr. V. D. S. Venkat2, Mrs. K. Sharmila3, and Mrs. M. Tharangini4
1
Associate Professor, Department of Electronics and Communication Engineering,
Gayatri Vidya Parishad College For Degree and PG Courses(A), Visakhapatnam, Andhra Pradesh, India
2,3,4
Student, Department of Electronics and Communication Engineering,
Gayatri Vidya Parishad College for Degree and PG Courses(A), Visakhapatnam, Andhra Pradesh, India
Correspondence should be addressed to Dr. P.A. Nageswara Rao;

Received 29 March 2024; Revised 12 April 2024; Accepted 25 April 2024

Copyright © 2024 Made Dr. P.A. Nageswara Rao et al. This open-access article is distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

ABSTRACT- The traffic control system is one of the to wait at the intersection unnecessarily as allowing them
challenging problems in metropolitan and developed cities. doesn’t disturb the moving vehicles. [5]The designed system
This is due to the large number of vehicles and the high makes sure that this drawback is removed to allow the
dynamics of the traffic system. Impoverished traffic systems maximum transportation of vehicles across the intersection
are the big reason for accidents and time losses. In this and to prevent unnecessary waiting time for motorists.[5]
project, the Fully Automatic Four-way Traffic light Melay model of Finite State Machine (FSM) is used to design
controller is implemented by using Verilog and we have the traffic light controller system as the output of the system
overcome some drawbacks i.e., we included the area (traffic light signals) depends only upon the current state of
detection parameter that improves the detection of vehicles the system.[6] This feature makes the system fully
compared to the design part in the base paper. automated. The system considers the four roads to have
different traffic and makes use of the Binary encoding
KEYWORDS- Finite State Machine, Hardware scheme.[6] Compared to other works, the proposed system is
Description Language, Verilog, Xilinix Vivado. more efficient by making use of a minimal number of states
which are necessary enough to allow the maximum
I. INTRODUCTION transportation of vehicles across the intersection.[7] The
Traffic congestion is one of the predominant problems reduction in several states also helps in achieving minimal
prevailing in cities and towns. In T-intersection and four-way power consumption. The traffic controller system also makes
intersections, the probabilities of accidents are slightly use of the maximum possible number of safe states. Before
higher. So, to ensure smooth flow of traffic and to avoid road the stoppage of traffic across each direction, the yellow
accidents, traffic light systems are used. signal is displayed in the corresponding displays which
We designed a traffic light controller system for four-way indicates that the flow of traffic will be stopped in a few
intersection roads. In this system, the waiting time of seconds.[7] The states containing yellow signals act as safe
vehicles at the intersection is reduced to a great extent. states and prevent the possibility of accidents. A Simulation-
Microcontroller and Microprocessor-based traffic light based system is designed and the same is done using Xilinx
systems are already present. But the disadvantage associated Vivado.[8] Complete information on the system design is
with these systems is that they work on a fixed time, and obtained using various facilities present in this software like
don’t have flexibility. So, this paper concentrates on utilization reports, power reports, etc.[8]
developing a reconfigurable traffic light controller system.
Verilog is chosen for modeling the traffic light controller II. METHODOLOGY
system, as usage of Verilog HDL allows the definition of the The paper concentrates on developing a traffic light
specifications of the parameters used in the design of the controller system for a four-way intersection with vehicle
system. Also, Verilog HDL is one of the commonly used detection. Each road has three light displays corresponding
HDLs as it has a simple syntax and somewhat resembles to the flow of traffic towards the other three roads. Hence
software programming languages. there are twelve light displays in total at the intersection.
Different types of traffic control systems are put forth by Using a common control logic. This simplifies the design
researchers for different real-time situations. A traffic light with four light displays. Each of these light displays has the
controller was designed using Verilog HDL considering two provision to show red, green, and yellow signals. The red
roads [1] and a T-junction [2]. A system for four-way signal indicates to stop, the green signal allows the flow of
intersections was implemented using two signals, red and traffic and the yellow signal specifies that the flow of traffic
green [3]. Another system uses three signals, red, yellow, and will be stopped in a few seconds. The designed system helps
green to regulate the traffic [4]. However, the drawback of to prevent vehicle collisions at the intersection by the use of
these systems for four-way intersections is that they don’t ‘safe’ (yellow state) states. The red, yellow, and green signals
allow the maximum possible movement of vehicles across of each light display are formed as individual outputs.
the intersection [3][4]. Vehicles from a few roads are made

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 International Journal of Innovative Research in Computer Science and Technology (IJIRCST)

III. IMPLEMENTATION OF TRAFFIC LIGHT Table 1: State table of the proposed system
CONTROLLER SYSTEM
No. of
The proposed traffic light controller system is designed to State North East South West
operate at a maximum frequency of 10.0 MHz. The period Clock cycles
(T) of the clock used in this system is given by the formula
T = 1/f S0 1 3 3 3 16

Where f is the maximum operating frequency of the system.

S1 2 2 3 3 4

IV. STATE DIAGRAM

S2 3 1 3 3 8
The vehicle movement during the S0 and S4 states such as
are comparatively higher than that during the other states
S3 3 2 2 3 4
such as S1, S2, S3, S5, S6, and S7. So, the green signal timing
for S0 and S4 states is set to be more than that of other states.
The signal timing for two states is set to 16 seconds and for S4 3 3 1 3 16
S2 and S6 states, the signal timing is set to 8 seconds, and for
S1, S3, S5, and S7, the signal timing is set to 4 seconds. This S5 3 3 2 2 4
implies that during the S0 and S4 states, the present state of
the displays will continue for 16 seconds and when the time
exceeds 16 seconds, the system goes into the succeeding next S6 3 3 3 1 8
state. Similarly, in other states, the present status of the
displays will continue for 8 and 4 seconds and when the time S7 2 3 3 2 4
exceeds 8 and 4 seconds, it moves into the succeeding even
state. After the S7 state, the system again enters into the S0
state and this cycle continues. The time taken for the system Similarly, if the bit is 2, it corresponds to a yellow signal and
to complete one full cycle is 64 seconds. Figure 1 illustrates indicates that the traffic flow will stop soon. If the bit is 1, it
the state diagram of the proposed system. corresponds to a green signal, and the flow of traffic in the
corresponding direction is allowed. The S1, S3, S5, and S7
states act as ‘safe’ states as the light displays show yellow
signals indicating that the flow of traffic will be stopped soon
so that vehicles from those directions can stop, since crossing
the intersection during the period of the yellow signal of the
current state may lead to accidents due to the flow of traffic
regulated during the succeeding S0 and S4 states.

VI. RESULTS AND DISCUSSION

The proposed system is designed as a Melay FSM using
Xilinx Vivado and Verilog HDL. Simulation, synthesis,
implementation, and bitstream generation were done and no
Figure 1: State diagram of the designed system. DRC violations were found.
A. Simulation
V. STATE TABLE Figure 2 In the digital symphony of Verilog, the traffic light
In each of the states, if the bit is 3, it indicates that the light controller’s waveform pirouettes through cycles,
display is showing a red signal, and so, the movement of orchestrating hues of safety and order are shown in below.
vehicles in the direction corresponding to the light display is
rejected.

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 International Journal of Innovative Research in Computer Science and Technology (IJIRCST)

Figure 2. Simulated waveform of the system

B. RTL Schematic
Figure 3 shows the RTL schematic of the designed system

Figure 3: RTL schematic of the system

C. Utilization Report during implementation. The obtained utilization report is

It was observed that the utilization report generated during shown in Figure 4.
synthesis matched with the utilization report generated

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Figure 4 Utilization report of the system

D. Power Report

Figure 5: Power report of the system

E. Device Layout After Implementation

Figure 6 shows the device layout obtained after the
implementation.

Figure 6: Device layout of the system

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 International Journal of Innovative Research in Computer Science and Technology (IJIRCST)

VI. CONCLUSION ABOUT THE AUTHORS

The traffic light controller system is well suited to regulate Dr. P. A. Nageswara Rao was born on 17-05-
traffic at four-way intersections. Verilog HDL is used for 1978. He received his B.E. from Andhra
programming purposes because if the user wishes to make University, AP, India in 2000. He completed
any changes in the system, it is possible to apply the required his M.E in Andhra University, AP, India in
2003. He was awarded a Ph.D From Andhra
changes easily through Verilog HDL code. University, Visakhapatnam, AP, India in 2016.
The simulated waveform matched the traffic light signals In the field of Process control instrumentation
obtained from the state table. The implemented system had a in 2016. His areas of interest are Process
minimal power utilization of 3.948 W and used only 0.03% Control Instrumentation, RF and Microwave
of the flip flops and 9.24% of the total IO (Input Output) Engineering, and Antennas. He has published
facilities present in the FPGA. 25 research Papers in various
Conferences/Journals/Proceedings at National
and international levels. He has a teaching
VII. FUTURE WORK experience of 22 years. Currently, he is
As a future scope, cameras and sensors can be integrated into working as an Associate Professor and Head of
the Department, of Electronics and
the designed system so that when the traffic controller system
Communication Engineering, Gayatri Vidya
sees more traffic or more vehicles, it can automatically divert Parishad College for Degree and PG
the traffic accordingly to ensure that there is no obstacle and Courses(A), Visakhapatnam, AP.
the way for the vehicles is clear.
V. D. S. Venkat was born on 22-06-2002. He
was Studying B. Tech (ECE) in Gayatri
CONFLICTS OF INTEREST Vidya Parishad College for Degree and PG
Courses(A), Visakhapatnam, AP., India
The authors declare that they have no conflict of interest.

REFERENCES Karanam Sharmila was born on 03-11-

2002. She was Studying B. Tech (ECE) in
1) Madras Institute of Technology Anna University Chennai,
Gayatri Vidya Parishad College for Degree and
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4, no. 6, pp. 740-743, Jun. 2022. [Online]. Available:
www.ijaem.net
2) Raj Kumar Goel Institute of Technology (RKGIT), Ghaziabad, Matta Tharangini was born on 07-05-2001.
Uttar Pradesh (201003), Department of Electronics and She was Studying B. Tech (ECE) in Gayatri
Communication Engineering, NBA Accredited. Vidya Parishad College for Degree and PG
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