SEHH2264: Computer Organisation 1

Lecture 3
Interconnections (continued)
and Input/Output

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Textbook: William Stallings
Computer Organization and Architecture
10th Edition
Chapter 12
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Agenda

◼Memory

◼I/O and CPU Interconnection

◼Timing

◼Transfer of Control

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The Bus
◼ The system bus is made up of the address, data
and control paths from the CPU. Memory and
memory-mapped I/O devices are connected to
this bus. Such a bus has to be able to operate at
the speed of the fastest device connected to it.

◼ The system bus demonstrates that a one size fits all

approach does not apply to computer design
because it would be hopelessly cost-ineffective to
interface low-cost, low-speed peripherals
connected to a high speed bus.

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The Bus
◼ In systems with more than one CPU (or at least
more than one device that can initiate data transfer
actions like a CPU) the bus has to decide which of
the devices that want to access the bus should be
granted access to it.

◼ This mechanism is called arbitration and is a key

feature of modern system buses.

◼A device that can take control of the system bus is

called a bus master, and a device that can only
respond to a transaction initiated by a remote bus
master is called a bus slave.

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The Bus

◼ In Figure 12.31, the CPU is a bus master and the

memory system a bus slave.

◼ One of the I/O ports has been labeled bus master

because it can control the bus (e.g., for DMA data
transfers), whereas the other peripheral is labeled
bus slave because it can respond only to read or
write accesses.

◼ The connection between the disk drive and its

controller is also labeled bus because it
represents a specialized and highly dedicated
example of the bus.
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+ Bus Structures and Topologies
◼ A simple bus structure is illustrated by the CPU plus memory plus
local bus in Figure 12.32. Only one device at a time can put data on
the data bus.

◼ Data is transferred between CPU and memory or peripherals. The

CPU is the permanent bus master and only the CPU can put data on
the bus or invite memory/peripherals to supply data via the bus.

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Bus Structures and Topologies
◼ Figure 12.33 illustrates a
bus structure that
employs two buses
linked by an expansion
interface.

◼ Each of these separate

bus systems may have
entirely different levels of
functionality; one might
be optimized for high-
speed processor-to-
memory transactions,
and the other to support
a large range of plug-in
peripherals.

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Bus Speed
◼ Suppose device A transmits data to device B. Let’s
go through the sequence of events that take place
when device A initiates the data transfer at t = 0.

◼ Initially, A drives data onto the data bus at time td,

the delay between device A initiating the transfer
and the data appearing on the bus. Data
propagates along the bus at about 70% of the
speed of light or about 1 ft/ns.

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BUS SPEED
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BUS SPEED
When the data reaches B, it must be captured.

The data setup time, ts, is the time for which the data must be available at the input to
system B for it to be recognized. The data hold, th, time is the time for which the data must
remain stable at system B’s input after it has been captured.

The time taken for a data transfer, tT, is, therefore, tT = td + tp + ts + th.

Inserting typical values for these parameters yields 4 + 1.5 + 2 + 0 = 7.5 ns, corresponding
to a data transfer rate of 1/(7.5 ns) = 109/7.5 = 133.3 MHz.

A 32-bit-wide bus can transfer data at a maximum rate of

133.3 x 32 / 8 = 533.2 MB/s.

In practice, a data transfer requires time to initiate it, called the latency, tL.

Taking latency into account gives a maximum data rate of 1/(tT + tL).

Higher data rates can be achieved with pipelining, by transmitting the next data element
before system B has completed reading the previous element.
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The Address Bus
◼ Some systems have an explicit address bus that operates in
parallel with the data bus. When the processor writes data to
memory, an address is transmitted to the memory system at the
same time the data is transmitted.

◼ Some systems combine address and data buses together into a

single multiplexed bus that carries both addresses and data
(albeit alternately).
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Multiplexed Data/Address Bus
◼ Figure
12.36 describes the multiplexed address/data
bus which requires fewer signal paths and the
connectors and sockets require fewer pins.

◼ Multiplexingaddresses and data onto the same lines

requires a multiplexer at one end of the transmission
path and a demultiplexer at the other end.

◼ Multiplexedbuses can be slower than non-

multiplexed buses and are often used when cost is
more important than speed.
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Burst Mode
◼ The efficiency of buses can be improved by operating in a
burst mode in which a sequence of data elements is
transmitted to consecutive memory addresses.

◼ Burst-mode operation is used to support cache memory

systems.

◼ Figure 12.37 illustrates the concept of burst mode

addressing where an address is transmitted for location i
and data for locations i, i+1, i+2, and i+3 are transmitted
without a further address.

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 15
+ The Control Bus
◼ The control bus regulates the flow of information on the bus.
Figure 12.38 describes a simple 2-line synchronous control bus
that uses a data-direction signal and a data validation signal. The
data direction signal is R/W* and is high to indicate a CPU read
operation and low to indicate a write operation.

write

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+ 16
The Control Bus
◼ Some systems have separate read and write strobes
rather than a R/W* signal. Individual READ* and
WRITE* signals indicate three states: an active read
state, an active write state, and a bus free state
(READ* and WRITE* both negated). A R/W* signal
introduces ambiguity because when R/W* = 0 the
bus is always executing a write operation, whereas
when R/W* = 1 indicates a read operation or the
bus is free.

◼ The active-low data valid signal, DAV*, is asserted by

the bus master to indicate that a data transfer is
taking place.

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Arbitrating for the Bus
◼ In a system with several bus masters connected to a
bus, a mechanism is needed to deal with
simultaneous bus requests. The process by which
requests are recognized and priority given to one of
them is called arbitration.

◼ localized arbitration and distributed arbitration.

◼ localized arbitration, an arbitration circuit receives requests
from the contending bus masters and then decides which of
them is to be given control of the bus.
◼ distributed arbitration, each of the masters takes part in the
arbitration process and the system lacks a specific arbiter—
each master monitors the other masters and decides whether
to continue competing for the bus or whether to give up and
wait until later.

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+ TIMING

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◼ Timing refers to the way in which events are co-ordinated on

the bus.

◼ Time taken by the system to execute a program

◼ Performance parameters:
◼ Clock speed
◼ Type and number of instructions available
◼ Average time required to execute an instruction
◼ Memory access time
◼ Power dissipation in the system
◼ Number of I/O devices and types of I/O devices connected
◼ The data transfer capacity of the bus
+ Timing

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◼ Micro-processor depending on its type can access one or

more bytes of data during the same clock cycle.
◼ The 8088 and 80188
◼ 8 bit wide data bus
◼ move 1 byte of data per a given clock cycle or 1 word (2 bytes)
of data over 2 clock cycles.
◼ The 8086, 80186, 80286 and 80386 SX
◼ 16 bit wide data bus
◼ move 1 word (2 bytes) of data over 1 clock cycle.
◼ The 80386 DX, 80486SX, and 80486 DX
◼ 32 bit wide data bus
◼ move a double word (4 bytes) of data over 1 clock cycle.
◼ The 8088/80188 would transfer the same contents of double
word over 4 clock cycles
+ Timing - Synchronous 20

◼ Buses use either synchronous timing or asychronous timing

◼ Synchronous- occurrence of events on the bus is determined
by common clock signals
◼ Control Bus includes clock line upon which a clock
transmits a regular sequence of alternating 1s and 0s of
equal duration
◼ A single 1-0 transmission is a clock cycle or bus cycle
◼ All other devices on the bus can read clock line
◼ Usually sync on leading edge and a single cycle for an
event

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+ Timing - Synchronous 21

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+ Timing - Asynchronous 22

◼ Asynchronous - interconnects devices

where information transfers between
devices are self-timed rather than
controlled by a synchronizing clock signal.
◼ Event driven
◼ Completion logic and Handshaking signals are
used to identify separate events
◼ Cheap, timing is not as critical as for
synchronous transmission, therefore hardware
can be made cheaper
◼ Set-up is very fast, so well suited for applications
where messages are generated at irregular
intervals, e.g data entry from the keyboard

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 Timing Diagram - Asynchronous 23

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+ Synchronous Timing vs Asynchronous Timing 24

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◼ Synchronous timing is simpler to implement
and test.
◼ Synchronous
timing is less flexible than
Asynchronous timing
◼ because all devices on a synchronous bus are tied to
a fixed clock rate, system cannot take advantage of
advances in device performance.

◼ Withasynchronous timing, a mixture of slow

and fast devices, using older and newer
technology, can share a bus.
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I/O Function
◼ I/O module can exchange data directly with the processor

◼ Processor can read data from or write data to an I/O module

◼ Processor identifies a specific device that is controlled by a
particular I/O module
◼ I/O instructions rather than memory referencing instructions

◼ In some cases it is desirable to allow I/O exchanges to occur

directly with memory
◼ The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
◼ The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
◼ This operation is known as direct memory access (DMA)

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 Read Memory
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Write
N Words
Address 0 Data

Data N–1

Read I/O Module Internal

Write Data

External
Address M Ports Data

Internal
Data Interrupt
Signals
External
Data

Instructions Address

Control
Data CPU Signals

Interrupt Data
Signals

Figure 3.15 Computer Modules

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CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

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Transfer of Control
◼ Reasons why transfer-of-control operations are
required:
◼ It is essential to be able to execute each instruction more
than once
◼ Virtually all programs involve some decision making
◼ It helps if there are mechanisms for breaking the task up
into smaller pieces that can be worked on one at a time

◼ Most common transfer-of-control operations

found in instruction sets:
◼ Branch
◼ Skip
◼ Procedure call

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 Memory 29
address Instruction

200
201
202 SUB X, Y
203 BRZ 211
Unconditional
branch Conditional
branch
210 BR 202
211

225 BRE R1, R2, 235

Conditional
branch
235

Figure 12.7 Branch Instructions

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Procedure Call Instructions
◼ Self-contained computer program that is incorporated into a
larger program
◼ At any point in the program the procedure may be invoked, or called
◼ Processor is instructed to go and execute the entire procedure and
then return to the point from which the call took place

◼ Two principal reasons for use of procedures:

◼ Economy
◼ A procedure allows the same piece of code to be used many times
◼ Modularity

◼ Involves two basic instructions:

◼ A call instruction that branches from the present location to the
procedure
◼ Return instruction that returns from the procedure to the place from
which it was called

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 Addresses Main Memory
31
4000

Main
4100 CALL Proc1
4101 Program

4500

4600 CALL Proc2

4601 Procedure
4650 CALL Proc2 Proc1
4651

RETURN

4800
Procedure
Proc2

RETURN

(a) Calls and returns (b) Execution sequence

Figure 12.8 Nested Procedures

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4601 4651
4101 4101 4101 4101 4101

(a) Initial stack (b) After (c) Initial (d) After (e) After (f) After (g) After
contents CALL Proc1 CALL Proc2 RETURN CALL Proc2 RETURN RETURN

Figure 12.9 Use of Stack to Implement Nested Procedures of Figure 12.8

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y2 Stack
Pointer
y1

Old Frame Pointer Frame

Pointer
Q: Return Point
Stack
x2 x2
Pointer

x1 x1

Old Frame Pointer Frame Old Frame Pointer

Pointer

P: Return Point P: Return Point

(a) P is active (b) P has called Q

Figure 12.10 Stack Frame Growth Using Sample Procedures P and Q

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x86 Operation Types
◼ The x86 provides a complex array of operation types including a
number of specialized instructions

◼ The intent was to provide tools for the compiler writer to produce
optimized machine language translation of high-level language
programs

◼ Provides four instructions to support procedure call/return:

◼ CALL
◼ ENTER
◼ LEAVE
◼ RETURN

◼ When a new procedure is called the following must be performed upon

entry to the new procedure:
◼ Push the return point on the stack
◼ Push the current frame pointer on the stack
◼ Copy the stack pointer as the new value of the frame pointer
◼ Adjust the stack pointer to allocate a frame

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Status bits (flags) 35

When the computer performs an operation, it stores status or condition

information in the CCR. The processor records whether the result is zero (Z),
negative in two’s complement terms (N), generated a carry (C), or arithmetic
overflow (V).

11011100
+11000000
110011100
Z = 0, N = 1
C = 1, V = 0

CISC processors, like the Intel IA32 update status flags after each operation.
RISC processors, like the ARM, require the programmer update the status
flags.
The ARM does it appending an S to the instruction; for example SUBS or
ADDS.
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Status bits (flags)

◼ Overflow (V):
◼ The signed result is too big or too small to fit in the destination
◼ Is ignored when doing unsigned operations

◼ Carry (C):
◼ Unsigned result is too big to fit in the destination.
◼ Is ignored when doing 2’s complement operations

◼ Zero (Z):
◼ The output value is zero

◼ Negative (N):
◼ The result is a negative value