CHAPTER

The Field-Effect
Transistor
In this chapter, we introduce a major type of transistor,
the metal-oxide-semiconductor field-effect transistor
3
(MOSFET). The MOSFET led to the electronics revolu-
tion of the 1970s and 1980s, in which the microproces-
sor made possible powerful desktop computers, laptop
computers, and sophisticated handheld calculators. The Courtesy of Mesa Boogie, Inc.
MOSFET can be made very small, so high-density very large scale integration (VLSI) circuits and high-
density memories are possible.
Two complementary devices, the n-channel MOSFET (NMOS) and the p-channel MOSFET (PMOS),
exist. Each device is equally important and allows a high degree of flexibility in electronics circuit design.
Another type of field-effect transistor is the junction FET. There are two general categories of junction
field-effect transistors (JFETs)—the pn junction FET (pn JFET) and the metal-semiconductor field-effect
transistor (MESFET), which is fabricated with a Schottky barrier junction. JFETs were developed before
MOSFETs, but the applications and uses of MOSFETs have far surpassed those of the JFET. However, we
will consider a few JFET circuits in this chapter.

PREVIEW
In this chapter, we will:
• Study and understand the operation and characteristics of the various types of MOSFETs.
• Understand and become familiar with the dc analysis and design techniques of MOSFET circuits.
• Examine three applications of MOSFET circuits.
• Investigate current source biasing of MOSFET circuits, such as those used in integrated circuits.
• Analyze the dc biasing of multistage or multitransistor circuits.
• Understand the operation and characteristics of the junction field-effect transistor, and analyze the dc
response of JFET circuits.
• Incorporate a MOS transistor in a design application that enhances the simple electronic thermome-
ter design using a diode discussed in Chapter 1.

119
120 Part 1 Semiconductor Devices and Basic Applications

3.1 MOS FIELD-EFFECT TRANSISTOR

Objective: • Understand the operation and characteristics of the various types of metal-
oxide semiconductor field-effect transistors (MOSFETs).

The metal-oxide-semiconductor field-effect transistor (MOSFET) became a practical reality in the 1970s.
The MOSFET, compared to BJTs, can be made very small (that is, it occupies a very small area on an IC
chip). Since digital circuits can be designed using only MOSFETs, with essentially no resistors or diodes re-
quired, high-density VLSI circuits, including microprocessors and memories, can be fabricated. The MOS-
FET has made possible the handheld calculator, the powerful personal computer, and the laptop computer.
MOSFETs can also be used in analog circuits, as we will see in the next chapter.
In the MOSFET, the current is controlled by an electric field applied perpendicular to both the semicon-
ductor surface and to the direction of current. The phenomenon used to modulate the conductance of a semi-
conductor, or control the current in a semiconductor, by applying an electric field perpendicular to the surface
is called the field effect. The basic transistor principle is that the voltage between two terminals controls the
current through the third terminal.
In the following two sections, we will discuss the various types of MOSFETs, develop the i–v charac-
teristics, and then consider the dc biasing of various MOSFET circuit configurations. After studying these
sections, you should be familiar and comfortable with the MOSFET and MOSFET circuits.

3.1.1 Two-Terminal MOS Structure

The heart of the MOSFET is the metal-oxide-semiconductor capacitor shown in Figure 3.l. The metal may be
aluminum or some other type of metal. In most cases, the metal is replaced by a high-conductivity polycrys-
talline silicon layer deposited on the oxide. However, the term metal is usually still used in referring to MOS-
FETs. In the figure, the parameter tox is the thickness of the oxide and ox is the oxide permittivity.
The physics of the MOS structure can be explained with the aid of a simple parallel-plate capacitor.1 Fig-
ure 3.2(a) shows a parallel-plate capacitor with the top plate at a negative voltage with respect to the bottom
plate. An insulator material separates the two plates. With this bias, a negative charge exists on the top plate,
a positive charge exists on the bottom plate, and an electric field is induced between the two plates, as shown.
A MOS capacitor with a p-type semiconductor substrate is shown in Figure 3.2(b). The top metal terminal,
also called the gate, is at a negative voltage with respect to the semiconductor substrate. From the example of
the parallel-plate capacitor, we can see that a negative charge will exist on the top metal plate and an electric

1
The capacitance of a parallel plate capacitor, neglecting fringing fields, is C = A/d , where A is the area of one plate, d is the distance
between plates, and is the permittivity of the medium between the plates.
 Chapter 3 The Field-Effect Transistor 121

Gate terminal
Metal
Insulator
tox eox
(oxide)
Semiconductor
substrate

Substrate or
body terminal

Figure 3.1 The basic MOS capacitor structure

– – – – – –
E-field –
– – – – – – + + + + + + V
– – – – – – – p-type
– +
d e E-field V E-field V
p-type h+ +
+ Accumulation
+ + + + + +
layer of holes

(a) (b) (c)

Figure 3.2 (a) A parallel-plate capacitor, showing the electric field and conductor charges, (b) a corresponding MOS
capacitor with a negative gate bias, showing the electric field and charge flow, and (c) the MOS capacitor with an
accumulation layer of holes

field will be induced in the direction shown in the figure. If the electric field penetrates the semiconductor, the
holes in the p-type semiconductor will experience a force toward the oxide-semiconductor interface. The equi-
librium distribution of charge in the MOS capacitor with this particular applied voltage is shown in Fig-
ure 3.2(c). An accumulation layer of positively charged holes at the oxide-semiconductor interface corresponds
to the positive charge on the bottom “plate” of the MOS capacitor.
Figure 3.3(a) shows the same MOS capacitor, but with the polarity of the applied voltage reversed. A pos-
itive charge now exists on the top metal plate and the induced electric field is in the opposite direction, as
shown. In this case, if the electric field penetrates the semiconductor, holes in the p-type material will experi-
ence a force away from the oxide-semiconductor interface. As the holes are pushed away from the interface, a
negative space-charge region is created, because of the fixed acceptor impurity atoms. The negative charge in
the induced depletion region corresponds to the negative charge on the bottom “plate” of the MOS capacitor.
Figure 3.3(b) shows the equilibrium distribution of charge in the MOS capacitor with this applied voltage.

+ + + + + + + + + +

+ +
xdT – – – – – – V
xd V
+ + + + –
p-type – p-type
+
V
E-field Induced negative
p-type h+ – Induced negative Electron
space-charge space-charge inversion
region region layer

(a) (b) (c)

Figure 3.3 The MOS capacitor with p-type substrate: (a) effect of positive gate bias, showing the electric field and
charge flow, (b) the MOS capacitor with an induced space- charge region due to a moderate positive gate bias, and (c)
the MOS capacitor with an induced space-charge region and electron inversion layer due to a larger positive gate bias
122 Part 1 Semiconductor Devices and Basic Applications

When a larger positive voltage is applied to the gate, the magnitude of the induced electric field in-
creases. Minority carrier electrons are attracted to the oxide-semiconductor interface, as shown in Figure
3.3(c). This region of minority carrier electrons is called an electron inversion layer. The magnitude of the
charge in the inversion layer is a function of the applied gate voltage.
The same basic charge distributions can be obtained in a MOS capacitor with an n-type semiconductor
substrate. Figure 3.4(a) shows this MOS capacitor structure, with a positive voltage applied to the top gate
terminal. A positive charge is created on the top gate and an electric field is induced in the direction shown.
In this situation, an accumulation layer of electrons is induced in the n-type semiconductor.

+ + + + + +
E + – – – – – – – – – –
– – – – – – V E – E –
n-type – V + + + + + + V
+ +
n-type n-type
Electron
accumulation
layer Induced positive space-charge region Hole inversion layer

(a) (b) (c)

Figure 3.4 The MOS capacitor with n-type substrate: (a) effect of a positive gate bias and the formation of an electron
accumulation layer, (b) the MOS capacitor with an induced space-charge region due to a moderate negative gate bias, and
(c) the MOS capacitor with an induced space-charge region and hole inversion layer due to a larger negative gate bias

Figure 3.4(b) shows the case when a negative voltage is applied to the gate terminal. A positive space-
charge region is induced in the n-type substrate by the induced electric field. When a larger negative voltage
is applied, a region of positive charge is created at the oxide-semiconductor interface, as shown in Figure
3.4(c). This region of minority carrier holes is called a hole inversion layer. The magnitude of the positive
charge in the inversion layer is a function of the applied gate voltage.
The term enhancement mode means that a voltage must be applied to the gate to create an inversion
layer. For the MOS capacitor with a p-type substrate, a positive gate voltage must be applied to create the
electron inversion layer; for the MOS capacitor with an n-type substrate, a negative gate voltage must be
applied to create the hole inversion layer.

3.1.2 n-Channel Enhancement-Mode MOSFET

We will now apply the concepts of an inversion layer charge in a MOS capacitor to create a transistor.

Transistor Structure
Figure 3.5(a) shows a simplified cross section of a MOS field-effect transistor. The gate, oxide, and p-type
substrate regions are the same as those of a MOS capacitor. In addition, we now have two n-regions, called
the source terminal and drain terminal. The current in a MOSFET is the result of the flow of charge in the
inversion layer, also called the channel region, adjacent to the oxide–semiconductor interface.
 Chapter 3 The Field-Effect Transistor 123

Source vGS vDS

Oxide Metal
electrode

Source metal Poly gate Gate oxide Drain metal

W
Gate
Source Drain
tox
n+ n+
n+ n+
Channel
L
p-type
Source Drain Field oxide

p-substrate
(Substrate bias)
(a) (b)

Figure 3.5 (a) Schematic diagram of an n-channel enhancement-mode MOSFET and (b) an n-channel MOSFET,
showing the field oxide and polysilicon gate

The channel length L and channel width W are defined on the figure. The channel length of a typical in-
tegrated circuit MOSFET is less than 1 µm (10−6 m), which means that MOSFETs are small devices. The
oxide thickness tox is typically on the order of 400 angstroms, or less.
The diagram in Figure 3.5(a) is a simplified sketch of the basic structure of the transistor. Figure 3.5(b)
shows a more detailed cross section of a MOSFET fabricated into an integrated circuit configuration. A thick
oxide, called the field oxide, is deposited outside the area in which the metal interconnect lines are formed.
The gate material is usually heavily doped polysilicon. Even though the actual structure of a MOSFET may
be fairly complex, the simplified diagram may be used to develop the basic transistor characteristics.

Basic Transistor Operation

With zero bias applied to the gate, the source and drain terminals are separated by the p-region, as shown in
Figure 3.6(a). This is equivalent to two back-to-back diodes, as shown in Figure 3.6(b). The current in this
case is essentially zero. If a large enough positive gate voltage is applied, an electron inversion layer is cre-
ated at the oxide–semiconductor interface and this layer “connects” the n-source to the n-drain, as shown in

Gate (G) G

Source (S) Drain (D) S D

n+ n+ –– –– –– –
n+ n+
L
Electron
p-type p
S D inversion layer

Substrate or body (B) Substrate or body (B)

(a) (b) (c)

Figure 3.6 (a) Cross section of the n-channel MOSFET prior to the formation of an electron inversion layer,
(b) equivalent back-to-back diodes between source and drain when the transistor is in cutoff, and (c) cross section after
the formation of an electron inversion layer
124 Part 1 Semiconductor Devices and Basic Applications

Figure 3.6(c). A current can then be generated between the source and drain terminals. Since a voltage must
be applied to the gate to create the inversion charge, this transistor is called an enhancement-mode MOS-
FET. Also, since the carriers in the inversion layer are electrons, this device is also called an n-channel
MOSFET (NMOS).
The source terminal supplies carriers that flow through the channel, and the drain terminal allows the car-
riers to drain from the channel. For the n-channel MOSFET, electrons flow from the source to the drain with
an applied drain-to-source voltage, which means the conventional current enters the drain and leaves the
source. The magnitude of the current is a function of the amount of charge in the inversion layer, which in
turn is a function of the applied gate voltage. Since the gate terminal is separated from the channel by an
oxide or insulator, there is no gate current. Similarly, since the channel and substrate are separated by a space-
charge region, there is essentially no current through the substrate.

3.1.3 Ideal MOSFET Current–Voltage

Characteristics—NMOS Device

The threshold voltage of the n-channel MOSFET, denoted as VT N , is defined2 as the applied gate voltage
needed to create an inversion charge in which the density is equal to the concentration of majority carriers in
the semiconductor substrate. In simple terms, we can think of the threshold voltage as the gate voltage re-
quired to “turn on” the transistor.
For the n-channel enhancement-mode MOSFET, the threshold voltage is positive because a positive gate
voltage is required to create the inversion charge. If the gate voltage is less than the threshold voltage, the cur-
rent in the device is essentially zero. If the gate voltage is greater than the threshold voltage, a drain-to-source
current is generated as the drain-to-source voltage is applied. The gate and drain voltages are measured with
respect to the source.
Figure 3.7(a) shows an n-channel enhancement-mode MOSFET with the source and substrate terminals
connected to ground. The gate-to-source voltage is less than the threshold voltage, and there is a small drain-
to-source voltage. With this bias configuration, there is no electron inversion layer, the drain-to-substrate pn
junction is reverse biased, and the drain current is zero (neglecting pn junction leakage currents).
Figure 3.7(b) shows the same MOSFET with an applied gate voltage greater than the threshold voltage.
In this situation, an electron inversion layer is created and, when a small drain voltage is applied, electrons in
the inversion layer flow from the source to the positive drain terminal. The conventional current enters the
drain terminal and leaves the source terminal. Note that a positive drain voltage creates a reverse-biased
drain-to-substrate pn junction, so current flows through the channel region and not through a pn junction.
The iD versus v DS characteristics3 for small values of v DS are shown in Figure 3.8. When vG S < VT N ,
the drain current is zero. When vG S is greater than VT N , the channel inversion charge is formed and the drain

2
The usual notation for threshold voltage is VT . However, since we have defined the thermal voltage as VT = kT /q , we will use VT N
for the threshold voltage of the n-channel device.
3
The voltage notation v DS and vG S , with the dual subscript, denotes the voltage between the drain (D) and source (S) and between the
gate (G) and source (S), respectively. Implicit in the notation is that the first subscript is positive with respect to the second subscript.
 Chapter 3 The Field-Effect Transistor 125

vGS < VTN +vDS vGS > VTN +vDS

S G D S G D

iD = 0 iD

n+ n+ – ––– – ––
n+ n+

Space- Space- Induced electron

p charge regions charge regions p inversion layer

(a) (b)

Figure 3.7 The n-channel enhancement-mode MOSFET (a) with an applied gate voltage vG S < VT N , and (b) with an
applied gate voltage vG S > VT N

current increases with v DS . Then, with a larger gate voltage, a larger inversion iD vGS2 > vGS1
charge density is created, and the drain current is greater for a given value of v DS .
Figure 3.9(a) shows the basic MOS structure for vG S > VT N and a small ap- vGS1 > VTN
plied v DS . In the figure, the thickness of the inversion channel layer qualitatively
indicates the relative charge density, which for this case is essentially constant
along the entire channel length. The corresponding iD versus v DS curve is also vGS < VTN
shown in the figure. vDS
Figure 3.9(b) shows the situation when v DS increases. As the drain voltage
increases, the voltage drop across the oxide near the drain terminal decreases, Figure 3.8 Plot of i D versus
v characteristic for small
which means that the induced inversion charge density near the drain also de- DS
values of v DS at three vG S
creases. The incremental conductance of the channel at the drain then decreases, voltages
which causes the slope of the iD versus v DS curve to decrease. This effect is
shown in the iD versus v DS curve in the figure.
As v DS increases to the point where the potential difference, vG S − v DS , across the oxide at the drain
terminal is equal to VT N , the induced inversion charge density at the drain terminal is zero. This effect is
shown schematically in Figure 3.9(c). For this condition, the incremental channel conductance at the drain is
zero, which means that the slope of the iD versus v DS curve is zero. We can write
vG S − v DS (sat) = VT N (3.1(a))

or
v DS (sat) = vG S − VT N (3.1(b))

where v DS (sat) is the drain-to-source voltage that produces zero inversion charge density at the drain
terminal.
When v DS becomes larger than v DS (sat), the point in the channel at which the inversion charge is just
zero moves toward the source terminal. In this case, electrons enter the channel at the source, travel through
the channel toward the drain, and then, at the point where the charge goes to zero, are injected into the space-
charge region, where they are swept by the E-field to the drain contact. In the ideal MOSFET, the drain cur-
rent is constant for v DS > v DS (sat). This region of the iD versus v DS characteristic is referred to as the satu-
ration region, which is shown in Figure 3.9(d).
As the applied gate-to-source voltage changes, the iD versus v DS curve changes. In Figure 3.8, we saw
that the initial slope of iD versus v DS increases as vG S increases. Also, Equation (3.1(b)) shows that v DS (sat)
126 Part 1 Semiconductor Devices and Basic Applications

vGS1 > VTN

Channel vGS1
inversion
charge
Oxide iD
S Oxide iD
vDS S
vDS

p-type Depletion Channel

region p-type inversion
charge

iD iD

vDS vDS
(a) (b)

vGS1 vGS1

Oxide iD Oxide iD
S S vDS (sat)
vDS (sat) vDS > vDS (sat)
E-field depletion region
Channel
p-type inversion
charge p-type Channel
inversion
charge

iD iD

Saturation
region

vDS (sat) vDS vDS (sat) vDS

(c) (d)

Figure 3.9 Cross section and i D versus v DS curve for an n-channel enhancement-mode MOSFET when vG S > VT N for
(a) a small v DS value, (b) a larger v DS value but for v DS < v DS (sat) , (c) v DS = v DS (sat), and (d) v DS > v DS (sat)

is a function of vG S . Therefore, we can generate the family of curves for this n-channel enhancement mode
MOSFET as shown in Figure 3.10.
Although the derivation of the current–voltage characteristics of the MOSFET is beyond the scope of
this text, we can define the relationships. The region for which v DS < v DS (sat) is known as the nonsatura-
tion or triode region. The ideal current–voltage characteristics in this region are described by the equation
i D = K n 2(vG S − VT N )v DS − v 2DS (3.2(a))
 Chapter 3 The Field-Effect Transistor 127

iD vDS (sat) = vGS – VTN

vGS5 > vGS4
Nonsaturation
region,
Saturation region
vDS < vDS (sat)
vDS > vDS (sat)
vGS4 > vGS3

vGS3 > vGS2

vGS2 > vGS1

vGS1 > VTN > 0

vDS

Figure 3.10 Family of iD versus v DS curves for an n-channel enhancement-mode MOSFET. Note that the v DS (sat)
voltage is a single point on each of the curves. This point denotes the transition between the nonsaturation region and
the saturation region

In the saturation region, the ideal current–voltage characteristics for vG S > VT N are described by the
equation
i D = K n (vG S − VT N )2 (3.2(b))
In the saturation region, since the ideal drain current is independent of the drain-to-source voltage, the incre-
mental or small-signal resistance is infinite. We see that
r0 = v DS / i D |vG S =const. = ∞
The parameter Kn is sometimes called the transconduction parameter for the n-channel device. However,
this term is not to be confused with the small-signal transconductance parameter introduced in the next chap-
ter. For simplicity, we will refer to this parameter as the conduction parameter, which for an n-channel de-
vice is given by
W µn Cox
Kn = (3.3(a))
2L
where Cox is the oxide capacitance per unit area. The capacitance is given by
Cox = ox /tox

where tox is the oxide thickness and ox is the oxide permittivity. For silicon devices,
−14
ox = (3.9)(8.85 × 10 ) F/cm. The parameter µn is the mobility of the electrons in the inversion layer. The
channel width W and channel length L were shown in Figure 3.5(a).
As Equation (3.3(a)) indicates, the conduction parameter is a function of both electrical and geometric
parameters. The oxide capacitance and carrier mobility are essentially constants for a given fabrication tech-
nology. However, the geometry, or width-to-length ratio W/L, is a variable in the design of MOSFETs that is
used to produce specific current–voltage characteristics in MOSFET circuits.
We can rewrite the conduction parameter in the form
kn W
Kn = · (3.3(b))
2 L
128 Part 1 Semiconductor Devices and Basic Applications

where kn = µn Cox and is called the process conduction parameter. Normally, kn is considered to be a con-
stant for a given fabrication technology, so Equation (3.3(b)) indicates that the width-to-length ratio W/L is
the transistor design variable.

EXAMPLE 3.1
Objective: Calculate the current in an n-channel MOSFET.
Consider an n-channel enhancement-mode MOSFET with the following parameters: VT N = 0.75 V,
W = 40 µm, L = 4 µm, µn = 650 cm2 /V–s, tox = 450 Å, and ox = (3.9)(8.85 × 10−14 ) F/cm. Determine
the current when VG S = 2VT N , for the transistor biased in the saturation region.
Solution: The conduction parameter is determined by Equation (3.3(a)). First, consider the units involved in
this equation, as follows:
cm2 F
W (cm) · µn ox
V–s cm F (C/V) A
Kn = = = = 2
2L(cm) · tox (cm) V–s V–s V
The value of the conduction parameter is therefore
W µn ox (40 × 10−4 )(650)(3.9)(8.85 × 10−14 )
Kn = =
2Ltox 2(4 × 10−4 )(450 × 10−8 )
or
K n = 0.249 mA/V2
From Equation (3.2(b)) for vG S = 2VT N , we find
i D = K n (vG S − VT N )2 = (0.249)(1.5 − 0.75)2 = 0.140 mA

Comment: The current capability of a transistor can be increased by increasing the conduction parameter.
For a given fabrication technology, K n is adjusted by varying the transistor width W.

EXERCISE PROBLEM
Ex 3.1: An NMOS transistor with VT N = 1 V has a drain current i D = 0.8 mA when vG S = 3 V and
v DS = 4.5 V. Calculate the drain current when: (a) vG S = 2 V, v DS = 4.5 V; and (b) vG S = 3 V, v DS = 1 V.
(Ans. (a) 0.2 mA (b) 0.6 mA)

3.1.4 p-Channel Enhancement-Mode MOSFET

The complementary device of the n-channel enhancement-mode MOSFET is the p-channel enhancement-
mode MOSFET.

Transistor Structure
Figure 3.11 shows a simplified cross section of the p-channel enhancement-mode transistor. The substrate is
now n-type and the source and drain areas are p-type. The channel length, channel width, and oxide thickness
parameter definitions are the same as those for the NMOS device shown in Figure 3.5(a).
 Chapter 3 The Field-Effect Transistor 129

+ –
vSD

+ – iD
vSG

Source Gate W Drain

tox
p+ p+
L

n-type

Body

Figure 3.11 Cross section of p-channel enhancement-mode MOSFET. The device is cut off for v SG = 0. The
dimension W extends into the plane of the page.

Basic Transistor Operation

The operation of the p-channel device is the same as that of the n-channel device, except the hole is the charge
carrier rather than the electron. A negative gate bias is required to induce an inversion layer of holes in the
channel region directly under the oxide. The threshold voltage for the p-channel device is denoted as VT P .4
Since the threshold voltage is defined as the gate voltage required to induce the inversion layer, then VT P < 0
for the p-channel enhancement-mode device.
Once the inversion layer has been created, the p-type source region is the source of the charge carrier so
that holes flow from the source to the drain. A negative drain voltage is therefore required to induce an elec-
tric field in the channel forcing the holes to move from the source to the drain. The conventional current di-
rection, then, for the PMOS transistor is into the source and out of the drain. The conventional current direc-
tion and voltage polarity for the PMOS device are reversed compared to the NMOS device.
Note in Figure 3.11 the reversal of the voltage subscripts. For v SG > 0, the gate voltage is negative with
respect to that at the source. Similarly, for v S D > 0, the drain voltage is negative with respect to that at the
source.

3.1.5 Ideal MOSFET Current–Voltage

Characteristics—PMOS Device

The ideal current–voltage characteristics of the p-channel enhancement-mode device are essentially the same
as those shown in Figure 3.10, noting that the drain current is out of the drain and v DS is replaced by v S D . The
saturation point is given by v S D (sat) = v SG + VT P . For the p-channel device biased in the nonsaturation
region, the current is given by
i D = K p 2(v SG + VT P )v S D − v S2 D (3.4(a))

4
Using a different threshold voltage parameter for a PMOS device compared to the NMOS device is for clarity only.
130 Part 1 Semiconductor Devices and Basic Applications

In the saturation region, the current is given by

i D = K p (v SG + VT P )2 (3.4(b))
and the drain current exits the drain terminal. The parameter K p is the conduction parameter for the p-chan-
nel device and is given by
W µ p Cox
Kp = (3.5(a))
2L
where W, L, and Cox are the channel width, length, and oxide capacitance per unit area, as previously defined.
The parameter µ p is the mobility of holes in the hole inversion layer. In general, the hole inversion layer mo-
bility is less than the electron inversion layer mobility.
We can also rewrite Equation (3.5(a)) in the form
kp W
Kp = · (3.5(b))
2 L
where k p = µ p Cox .
For a p-channel MOSFET biased in the saturation region, we have
v S D > v S D (sat) = v SG + VT P (3.6)

EXAMPLE 3.2
Objective: Determine the source-to-drain voltage required to bias a p-channel enhancement-mode MOS-
FET in the saturation region.
Consider an enhancement-mode p-channel MOSFET for which K p = 0.2 mA/V2, VT P = − 0.50 V, and
i D = 0.50 mA.
Solution: In the saturation region, the drain current is given by
i D = K p (v SG + VT P )2
or
0.50 = 0.2(v SG − 0.50)2
which yields
v SG = 2.08 V
To bias this p-channel MOSFET in the saturation region, the following must apply:
v S D > v S D (sat) = v SG + VT P = 2.08 − 0.5 = 1.58 V

Comment: Biasing a transistor in either the saturation or the nonsaturation region depends on both the gate-
to-source voltage and the drain-to-source voltage.

EXERCISE PROBLEM
Ex 3.2: (a) For a PMOS device, the threshold voltage is VT P = −2 V and the applied source-to-gate volt-
age is v SG = 3 V. Determine the region of operation when: (i) v S D = 0.5 V; (ii) v S D = 2 V; and (iii)
v S D = 5 V. (b) Repeat part (a) for a depletion-mode PMOS device with VT P = +0.5 V. (Ans. (a) (i) non-
saturation, (ii) saturation, (iii) saturation; (b) nonsaturation, (ii) nonsaturation, (iii) saturation)
 Chapter 3 The Field-Effect Transistor 131

3.1.6 Circuit Symbols and Conventions

The conventional circuit symbol for the n-channel enhancement-mode MOSFET is shown in Figure 3.12(a).
The vertical solid line denotes the gate electrode, the vertical broken line denotes the channel (the broken line
indicates the device is enhancement mode), and the separation between the gate line and channel line denotes
the oxide that insulates the gate from the channel. The polarity of the pn junction between the substrate and
the channel is indicated by the arrowhead on the body or substrate terminal. The direction of the arrowhead
indicates the type of transistor, which in this case is an n-channel device. This symbol shows the four-termi-
nal structure of the MOSFET device.

D D D

iD iD iD

+ + +
B vDS G vDS G vDS
G – + +
+ – –
vGS vGS vGS
– – –

S S S
(a) (b) (c)

Figure 3.12 The n-channel enhancement-mode MOSFET: (a) conventional circuit symbol, (b) circuit symbol that will
be used in this text, and (c) a simplified circuit symbol used in more advanced texts

In most applications in this text, we will implicitly assume that the source and substrate terminals are
connected together. Explicitly drawing the substrate terminal for each transistor in a circuit becomes redun-
dant and makes the circuits appear more complex. Instead, we will use the circuit symbol for the n-channel
MOSFET shown in Figure 3.12(b). In this symbol, the arrowhead is on the source terminal and it indicates
the direction of current, which for the n-channel device is out of the source. By including the arrowhead in
the symbol, we do not need to explicitly indicate the source and drain terminals. We will use this circuit sym-
bol throughout the text except in specific applications.
In more advanced texts and journal articles, the circuit symbol of the n-channel MOSFET shown in Fig-
ure 3.12(c) is generally used. The gate terminal is obvious and it is implicitly understood that the “top” ter-
minal is the drain and the “bottom” terminal is the source. The top terminal, in this case the drain, is usually
at a more positive voltage than the bottom terminal. In this introductory text, we will use the symbol shown
in Figure 3.12(b) for clarity.
The conventional circuit symbol for the p-channel enhancement-mode MOSFET appears in Figure
3.13(a). Note that the arrowhead direction on the substrate terminal is reversed from that in the n-channel en-
hancement-mode device. This circuit symbol again shows the four terminal structure of the MOSFET device.
The circuit symbol for the p-channel enhancement-mode device shown in Figure 3.13(b) will be used in
this text. The arrowhead is on the source terminal indicating the direction of the current, which for the p-chan-
nel device is into the source terminal.
132 Part 1 Semiconductor Devices and Basic Applications

S S S

+ + +
vSG vSG vSG
– + + +
G
vDS – –
B G vSD G vSD
– – –

iD iD iD

D D D
(a) (b) (c)

Figure 3.13 The p-channel enhancement-mode MOSFET: (a) conventional circuit symbol, (b) circuit symbol that will
be used in this text, and (c) a simplified circuit symbol used in more advanced texts

In more advanced texts and journal articles, the circuit symbol of the p-channel MOSFET shown in Fig-
ure 3.13(c) is generally used. Again, the gate terminal is obvious but includes the O symbol to indicate that
this is a PMOS device. It is implicitly understood that the “top” terminal is the source and the “bottom” ter-
minal is the drain. The top terminal, in this case the source, is normally at a higher potential than the bottom
terminal. Again, in this text, we will use the symbol shown in Figure 3.13(b) for clarity.

3.1.7 Additional MOSFET Structures and Circuit Symbols

Before we start analyzing MOSFET circuits, there are two other MOSFET structures in addition to the n-
channel enhancement-mode device and the p-channel enhancement-mode device that need to be considered.

n-Channel Depletion-Mode MOSFET

Figure 3.14(a) shows the cross section of an n-channel depletion-mode MOSFET. When zero volts are ap-
plied to the gate, an n-channel region or inversion layer exists under the oxide as a result, for example, of im-
purities introduced during device fabrication. Since an n-region connects the n-source and n-drain, a drain-
to-source current may be generated in the channel even with zero gate voltage. The term depletion mode

vGS = 0 +vDS VTN < vGS < 0 +vDS vGS > 0 +vDS
S G D S G D S G D

iD iD iD

– – – – –
n+ n+ n+ n+ n+ n+
Electron
n-channel Depletion accumulation
p-type p-type region p-type layer

(a) (b) (c)

Figure 3.14 Cross section of an n-channel depletion mode MOSFET for: (a) vG S = 0, (b) vG S < 0, and (c) vG S > 0