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Unit-4 Question Bank

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Unit-4 Question Bank

Uploaded by

Akshat Srivastava
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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ABES ENGINEERING COLLEGE,GHAZIABAD

Unit No-04 Question Bank


Paper Code:BCS302
Paper Name: Computer Organization and Architecture

No. Questions CO KL
1. Consider a machine with a byte addressable main
memory of 216 bytes and block size of 8 bytes. Assume CO 4 K3
that a direct mapped cache cosnsiting of 32 lines used
with this machine. How many bits will be there in Tag
line, word field of format of main memory addresses ?
UGC-NET-2020
2. Consider a direct mapped cache of size 32 KB with
block size 32 bytes. The CPU generate 32-bit address. CO 4 K3
The number of bits required for cache indexing and Tag
bit respectively.
GATE 2005

3. Write a short note on Magnetic Tape, Magnetic disk and


Optical disk. CO 4 K1

4. Explain the following terms with example.


a) Locality of reference CO 4 K1
b) Cache write back
c) Cache write through
d) Simultaneous Access

5. Consider a fully associative cache with 8 cache blocks


(0-7). The memory block requests are in the order:- CO 4 K3
4,3,25,,8,19,6,25,8,16,35,45,22,8,3,16,25,7.
If LRU(Least Recent Unit) replacement policy is used.
Which cache block will have memory block 7 ?Also
calcu;ate the hit ratio and miss ratio.
GATE 2004

6. What are the differences between SRAM & DRAM?


CO 4 K1
7. Discuss the Concept of Cache Memory with an
example. CO 4 K2

8. The logical address space in a computer system


consisting 8 pages and 1024 words each, mapped into a CO 4 K3
physical memory of 32 frames. How many bits are
there in the physical address and logical address
respectively?

9. Consider a cache consisting of 256 block of 16 words

ABES Engineering College


D/O CSE-AIML Page 1
each for a total of 4096 words and assume that the main CO 4 K3
memory is addressable by a 16 bit addresses and it
consist of 4K blocks.How many bits are there in
TAG,SET, WORD field for 2-way set associative
technique ?
A
KTU 2020-21

10. A virtual memory has a page size of 1k words. There


are 8 pages and 4 blocks. The associative memory page
contains the following entries.
PAGE BLOCK
0 3
2 1 K3
5 2 CO 4
7 0
Make a list of virtual addresses (in decimal) that will
cause page fault if used by CPU.

11. A Digital computer has a memory unit of 64 K*16 and


a cache memory of 1K words.The Cache uses direct
mapping with a block size of 4 words.
Calculate: K3
a) How many bits are there in the tag, CO 4
index, block and word fields of the address
format.
b)
c) How many bits are there in each word of
cache
d) how many blocks can cache accommodate.
AKTU 2021-22

12. Discuss 2D RAM and 2.5D RAM with suitable K2


diagram. CO 4

13. Calculate the page fault for a given string with K3


the help of LRU & FIFO page replacement
algorithm , Size of frames =4 and string CO 4
1,2,3,4,2,1,5,6,2,1,2,3,7,6,3,2,1,2,3,6
AKTU 2020-
ABES Engineering College
D/O CSE-AIML Page 2
21

14. What do you mean by Virtual memory? Discuss 𝐾2


how Paging helps in implementing Virtual memory?
CO 4

K2
15. Discuss the memory hierarchy in computer
system in the context of speed,size and cost. CO 4
AKTU 2020-21

16. Discuss the following:

K2
a) RAM Vs ROM
b) HIT Ratio and MISS Ratio CO 4
c) FIFO Vs LRU

K2
17. Discuss the different mapping techniques used in cache
memories and their relative merits and demerits. CO 4

18. A computer uses RAM chips of 1024 * 1 capacity.


(a.) How many chips are needed & how should their CO 4 K3
address line be connected to provide a memory capacity
of 1024 * 8 ?
(b.) How many chips are needed to provide a memory
capacity of 16 KB ? AKTU 2020-21

19. An eight way set associative cache consists of a total of


256 blocks. The main memory contain 8192
blocks ,each consisting of 128 words.
K3
(a.) How many bits are there in the main memory
CO 4
address?
(b)How many bits are there in TAG, SET and WORD
fields ?
AKTU 2022-23
UGC-NET 2012

20. What is the average memory access time time for a


machine with a cache hit rate of 80 % and cache access
time of 5 ns and main memory access time of 100 ns CO 4 K3
when
(a.) Simultaneously access memory organizations is
used
(b.) Hierachical memory organizations is used.

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ABES Engineering College
D/O CSE-AIML Page 4

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