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Assignment 2_21EC733

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0% found this document useful (0 votes)
20 views2 pages

Assignment 2_21EC733

Uploaded by

Pallavi Gaonkar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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JAIN COLLEGE OF ENGINEERING, BELAGAVI

Department of Electronics & Communication Engineering


Academic Year: 2024-25
Assignment II

Sem (Div.): VII (A, B & C)


Sub: Digital System Design using Verilog Sub Code: 21EC733
Date of Assignment: 11/11/2024 Submission Date: 20/11/2024
CO’ Bloom’s
Q. No. Questions PO’s Cognitive
s Levels
Module 3
1 Explain system level parallelism and pipelining
Determine contents after each of the following TMS320
C54XX addressing mode is used. Assume current content
2 AR4 to be 200h and AR0 as 20h

3 Compare architectural features of 3 fixed point DSPs.


Write status register(ST0) processor mode status register
4
(PMST) format and explain various bit functions.
With a block diagram explain functional architecture of
5
TMS320C54XX processor.
Write a program to compute sum of three product terms given
by the equation
6

7 Describe operation of hardware timer with a neat diagram


Sketch functional diagram of ALU of TMS320 C54XX and
8
briefly explain.
Module 4
Determine the value of each of the following 16 bit numbers
9 represented using given Q notation a) 4400h as Q0 b) 0.3125
as Q15 c)D800h ad Q15 d)FEA0h as Q7
Explan the implementation of FIR filter in TMS 320 CS4XX
10
DSP using memory organization and block diagram
Determine the following for 8 and 256 point FFT computation
i) No of stages
ii) No of Butterflies in each stage
11
iii) No of Butterflies needed for entire computation
iv) No of Butterflies that require complex twiddle
factors
Derive an optimum scaling factor for DIT FFT butterfly and
12
explain the butterfly computation in DIT-FFT
13 Implement the block diagram of FIR filter and briefly explain
Sketch the block diagram of second order IIR filter and briefly
14
explain
15 Write a program to multiply two Q15 numbers.
16 Write a subroutine for 8 point DIT FFT algorithm.
Prepared by Approved by HOD

Signature: Signature:

Name: Prof. DP/KP/SH Name:

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