1

Subject : Digital Logic

Chapter : Combinational Circuit

1. [MCQ] Y I0 MUX
2×1 f2
Match List-I with List-II as shown below and select X I1 S0
the correct answer using the codes given below the
B I0 MUX
lists: 2×1
A I1 S0 f1
List-I List-II
B I0 Z
Y
P. B I1 S0 1. OR (a) X = 0, Y = 1 and Z = A
(b) X = 1, Y = 0 and Z = A
A
(c) X = 0, Y = 1 and Z = B
B I0
Q. Y 2. NOR (d) X = 1, Y = 0 and Z = A
1 I1 S0

A
3. [MCQ]
B I0
R. Y 3. NAND The output of MUX as configured below, will be
0 I1 S0

R I0 4×1
A
I1 MUX
1 I0
Y I2 f
S. I1 S0 4. XOR
B
I3
A S1 S0
5. XNOR
P Q R S
P Q
(a) 4 2 1 3
(a) f = PQ + QR + PR (b) f = (P  Q) R
(b) 4 1 3 2
(c) f = (P  Q) R (d) f=PQR
(c) 5 2 3 1
(d) 5 1 2 3
4. [MCQ]
A combinational circuit using 8 × 1 MUX, is shown
2. [MCQ] below. The minimized expression for Z, is
Two multiplexers of size 2 × 1 are coupled as shown
below, to implement 2-input NAND logic such that
f 2 = AB . Then X, Y and Z should be selected as
 1 I0 MUX If de-multiplexer has active high outputs instead of
1 I1 active low outputs, then in order that outputs do not
1 I2 change
0 I3 De-MUX 0
0 I4 1×8 y1
Z 1
0 I5 2
+VCC
I6 3
1
Din 4
0 I7 S2 S1 S0 5
6
y2
7
(MSB) ABC (LSB)
(a) C(A + B) (b) C(A + B) x y z

(c) C + AB (d) C + AB (a) NAND gates should be replaced by NOR

gates
(b) NAND gates should be replaced by OR gates
5. [MCQ]
(c) NAND gates should be replaced by AND
A 2 × 1 MUX having switching delay of 1 sec is
gates
configured as shown below. The select input ‘S0’
and the output of MUX, are interconnected. The (d) the inputs x, y, z should be inverted
input which gets selected when S0 = 0, is tied to ‘1’ 8. [MCQ]
and the input which gets selected when S0 = 1, is tied The figure below, shows the interconnection of a
to ‘0’. The output V0 will be PLA and 2 × 1 MUX. The output function f(a, b, c)
S=0 MUX is
1 2×1
V0 a
0 S0
S=1
b
MUX
(a) 1 0
(b) 0 out f
c 1S
(c) Pulse train of frequency 1 MHz b 0

(d) Pulse train of frequency 0.5 MHz a

(a) ab + bc + ab
6. [MCQ] (b) (a + b)(a + c)(a + b)
A designer has multiplexer units of size 2 × 1 and
(c) ab + bc + ab
multiplexer of size 16 × 1 is to be realized. The
number of units of 2 × 1 MUXs required, will be (d) (a + b)(b + c)(a + b)
(a) 30 (b) 7
(c) 15 (d) 11 9. [MCQ]
The schematic shown below, implements the
7. [MCQ] function F (A, B, C, D). The correct expression for
F is
A demultiplexer of size 1 × 8 with active low
outputs, is programmed as shown below. The
circuits has three inputs x, y, z and generates two
outputs y1, y2.
 11. [MCQ]
C 0
The logic diagram of a 3 × 8 decoder with active low
0 1 out 0
outputs is shown below. What is the state of outputs
S0 out F Q7 …… Q0 for the set of inputs E3 = E1 = 1, E2 = 0,
1 S0 A2 = A1 = 1 and A0 = 0?
A
A2 A1 A0 E1
1 0 E2
D MSB LSB E3
C 1 out
3 × 8 Decoder
S0

B
(a) F = AC + BD + CD Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

(b) F = AC + BD + CD (a) 1111 1111 (b) 1011 1111

(c) F = AB + BC + BD (c) 1111 0111 (d) 0000 0000

(d) F = AC + BD + CD
12. [MCQ]
A 3 line to 8 line decoder with active low outputs, is
10. [MCQ]
used to realize Boolean function involving three
An 8 × 1 MUX is configured as shown below to variables x, y and z (x is MSB and z is LSB) as
implement a function f(a, b, c), a is MSB. shown below.
Alternatively, the same function can also be
The minimized Boolean function f(x, y, z) in POS
implemented using smaller size 2 × 1 MUX and 4 ×
format, will be
1 MUX. The correct alternative is
0
z A0 1
0
2
+VCC 1
2 3
out y A1 Decoder
3 F (a, b, c) 4
3×8
4 5
5 x A2 6
6 7
7 S2 S1 S0
a b c (a) (x + y + z)(x + y + z)(x + y + z)(x + y + z)
(b) (x + y + z)(x + y + z)(x + y + z)(x + y + z)
(c) (x + z)(y + z)(x + y + z)
1 0
c out f1 (d) (x + z)(y + z)(x + y + z)
(a) 1 (b)
S0
a 13. [MCQ]
0 1 0 A 3 line to 8 line decoder with three inputs A, B, C
out f3 0 1 and two outputs y1 and y2, is configured as shown
(c) a (d) 1 2 out f4
below. The minimized expressions of outputs will be
1 S0
a 3 S1 S0
c
b c
 (a) 0100 (b) 1110
(c) 0011 (d) 1010

16. [MCQ]
In a 4-bit carry look ahead adder, the X-OR gate has
delay of 10ns and AND/OR gate has delay of 5ns
each. The sum will appear after delay of
(a) y1 = AB + ABC; y 2 = A  B
(a) 35 ns (b) 30 ns
(b) y1 = AB + ABC ; y 2 = A  B (c) 25 ns (d) 20 ns
(c) y1 = AB + AC ; y 2 = AB + AC

(d) y1 = AB + AC ; y 2 = AB + BC 17. [MCQ]

A PLA has 3 inputs, 7 product terms, 2 sum terms
and 2 outputs. The size of PLA in terms of fusible
14. [MCQ] links will be
A designer has sufficient number of units of decoder (a) 68 (b) 53
with enable input of size 4 × 24 and a decoder of size
(c) 48 (d) 58
8 × 28 is to be realized. The number of units of 4 × 24
decoders, required will be
(a) 17 18. [MCQ]

(b) 12 Notwithstanding overflow, the addition/subtraction

of k bit signed binary numbers can be realized by
(c) 8
using k full adders and
(d) 16
(a) k 2-input AND (b) k 2-input OR
(c) k 2-input X-OR (d) k 2-input NOR
15. [MCQ]
19. [MCQ]
The digital circuit shown below, is a programmed
Eight 1-bit full adders are cascaded. Each 1-bit full
ROM where cross (×) mark denotes the connection
adder generates carry out bit in 10 ns and sum bit in
retained. The nibble content of PROM of size 22 × 4,
30 ns. The number of additions performed per
at memory location 11, will be
second, will be
(a) 109 (b) 0.5 × 107
(c) 107 (d) 0.125 × 107

20. [MCQ]
How many don’t care inputs are there in a BCD
adder?
(a) 312 (b) 128
(c) 256 (d) 200

21. [MCQ]
The circuit shown below, is a controlled half
adder/half subtractor. The inputs to half adder/half
subtractor are x and y while z is a control. The
outputs are y1 and y2.
 Then the circuit behaves as 7 the binary output is 2 less than binary input. What
completes the design?
(a) One FA and one HS
(b) One HA and one HS
(c) One HA only
(d) One FA only
(a) Half adder for z = 0
(b) Half subtractor for z = 1
25. [MCQ]
(c) Half adder for z = 1 and half subtractor for z
Identify the circuit shown below?
=0
(d) Half adder regardless of whether z = 0 or z =
1 due to design defect

22. [MCQ]
In order to get 9’s complement of a BCD data, which
one of the following should be added to its 1’s
(a) Bidirectional buffer
complement?
(b) De-multiplexer
(a) 1010 (b) 1000
(c) Multiplexer
(c) 1100 (d) 0110
(d) Encoder

23. [MCQ]
26. [MCQ]
Let X = x3x2x1x0 and Y = y3y2y1y0 be two, 4-bit
signed number inputted to the circuit shown below. To design a 2-bit comparator, the following are
The output z = 1 implies needed
y3 y2 y1 y0 (a) Two 1-bit comparators, 2 AND gates, 1 OR
gate
x3 x2 x1 x0 (b) Two 1-bit comparators, 3 AND gates, 2 OR
gate
FA FA FA FA
C4 C3 C2 C1 C0=1 (c) Three 1-bit comparators, 2 AND gates, 1 OR
S3 S2 S1 S0 gate
z (d) Three 1-bit comparators, 3 AND gates, 2 OR
gate
(a) X=Y
(b) X<Y
27. [MCQ]
(c) X=Y
The minimized Boolean expression for F = (A + D)
(d) X>Y
(B  C) + AD’ is
(a) (A + D) (B’C’ + BC) + AD’
24. [MCQ]
(b) ABC’ + AB’C + BC’D + B’CD
The design of a combinational logic circuit with
three inputs x, y, z and three outputs A, B, C is (c) BC’D + B’CD + AD’
attempted. The constraint is that designer has only (d) BC’D + B’CD
HA, HS, FA and FS units only in his inventory.
When the binary input is 0, 1, 2 or 3 the binary output
is same as input and when binary input is 4, 5, 6 or 28. [NAT]
 Let f(x1, x2, x3, x4) = x1x2 + x1x3 + x2x3 + x4. The The number of essential prime implicants in the
number of minterms for which f = 1 is ________. output expression Y is ________ .

29. [MCQ]
The digital input signals x, y, z (x as the MSB and z
as the LSB) are used to realize the Boolean function
F = M0. M4. M6. M7, where Mi denotes the ith max
term. The simplified expression for F is given by
33. [MCQ]
(a) 𝑦⊕𝑧 (b) ( y + z )( x + y ) The given expression can be reduced to _________
(c) 0 (d) y z + xy f = AB + AC + ABC ( AB + C )
30. [MCQ] (a) A
The ideal logic are employed to implement a logic
(b) AB + A + C
circuit for the Boolean function obtained by the
given k-map. Which of the following is/are the (c) A + C + ABC
simplified Boolean function(s) (d) 1

34. [MCQ]
Choose the correct statements for the given Boolean
function.
F ( A, B, C ) = ABC + ABC + ABC + ABC

(a) Given is a self dual function

(a) acd + (b) Given is not a neutral function because it has
(b) ac + abd + acd 2n–1 terms
(c) cd + ac + ad + abc (c) Given is a neutral function
(d) ac + acd + bcd (d) Given function is not consisting of any mutual
exclusive term (min term)

31. [MCQ]
35. [NAT]
A Boolean expression F(A, B, C, D) = m (4, 7, 15).
If F = f1 . f2 , where f1 = πM(5, 6, 12, 13, 14), then The number of switching functions obtained by the
which of the below statements is/are correct? given k-map in canonical SOP form of 4-variable
function, adjusted in 3-variable k-map is
(a) The number of full specified function, f2 that
_______________. (Where a, b, c, d are the
satisfy the given condition is 16.
variables.)
(b) f2 = B satisfies the given condition.
(c) f2 = BC + BCD satisfies the given condition.
(d) f2 = ABD satisfies the given condition.

32. [NAT]
36. [MCQ] 40. [MCQ]

Find EPI, RPI of the given function are A  B + A  C + A Can be expand to

F(A,B,C,D) = m (0, 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12)
(a) m (0, 1, 2) (b) M (1, 6, 7)
(a) 1, 2 (b) 2, 1
(c) m (1, 6, 7) (d) m (0, 2, 3, 4, 5)
(c) 2, 2 (d) 1, 1

37. [MCQ] 41. [NAT]

Consider the given k-map of and select the correct Two function f1 & f2 are given as follows
options f1(A, B, C, D) = m (0, 1, 5, 6, 7, 8, 15)

f2(A, B, C, D) = M (0, 1, 3, 5, 9, 10, 11, 12)

Then the no. of essential prime implicates of the
function f3 = f1 . f2 is equal to _______________

42. [MCQ]
The minimized Boolean function(s) for the given 3-
(a) EPI’s = 3, RPI’s = 1
Variable function
(b) SPI = 3
F(A, B, C) = m (0, 1, 2, 5, 7) + d(3, 6)
(c) EPI’s = 3
(d) RPI = 1, SPI’s = 0 (a) 𝑓 = A + C in Positive logic

38. [NAT] (b) 𝑓 = C. A in Negative logic

For the function F(A,B,C,D) = M (10,14), the (c) 𝑓 = A.C in Negative logic
literal cost is___________
(d) Function having zero EFPI’s
43. [MCQ]
39. [NAT]
Which of the following gives the simplified product
The number of EPI’s in the given K-map is of sums from the Boolean function F = m1 + m2 + m5
__________. + m6 + m9 + m10 + m14 are the minterms. Considering
the outputs P, Q, R & S where P is the MSB, S is the
LSB

(a) RS (b) RS
 (c) RS (d) (R + S )R + S

44. [MCQ]

The building block of a practical digital circuit is

shown in figure
(a) Two 2 Input X-OR gates
Which of the following is the Boolean expression at
(b) One 2 input X-OR and one 2 input X-NOR
x3 produced by the logic gate(s) in black-box to
gate
avoid the static hazard, if the output Boolean
expression Y0 is m (0,1,5,7) (c) 4 NAND gates
(d) One 2 input X-OR gate and Two 2 input
NAND gates

46. [MCQ]

Find the number of EPI’s and RPI’s in the given K-

(a) x3 = bc (b) 𝑥3 = 𝑏 + 𝑐 map respectively

(c) 𝑥3 = 𝑏𝑐 (d) 𝑥3 = 𝑎𝑏

45. [MCQ]

The function which is obtained by the given K-map

can be implemented by:

(a) 1, 3 (b) 3, 1
(c) 1, 1 (d) 3, 3


 Answer Key
1. (d) 24. (c)
2. (c) 25. (c)
3. (d) 26. (b)
4. (c) 27. (c)
5. (d) 28. (12)
6. (c) 29. (b)
7. (b) 30. (b, d)
8. (b) 31. (b, c)
9. (d) 32. (1)
10. (b) 33. (d)
11. (a) 34. (a, c, d)
12. (c) 35. (5)
13. (a) 36. (b)
14. (a) 37. (a)
15. (d) 38. (3)
16. (b) 39. (2)
17. (d) 40. (c)
18. (c) 41. (3)
19. (c) 42. (b)
20. (a) 43. (d)
21. (c) 44. (a)
22. (a) 45. (a)
23. (c) 46. (b)

