SATTAR.

CHANDRA SEKHAR

Phone: +919052560121 & 8247264341 E-mail: [email protected]

Summary

12+ years’ experience as Design & validation Engineer as well as SR Product Application Engineer specializing in
semiconductor (FPGA) industry. Having good technical understanding and as well as working expertise across
multiple platforms such as Smart NICs, computational storage, cache coherent interconnects and PCIe IP.

Education:

Master of Technology, VLSI 2009-2011

Jawaharlal Nehru Technological University, Hyderabad

Professional Experience Details:

 Currently working as Senior architect FPGA in Wipro from April 2022 to till date.

 Worked as Principal engineer in validation and emulation at microchip from Nov-2020 to April 2022

 Worked as Sr Design & Product Application Engineer in Xilinx as from May 2017 to Aug-2020

 Worked as Engineer (Contract Employee) in Xilinx from April 2015 to March 2017

 Worked at INTELLET TECH CORP PVT LTD as Design Engineer (R&D) from Nov 2012 to March 2015.

 Worked as FPGA Engineer in Microware from Oct 2011 to Nov 2012.

Technical Skills:

HDL - Verilog, system Verilog .

Scripting Languages - Perl.
Standard Interfaces - Transceivers, Aurora, PCIe, AXI.
Aviation Communication Protocols - MIL STD 1553, ARNIC 429
Tools - Questa sim, Xilinx Ise, Model Sim, MATLAB, vivado .
Hardware Platforms - Xilinx FPGA

Professional Experience Details:

Senior architect FPGA: Wipro

Worked on client project for system validation using the internal FPGA boards.

Principal validation & Emulation Engineer:

Microchip (India) Hyderabad, India Nov 2020 – April 2022.

 Worked on validation of Microchip internal chip on Xilinx FPGA platform.

 Worked validation post silicon chip of PCIe gen 4 and gen5.

 Worked on SOC silicon validation.

Responsibilities:

 Defining and develop of Prototyping methodology of the targeted FPGA Platform.

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  Project Management: Estimating a Project Duration along with the Project management phases and
scheduling with Design specification & Resource scoping and taking care of Team Based Design flow.

 Developing comprehensive test plan to cover all the functional features defined in the target specification and
execute

 Engaging in system-level debug/triage efforts involving in the PCIe IPas well as transceivers.

 Leading collaborative technical discussions to drive resolution on technical issues and roll out technical
initiatives.

 Supporting issues on customer platforms as requested by customer support teams.

Sr Product Application Engineer – Silicon & IP Team.

Xilinx Inc. (India) Hyderabad, India May 2017 – Aug2020.

Worked as an Sr Design & Product Application Engineer in Xilinx as from May 2017 to Aug 2020.

 Worked on Xilinx FPGA IP core of Xilinx PCIe , Xilinx Transceivers, & Aurora interface protocols
for end user Application along with the work of FPGA based PCIe validation, Design testing as well as board
bring up for Characterization work.
 Worked on issue related to high-speed optical transceiver products and prototypes like testing, debugging
and Implementing the solutions to the problems ,also generation of DVT reports with respect to customer
Issue on Xilinx FPGA Evaluation board.
 Worked with the development team to fix bug fixes of Aurora protocol ,Xilinx FPGA PCIe, GT Transceiver’s
and Advanced Applications Engineer for 3 years with expertise in FPGA Architecture, Transceivers, Boards,
Quality & Reliability, Video IP, PCIe, Transceivers , also Responsible for technical interface between customer
team and development team.
 Debugging using Chip Scope, ILA ,VIO and lab bench oscilloscopes/protocol analyzers for bug fixes as well
as ability to build FPGA based reference designs including test benches for functional simulation and HW.

 Working with cross-functional, global team of hardware designers(PCB), software engineer’s(Firmware and
App), verification and validation engineers.

Design Engineer – Viper Team

Xilinx Inc (India) Hyderabad, India April 2015 – March 2017 .

 Analyse the failed test case for every Regression and raise the bug case using the JIRA.
 Writing of RTL for bug fix for DSP cores in Verilog.
 Writing test cases and test-bench for DSP IP core regression failure cases using Verilog
 Development of regression frame work using the Perl & python scripting .

FPGA design Engineer - R&D Team.

INTELLET TECH CORP PVT LTD Hyderabad, India Nov 2012 – March 2015 .

Worked at INTELLET TECH CORP PVT LTD as FPGA Design Engineer (R&D) from Nov 2012 to March 2015

 Carried out project based on FPGA for DRDO in the field of Baseband, MIL 1553B.

 Created a detailed test-plan to verify the MIL STD 1553 USB Card and verified the RTL as per the test plan
 Having Hands on Experience as well as Deep Knowledge on MIL STD 1553 Design & Verification.

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  Project based on the Video and Image processing application Development.

Microware Hyderabad, India Oct 2011 – Nov 2012 .

Worked as FPGA Engineer in Microware from Oct 2011 to Nov 2012.

 Worked on Bluetooth project for RCI.

 Developed PRBS test JIG for validation purpose of hardware.

Key strength :

 Resourceful with strong problem-solving skills & Debugging.

 In-depth product knowledge to provide technical expertise to customer teams through presentations and
product demonstrations.
 Creation of detailed design and implementation specifications for complex products/applications/systems.
 Strong in debugging.

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