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Synthesis

Vlsi

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11 views

Synthesis

Vlsi

Uploaded by

avulagowtham002
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Synthesis Methodology and Netlist Qualification

Abstract
This article provides an in-depth explanation of synthesis flow and post-synthesis netlist quality
checks. In the ASIC design flow, synthesis is a crucial front-end process. The synthesized netlist
becomes the input for the back-end design phase. Ensuring the netlist meets all quality checks
minimizes iterations, reducing turnaround time and effort. This article addresses essential questions
such as:
• What is synthesis?
• Why is synthesis necessary?
• What are the inputs and outputs of synthesis?
• What is the synthesis flow?
• What checks ensure netlist quality?

Introduction
Synthesis involves transforming RTL (Register Transfer Level) code into a gate-level netlist. This
process incorporates logic optimization, area and power optimization, and scan insertion. Tools like
Synopsys Design Compiler/Fusion Compiler and Cadence Genus are commonly used for synthesis.
This stage bridges the gap between the high-level design and its physical implementation.

Overview of Synthesis
Synthesis is a critical stage where RTL code is converted into a gate-level netlist. It allows designers
to visualize how the design will appear after manufacturing. By analyzing timing, area, and power
metrics, designers can make adjustments early, saving resources.
The synthesis process consists of three main stages:
1. Translation
2. Optimization
3. Mapping

Inputs and Outputs of Synthesis


Inputs:
1. Timing Library (.lib/.db): Contains timing, power, and area information of standard cells.
2. Physical Library (LEF, Milkyway): Includes details about metal, vias, standard cells, and
macros.
3. RTL: High-level descriptive code written in Verilog or VHDL.
4. SDC (Synopsys Design Constraints): Design constraints for timing.
5. DEF (Design Exchange Format): Placement information for Physical Aware Synthesis.
6. UPF (Unified Power Format): Specifies power intent for the design.
Outputs:
1. Netlist: Optimized gate-level representation of the design.
2. Updated UPF: Reflects the design's new power intent.
3. Updated DEF: Includes macro and standard cell placements.
4. Updated SDC: Refined timing constraints.
5. Reports: Summaries of QoR (Quality of Results) metrics.

Types of Synthesis
1. Logical Synthesis: Traditional synthesis that processes HDL code to generate a netlist based
on user constraints.
2. Physical Aware Synthesis: Incorporates physical information such as macro placements and
RC coefficients for accurate wire delay calculations.
o Advantages: Improved PPA (Power, Performance, Area), better timing correlation
with physical design, and reduced iterations.

Synthesis Flow
The synthesis flow involves several steps:
1. Elaboration:

• Converts RTL into logical hierarchy using technology-independent cells (Gtech).


• Checks for uniqueness, unresolved references, and timing loops.
2. Compilation and Optimization:

• Maps Gtech cells to technology-specific cells.


• Removes redundant registers and optimizes design constraints.
3. DFT (Design for Testability):

• Inserts scan chains and ensures testability coverage.


4. Outputs Generation:

• Produces a qualified netlist, updated UPF, DEF, and SDC files.

Netlist Quality Checks


Post-synthesis, the netlist undergoes rigorous checks to ensure quality:
1. No Clocks:

• Ensures all registers are clocked.


• Command: check_timing -include {no_clock}
2. Unconstrained Endpoints:

• Verifies IO constraints and timing paths.


• Command: check_timing -include {unconstrained_endpoints}
3. Timing Checks:

• Validates paths based on constraints like clock period and setup time.
• Command: report_timing
4. LEC (Logic Equivalence Check):

• Confirms equivalence between RTL and synthesized netlist.


• Tools: Synopsys Formality, Cadence Conformal.
5. Timing Loops:

• Identifies unintended logical loops in the design.


• Command: check_timing -include {loops}
6. Empty Modules:

• Detects and handles modules without logical content.


• Command: check_design
7. Removed Flops:

• Reports registers removed during optimization.


• Commands: report_unloaded_registers, report_constant_registers
8. Floating and Multidriven Pins:

• Identifies disconnected or conflicting pin connections.


9. Latches:

• Flags inferred latches, which are generally undesirable.

Conclusion
Synthesis and netlist quality checks are vital for efficient ASIC design. They ensure that the transition
from RTL to gate-level representation meets design constraints and maintains functionality. By
addressing these checks early, designers can avoid costly iterations in the physical design stages.
Keywords: Synthesis, Netlist, ASIC Design, QoR, RTL, Logical Equivalence Check, Timing.

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