CHAPTER 1

INTRODUCTION

The domain of digital electronics has witnessed substantial growth over the past decade, marked by
rapid technological advancements. The successful implementation of digital technology necessitates
the development of high-speed and power-efficient multipliers, a critical component in the design of
digital systems. Multipliers are circuits designed to generate the product of given inputs, capable of
handling various bit lengths in arithmetic and logic circuits. Leveraging advanced adders in multipliers
helps reduce the overall delay time, contributing to enhanced performance.

In the realm of multiplier design, the utilization of Vedic multipliers stands out as an effective
strategy. Vedic multipliers, by incorporating advanced techniques and algorithms, exhibit a reduced
number of steps in their operation compared to traditional array multipliers. This not only leads to a
faster processing speed but also contributes to lower memory usage and power consumption, making
the system more energy-efficient.

In evaluating the performance of digital processing systems, three essential parameters come into play:
power consumption, area utilization, and processing speed. Multipliers execute multiplication
operations by generating partial products, reducing them, and then summing them up to obtain the
final output. The choice of adder significantly influences the delay and power consumption of the
multiplier. Adders perform crucial operations, including the generation of carry and the calculation of
the sum. Different types of adders, such as ripple carry adder (RCA), carry-save adder (CSA), carry-
look-ahead adder (CLAA), carry-select adder (CSA), among others, cater to specific requirements
based on the time needed to execute these operations. This diverse range of adders allows for
flexibility in designing multipliers tailored to meet specific performance criteria.

1.1 Vedic Mathematics – An Overview

Vedic Mathematics is the name given to a set of rules derived from Ancient Indian Scriptures,
elucidating different mathematical results and procedures in simple and understandable forms. The
word Vedic is derived from the word Veda which means the Store-house of all knowledge.

It is claimed to be a part of the Sthapatya Veda, a book on civil engineering and architecture, which is
an Upaveda (supplement) of the Atharva Veda. It covers explanations of several modern mathematical
1
terms including arithmetic, geometry (plane,co-ordinate), trigonometry, quadratic equations,
factorization and even calculus.

The beauty of Vedic mathematics lies in the fact that it reduces the otherwise cumbersome-looking
calculations in conventional mathematics to very simple ones. This is because the Vedic formulae are
claimed to be based on the natural principles on which the human mind works.

Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with various branches of
mathematics like arithmetic, algebra, geometry, etc. Of these, there are two Vedic Sutras meant for
quicker multiplication. They have been traditionally used for the multiplication of two numbers in the
decimal number system. They are -

1. Nikhilam Navatashcaramam Dashatah: All from 9 and last from 10

2. Urdhva Tiryakbhyam: Vertically and crosswise

1.2 Motivation
Multiplication involves two basic operations -the generation of partial products and their accumulation.
Clearly, a smaller number of partial products reduces the complexity, and, as a result, reduces the
partial products accumulation time.
When two n-bit numbers are multiplied, a 2n-bit product is produced. Previous research on
multiplication, i.e. shift and add techniques, focused on multiplying two n-bit numbers to produce n
partial products and then adding the n partial products to generate a 2n-bit product. In which case, the
process is sequential and requires n processor cycles for an n-n multiplication. Advances in VLSI have
rendered Parallel Multipliers – fully combinational multipliers, which minimize the number of clock
cycles/steps required, feasible.
Two most common multiplication algorithms followed in the digital hardware are the Array
multiplication algorithm and Booth multiplication algorithm. The computation time taken by the array
multiplier is comparatively less because the partial products are calculated independently in parallel.
The delay associated with the array multiplier is the time taken by the signals to propagate through the
gates that form the multiplication array.In the case of Booth multiplication algorithm, it multiplies two
signed binary numbers in two's complement notation. Andrew Donald Booth used desk calculators that
were faster at shifting than adding and created the algorithm to increase their speed. It is possible to
reduce the number of partial products by half, by using the technique of Radix-4 Booth recoding. But
both do have their own limitations. The search for a new design of a multiplier which will radically
2
improve the performance is always on.
The main motivation of this project is to make use of the simplicity of the Vedic sutras and adapt it for
binary arithmetic to get an efficient and optimum digital multiplier fulfilling the demands of the
growing technology. Fortunately or unfortunately, the potential of the Vedic Algorithms has remained
untapped and unplun-dered for long. It would be a source of pride to prove that the Indian-originated
methods can surpass the existing algorithms and to use them widely in various applications for the
benefit of the industry.

1.3 Objective
The aim of this project is to design and implement an optimized digital multiplier which will multiply
two real integers incorporating Vedic Multiplication principles.
The goals are:
 To reduce the computational time
 To optimize the area occupied
 To minimize the power consumed
 To develop novel algorithms for obtaining a highly optimum multiplier

1.4 Project Report Organization

Chapter 1, the Introduction describes the need for efficient multipliers followed by a brief overview of
Vedic Sutras. It illustrates the motivation behind taking up this project and states the objectives.
Chapter 2, Literature Review, deals with all the multiplication and addition schemes reported in
literature. It puts forward the concepts already proposed on related areas injournals and conferences.
Chapter 3, Theoretical Background - Algorithms presents the Vedic Multiplication Algorithms -
Urdhva Tiryakbhyam and Nikhilam, in detail, then proceeds with an explanation of the Karatsuba-
Ofman Algorithm and concludes by justifying the selection of the Carry Look Ahead (CLA) Adder.
Chapter 4 , Design & Implementation, expounds on the main work done in the project, beginning with
an explanation of the modular hierarchy followed in this project.
Chapter 5, the Conclusion completes the report by summarizing the work and considering the future
scope.

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 CHAPTER-2
LITERATURE SURVEY

1. D Surya Teja and P Jagadeesh introduce a detailed study entailed a comparison of the
performance of two groups, each consisting of ten data samples, resulting in a total of twenty
samples. The comparison was conducted using a Vedic multiplier. The initial group employed a
Vedic multiplier integrated with CSLA, but the subsequent group employed a Vedic multiplier
integrated with a unique CLA adder. The design was simulated using ModelSim to assess the
delay and power consumption, and the outcomes were compared with those of a conventional
Carry choose adder to ascertain the enhancements in latency and power usage. The VHDL
language and ModelSim software were utilized for the implementation. VHDL code has been
created for both the multiplier and two separate adders. Simulations have been performed with
different input sizes to evaluate the multiplier's performance in different situations
2. The VLSI architecture for a high-speed 32-bit multiplier, as proposed by G. Challa Ram, D.
Sudha Rani, R. Balasnikesava, and K. BalaSindhuri, incorporates the application of the Urdhva
Triyagbhyam and Nikhilam Navatasharamam Dashatah Vedic mathematical sutras. This
innovative design also employs a binary to excess 1 code converter adder, contributing to the
reduction of delays in the system. The implementation and synthesis of this architecture involve
the utilization of a binary to excess 1 code converter, further optimizing the performance of the
multiplier. Notably, the use of the Urdhva Triyagbhyam sutra demonstrates superior efficiency
when compared to a multiplier employing the Nikhilam Navatasharamam Dashatah sutra.
3. M. BalaMurugesh, S. Nagaraj, J. Jayasree, and G. Vijay Kumar Roddy introduce an enhanced
iteration of a binary Vedic multiplier in their work. This modified design incorporates the
application of the Urdhva Triyagbhyam sutra alongside a customized version of the ripple carry
adder. The notable advantage of this approach lies in its ability to reduce both the number of
components and delay time when compared to other multipliers that employ the conventional
ripple carry adder. The simulation of the designed multiplier is conducted using Modelsim for
Verilog HDL, and synthesis is carried out through Xilinx ISE, ensuring a comprehensive
evaluation and optimization of the proposed architecture.

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4. Siva S. Sinthura, Afreen Begum, B. Amala, A. Vimala, and V. Vidliya Aparna present a
comprehensive exploration of the development of four distinct 32-bit multipliers employing
carry save adders. Their study encompasses a detailed analysis of the speed, area, and power
characteristics of these multipliers, offering insights into their respective applications. The
considered multipliers include the Wallace Tree, Dadda, Vedic, and Booth multipliers. Utilizing
the Xilinx ISE tool for synthesis after Verilog-based development, the authors found that the
Wallace and the modified Booth multipliers exhibited superior performance in terms of both
speed and area when compared to the other two multipliers in consideration. This comparative
evaluation sheds light on the strengths and applications of each multiplier design.
5. The implementation of an 8 - bit Vedic multiplier enhanced in terms of propagation delay when
compared with conventional multipliers like Array multiplier, Braun multiplier, Modified Booth
multiplier and Wallace tree multiplier has been given by Pavan Kumar U.C.S, et al, 2013. Here,
they have utilized an 8 - bit barrel shifter which requires only one clock cycle for n number of
shifts. The design could achieve propagation delay of 6.781 ns using barrel shifter in base
selection module and multiplier.
6. S. Deepak, et al, 2012, have proposed a new multiplier design which reduces the number of
partial products by 25 %. This multiplier has reported to have been used with different adders
available in literature to implement multiplier accumulator (MAC) unit and parameters such as
propagation delay, power consumed and area occupied have been compared in each case. From
the results, Kogge Stone adder was been chosen as it was claimed to have provided optimum
values of delay and power dissipation. The results obtained have been compared with that of
other multipliers and it has been reported that the proposed multiplier has the lower propagation
delay when compared with Array and Booth multipliers.

5
 CHAPTER 3
WORK DONE

3.1 System Implementation/Block Diagram and Explanation

The proposed system illustrated in Figure 3.1 aims to minimize carry propagation time and optimize
hardware complexity for the 32-bit Vedic multiplier operation. This system is designed to implement a
vertical and cross-wise equation-based logical process for the 32-bit multiplication operation. Our
objective is to modify the architecture of the 32-bit multiplier using Vedic mathematics techniques,
specifically focusing on the implementation of vertical and cross-wise equations.

Figure 1: -Vedic Multiplier Hardware Block Diagram

The process begins with the design of a 4-bit multiplication operation, followed by the development of
an 8-bit multiplication process using the result of the 4-bit multiplication. Ultimately, we construct a
32-bit multiplier architecture by extending the process to 16 bits. This hierarchical structure is
strategically employed to reduce complexity and processing time. It allows for a 32-bit multiplicand

6
register size, placing the multiplier in the least significant half of the product register, while clearing
the most significant half.

The iterative nature of the next 32 stages involves adding the multiplicand to the most significant half
of the product register if the least significant bit of the product register is "1". This addition is followed
by adjusting the content of the product register by a slight right shift. The carry bit is then inserted into
the most significant bit of the product register.
This method not only streamlines the multiplication process but also enables the efficient use of
hardware resources, leading to a reduction in complexity and processing time. The systematic
application of Vedic mathematics techniques contributes to an optimized 32-bit multiplier architecture,
meeting the goals of enhanced efficiency and reduced computational overhead.

3.2 Vedic Multiplier Using Carry Look Ahead Adder

The implementation of a Vedic multiplier, in conjunction with a carry look-ahead adder (CLAA), is
poised to enhance the speed of addition operations while concurrently mitigating power dissipation.
The utilization of a carry look-ahead adder enables the prediction of carry bits for subsequent steps
based on input signals. Given that the carry generated at each bit position depends on the three inputs
to that position, the CLAA facilitates the anticipation of subsequent carries. The multiplier architecture
is rooted in the Vertical and Crosswise structure of Ancient Indian Vedic Mathematics, a pivotal
feature in the proposed methodology. This approach enables the creation of all partial products and
their sum in a single step, fostering modularity and reducing design complexity for higher-bit inputs.

The Vedic multiplier, developed using Electronic Design Automation (EDA) tools such as Xilinx ISE
and implemented in Verilog, is particularly well-suited for high-speed processors. In applications like
microprocessors, digital signal processing (DSP), and communication, where high-speed multipliers
are indispensable, the proposed Vedic Multiplication approach offers a compelling solution. As the
demand for high-speed CPUs continues to rise, so does the imperative for efficient and swift
multipliers.

Figure 2.2 elucidates the functionality of a 32-bit Vedic multiplier, where the bits are bifurcated into
two equal segments: the first 16 bits from [15:0] and the subsequent 16 bits from [31:16]. The Vedic
multiplier orchestrates vertical operations, multiplying the initial 16 bits of both the multiplier and
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multiplicand (a [15:0] and b [15:0]). The first 16 bits of the partial output, c [15:0], determine the
initial 16 bits of the final output. Simultaneously, crosswise operations transpire, with a [31:16] being
multiplied by b [15:0], and vice versa. The outcome from the partial multiplication feeds into the carry
look-ahead adder. The sum from the initial partial addition operation is then inputted into a second
carry look-ahead adder, alongside c [31:0]. The first 16 bits from this operation yield the S [31:16] bits
of the final output. The result from the second vertical multiplication of a [31:16] and b [31:16] is
directed to a third carry look-ahead adder, along with the carry from the second carry look-ahead adder
and d [31:16]. This process generates S [63:32] and determines the carry for subsequent calculations.

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 Figure 2-: Vedic multiplier block diagram

3.3 Carry Look Ahead Adder

Carry look-ahead adders represent an efficient means of accelerating binary number combination and
minimizing computation time. These adders function by generating two critical signals: propagate (P)
and generate (G), often denoted as the Carry Propagator and Carry Generator. Unlike the carry
generator, which produces an output carry independently of the input carry, the carry propagator
facilitates carry propagation to the subsequent level. Illustrated in the block schematic of a 4-bit carry
look-ahead adder in Figure 2, the procedure of carry look-ahead addition is employed to enhance the
adder section and optimize its design. Acknowledging the impact of transmission delays, the primary
objective is to curtail the transform function through the incorporation of the carry look-ahead adder
unit. The focal points of this transformation operation encompass the refinement of the carry selection
procedure and the overarching goal of diminishing the number of gates within the transform
architecture. The ultimate aim is to augment system speed while concurrently reducing power
consumption.

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 Figure 3:- Carry Look Ahead block diagram

CHAPTER 4
RESULTS

4.1 RTL Schematic

Fig 4 shows the schematic diagram of 32 bit Vedic multiplier using carry look ahead adder using Xilinx Vivado .

Fig 4:- RTL Schematic

4.2 Simulation Result: -

Fig 5 shows the simulation result of 32 bit vedic multiplier where two 32 bit numbers are multiplied and resulted
output is store as 64 bit output.

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 Fig 5:- Simulation Result

CHAPTER 5
Conclusion & Future Scope
5.1 Conclusion
From the preceding discussion, it is deduced that when designing any multiplier, critical parameters
such as the number of steps, delay time, memory utilization, area, and response time necessitate
careful consideration. The implementation of Vedic Multiplication (VM) using Carry Look-Ahead
Adder (CLAA) introduces a noteworthy approach, particularly in the context of variable bit lengths. In
terms of delay time, Vedic Multiplier exhibits superior performance compared to alternative
multiplication methods. However, a notable caveat emerges as it demands a greater number of Look-
Up Tables (LUTs) for higher bit sizes. While this condition allows the implementation of more
intricate logic essential for specific applications, it also poses challenges. The augmented LUT
requirement can result in higher resource utilization within the design, potentially imposing constraints
on available logic blocks. Furthermore, there is a propensity for increased power consumption, which
becomes a pertinent concern in applications governed by stringent power budgets. The need to strike a
balance between enhanced performance and resource-efficient design is thus paramount in the
deployment of Vedic Multipliers.

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5.2 Future Scope
In the future, advancements in the system are anticipated through the integration of optimized adders. This
strategic enhancement is expected to result in a reduction in both memory usage and power consumption,
contributing to an overall enhancement in the multiplier's performance. The incorporation of optimized adders
holds the potential to significantly improve efficiency and resource utilization, addressing concerns related to
memory requirements and power efficiency. This forward-looking approach aligns with the ongoing pursuit of
advancements in computational efficiency, laying the groundwork for a more efficient and high-performing
multiplier in the future.

REFERENCES

1. M.Bala Murugesh S.Nagaraj, J.Jayasree. G.Vijay Kumar Reddy "Modified High Speed 32-bit Vedic
Multiplier Design and Implementation", Proceedings of the International Conference on Electronics and
Sustainable Communication Systems (ICESC), 2020.

2. V. Vijayalakshmi, R. Seshadri. S. Ramakrishnan "Design and implementation of 32 bit unsigned multiplier

using CLAA and CSLA", International Conference on Emerging Trends in VLSI. Embedded System. Nano
Electronics and Telecommu- nication System (ICEVENT). 2013.

3. Soniya, Suresh Kumar "A Review of Different Type of Multipliers and Multiplier- Accumulator Unit"
International Journal of Emerging Trends Technology in Com- puter Science (IJETTCS), 2013.

4. R. Vasim Akram, Mohammad Rahmatullah khan. B.Raj Kumar. "Design of High Speed Low Power 32-bit
Multiplier using Reversible Logic". International Journal of VLSI System Design and Communication System,
vol. 02. 2014.

5. V. Murlidharan, N Satish Kumar." Design and implementation of low power and high speed multiplier using
quaternary carry look-ahead adder", International jour- nal of advance research in Electrical Electronics and

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Instrumentation Engineering. June 2020.

6. N. Fahmina Afreen, M. Mahaboob Basha, S. Mohan Das "Design And Implemen- tation Of Area- Delay-
Power Efficient CSLA Based 32-Bit Array Multiplier", 2nd IEEE International Conference On Recent Trends
in Electronics Information Com- munication Technology (RTEICT). May 19-20, 2017.

7. Siva.S.Sinthura. Afreen Begum. B.Amala. A.Vimala. V.Vidhya Aparna "Imple menation and Analysis of
different 32-bit multipliers on aspects of Power. Speed and Area", 2nd International Conference on Trends in
Electronics and Informatics (ICOEI) 2018.

APPENDIX
Simulation Code
`timescale 1ns / 1ps

module ha(a, b, sum, carry);

// a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry=a&b;
assign sum=a^b;
endmodule

module vedic2(m,n,w);
input [1:0]m;
input [1:0]n;
output [3:0]w;
wire [3:0]w;
wire [3:0]cout;
//stage 1
// four multiplication operation of bits accourding to vedic logic done using and gates
assign w[0]=m[0]&m[0];
assign cout[0]=m[1]&n[0];
assign cout[1]=m[0]&n[1];
assign cout[2]=m[1]&n[1];
//stage two
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// using two half adders
ha z1(cout[0],cout[1],w[1],cout[3]);
ha z2(cout[2],cout[3],w[2],w[3]);
endmodule

////////////////////////////////////////////////////////////////////////////////////////////////////////////

module CLA_Adder
#(parameter WIDTH=4)
(
input [WIDTH-1:0] i_add1,
input [WIDTH-1:0] i_add2,
output [WIDTH:0] o_result
);

wire [WIDTH:0] w_C;

wire [WIDTH-1:0] w_G, w_P, w_SUM;

// Create the Full Adders

genvar ii;
generate
for (ii=0; ii<WIDTH; ii=ii+1)
begin
full_adder full_adder_inst
(
.i_bit1(i_add1[ii]),
.i_bit2(i_add2[ii]),
.i_carry(w_C[ii]),
.o_sum(w_SUM[ii]),
.o_carry()
);
end
endgenerate

// Create the Generate (G) Terms: Gi=Ai*Bi

// Create the Propagate Terms: Pi=Ai+Bi
// Create the Carry Terms:
genvar jj;
generate
for (jj=0; jj<WIDTH; jj=jj+1)
begin
assign w_G[jj] = i_add1[jj] & i_add2[jj];
assign w_P[jj] = i_add1[jj] | i_add2[jj];
assign w_C[jj+1] = w_G[jj] | (w_P[jj] & w_C[jj]);
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end
endgenerate

assign w_C[0] = 1'b0; // no carry input on first adder

assign o_result = {w_C[WIDTH], w_SUM}; // Verilog Concatenation

endmodule // carry_lookahead_adder

module half_adder(x,y,s,c);
input x,y;
output s,c;
assign s=x^y;
assign c=x&y;
endmodule // half adder

module full_adder(x,y,c_in,s,c_out);
input x,y,c_in;
output s,c_out;
assign s = (x^y) ^ c_in;
assign c_out = (y&c_in)| (x&y) | (x&c_in);
endmodule // full_adder

//////////////////////////////////////////////////////////////////////////////////////////////////////////////

module vedic4(m,n,w);
input [3:0]m;
input [3:0]n;
output [7:0]w;

wire [3:0]s0;
wire [3:0]s1;
wire [3:0]s2;
wire [3:0]s3;
wire [7:0]w;
wire [3:0]cout1;
wire [5:0]cout2;
wire [5:0]cout3;
wire [5:0]cout4;
wire [3:0]s4;
wire [5:0]s5;
wire [5:0]s6;
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// using 4 2x2 multipliers
vedic2 e1(m[1:0],n[1:0],s0[3:0]);
vedic2 e2(m[3:2],n[1:0],s1[3:0]);
vedic2 e3(m[1:0],n[3:2],s2[3:0]);
vedic2 e4(m[3:2],n[3:2],s3[3:0]);
// stage 1 adders
assign cout1 ={2'b0,s0[3:2]};
CLA_Adder #(4)e5(s1[3:0],cout1,s4);
assign cout2 ={2'b0,s2[3:0]};
assign cout3 ={s3[3:0],2'b0};
CLA_Adder #(6) e6(cout2,cout3,s5);
assign cout4={2'b0,s4[3:0]};
// stage 2 adder
CLA_Adder #(6) e7(cout4,s5,s6);
// fnal output assignment
assign w[1:0]=s0[1:0];
assign w[7:2]=s6[5:0];
endmodule

module vedic8(m,n,w);

input [7:0]m;
input [7:0]n;
output [15:0]w;

wire [15:0]s0;
wire [15:0]s1;
wire [15:0]s2;
wire [15:0]s3;
wire [15:0]w;
wire [7:0]cout1;
wire [11:0]cout2;
wire [11:0]cout3;
wire [11:0]cout4;
wire [7:0]s4;
wire [11:0]s5;
wire [11:0]s6;
// using 4 4x4 multipliers
vedic4 e1(m[3:0],n[3:0],s0[15:0]);
vedic4 e2(m[7:4],n[3:0],s1[15:0]);
vedic4 e3(m[3:0],n[7:4],s2[15:0]);
vedic4 e4(m[7:4],n[7:4],s3[15:0]);

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// stage 1 adders
assign cout1 ={4'b0,s0[7:4]};
CLA_Adder #(8) z5(s1[7:0],temp1,s4);
assign cout2 ={4'b0,s2[7:0]};
assign cout3 ={s3[7:0],4'b0};
CLA_Adder #(12)(cout2,cout3,s5);
assign cout4={4'b0,s4[7:0]};
// stage 2 adder
CLA_Adder #(12) e7(cout,s5,s6);
// fnal output assignment
assign w[3:0]=s0[3:0];
assign w[15:4]=s6[11:0];

endmodule

module vedic16(m,n,w);
input [15:0]m;
input [15:0]n;
output [31:0]w;

wire [15:0]s0;
wire [15:0]s1;
wire [15:0]s2;
wire [15:0]s3;
wire [31:0]w;
wire [15:0]cout1;
wire [23:0]cout2;
wire [23:0]cout3;
wire [23:0]cout4;
wire [15:0]s4;
wire [23:0]s5;
wire [23:0]s6;
// using 4 8x8 multipliers
vedic8 e1(m[7:0],n[7:0],s0[15:0]);
vedic8 e2(m[15:8],n[7:0],s1[15:0]);
vedic8 e3(m[7:0],n[15:8],s2[15:0]);
vedic8 e4(m[15:8],n[15:8],s3[15:0]);

// stage 1 adders
assign cout1 ={8'b0,s0[15:8]};
CLA_Adder #(16) z5(s1[15:0],cout1,s4);
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assign cout2 ={8'b0,s2[15:0]};
assign cout3 ={s3[15:0],8'b0};
CLA_Adder #(24) e6(cout2,cout3,s5);
assign cout4={8'b0,s4[15:0]};

//stage 2 adder
CLA_Adder #(24) z7(cout4,s5,s6);
// fnal output assignment
assign w[7:0]=s0[7:0];
assign w[31:8]=s6[23:0];

endmodule

module vedic_32x32(m,n,w);
input [31:0]m;
input [31:0]n;
output [63:0]w;

wire [31:0]s0;
wire [31:0]s1;
wire [31:0]s2;
wire [31:0]s3;
wire [63:0]w;
wire [31:0]cout1;
wire [47:0]cout2;
wire [47:0]cout3;
wire [47:0]cout4;
wire [31:0]s4;
wire [47:0]s5;
wire [47:0]s6;
// using 4 16x16 multipliers
vedic16 e1(m[15:0],n[15:0],s0[31:0]);
vedic16 e2(m[31:16],n[15:0],s1[31:0]);
vedic16 e3(m[15:0],n[31:16],s2[31:0]);
vedic16 e4(m[31:16],n[31:16],s3[31:0]);

// stage 1 adders
assign cout1 ={16'b0,s0[31:16]};
CLA_Adder #(32) e5(s1[31:0],cout1,s4);
assign cout2 ={16'b0,s2[31:0]};
assign cout3 ={s3[31:0],16'b0};
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 CLA_Adder #(48) e6(cout2,cout3,s5);
assign cout4={16'b0,s4[31:0]};

//stage 2 adder
CLA_Adder #(48) e7(cout4,s5,s6);
// fnal output assignment
assign w[15:0]=s5[15:0];
assign w[63:16]=s6[47:0];

endmodule

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