Ch.

5 Digital building blocks

 Arithmetic circuits
 Number systems
 Sequential building blocks
 Memory arrays
 Logic arrays

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Arithmetic circuits

 Addition
 Half adder
 Having two inputs, A and B, and two outputs, S and Cout
 S: the sum of A and B
 Cout : carry out Half Full
Adder Adder
 In a multi-bit adder, added
or carried into the next most A B A B

significant bit Cout Cout Cin

+ +
 Built from an XOR gate and an S S
AND gate
A B Cout S Cin A B Cout S
0 0 0 0 0 0 0 0 0
 Full adder 0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S =AB 1 0 1 1 0
Cout = AB 1 1 0 1 0
1 1 1 1 1

S = A  B Cin
Cout = AB + ACin + BCin

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 Carry propagate adder (CPA)
 Operation
 Summing two N-bit inputs, A and B, and a carry in , Cin, to produce an N-bit
result, S and a carry out, Cout.
 The carry out of one bit propagates into the next bit
 Types
 Ripple-carry adder: slow
 Carry-lookahead adder: fast
 Prefix adder: faster

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 Ripple-carry adder
 The simplest way to build an N-bit carry propagate adder
 To chain together N full adders
 The Cout of one stage acts as the Cin of the next stage

A31 B31 A30 B30 A1 B1 A0 B0

Cout Cin
+ C30 + C29 C1 + C0 +
S31 S30 S1 S0

 Disadvantage
 Being slow when N is large
 The carry signals must propagate through every bit in the adder
 The delay of the adder, tripple
 Grows directly with the number of bits
 tripple = N tFA
 tFA: the delay of a full adder

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 Carry-lookahead adder
 Compute carry out (Cout) for k-bit blocks using generate and propagate
signals
 Dividing the adder into blocks and providing circuitry to quickly determine the
carry out of a block as soon as the carry in is known
 Operations
 Use generate (G) and propagate (P) signals that describe how a column or block
determines the carry out
 The i th column of an adder
 Generate a carry if it produces a carry out independent of the carry in
 The generate signal for column i, Gi = AiBi
 Said to propagate a carry if it produces a carry out whenever there is a
carry in
 The i th column will propagate a carry in, Ci-1, if either Ai or Bi is 1
 Pi = Ai + Bi
 The ith column of an adder
 Generate a carryout, Ci, if it either generates a carry, Gi, or propagates a
carry in, PiCi-1
 Ci = AiBi +(Ai+Bi) Ci-1 = Gi + PiCi-1

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 Extension to multiple-bit blocks
 A block generates a carry
 if the most significant column generates a carry,
 or if the most significant column propagates a carry and the previous
column generated a carry
 A block propagates a carry
 if all the columns in the block propagate the carry
 Define
 Gi:j : generate signal for blocks spanning column i through j
 Pi:j : propagate signal for blocks spanning column i through j
 For example, for a 4-bit block
 The generate logic for a block spanning columns 3 through 0
 G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )
 The propagate logic for a block spanning column 3 through 0
 P3:0 = P3P2 P1P0
 The carry out of the 4-bit block (Ci)
 Ci = Gi:j + Pi:j Ci-1

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 Ex) 32-bit carry-lookahead adder
B31:28 A31:28 B27:24 A27:24 B7:4 A7:4 B3:0 A3:0

4-bit CLA C27 4-bit CLA C23 C7 4-bit CLA C3 4-bit CLA
Cout Cin
Block Block Block Block

S31:28 S27:24 S7:4 S3:0

B3 A3 B2 A2 B1 A1 B0 A0
C2 C1 C0
Cin
+ + + +
S3 S2 S1 S0

G3:0 G3
P3
G2
P2
G1
P1
G0

P3
Cout P3:0 P2
P1
Cin
P0

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 Delay of an N-bit carry-lookahead adder with k-bit blocks:
 tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
 Where
 tpg: the delay of the individual generate/propagate gates to generate P and
G
 tpg_block : the delay to find the generate/propagate signals Pi:j and Gi:j for a k-
bit block
 tAND_OR: the delay from Cin to Cout of the final AND/OR gate in the k-bit CLA
block
 An N-bit carry-lookahead adder
 generally much faster than a ripple-carry adder, for N > 16
 The adder delay still increases linearly with N

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 Prefix adder
 Computes the carry in (Ci-1) for each column, i, as fast as possible and then
computes the sum,
 Si = (Ai  Bi)  Ci-1
 First, compute G and P for pairs of columns, then for blocks of 4, then for blocks
of 8, then 16, and so forth until the generate signal for every column is known
 Has log2N stages
 Define column i=-1 to hold Cin
 G-1 = Cin Ci-1 = Gi-1:-1
 P-1 = 0 because there is a carry out of column i-1 if the block spanning
columns i-1 through -1 generates a carry
∴ Si = (Ai  Bi)  Gi-1:-1
 Challenge
 Quickly compute G-1:-1, G0:-1, G1:-1, G2:-1, … , GN-2:-1 (These are called prefixes,
along with P-1:-1, P0:-1, P1:-1, P2:-1, … , PN-2:-1 )

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 Ex) 16-bit prefix adder 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1

14:13 12:11 10:9 8:7 6:5 4:3 2:1 0:-1

14:11 13:11 10:7 9:7 6:3 5:3 2:-1 1:-1

14:7 13:7 12:7 11:7 6:-1 5:-1 4:-1 3:-1

14:-1 13:-1 12:-1 11:-1 10:-1 9:-1 8:-1 7:-1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Legend i i
i:j

Ai Bi Pi:k Pk-1:jGi:k Gk-1:j Gi-1:-1 Ai Bi

Pi:i Gi:i

Pi:j Gi:j
Si
 Begins with a precomputation to form Pi and Gi for each column from Ai
and Bi using AND and OR gates
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  Uses log2N = 4 levels of black cells to form the prefixes of Gi:j and Pi:j
 A black cell
 Takes inputs from the upper part of a block spanning bits i:k
and from the lower part spanning bits k-1:j
 The generate and propagate signals for the entire block spanning bits i:j
 Gi:j = Gi:k + Pi:k Gk-1:j
 Pi:j = Pi:kPk-1:j
 In other words
 A block spanning bits i:j will generate a carry if the upper part (i:k)
generates a carry or if the upper part propagates a carry generated in the
lower part (k-1:j)
 A block will propagate a carry if both the upper and lower parts propagate
the carry.
 The delay of an N-bit prefix adder
 tPA = tpg + log2N(tpg_prefix ) + tXOR
 Where
 tpg is the delay of the column generate and propagate gates (AND or
OR gate)
 tpg_prefix is the delay of the black prefix cell (AND-OR gate)
 The delay grows logarithmically with the number of columns in the adder
 This speedup is significant for adder with 32 or more bits
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 Subtraction
 Using two’s complement number representation
 To compute Y = A – B
 Create the two’s complement of B
 Invert the bits of B to obtain B and add 1 to get –B = B +1
 Add this quantity to A to get Y = A + B + 1 = A – B

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 Comparators
 Functions
 Determine whether two binary numbers are equal or if one is
greater or less than the other
 Types
 Equality comparator
 Produces a single output indicating whether A is equal to B (A==B)

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 Magnitude comparator
 Produces one or more outputs indicating the relative values of A and
B
 Done by computing A-B and looking at the sign of the result
 The result is negative(i.e., the sign bit is 1) → A is less than B
 Otherwise, A is greater than or equal to B
 N-bit magnitude comparator
A B
N N

-
N
[N-1]

A<B

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 ALU (Arithmetic/Logical Unit)
 Combines a variety of mathematical and logical operations into
a single unit
 Receives a control signal, F, that specifies which function to
perform
 Symbol ALU operations
A B F2:0 Function
N N
000 A AND B

3 F 001 A OR B
ALU
N 010 A+B
Y 011 not used
 Control signals 100 A AND ~B
 Shown in blue
101 A OR ~B
110 A– B
111 SLT

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 Implementation
 Operates on A and BB
 BB: either B or B A B
N N
 Depending on F2
 F1:0 = 00
 A AND BB
 F1:0 = 01 N

0
 A OR BB F2
 F1:0 = 10 N
 Addition or subtraction
 F2= 0: A+B
 F2=1: A+ B+1= A-B
 F2:0 = 111 Cout +
 SLT(set if less than)
[N-1] S

 SLT

Extend
Zero
 Function
N N N N
 A<B→Y=1

0
3

2
 Otherwise, Y = 0 F1:0 2
N
Y
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  Performed by computing S = A – B
 S is negative → A < B
 Zero extend unit
 Produces an N-bit output by concatenating its 1-bit input with 0’s in the
most significant bits
 The sign bit(the N-1th bit) of S
 The input to the zero extend unit
 extra outputs
 Overflow flag
 Indicating that the result of the adder overflowed
 Zero flag
 Indicating that the ALU output is 0

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 Shifters and rotators
 Shifter
 Shifting a binary number left or right by a specified number of positions
 Commonly used shifters
 Logical shifter
 Shifts the number to the left (LSL) or right (LSR) and fills empty spots
with 0’s
 Ex) 11001 LSR 2 = 00110; 11001 LSL 2 = 00100
 Arithmetic shifter
 Arithmetic shift left (ASL): same as logical shift left (LSL)
 On right shifts, fills the most significant bits with a copy of the old
most significant bit
 Useful for multiplying and dividing signed numbers
 Ex) 11001 ASR 2 = 11110; 11001 ASL 2 = 00100
 Rotator
 Rotates number in circle such that empty spots are filled with bits
shifted off the other end
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  Ex) 11001 ROR 2 = 01110; 11001 ROL 2 = 00111
 Shifter design
 4-bit shifters
 Built from 4 4:1 multiplexers
 For an N-bit shifter, N N:1 multiplexers

Shift left Logical shift right arithmetic shift right

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  Operators
 <<, >>, and >>>: shift left, logical shift right, arithmetic shift right
 Shifters as Multipliers and Dividers
 Left shifter
 A special case of multiplication
 Left shift by N bits
 Multiplying the number by 2N
 Ex) 0000112 << 4 = 1100002
 Equivalent to 310 Χ 24 = 4810
 Arithmetic right shift
 A special case of division
 Arithmetic right shift by N bits
 Dividing the number by 2N
 Ex) 111002 >>> 2 = 111112
 Equivalent to -410/22 = -110

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 Multiplication
 Steps of multiplication
 Partial products are formed by multiplying a single digit of the
multiplier with the entire multiplicand
 Partial products in binary multiplication
 Either the multiplicand or all 0’s
 Multiplication of 1-bit binary numbers → equivalent to the AND operation
 Shifted partial products are summed to form the result
Decimal Binary
230 multiplicand 0101
x 42 multiplier x 0111
460 partial 0101
+ 920 products 0101
9660 0101
+ 0000
result 0100011
230 x 42 = 9660 5 x 7 = 35

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  4 X 4 multiplier
 Operations
 The partial product of the first row
 B0 AND the multiplicand bits (A3, A2, A1, A0)
 Added to the shifted second partial product, B1 AND (A3, A2, A1, A0)
 Subsequent rows of AND gates and adders form and add the
remaining partial product
A3 A2 A1 A0
A B
4 4
B0
B1
0
x
A3 A2 A1 A0 0
8
x B3 B2 B1 B0 B2
P
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1 0
B3
A3B2 A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0

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 Division
 Concept of binary division (Q = A/B)
 A = AM-1AM-2∙∙∙A1A0: in the range [2M-1,2M-1]
 Q = QN-1QN-2∙∙∙Q1Q0: in the range [2N-1, 2N-1]
 Division concept (similar with decimal division)
R = AM-1∙∙∙AN-1
for i = N-1 to 0
D=R-B
if D < 0 then Qi = 0, R’ = R // R < B
else Qi = 1, R’ = D // R ≥ B
if i ≠ 0 then R = {2R’,Ai-1}

 The partial remainder is initialized to the parts of the dividend, A

 The divisor, B, is repeatedly subtracted from the partial remainder, R
 If the difference, D, is negative, the quotient bit, Qi, is 0 and the difference is
discarded
 Otherwise, Qi is 1, and the partial difference is updated to be the difference
 The partial remainder is doubled (left-shifted by one column), and the process
repeats

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 Ex) A=0101, B=0010
 M-1=3 → M=4, N-1=1 → N=2
 R=A3A2A1=010
 i = N-1 = 1
 D = R – B = 0010-0010 = 0 ≥ 0 → Q1=1, R’=D=0000
 R = {2R’,A0} = {000,1} = 0001
 i=0
 D = R – B = 0001-0010 < 0 → Q0=0, R’=R=0001

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 Algorithm of binary division (Q = A/B)
 A,B: M-bit unsigned numbers in the range [0, 2M-1]
 R: partial remainder, D: difference
R’ = 0
for i = M-1 to 0
R={R’<<1,Ai}
D=R-B
if D < 0 then Qi = 0, R’ = R // R < B
else Qi = 1, R’ = D // R ≥ B
R = R’
 The partial remainder, R, is initialized to 0
 The divisor, B, is repeatedly subtracted from the partial remainder
 If the difference, D, is negative, the quotient bit, Qi, is 0 and the difference is
discarded
 Otherwise, Qi is 1, and the partial difference is updated to be the difference
 The partial remainder is doubled (left-shifted by one column), the next most
significant bit of A becomes the least significant bit of R, and the process
repeats

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 Ex) A=0101, B=0010
 M-1=3 → M=4
 R’=0
 i=M-1=3
 R = [000,A3] = [000,0] = 0000
 D=R–B= 0000-0010 < 0 → Q3=0, R’=R=0000
 i=2
 R = [000,A2] = [000,1] = 0001
 D=R–B= 0001-0010 < 0 → Q2=0, R’=R=0001
 i=1
 R = [001,A1] = [001,0] = 0010
 D=R–B= 0010-0010 = 0 ≥ 0 → Q1=1, R’=D=0000
 i=0
 R = [2R’, A0] = [000,1] = 0001
 D=R–B= 0001-0010 < 0 → Q0=0, R’=R=0001
 R = R’ = 0001

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 4 bit array divider
 The signal N indicates whether R – B is negative (N=1 for negative )
 Obtained from the D output of the leftmost block in the row,
which is the sign of the difference

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 The delay of an M-bit array divider
 Increases proportionally to M2
 Because the carry must ripple through all M stages in a row before the
sign is determined and the multiplexer selects R or D
 This repeats for all M rows

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Number systems

 Fixed-point number systems

 Having an implied binary point between the integer and
fraction bits
 Notation
 Ex) fixed point number with four integer bits and four fraction bits
 01101100 → 22+21+2-1+2-2 = 6.75
 Representation
 Ex) -2.375 (2.375 → 00100110)
 Sign/magnitude notation
 10100110
 Two’s complement
 11011010
 By inverting the bits of the absolute value and adding a 1 to the least
significant bit

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 Floating-point number systems
 Having a sign, mantissa(M), base(B) and exponent(E): M × BE
 Ex) 4.1 Χ 103
 A mantissa: 4.1
Position of the decimal point
 Base: 10 : Right after the most significant digit
 Exponent: 3
 32-bit floating point numbers
 1 sign bit + 8 exponent bits + 23 mantissa bits
 Ex) 22810 = 111001002 = 1.11001 × 27
1 bit 8 bits 23 bits
Version 1: 0 00000111 11 1001 0000 0000 0000 0000
Sign Exponent Mantissa
 Implicit leading one
 In binary floating point, the first bit of the mantissa is always 1 → it
need not be stored
1 bit 8 bits 23 bits
Version 2: 0 00000111 110 0100 0000 0000 0000 0000
Sign Exponent Fraction
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  Biased exponent
 Original exponent plus a constant bias
 32-bit floating point: a bias of 127 → IEEE 754 floating point standard
 Ex) for exponent of 7, the bias exponent is 7+127=134
1 bit 8 bits 23 bits
Version 3: 0 10000110 110 0100 0000 0000 0000 0000
Sign Biased Fraction
Exponent
 The exponent -4: -4+127 = 123 = 011110112
 Special cases
 IEEE 754 standard
Number Sign Exponent Fraction
0 X 00000000 00000000000000000000000
∞ 0 11111111 00000000000000000000000
-∞ 1 11111111 00000000000000000000000
NaN X 11111111 non-zero
Numbers that don’t exist

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 Single- and double-precision formats
Format Total bits Sign bits Exponent bits Fraction bits
Single 32 1 8 23
double 64 1 11 52

 Rounding
 Modes
 Round down
 Round up
 Round toward zero
 Round to nearest
 Default rounding mode
 If two numbers are equally near, the one with a 0 in the least
significant position of the fraction is chosen
 Cf) overflow: when the magnitude of a number is too large to be
represented
 In round to nearest mode, overflow are rounded up to ±∞

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  Underflow: when it is too tiny to be represented
 Underflows are rounded down to 0
 Floating point addition
 Steps for adding floating-point numbers with the same sign
 1. Extract exponent and fraction bits
 2. Prepend leading 1 to form mantissa
 3. Compare exponents
 4. Shift smaller mantissa if necessary
 5. Add mantissas
 6. Normalize mantissa and adjust exponent if necessary
 7. Round result
 8. Assemble exponent and fraction back into floating-point number

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 Ex) 7.875 (1.11111 × 22) + 0.1875 (1.1 × 2-3)

Extract exponent and fraction bits

Prepend leading 1 to form mantissa

Compare exponents

Shift smaller mantissa if necessary

Add mantissas

Normalize mantissa and adjust exponent

if necessary

Round result
Assemble exponent and fraction back
into floating-point number

34 컴퓨터 구조
Sequential building blocks

 Counters
 N-bit binary counter
 A sequential arithmetic circuit with clock and reset inputs and an
N-bit output, Q
 Advances through all 2N possible outputs in binary order, incrementing
on the rising edge of the clock
 Composed of an adder and a resettable register

35 컴퓨터 구조
 Shift registers
 Having a clock, a serial input, Sin, a serial output, Sout, and N
parallel outputs, QN-1:0
[ symbol ] [ implementation ]
CLK
N
Q S in S out

S in S out
Q0 Q1 Q2 Q N-1

 Operations
 On each rising edge of the clock
 a new bit is shifted in from Sin and all the subsequent contents are
shifted forward
 Viewed as serial-to-parallel converters
 The input is provided serially at Sin.
 After N cycles, the past N inputs are available in parallel at Q

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 Parallel-to-serial converter
 Loading N bits in parallel, then, shifting them out one at a time

D0 D1 D2 DN-1
Load
Clk
S in 0 0 0 0 S out
1 1 1 1

Q0 Q1 Q2 Q N-1

 Operations
 When Load = 1, acts as a normal N-bit register
 When Load = 0, acts as a shift register

37 컴퓨터 구조
Memory arrays

 Three types of memory arrays

 Dynamic random access memory (DRAM)
 Static random access memory (SRAM)
 Read only memory (ROM)
 Operation
 Reads or writes the contents of one of the rows of the array
 Address
 Specifying the row Address
N
Array
 Data
 The value read or written
M
 Array with N-bit addresses and M-bit data Data
 Having 2N rows and M columns
 Word
 Each row of data

38 컴퓨터 구조
 Definition
 The depth
 The number of rows
 The width
 The number of columns
 Called the word size
 Total size of the array
 depth x width = 2N × M
 Bit cell
 Storing 1 bit of data
 Memory arrays are built as an array of bit cells
 When the wordline is HIGH
 The stored bit transfers to or from the bitline [bit cell]
 Otherwise
 The bitline is disconnected from the bit cell

39 컴퓨터 구조
 Operation
 To read a bit cell
 The bitline is initially left floating
 The wordline is turned on, allowing the stored value to drive the bitline to
0 or 1
 To write a bit cell
 The bitline is strongly driven to the desired value
 The wordline is turned on, connecting the bitline to the stored bit
 The strongly driven bitline overpowers the contents of the bit cell, writing
the desired value into the stored bit

40 컴퓨터 구조
 Organization
 During a memory read
 A wordline is asserted, and the corresponding row of bit cells drives the bitline
HIGH or LOW
 During a memory write
 The bitlines are driven HIGH or LOW first and then a wordline is asserting
 Allowing the bitline values to be stored in that row of bit cells
2:4
Decoder bitline2 bitline1 bitline0
wordline3
11
2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline2
10
stored stored stored
wordline1 bit = 1 bit = 0 bit = 0
01
stored stored stored
bit = 1 bit = 1 bit = 0
wordline0
00
stored stored stored
bit = 0 bit = 1 bit = 1

Data2 Data1 Data0

41 컴퓨터 구조
 Memory types
 RAM (random access memory)
 Volatile, meaning that it loses its data when the power is turned off
 Any data word is accessed with the same delay as any other
 Two major types
 Dynamic RAM
 Stores data as a charge on a capacitor
 Static RAM
 Stores data using a pair of cross-coupled inverters
 ROM (read only memory)
 Nonvolatile, meaning that it retains its data indefinitely, even without power
 ROMs are randomly accessed too.
 Most modern ROMs can be written as well as read

42 컴퓨터 구조
  Dynamic RAM (random access memory)
 The bit value is stored on a capacitor
 The nMOS transistor behaves as a switch
 Called dynamic because the value needs to be refreshed (rewritten)
periodically and after being read
 Charge leakage from the capacitor degrades the value
 Reading destroys the stored value

bitline bitline bitline

wordline wordline wordline

stored
stored + + stored
bit
bit = 1 bit = 0

[DRAM bit cell] Upon a read,

 Data values are transferred from the capacitor to the bitlitne
 Reading destroys the bit value stored on the capacitor
Upon a write
Data values are transferred from the bitline to the capacitor

43 컴퓨터 구조
 Static RAM (random access memory)
 Stored bits do not need to be refreshed [SRAM bit cell]

bitline bitline
 Operation wordline
 When the wordline is asserted
 Both nMOS transistors turn on
 Data values are transferred to or from the bitlines
 If noise degrades the value of the stored bit, the cross-coupled inverters restore
the value
 Memory comparison
Memory type Transistors per Latency
bit cell
Flip-flop ~ 20 fast
SRAM 6 Medium
DRAM 1 Slow

44 컴퓨터 구조
 ROM (read only memory) [ROM bit cell]
bitline
 Stores a bit as the presence or absence of a transistor
wordline
 Operation
 To read the cell
 The bitline is weakly pulled high bit cell
containing 0
 The wordline is turned on
 If the transistor is present bitline
 It pulls the bitline low wordline
 If it is absent
bit cell
 The bitline remains high containing 1
 The contents of a ROM
 can be indicated using the dot notation
 A dot at the intersection of a row and a column
 Indicates that the data bit is 1
 Ex) the top wordline has a single dot on Data1
 The data word stores at Address 11 is 010

45 컴퓨터 구조
 Logic using memory arrays Data2  A1  A0
Data1  A1  A0
Data0  A1 A0

 Memory arrays used to perform logic

 Called lookup tables (LUTs): look up output at each input combination (address)
 Ex) a LUT to perform Y = AB 4-word x 1-bit Array

2:4
Decoder bitline
Truth
Table 00
stored
A A1
bit = 0
A B Y 01
B A0
0 0 0 stored
0 1 0 bit = 0
1 0 0 10
1 1 1 stored
bit = 0
11
stored
bit = 1

46 컴퓨터 구조
 Verilog memory arrays
// 2N-word x M-bit RAM
module ram #(parameter N=6, M=32)
( input clk,
input we,
input [N-1:0] adr, //address
input [M-1:0] din,
output [M-1:0] dout);

reg [M-1:0] mem[2**N-1:0];

always @(posedge clk)

if (we) mem[adr] <= din;

assign dout = mem[adr];

endmodule

47 컴퓨터 구조
Logic arrays

 Logic arrays
 Configured to perform any function without the user having to
connect wires in specific ways
 Most logic arrays
 Reconfigurable, allowing designs to be modified without replacing the
hardware
 Two types
 Programmable logic arrays (PLAs)
 Field programmable gate arrays (FPGAs)
 Programmable logic array
 Performing only combinational logic functions
 Implemented two-level combinational logic in sum-of-products
(SOP) form
 Built from an AND array followed by an OR array

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  M x N x P-bit PLA Inputs
M

AND Implicants OR
ARRAY N ARRAY

P
Outputs
 Ex) 3 x 3 x 2-bit PLA
[dot notation] [using two level logic]
A B C A B C
OR ARRAY OR ARRAY

ABC
ABC
ABC
ABC

AB AB

AND ARRAY AND ARRAY

X Y X Y

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  Programmable logic devices (PLDs)
 Souped-up PLAs that add registers and various other features to
the basic AND/OR planes
 Field programmable gate array (FPGA)
 An array of reconfigurable gates
 Implement both combinational and sequential logic
 Implement multilevel logic functions
 Cf) PLAs: implement only two-level logic
 Composed of
 CLBs (Configurable logic blocks): perform logic
 Surrounded by IOBs for interfacing with external devices
 CLBs can connect to other CLBs and IOBs through programmable
routing channels
 IOBs (Input/output buffers): interface with outside world
 Programmable interconnection: connect CLBs and IOBs
 Some FPGAs include other building blocks such as multipliers and RAMs

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  Ex) Spartan block diagram

Boundary scan

Read back

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 Configurable logic blocks (CLBs)
 Contains
 LUTs (lookup tables): perform combinational logic
 Configurable Multiplexers: connect LUTs and flip-flops(registers)
 Flip-flops: perform sequential functions

[ Xilinx Spartan CLB]

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  CLB Configuration Example
 Configure the Spartan CLB to perform the following functions

X  ABC  ABC , Y  AB
 Configure the F-LUT to compute X and the G-LUT to compute Y

(A) (B) (C) (X) (A) (B) (Y)

0 G4
F4 F3 F2 F1 F G4 G3 G2 G1 G
0 G3
X 0 0 0 0 X X 0 0 0 G
A G2 Y
X 0 0 1 1 X X 0 1 0
B G1
X 0 1 0 0 X X 1 0 1
X 0 1 1 0 X X 1 1 0
X 1 0 0 0
0 F4
X 1 0 1 0
A F3
X 1 1 0 1 F
B F2 X
x 1 1 1 0
C F1

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 Array implementation
 ROMs and PLAs use pseudo nMOS or dynamic circuits
 In order to minimize their size and cost
 ROM implementaion
 Each decoder output: connected to the gates of the nMOS transistors
in its row
 the weak pMOS transistor pulls the output HIGH
 only if there is no path to GND through the pull-down (nMOS)
network
 Pull-down transistors are placed at every junction without a dot
Single weak pMOS
that is always on

Parallel nMOS

[ dot notation] [ pseudo-nMOS circuit]

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  Ex) when AB=11
 The 11 wordline is HIGH
 transistors on X and Z turn on and pull those outputs LOW
 The Y output has no transistor connecting the 11 wordline
 Y is pulled HIGH by the weak pull-up
 PLA implementaion
 3 x 3 x 2-bit PLA using pseudo-nMOS circuits

 Pull-down (nMOS) transistors

 Placed on the complement of dotted literals in the AND array and on
dotted rows in the OR array
 The column in the OR array
 Sent through an inverter before they are fed to the output bits
55 컴퓨터 구조
Exercises

 5.1, 5.7, 5.13, 5.31, 5.43, 5.51(a), 5.57

56 컴퓨터 구조