i.

MX 8M Mini Applications Processor

Reference Manual

Document Number: IMX8MMRM

Rev. 3, 11/2020
 i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
2 NXP Semiconductors
 Contents
Section number Title Page

Chapter 1
Introduction
1.1 Product Overview ........................................................................................................................................................ 7

1.2 Target Applications.......................................................................................................................................................7

1.3 Acronyms and Abbreviations....................................................................................................................................... 7

1.4 Features......................................................................................................................................................................... 10

1.5 Architectural Overview.................................................................................................................................................16

1.6 Primary Boot Options................................................................................................................................................... 17

1.7 Endianness Support.......................................................................................................................................................18

Chapter 2
Memory Map
2.1 Memory.........................................................................................................................................................................19

Chapter 3
Security
3.1 System Security............................................................................................................................................................ 33

3.2 Resource Domain Controller (RDC)............................................................................................................................ 35

Chapter 4
ARM Platform and Debug
4.1 ARM Cortex A53 Platform (A53)................................................................................................................................ 79

4.2 ARM Cortex M4 Platform (M4)...................................................................................................................................85

4.3 Messaging Unit (MU)................................................................................................................................................... 117

4.4 Semaphore (SEMA4)....................................................................................................................................................156

4.5 On-Chip RAM Memory Controller (OCRAM)............................................................................................................174

4.6 Network Interconnect Bus System (NIC)..................................................................................................................... 177

4.7 AHB to IP Bridge (AIPSTZ)........................................................................................................................................ 178

4.8 Shared Peripheral Bus Arbiter (SPBA).........................................................................................................................200

4.9 System Counter (SYS_CTR)........................................................................................................................................ 214

4.10 TrustZone Address Space Controller (TZASC)........................................................................................................... 252

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 3
Section number Title Page

4.11 System Debug............................................................................................................................................................... 254

4.12 System JTAG Controller (SJC).................................................................................................................................... 258

Chapter 5
Clocks and Power Management
5.1 Clock Control Module (CCM)......................................................................................................................................289

5.2 General Power Controller (GPC)..................................................................................................................................618

5.3 Crystal Oscillator (XTALOSC).................................................................................................................................... 758

5.4 Thermal Monitoring Unit (TMU)................................................................................................................................. 762

Chapter 6
SNVS, Reset, Fuse, and Boot
6.1 System Boot.................................................................................................................................................................. 777

6.2 Fusemap........................................................................................................................................................................ 855

6.3 On-Chip OTP Controller (OCOTP_CTRL)..................................................................................................................865

6.4 Secure Non-Volatile Storage (SNVS).......................................................................................................................... 894

6.5 System Reset Controller (SRC).................................................................................................................................... 928

6.6 Watchdog Timer (WDOG)........................................................................................................................................... 978

Chapter 7
Interrupts and DMA
7.1 Interrupts and DMA Events.......................................................................................................................................... 995

7.2 Smart Direct Memory Access Controller (SDMA)...................................................................................................... 1010

Chapter 8
Chip IO and Pinmux
8.1 External Signals and Pin Multiplexing......................................................................................................................... 1259

8.2 IOMUX Controller (IOMUXC)....................................................................................................................................1275

8.3 General Purpose Input/Output (GPIO)......................................................................................................................... 1685

Chapter 9
External Memory
9.1 External Memory Overview......................................................................................................................................... 1705

9.2 DDR Controller (DDRC)..............................................................................................................................................1707

9.3 DDR PHY (DDR_PHY)............................................................................................................................................... 1906

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

4 NXP Semiconductors
Section number Title Page

9.4 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA).......................................................................................... 2221

9.5 62BIT Correcting ECC Accelerator (BCH)..................................................................................................................2259

9.6 General Purpose Media Interface (GPMI)....................................................................................................................2316

Chapter 10
Mass Storage
10.1 Enhanced Configurable SPI (ECSPI)........................................................................................................................... 2367

10.2 FlexSPI Controller (FlexSPI)........................................................................................................................................2396

10.3 Ultra Secured Digital Host Controller (uSDHC).......................................................................................................... 2520

Chapter 11
Connectivity
11.1 Universal Serial Bus Controller (USB).........................................................................................................................2651

11.2 Universal Serial Bus 2.0 PHY (USB2_PHY)............................................................................................................... 2927

11.3 PCI Express (PCIe)....................................................................................................................................................... 2940

11.4 PCI Express PHY (PCIe_PHY).................................................................................................................................... 3316

11.5 Ethernet MAC (ENET)................................................................................................................................................. 3702

Chapter 12
Timers
12.1 General Purpose Timer (GPT)...................................................................................................................................... 3855

12.2 Pulse Width Modulation (PWM).................................................................................................................................. 3877

Chapter 13
Multimedia
13.1 Multimedia Overview................................................................................................................................................... 3891

13.2 Display Block Control (DISPLAY_BLK_CTRL)........................................................................................................3897

13.3 Enhanced LCD Interface (eLCDIF)..............................................................................................................................3924

13.4 CSI Bridge (CSI)...........................................................................................................................................................3967

13.5 MIPI CSI Host Controller (MIPI_CSI).........................................................................................................................4004

13.6 MIPI DSI Host Controller (MIPI_DSI)........................................................................................................................ 4054

13.7 MIPI D-PHY (MIPI_DPHY)........................................................................................................................................4123

13.8 Sony/Philips Digital Interface (SPDIF)........................................................................................................................ 4175

13.9 PDM Microphone Interface (MICFIL).........................................................................................................................4211

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 5
Section number Title Page

13.10 Synchronous Audio Interface (SAI)............................................................................................................................. 4267

Chapter 14
Graphics Processing Unit (GPU)
14.1 GPU Overview..............................................................................................................................................................4321

14.2 2D Graphics Processing Unit (GPU2D)....................................................................................................................... 4322

14.3 3D Graphics Processing Unit (GPU3D)....................................................................................................................... 4336

Chapter 15
Video Processing Unit (VPU)
15.1 VPU Block Control (VPU_BLK_CTRL).....................................................................................................................4343

15.2 VPU G1 (VPU_G1)...................................................................................................................................................... 4350

15.3 VPU G2 (VPU_G2)...................................................................................................................................................... 4523

15.4 VPU H1 (VPU_H1)...................................................................................................................................................... 4757

Chapter 16
Low Speed Communication and Interconnects
16.1 I2C Controller (I2C)..................................................................................................................................................... 5215

16.2 Universal Asynchronous Receiver/Transmitter (UART)............................................................................................. 5238

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

6 NXP Semiconductors
Chapter 1
Introduction

1.1 Product Overview

This chapter introduces the architecture of the i.MX 8M Mini Applications Processor.
The i.MX 8M Mini is a family of products focused on delivering an excellent video and
audio experience, combining media-specific features with high-performance processing
optimized for low-power consumption.

1.2 Target Applications

The i.MX 8M Mini Media Applications Processor is built to achieve both high
performance and low power consumption and relies on a powerful fully coherent core
complex based on a quad Cortex-A53 cluster with video and graphics accelerators.
The i.MX 8M Family provides additional computing resources and peripherals:
• Advanced security modules for secure boot, cipher acceleration and DRM support
• General purpose Cortex-M4 processor for low power processing
• A wide range of audio interfaces including I2S, AC97, TDM and S/PDIF
• Large set of peripherals that are commonly used in consumer/industrial markets
including USB 2.0, PCIe and Ethernet

1.3 Acronyms and Abbreviations

The table below contains acronyms and abbreviations used in this document.
Acronyms and Abbreviated Terms

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 7
Acronyms and Abbreviations

Term Meaning
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AIPS Arm IP Bus
ALU Arithmetic Logic Unit
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
ASRC Asynchronous Sample Rate Converter
AXI Advanced eXtensible Interface
BIST Built-In Self Test
CA/CM Arm Cortex-A/Cortex-M
CAAM Cryptographic Acceleration and Assurance Module
CA53 ARM Cortex A53 Core
CAN Controller Area Network
CPU Central Processing Unit
CSI CMOS Sensor Interface
CSU Central Security Unit
CTI Cross Trigger Interface
D-cache Data cache
DAP Debug Access Port
DDR Double data rate
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
ECC Error correcting codes
ECSPI Enhanced Configurable SPI
LPSPI Low-power SPI
EDMA Enhanced Direct Memory Access
EIM External Interface Module
ENET Ethernet
EPIT Enhanced Periodic Interrupt Timer
EPROM Erasable Programmable Read-Only Memory
ETF Embedded Trace FIFO
ETM Embedded Trace Macrocell
FIFO First-In-First-Out
GIC General Interrupt Controller
GPC General Power Controller
GPIO General-Purpose I/O
GPR General-Purpose Register
GPS Global Positioning System
GPT General-Purpose Timer
GPU Graphics Processing Unit

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

8 NXP Semiconductors
 Chapter 1 Introduction

Term Meaning
GPV Global Programmers View
HAB High-Assurance Boot
I-cache Instruction cache
I2C or I2C Inter-Integrated Circuit
IC Integrated Circuit
IEEE Institute of Electrical and Electronics Engineers
IOMUX Input-Output Multiplexer
IP Intellectual Property
IrDA Infrared Data Association
JTAG Joint Test Action Group (a serial bus protocol usually used for test purposes)
ELCDIF Liquid Crystal Display Interface
LDO Low-Dropout
LIFO Last-In-First-Out
LRU Least-Recently Used
LSB Least-Significant Byte
LUT Look-Up Table
LVDS Low Voltage Differential Signaling
MAC Medium Access Control
MCM Miscellaneous Control Module
MMC Multimedia Card
MSB Most-Significant Byte
MT/s Mega Transfers per second
OCRAM On-Chip Random-Access Memory
OCOTP On-Chip One-Time Programmable Controller
PCI Peripheral Component Interconnect
PCIe PCI express
PCMCIA Personal Computer Memory Card International Association
PGC Power Gating Controller
PIC Programmable Interrupt Controller
PMU Power Management Unit
POR Power-On Reset
PSRAM Pseudo-Static Random Access Memory
PWM Pulse Width Modulation
PXP Pixel Pipeline
QoS Quality of Service
R2D Radians to Degrees
RISC Reduced Instruction Set Computing
ROM Read-Only Memory
ROMCP ROM Controller with Patch
RTOS Real-Time Operating System
Rx Receive

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 9
Features

Term Meaning
SAI Synchronous Audio Interface
SCU Snoop Control Unit
SD Secure Digital
SDIO Secure Digital Input/Output
SDLC Synchronous Data Link Control
SDMA Smart DMA
SIM Subscriber Identification Module
SNVS Secure Non-Volatile Storage
SoC System-on-Chip
SPBA Shared Peripheral Bus Arbiter
SPDIF Sony Phillips Digital Interface
SPI Serial Peripheral Interface
SRAM Static Random-Access Memory
SRC System Reset Controller
TFT Thin-Film Transistor
TPIU Trace Port Interface Unit
TSGEN Time Stamp Generator
Tx Transmit
TZASC TrustZone Address Space Controller
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
USDHC Ultra Secured Digital Host Controller
WDOG Watchdog
WLAN Wireless Local Area Network
WXGA Wide Extended Graphics Array

1.4 Features

1.4.1 Arm Cortex-A53 MPCore™ Platform

The i.MX 8M Family Applications Processors are based on the Arm Cortex-A53
MPCore™ Platform, which has the following features:
• Quad symmetric Cortex-A53 processors, including:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

10 NXP Semiconductors
 Chapter 1 Introduction

• Media Processing Engine (MPE) with NEON technology supporting the

Advanced Single Instruction Multiple Data architecture
• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture
• Support of 64-bit Armv8-A architecture
• 512 KB unified L2 cache
• Target frequency of 1.8GHz

1.4.2 Arm Cortex-M4 Platform

Cortex-M4 Core Platform include the following:
• Low power microcontroller available for customer application:
• Low power standby mode
• IoT features including Weave
• Manage IR or wireless remote
• Arm Cortex M4 CPU Processor, including:
• 16 KB L1 Instruction Cache
• 16 KB L1 Data Cache
• 256 KB TCM

1.4.3 System Bus and Interconnect

System bus and interconnect include the following:

• Network interconnect (NoC) AXI arbiter

• Quality of service controller (QoSC) to configure priorities and limits of AXI
transcations
• Performance monitor (PERFMON) to monitor AXI bus activity
• Debug monitor (DBGMON) to record AXI transactions preceding a system reset

1.4.4 Clocking and Resets

Clocking and resets include:

• Clock control module (CCM) provides centralized clock generation and control
• Simplified clock tree structure

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 11
Features

• Unified clock programming model for each clock root

• Multicore awareness for resource domains
• System reset controller (SRC) provides reset generation and distribution

1.4.5 Interrupts and DMA

Interrupts and DMA include:
• 128 shared peripheral interrupts routed to Cortex-A53 Global Interrupt Controller
(GIC) and Cortex-M4 nested vector interrupt controller (NVIC) for flexible interrupt
handling
• Three Smart direct memory access (SDMA) engines. Although these three engines
are identical to each other, they are integrated into the processor to serve different
peripherals.
• SDMA-1 is a general-purpose DMA engine which can be used by low speed
peripherals including UART, SPI and also others peripherals.
• SDMA-2 and SMDA-3 is used for audio interface, including SAI-1/2/3/5/6,
SPDIF and PDM audio input.

1.4.6 On-Chip Memory

The on-chip memory system consists of the following:

• Boot ROM (256KB)
• On-chip RAM (256KB + 32KB)

1.4.7 External Memory Interface

The external memory interfaces supported on this chip include:

• 16/32-bit DRAM Interface:
• LPDDR4-3000
• DDR4-2400
• DDR3L-1600
• 8-bit NAND FLASH, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
• eMMC 5.1 FLASH (2 interfaces)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

12 NXP Semiconductors
 Chapter 1 Introduction

• SPI NOR FLASH (3 interfaces)

• FlexSPI FLASH with support for XIP (for M4 in low-power mode) and parallel read
mode of two identical FLASH devices

1.4.8 Timers
The timers on this chip include:

• One local generic timer integrated into each Cortex-A53 CPU

• Global system counter with timer bus interface to Cortex-A53 MPCore generic
timers
• One local system timer (SysTick) integrated into the Cortex-M4 CPU
• Six general purpose timer (GPT) modules
• Three watchdog timer (WDOG) modules
• Four pulse width modulation (PWM) modules

1.4.9 Graphics Processing Unit (GPU)

The chip incorporates the following Graphics Processing Unit (GPU) features:
• 2D/3D acceleration
• Target frequency of 800 MHz
• Support OpenGL ES 1.1, 2.0, OpenVG 1.1
• TrustZone support using a local MMU to manage secure regions
• Support multi-source composition
• Support one-pass filter
• Support tile format

1.4.10 Video Processing Unit (VPU)

The chip incorporates the following Video Processing Unit (VPU) features:
• VP9 Profile 0, 2 (10 bit) decoder (VPU G2)
• HEVC/H.265 decoder (VPU G2)
• AVC/H.264 Baseline, Main, High decoder (VPU G1)
• VP8 decoder (VPU G1)
• AVC/H.264 Encoder (VPU H1)
• VP8 encoder (VPU H1)
• TrustZone support

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 13
Features

1.4.11 Display Interfaces

The chip has the following display support:
• LCDIF Display Controller:
• Supports one layer
• Supports up to 1920x1200p60 display through MIPI DSI
• MIPI Interface:
• 4-lane MIPI CSI interface
• 4-lane MIPI DSI interface
• CSI Interface:
• CSI is a simple camera interface which is used to capture the MIPI CSI input and
save the pixels into memory

1.4.12 Audio
Audio include the following:
• S/PDIF Input and Output, including a Raw Capture input mode
• Five external SAI (synchronous audio interface) modules supporting I2S, AC97,
TDM, codec/DSP and DSD interfaces, including one SAI with 8 TX and 8 RX lanes,
one SAI with 4 TX and 4 RX lanes, two SAI with 2 TX and 2 RX lanes, and one SAI
with 1 TX and 1 RX lanes. Supports over 20 channels of audio subject to I/O
limitations.

1.4.13 General Connectivity Interfaces

The chip contains a rich set of general connectivity interfaces, including:
• One PCI Express (PCIe):
• Single lane supporting PCIe Gen 2
• Dual mode operation to function as root complex or endpoint
• Integrated PHY interface
• Supports L1 low power substate
• Two USB 2.0 OTG controllers with integrated PHY interface
• Spread spectrum clock support
• Three Ultra Secure Digital Host Controller (uSDHC) interfaces
• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

14 NXP Semiconductors
 Chapter 1 Introduction

• SD/SDIO 3.01 compliance with 200 MHZ SDR signaling to support up to 100
MB/sec
• Support for SDXC (extended capacity)
• One Gigabit Ethernet controller with support for EEE, Ethernet AVB and IEEE1588
• Four universal asynchronous receiver/transmitter (UART) modules
• Four I2C modules
• Three SPI modules

1.4.14 Security

Security functions are enabled and accelerated by the following hardware:

• RDC – Resource Domain Controller:
• Supports 4 domains and up to 8 regions
• Arm TrustZone including the TZ architecture:
• ARM Cortex-A53 MPCore TrustZone support
• On-chip RAM (OCRAM) secure region protection using OCRAM controller
• High Assurance Boot (HAB)
• Cryptographic Acceleration and Assurance Module (CAAM)
• Support Widevine and PlayReady content protection
• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC)
algorithms
• Real-time integrity checker (RTIC)
• DRM support for RSA, AES, 3DES, DES
• True random number generation (RNG)
• Manufacturing protection support
• Secure Non-Volatile Storage (SNVS), including
• Secure Real Time Clock (SRTC)
• Secure JTAG Controller (SJC)

1.4.15 Multicore Support

Multicore support contains:
• Resource domain controller (RDC) to support isolation and safe sharing of system
resources
• Messaging unit (MU)
• Hardware Semaphore (SEMA4)
• Shared bus topology

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 15
Architectural Overview

1.4.16 GPIO and Pin Multiplexing

• General-purpose input/output (GPIO) modules with interrupt capability

• Input/output multiplexing controller (IOMUXC) to provide centralized pad control

1.4.17 Power Management

The power management unit consists of:

• Temperature sensor with programmable trip points

• Flexible power domain partitioning with internal power switches to support efficient
power management

1.4.18 System Debug

The system debug features are:
• ARM CoreSight debug and trace architecture
• Trace Port Interface Unit (TPIU) to support off-chip real-time trace
• Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering
• Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs
• Cross Triggering Interface (CTI)
• Support for 5-pin (JTAG) debug interfaces

1.5 Architectural Overview

This section contains the i.MX 8M Mini architectural details.

1.5.1 Block Diagram

The high-level block diagram is shown in the figure below.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

16 NXP Semiconductors
 Chapter 1 Introduction

LPDDR4 Battery Ctrl JTAG Crystal&

/DDR4/DDR3L Device (IEEE1149.6) Clock Source

eMMC 5.0 Arm Cortex A53 Debug Clock & Reset

External Memory
FLASH MPCore Platform DAP PLLs
DDR Controller CPU3
TPIU CCM
SD/eMMC CPU2
NAND FLASH GPMI&BCH CPU1 CTIs GPC
CPU0 SJC SRC
QSPI I$ 32KB D$ 32KB
Quad SPI XTAL OSC
NEON CRYPTO
Flash
Timers RC OSC
SCU & Timer
Internal Memory WDOG(3)
L2 Cache 512 KB
OCRAM 256KB GPT(6)
AXI and AHB Switch Fabric
OCRAM_S 32KB Arm Cortex M4 AP Peripherals
System Counter MMC/SD
Platform
ROM 256KB uSDHC(3) eMMC/eSD
Cortex-M4 Core
I$ 16KB OCOTP MMC/SD
Security D$ 16KB
SDXC
CAAM NVIC FPU MPU USB 2.0
(32KB RAM)
Smart DMA OTG (2)
Tamper TCM 256KB SDMA(3) USB OTG
Detection CSU AVB ENET (dev/host)
OCOTP (eFuse)
PCIe v2.1
Multi-Core Unit 10/100/1000M
SNVS(RTC) SPBA(2) Ethernet
RDC MU I2C(4)
SEMAPHORE eCSPI(3)
Shared Peripherals PCIe Bus
LCD Panel Display Interface
Graphics/Video eCSPI(3) PWM(4)
LCDIF
GPU SAI(5)
MIPI DSI UART(4)
VPU WLAN
Camera UART(3)
MIPI CSI2 GPIO(5)
Power Management SPDIF(1)
CSI IOMUX
Temp Monitor PDM

Figure 1-1. Block Diagram

1.6 Primary Boot Options

The i.MX 8M Mini supports the following boot devices:
• NAND FLASH (including SLC and MLC)
• SDIO / MMC / SDXC
• eSD 3.0/eMMC 5.1 (fast boot)
• SPI (serial FLASH)
• USB
• QSPI
• Ethernet (via plug-in mode)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 17
Endianness Support

The Quad-A53 core on i.MX 8M Mini is enabled during boot as the primary core to
handle the entire secure boot flow. The chip will always boot from the A53 core first, the
M4 core will be held in reset during the A53 boot and won’t run until it is enabled by the
A53 core. The image for the M4 core will be loaded into memory and authenticated by
the A53 core.

1.7 Endianness Support

This chip supports Little Endian mode only.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

18 NXP Semiconductors
Chapter 2
Memory Map

2.1 Memory
This chapter introduces the memory architecture of the chip. The system memory high-
level partition is defined below:

2.1.1 Memory system overview

2.1.1.1 On-chip L1, L2 caches, TCM

Cortex-A53 MPcore Platform
• Level 1 Cache (4x per Cortex-A53 Core)
• Instruction (32 KB)
• Data (32 KB)
• Level 2 Cache, shared by the four Cortex-A53 cores:
• Unified instruction and data (512 KB)
Cortex M4 Platform
• Cache
• Instruction (16 KB)
• Data (16 KB)
• Tightly-Coupled-Memory
• TCML on Code Bus (128KB)
• TCMH on System Bus (128KB)

2.1.1.2 On-chip memories

• Boot ROM (256 KB)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 19
Memory

• On-Chip RAM - OCRAM (256 KB)

• On-Chip RAM for State Retention - OCRAM_S (32 KB)

2.1.1.3 External L3 memories

The chip supports external memories, via the following memory interfaces / controllers:
• 16/32-bit DRAM Interface:
• LPDDR4-3000, DDR4-2400, DDR3L-1600
• 8-bit NAND FLASH, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFI 2.x compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
• eMMC 5.0 FLASH
• SPI NOR FLASH
• Quad SPI FLASH with support for XIP (for M4 in low-power mode) and parallel
read mode of two identical FLASH devices

2.1.2 Cortex-A53 Memory Map

Start Address End Address Region Size Description

1_0000_0000 2_3FFF_FFFF DDR Address 5120MB DDR Memory (Quad-A53 only)
4000_0000 FFFF_FFFF DDR Address 3072MB DDR Memory (All modules)
3FC0_0000 3FFF_FFFF Reserved 4MB Reserved
3F80_0000 3FBF_FFFF Reserved 4MB Reserved
3F40_0000 3F7F_FFFF Reserved 4MB Reserved
3E00_0000 3F3F_FFFF Reserved 20MB Reserved
3DC0_0000 3DFF_FFFF DDRC 4MB Reserved
3D80_0000 3DBF_FFFF DDRC 4MB DDR PERF_MON
3D40_0000 3D7F_FFFF DDRC 4MB DDR CTL
3C00_0000 3D3F_FFFF DDRC 20MB DDR PHY
3890_0000 3BFF_FFFF Reserved 55MB Reserved
3880_0000 388F_FFFF GIC 1MB GIC REG
3870_0000 387F_FFFF Reserved 1MB Reserved
3850_0000 386F_FFFF Reserved 2MB Reserved
3830_0000 384F_FFFF VPU 2MB VPU
3820_0000 382F_FFFF Reserved 1MB Reserved
3810_0000 381F_FFFF Reserved 1MB Reserved
3801_0000 380F_FFFF Reserved 960KB Reserved
3800_0000 3800_FFFF GPU REG 64KB GPU REG

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

20 NXP Semiconductors
 Chapter 2 Memory Map

Start Address End Address Region Size Description

3600_0000 37FF_FFFF QSPI RX Buffers 32MB Reserved (QSPI2 RX Buffer)
3400_0000 35FF_FFFF 32MB QSPI1 RX Buffer
33C0_0000 33FF_FFFF PCIe REG 4MB Reserved
3380_0000 33BF_FFFF 4MB PCIe1 REG
3310_0000 337F_FFFF Reserved 7MB Reserved
3301_0000 330F_FFFF Reserved 960KB Reserved
3300_8000 3300_FFFF QSPI TX Buffers 32KB QSPI1 TX Buffer
3300_0000 3300_7FFF APBH DMA 32KB APBH DMA
32C0_0000 32FF_FFFF Periph (AIPS) 4MB AIPS4
3290_0000 32BF_FFFF Reserved 3MB Reserved
3280_0000 328F_FFFF GPV_8 1MB "HSIO" configuration
3270_0000 327F_FFFF GPV_7 1MB NoC configuration
3260_0000 326F_FFFF GPV_6 1MB "m4" configuration port
3250_0000 325F_FFFF GPV_5 1MB "display" configuration port
3240_0000 324F_FFFF GPV_4 1MB "enet" configuration port
3230_0000 323F_FFFF GPV_3 1MB "per_m" configuration port
3220_0000 322F_FFFF GPV_2 1MB "per_s" configuration port
3210_0000 321F_FFFF GPV_1 1MB "wakeup" configuration port
3200_0000 320F_FFFF GPV_0 1MB "main" configuration port
3100_0000 31FF_FFFF Reserved 16MB Reserved
30C0_0000 30FF_FFFF Periph (AIPS) 4MB Reserved
3080_0000 30BF_FFFF 4MB AIPS-3, See IP listing on separate map.
3040_0000 307F_FFFF 4MB AIPS-2, See IP listing on separate map.
3000_0000 303F_FFFF 4MB AIPS-1, See IP listing on separate map.
2900_0000 2FFF_FFFF Reserved 112MB Reserved
2800_0000 28FF_FFFF A53 / DAP 16MB A53 / DAP
2000_0000 27FF_FFFF Reserved 128MB Reserved
1800_0000 1FFF_FFFF PCIe-1 128MB PCIe-1
0800_0000 17FF_FFFF QSPI 256MB QSPI
0400_0000 07FF_FFFF Reserved 64MB Reserved
0100_0000 03FF_FFFF Reserved 48MB Reserved
00C0_0000 00FF_FFFF Reserved 4MB Reserved
00B0_0000 00BF_FFFF Reserved 1MB Reserved
00A0_0000 00AF_FFFF OCRAM 1MB Reserved (OCRAM)
0094_8000 009F_FFFF 736KB Reserved (OCRAM)
0094_0000 0094_7FFF 32KB Reserved (OCRAM)
0092_0000 0093_FFFF 128KB OCRAM 128KB
0090_0000 0091_FFFF 128KB OCRAM 128KB
0084_0000 008F_FFFF Reserved 768KB Reserved
0082_0000 0083_FFFF TCM 128KB Reserved (TCM)
0080_0000 0081_FFFF 128KB TCMU

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 21
Memory

Start Address End Address Region Size Description

007E_0000 007F_FFFF 128KB TCML
007C_0000 007D_FFFF 128KB Reserved (TCM)
0070_0000 007B_FFFF Reserved 768KB Reserved
0060_0000 006F_FFFF Reserved 1MB Reserved
0050_0000 005F_FFFF Reserved 1MB Reserved
0040_0000 004F_FFFF Reserved 1MB Reserved
0020_0000 003F_FFFF Reserved 2MB Reserved
0019_0000 001F_FFFF Reserved 448KB Reserved
0018_8000 0018_FFFF OCRAM_S 32KB Reserved (OCRAM_S)
0018_0000 0018_7FFF 32KB OCRAM_S
0011_0000 0017_FFFF Reserved 448KB Reserved
0010_8000 0010_FFFF CAAM 32KB Reserved (CAAM)
0010_0000 0010_7FFF 32KB CAAM (32K secure RAM)
0004_0000 000F_FFFF Reserved 768KB Reserved
0003_F000 0003_FFFF Boot ROM 4KB Boot ROM - Protected 4KB area
0000_0000 0003_EFFF 252KB Boot ROM

2.1.3 Cortex-M4 Memory Map

Start Address End Address Region Size Allocation

E010_0000 FFFF_FFFF Reserved 511MB Reserved
E000_0000 E00F_FFFF CM4 PPB 1MB CM4 PPB
D800_0000 DFFF_FFFF Reserved 128MB Reserved
D000_0000 D7FF_FFFF PCIe-1 128MB PCIe-1
C000_0000 CFFF_FFFF FLASH 256MB QSPI
4000_0000 BFFF_FFFF DDR Address 2048MB DDR Memory
3FC0_0000 3FFF_FFFF Reserved 4MB Reserved
3F80_0000 3FBF_FFFF Reserved 4MB Reserved
3F40_0000 3F7F_FFFF Reserved 4MB Reserved
3E00_0000 3F3F_FFFF Reserved 20MB Reserved
3DC0_0000 3DFF_FFFF DDRC 4MB Reserved
3D80_0000 3DBF_FFFF DDRC 4MB DDR PERF_MON
3D40_0000 3D7F_FFFF DDRC 4MB DDR CTL
3C00_0000 3D3F_FFFF DDRC 20MB DDR PHY
3890_0000 3BFF_FFFF Reserved 55MB Reserved
3880_0000 388F_FFFF GIC 1MB GIC
3870_0000 387F_FFFF Reserved 1MB Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

22 NXP Semiconductors
 Chapter 2 Memory Map

Start Address End Address Region Size Allocation

3850_0000 386F_FFFF Reserved 2MB Reserved
3830_0000 384F_FFFF VPU 2MB VPU
3820_0000 382F_FFFF Reserved 1MB Reserved
3810_0000 381F_FFFF Reserved 1MB Reserved
3801_0000 380F_FFFF Reserved 960KB Reserved
3800_0000 3800_FFFF GPU REG 64KB GPU REG
3600_0000 37FF_FFFF QSPI RX Buffers 32MB Reserved (QSPI2 RX Buffer)
3400_0000 35FF_FFFF 32MB QSPI1 RX Buffer
33C0_0000 33FF_FFFF PCIe REG 4MB Reserved
3380_0000 33BF_FFFF 4MB PCIe1 REG
3310_0000 337F_FFFF Reserved 7MB Reserved
3301_0000 330F_FFFF Reserved 960KB Reserved
3300_8000 3300_FFFF QSPI TX Buffers 32KB QSPI1 TX Buffer
3300_0000 3300_7FFF APBH DMA 32KB APBH DMA
32C0_0000 32FF_FFFF Periph (AIPS) 4MB AIPS4
3290_0000 32BF_FFFF Reserved 3MB Reserved
3280_0000 328F_FFFF GPV_8 1MB "HSIO" configuration
3270_0000 327F_FFFF GPV_7 1MB NoC configuration
3260_0000 326F_FFFF GPV_6 1MB "m4" configuration port
3250_0000 325F_FFFF GPV_5 1MB "display" configuration port
3240_0000 324F_FFFF GPV_4 1MB "enet" configuration port
3230_0000 323F_FFFF GPV_3 1MB "per_m" configuration port
3220_0000 322F_FFFF GPV_2 1MB "per_s" configuration port
3210_0000 321F_FFFF GPV_1 1MB "wakeup" configuration port
3200_0000 320F_FFFF GPV_0 1MB "main" configuration port
3100_0000 31FF_FFFF Reserved 16MB Reserved
30C0_0000 30FF_FFFF Pheriph (AIPS) 4MB Reserved
3080_0000 30BF_FFFF 4MB AIPS-3, See IP listing on separate map.
3040_0000 307F_FFFF 4MB AIPS-2, See IP listing on separate map.
3000_0000 303F_FFFF 4MB AIPS-1, See IP listing on separate map.
2900_0000 2FFF_FFFF Reserved 112MB Reserved
2800_0000 28FF_FFFF A53/ DAP 16MB A53/ DAP
2400_0000 27FF_FFFF Reserved 64MB Reserved
2200_0000 23FF_FFFF Reserved 32MB Reserved
2100_0000 21FF_FFFF Reserved 16MB Reserved
2040_0000 20FF_FFFF Reserved 12MB Reserved
2030_0000 203F_FFFF CM4 ALIAS SYSTEM 1MB Reserved (OCRAM)
2024_8000 202F_FFFF 736KB Reserved (OCRAM)
2024_0000 2024_7FFF 32KB Reserved (OCRAM)
2022_0000 2023_FFFF 128KB OCRAM_128KB
2020_0000 2021_FFFF 128KB OCRAM_128KB

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 23
Memory

Start Address End Address Region Size Allocation

2019_0000 201F_FFFF 448KB Reserved
2018_8000 2018_FFFF 32KB Reserved (OCRAM_S)
2018_0000 2018_7FFF 32KB OCRAM_S
2011_0000 2017_FFFF 448KB Reserved
2010_8000 2010_FFFF 32KB CAAM (Reserved)
2010_0000 2010_7FFF 32KB CAAM (32K secure RAM)
2006_0000 200F_FFFF Reserved 640KB Reserved
2002_0000 2005_FFFF Boot ROM 256KB Boot ROM (ROMCP)
2000_0000 2001_FFFF TCM 128KB TCMU
1FFE_0000 1FFF_FFFF 128KB TCML
1000_0000 1FFD_FFFF CM4 ALIAS CODE 262016KB DDR Code alias
0800_0000 0FFF_FFFF 128MB QSPI Code alias
0400_0000 07FF_FFFF 64MB Reserved
0100_0000 03FF_FFFF Reserved 48MB Reserved
00C0_0000 00FF_FFFF Reserved 4MB Reserved
00B0_0000 00BF_FFFF Reserved 1MB Reserved
00A0_0000 00AF_FFFF OCRAM 1MB Reserved (OCRAM)
0094_8000 009F_FFFF 736KB Reserved (OCRAM)
0094_0000 0094_7FFF 32KB Reserved (OCRAM)
0092_0000 0093_FFFF 128KB OCRAM_128KB
0090_0000 0091_FFFF 128KB OCRAM_128KB
0081_0000 008F_FFFF Reserved 960KB Reserved
0080_8000 0080_FFFF Reserved 32KB Reserved
0080_0000 0080_7FFF Reserved 32KB Reserved
007F_8000 007F_FFFF Reserved 32KB Reserved
007F_0000 007F_7FFF Reserved 32KB Reserved
0070_0000 007E_FFFF Reserved 960KB Reserved
0060_0000 006F_FFFF Reserved 1MB Reserved
0050_0000 005F_FFFF Reserved 1MB Reserved
0040_0000 004F_FFFF Reserved 1MB Reserved
0020_0000 003F_FFFF Reserved 2MB Reserved
0019_0000 001F_FFFF Reserved 448KB Reserved
0018_8000 0018_FFFF OCRAM_S 32KB Reserved (OCRAM_S)
0018_0000 0018_7FFF 32KB OCRAM_S
0011_0000 0017_FFFF Reserved 448KB Reserved
0010_8000 0010_FFFF CAAM 32KB Reserved (CAAM)
0010_0000 0010_7FFF 32KB CAAM (32K secure RAM)
0002_0000 000F_FFFF Reserved 896KB Reserved
0000_0000 0001_FFFF TCML 128KB TCML alias

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

24 NXP Semiconductors
 Chapter 2 Memory Map

2.1.4 DMA memory maps

The Smart DMA memory maps are defined in the following tables.
Table 2-1. SDMA1 Peripheral Memory Map
Address Peripheral
0xF000 SPBA
0xE000 Reserved for SDMA internal registers
0xD000 Reserved
0xC000 Reserved
0xB000 Reserved
0xA000 Reserved
0x9000 UART2
0x8000 UART3
0x7000 Reserved for SDMA internal registers
0x6000 UART1
0x5000 Reserved
0x4000 eCSPI3
0x3000 eCSPI2
0x2000 eCSPI1
0x1000 Reserved
0x0000 Reserved for SDMA internal memory

Table 2-2. SDMA2/3 Peripheral Memory Map

Address Peripheral
0xF000 SPBA
0xE000 Reserved for SDMA internal registers
0xD000 Reserved
0xC000 Reserved
0xB000 Reserved
0xA000 Reserved
0x9000 SPDIF1
0x8000 MICFIL
0x7000 Reserved for SDMA internal registers
0x6000 SAI6
0x5000 SAI5
0x4000 Reserved
0x3000 SAI3
0x2000 SAI2

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 25
Memory

Table 2-2. SDMA2/3 Peripheral Memory Map (continued)

Address Peripheral
0x1000 SAI1
0x0000 Reserved for SDMA internal memory

2.1.5 AIPS Memory Maps

Table 2-3. AIPS1 Memory Map
Start Address End Address Region NIC Port Size
303F_0000 303F_FFFF AIPS-1 (s_b_0) Reserved 64KB
303E_0000 303E_FFFF CSU 64KB
303D_0000 303D_FFFF RDC 64KB
303C_0000 303C_FFFF SEMAPHORE2 64KB
303B_0000 303B_FFFF SEMAPHORE1 64KB
303A_0000 303A_FFFF GPC 64KB
3039_0000 3039_FFFF SRC 64KB
3038_0000 3038_FFFF CCM 64KB
3037_0000 3037_FFFF SNVS_HP 64KB
3036_0000 3036_FFFF ANA_PLL 64KB
3035_0000 3035_FFFF OCOTP_CTRL 64KB
3034_0000 3034_FFFF IOMUXC_GPR 64KB
3033_0000 3033_FFFF IOMUXC 64KB
3032_0000 3032_FFFF Reserved 64KB
3031_0000 3031_FFFF ROMCP 64KB
3030_0000 3030_FFFF Reserved 64KB
302F_0000 302F_FFFF GPT3 64KB
302E_0000 302E_FFFF GPT2 64KB
302D_0000 302D_FFFF GPT1 64KB
302C_0000 302C_FFFF SDMA2 64KB
302B_0000 302B_FFFF SDMA3 64KB
302A_0000 302A_FFFF WDOG3 64KB
3029_0000 3029_FFFF WDOG2 64KB
3028_0000 3028_FFFF WDOG1 64KB
3027_0000 3027_FFFF ANA_OSC 64KB
3026_0000 3026_FFFF TMU (ANA_TSENSOR) 64KB
3025_0000 3025_FFFF Reserved 64KB
3024_0000 3024_FFFF GPIO5 64KB
3023_0000 3023_FFFF GPIO4 64KB

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

26 NXP Semiconductors
 Chapter 2 Memory Map

Table 2-3. AIPS1 Memory Map (continued)

Start Address End Address Region NIC Port Size
3022_0000 3022_FFFF GPIO3 64KB
3021_0000 3021_FFFF GPIO2 64KB
3020_0000 3020_FFFF GPIO1 64KB
301F_0000 301F_FFFF AIPS1_Configuration 64KB
3014_0000 301E_FFFF AIPS-1 Glob. Module Reserved 704KB
Enable
3010_0000 3013_FFFF Reserved 256KB
300F_0000 300F_FFFF AIPS-1 (s_b_1, via SPBA2 64KB
SPBA) Glob. Module
300E_0000 300E_FFFF Reserved for SDMA2 64KB
Enable internal memory
300D_0000 300D_FFFF Reserved 64KB
300C_0000 300C_FFFF Reserved 64KB
300B_0000 300B_FFFF Reserved 64KB
300A_0000 300A_FFFF SPDIF2 64KB
3009_0000 3009_FFFF SPDIF1 64KB
3008_0000 3008_FFFF MICFIL 64KB
3007_0000 3007_FFFF Reserved for SDMA2 64KB
internal memory
3006_0000 3006_FFFF SAI6 64KB
3005_0000 3005_FFFF SAI5 64KB
3004_0000 3004_FFFF Reserved 64KB
3003_0000 3003_FFFF SAI3 64KB
3002_0000 3002_FFFF SAI2 64KB
3001_0000 3001_FFFF SAI1 64KB
3000_0000 3000_FFFF Reserved for SDMA2 64KB
internal memory

Table 2-4. AIPS2 Memory Map

Start Address End Address Region NIC Port Size
307F_0000 307F_FFFF AIPS-2 (s_b_1) QoSC 64KB
307E_0000 307E_FFFF Reserved 64KB
307D_0000 307D_FFFF PERFMON2 64KB
307C_0000 307C_FFFF PERFMON1 64KB
307B_0000 307B_FFFF Reserved 64KB
307A_0000 307A_FFFF Reserved 64KB
3079_0000 3079_FFFF Reserved 64KB
3078_0000 3078_FFFF Reserved 64KB
3077_0000 3077_FFFF Reserved 64KB
3076_0000 3076_FFFF Reserved 64KB

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 27
Memory

Table 2-4. AIPS2 Memory Map (continued)

Start Address End Address Region NIC Port Size
3075_0000 3075_FFFF Reserved 64KB
3074_0000 3074_FFFF Reserved 64KB
3073_0000 3073_FFFF Reserved 64KB
3072_0000 3072_FFFF Reserved 64KB
3071_0000 3071_FFFF Reserved 64KB
3070_0000 3070_FFFF GPT4 64KB
306F_0000 306F_FFFF GPT5 64KB
306E_0000 306E_FFFF GPT6 64KB
306D_0000 306D_FFFF Reserved 64KB
306C_0000 306C_FFFF System_Counter_CTRL 64KB
306B_0000 306B_FFFF System_Counter_CMP 64KB
306A_0000 306A_FFFF System_Counter_RD 64KB
3069_0000 3069_FFFF PWM4 64KB
3068_0000 3068_FFFF PWM3 64KB
3067_0000 3067_FFFF PWM2 64KB
3066_0000 3066_FFFF PWM1 64KB
3065_0000 3065_FFFF Reserved 64KB
3064_0000 3064_FFFF Reserved 64KB
3063_0000 3063_FFFF Reserved 64KB
3062_0000 3062_FFFF Reserved 64KB
3061_0000 3061_FFFF Reserved 64KB
3060_0000 3060_FFFF Reserved 64KB
305F_0000 305F_FFFF AIPS2_configuration 64KB
3050_0000 305E_FFFF AIPS-2 Glob. Module Reserved 960KB
Enable
3040_0000 304F_FFFF Reserved 1024K
B

Table 2-5. AIPS3 Memory Map

Start Address End Address Region NIC Port Size
30BF_0000 30BF_FFFF AIPS-3 (s_b_2) Reserved 64KB
30BE_0000 30BE_FFFF ENET1 64KB
30BD_0000 30BD_FFFF SDMA1 64KB
30BC_0000 30BC_FFFF Reserved 64KB
30BB_0000 30BB_FFFF QSPI 64KB
30BA_0000 30BA_FFFF Reserved 64KB
30B9_0000 30B9_FFFF Reserved 64KB
30B8_0000 30B8_FFFF Reserved 64KB
30B7_0000 30B7_FFFF Reserved 64KB
30B6_0000 30B6_FFFF uSDHC3 64KB

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

28 NXP Semiconductors
 Chapter 2 Memory Map

Table 2-5. AIPS3 Memory Map (continued)

Start Address End Address Region NIC Port Size
30B5_0000 30B5_FFFF uSDHC2 64KB
30B4_0000 30B4_FFFF uSDHC1 64KB
30B3_0000 30B3_FFFF Reserved 64KB
30B2_0000 30B2_FFFF Reserved 64KB
30B1_0000 30B1_FFFF Reserved 64KB
30B0_0000 30B0_FFFF Reserved 64KB
30AF_0000 30AF_FFFF Reserved 64KB
30AE_0000 30AE_FFFF Reserved 64KB
30AD_0000 30AD_FFFF Reserved 64KB
30AC_0000 30AC_FFFF SEMAPHORE_HS 64KB
30AB_0000 30AB_FFFF MU_B 64KB
30AA_0000 30AA_FFFF MU_A 64KB
30A9_0000 30A9_FFFF Reserved 64KB
30A8_0000 30A8_FFFF Reserved 64KB
30A7_0000 30A7_FFFF Reserved 64KB
30A6_0000 30A6_FFFF UART4 64KB
30A5_0000 30A5_FFFF I2C4 64KB
30A4_0000 30A4_FFFF I2C3 64KB
30A3_0000 30A3_FFFF I2C2 64KB
30A2_0000 30A2_FFFF I2C1 64KB
30A1_0000 30A1_FFFF Reserved 64KB
30A0_0000 30A0_FFFF Reserved 64KB
309F_0000 309F_FFFF AIPS3_Configuration 64KB
3094_0000 309E_FFFF AIPS-3 Glob. Module Reserved 704KB
Enable
3090_0000 3093_FFFF CAAM 256KB
308F_0000 308F_FFFF AIPS-3 (s_b_2, via SPBA1 64KB
SPBA) Glob. Module
308E_0000 308E_FFFF Reserved for SDMA 64KB
Enable internal registers
308D_0000 308D_FFFF Reserved 64KB
308C_0000 308C_FFFF Reserved 64KB
308B_0000 308B_FFFF Reserved 64KB
308A_0000 308A_FFFF Reserved 64KB
3089_0000 3089_FFFF UART2 64KB
3088_0000 3088_FFFF UART3 64KB
3087_0000 3087_FFFF Reserved for SDMA 64KB
internal registers
3086_0000 3086_FFFF UART1 64KB
3085_0000 3085_FFFF Reserved 64KB
3084_0000 3084_FFFF eCSPI3 64KB
3083_0000 3083_FFFF eCSPI2 64KB

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 29
Memory

Table 2-5. AIPS3 Memory Map (continued)

Start Address End Address Region NIC Port Size
3082_0000 3082_FFFF eCSPI1 64KB
3081_0000 3081_FFFF Reserved 64KB
3080_0000 3080_FFFF Reserved for SDMA 64KB
internal memory

Table 2-6. AIPS4 Memory Map

Start Address End Address Region NIC Port Size
32FF_0000 32FF_FFFF AIPS-4 (s_h_10) Reserved 64KB
32FE_0000 32FE_FFFF PLATFORM_CTRL 64KB
32FD_0000 32FD_FFFF Reserved 64KB
32FC_0000 32FC_FFFF Reserved 64KB
32FB_0000 32FB_FFFF Reserved 64KB
32FA_0000 32FA_FFFF Reserved 64KB
32F9_0000 32F9_FFFF Reserved 64KB
32F8_0000 32F8_FFFF TZASC 64KB
32F7_0000 32F7_FFFF Reserved 64KB
32F6_0000 32F6_FFFF Reserved 64KB
32F5_0000 32F5_FFFF Reserved 64KB
32F4_0000 32F4_FFFF Reserved 64KB
32F3_0000 32F3_FFFF Reserved 64KB
32F2_0000 32F2_FFFF Reserved 64KB
32F1_0000 32F1_FFFF Reserved 64KB
32F0_0000 32F0_FFFF PCIE_PHY1 64KB
32EF_0000 32EF_FFFF Reserved 64KB
32EE_0000 32EE_FFFF Reserved 64KB
32ED_0000 32ED_FFFF Reserved 64KB
32EC_0000 32EC_FFFF Reserved 64KB
32EB_0000 32EB_FFFF Reserved 64KB
32EA_0000 32EA_FFFF Reserved 64KB
32E9_0000 32E9_FFFF Reserved 64KB
32E8_0000 32E8_FFFF Reserved 64KB
32E7_0000 32E7_FFFF Reserved 64KB
32E6_0000 32E6_FFFF Reserved 64KB
32E5_0000 32E5_FFFF USB2 64KB
32E4_0000 32E4_FFFF USB1 64KB
32E3_0000 32E3_FFFF MIPI_CSI 64KB
32E2_0000 32E2_FFFF CSI 64KB
32E1_0000 32E1_FFFF MIPI_DSI 64KB
32E0_0000 32E0_FFFF LCDIF 64KB

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

30 NXP Semiconductors
 Chapter 2 Memory Map

Table 2-6. AIPS4 Memory Map (continued)

Start Address End Address Region NIC Port Size
32DF_0000 32DF_FFFF AIPS4_configuration 64KB
32D0_0000 32DE_FFFF AIPS-4 Glob. Module Reserved 960KB
Enable
32C0_0000 32CF_FFFF Reserved 1024KB

2.1.6 DAP Memory Map

Table 2-7. DAP Memory Map Table
Start Address End Address Size Allocation
28C0_A000 28FF_FFFF 4056KB Reserved
28C0_9000 28C0_9FFF 4KB HUGO_CXCTI1
28C0_8000 28C0_8FFF 4KB HUGO_CXCTI0
28C0_7000 28C0_7FFF 4KB CXTPIU
28C0_6000 28C0_6FFF 4KB CXTMC_ETR
28C0_5000 28C0_5FFF 4KB ATB_REPLICATOR
28C0_4000 28C0_4FFF 4KB CXTMC_ETB
28C0_3000 28C0_3FFF 4KB HUGO_ATB_FUNNEL
28C0_2000 28C0_2FFF 4KB CXTSGEN_READ
28C0_1000 28C0_1FFF 4KB CXTSGEN_CTRL
28C0_0000 28C0_0FFF 4KB HUGO ROM Table
28B5_0000 28BF_FFFF 704KB Reserved
28B4_0000 28B4_FFFF 64KB Reserved
28B3_0000 28B3_FFFF 64KB Reserved
28B2_0000 28B2_FFFF 64KB Reserved
28B1_0000 28B1_FFFF 64KB Reserved
28A5_0000 28B0_FFFF 768KB Reserved
28A4_0000 28A4_FFFF 64KB Reserved
28A3_0000 28A3_FFFF 64KB Reserved
28A2_0000 28A2_FFFF 64KB Reserved
28A1_0000 28A1_FFFF 64KB Reserved
2895_0000 28A0_FFFF 768KB Reserved
2894_0000 2894_FFFF 64KB Reserved
2893_0000 2893_FFFF 64KB Reserved
2892_0000 2892_FFFF 64KB Reserved
2891_0000 2891_FFFF 64KB Reserved
2885_0000 2890_FFFF 768KB Reserved
2884_0000 2884_FFFF 64KB Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 31
Memory

Table 2-7. DAP Memory Map Table (continued)

Start Address End Address Size Allocation
2883_0000 2883_FFFF 64KB Reserved
2882_0000 2882_FFFF 64KB Reserved
2881_0000 2881_FFFF 64KB Reserved
2880_0000 2880_FFFF 64KB Reserved
2875_0000 287F_FFFF 704KB Reserved
2874_0000 2874_FFFF 64KB MP4-CPU3 Trace
2873_0000 2873_FFFF 64KB MP4-CPU3 PMU
2872_0000 2872_FFFF 64KB MP4-CPU3 CTI
2871_0000 2871_FFFF 64KB MP4-CPU3 Debug
2865_0000 2870_FFFF 768KB Reserved
2864_0000 2864_FFFF 64KB MP4-CPU2 Trace
2863_0000 2863_FFFF 64KB MP4-CPU2 PMU
2862_0000 2862_FFFF 64KB MP4-CPU2 CTI
2861_0000 2861_FFFF 64KB MP4-CPU2 Debug
2855_0000 2860_FFFF 768KB Reserved
2854_0000 2854_FFFF 64KB MP4-CPU1 Trace
2853_0000 2853_FFFF 64KB MP4-CPU1 PMU
2852_0000 2852_FFFF 64KB MP4-CPU1 CTI
2851_0000 2851_FFFF 64KB MP4-CPU1 Debug
2845_0000 2850_FFFF 768KB Reserved
2844_0000 2844_FFFF 64KB MP4-CPU0 Trace
2843_0000 2843_FFFF 64KB MP4-CPU0 PMU
2842_0000 2842_FFFF 64KB MP4-CPU0 CTI
2841_0000 2841_FFFF 64KB MP4-CPU0 Debug
2840_0000 2840_FFFF 64KB MP4 ROM Table
2801_0000 283F_FFFF 4032KB Reserved
2800_0000 2800_FFFF 64KB DAP ROM Table

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

32 NXP Semiconductors
Chapter 3
Security

3.1 System Security

3.1.1 Overview
The security system modules are described in the sections below.

3.1.2 Central Security Unit (CSU)

The chip uses the CSU to manage security for all masters/slaves that don’t directly
support security like the CPU core.

3.1.3 Cryptographic Acceleration and Assurance Module (CAAM)

CAAM is the chip's cryptographic acceleration and assurance module, which serves as
NXP's latest cryptographic acceleration and offloading hardware. It combines functions
previously implemented in separate modules to create a modular and scalable
acceleration and assurance engine. It also implements block encryption algorithms,
stream cipher algorithms, hashing algorithms, public key algorithms, run-time integrity
checking, a secure memory controller, and a hardware random number generator.
CAAM supports the following key features:
• PKHA block to support Public Key Cryptography with RSA 4096 and ECC
algorithms
• 3 Job Rings
• RTIC (real time integrity checking)
• AES, DES, 3DES support
• Widevine cipher text stealing (AES-CBC-CTS mode)
• PlayReady content protection

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 33
System Security

In order to provide better video content protection, CAAM also supports the domain
based resource protection.

3.1.4 Secure Non-Volatile Storage (SNVS)

Secure Non-Volatile Storage (SNVS) is a companion logic block to the Cryptographic
Acceleration and Assurance Module (CAAM). This block is the chip's central reporting
point for security-relevant events, such as the success or failure of boot software
validation and the detection of potential security compromises. This security event
information allows the SNVS to determine whether the chip is in a trustworthy state.

3.1.5 On-Chip OTP Controller (OCOTP_CTRL)

The OCOPT_CTRL is used to control the 8K bit OTP fuse in the chip. It supports:
• Load fuse into shadow registers after power-on reset;
• Register interface to allow SW to read, override or program the fuse
• Flexible permission control to the fuse, including read-protect, override-protect,
program-protect, lock and etc
• Programming sequence to allow single bit to be programmed individually, and also
allow the non-programmed bit to be programmed later
For the 8K bits fuse, following bits are reserved for various IP requirements:
• Fuse control to disable each of the four Cortex A53 cores.
• Fuse control to disable individual IP modules such as MIPI, ENET, USB, PCIe and
etc.
• Fuse for ROM patch, with a dedicated fuse lock bit for security purpose.

3.1.6 TrustZone
TrustZone security architecture is supported in the chip. For on-chip RAM, both
OCRAM/OCRAM_S have TrustZone access control support through its TZ wrapper
logic. One region with configurable address range of the OCRAM/OCRAM_S can be set
to TZ access only. DRAM has a dedicated TZASC block that can support up to 16
configurable memory regions.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

34 NXP Semiconductors
 Chapter 3 Security

3.1.7 Resource Domain Controller (RDC)

The chip uses domain based resource control architecture for the memory/peripheral
resource sharing and isolation between the Quad-core Cortex A53 platform, Cortex M4
core, and other bus masters. RDC supports flexible configuration on IP’s access
permission, each individual IP can, for example, be configured as A-core only or M-core
only. RDC also supports multiple regions with flexible access permission control for each
memory space. The memory region access control is defined in the table below. The
security and exclusive support for DRAM will be done by the TZASC and the DRAM
controller itself.
NOTE
The RDC and TrustZone features are completely independent
of each other but will be used together.

Table 3-1. Memory Region Access Control

Memory Space Regions Supported Granularity Security Support Exclusive Support
DRAM 8 regions 4K Bytes
QSPI1 8 regions 4K Bytes
PCIe1 8 regions 4K Bytes
OCRAM 5 regions 128 Bytes
OCRAM_S 5 regions 128 Bytes
TCM 5 regions 128 Bytes
GIC 4 regions 4K Bytes
GPU 8 regions 4K Bytes
VPU 4 regions 4K Bytes
DEBUG(DAP) 4 regions 4K Bytes
DDRC (REG ) 5 regions 4K Bytes

3.2 Resource Domain Controller (RDC)

3.2.1 Overview
The Resource Domain Controller (RDC) provides robust support for the isolation of
destination memory mapped locations such as peripherals and memory to a single core, a
bus master, or set of cores and bus masters.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 35
Resource Domain Controller (RDC)

3.2.1.1 Block Diagram

Many of today's processors have multiple cores for increased performance and flexibility.
In some cases, the cores serve different functions (e.g. user level applications versus real
time machine control) and in such cases the software for each core may be developed by
different providers.

Figure 3-1. Dedicated and Shared Peripherals

For efficiency reasons the code on the cores may share chip resources such as peripherals
and memory. The sharing of chip resources between the somewhat independent
processing domains allows for the opportunity of data collisions where information
stored in peripherals or memory by a process on one core is overwritten by software
running on another core. Without careful collaboration between the two operating
systems inadvertent malfunction or degradation in performance may result.
The RDC provides a mechanism to allow boot time configuration code to establish
resource domains by assigning cores, bus masters, peripherals and memory regions to
domain identifiers. Once configured, bus transactions are monitored to restrict accesses
initiated by cores and bus masters to their respective peripherals and memory.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

36 NXP Semiconductors
 Chapter 3 Security

For shared peripherals, the RDC provides a semaphore-based locking mechanism to

provide for temporary exclusivity while the domain software uses the peripheral. Once
the software of one domain has finished the task and finished with the peripheral then it
may release the semaphore making the peripheral available to the other domain.

3.2.1.2 Features
Resource domain subsystem has the following features:
• Assignment of cores, bus masters, peripherals, and memory regions to a resource
domain
• Fixed memory resolution of 128 Bytes for small address spaces and 4 KB for large
address spaces
• Four resource domain identifiers (DIDs)
• Memory read/write access controls for each resource domain and region
• Optional semaphore-based, hardware-enforced exclusive access of shared peripherals
to a resource domain
• Prioritized access permissions for overlapping memory regions
• Automatic restoration of resource domain access permissions to memory regions in
the power-down domain

3.2.2 Functional Description

The RDC is the central location for creation of isolated resource domains and for the
enablement of semaphore-based access also known as “safe sharing”. Configuration
software assigns one of resource domain identifiers to each core and bus master, and
allocates each memory region and peripheral to one or more resource domains.
Memory Read or Write access privileges for each resource domain are declared for each
memory region. In addition, the software configuration determines which shared
peripherals (those peripherals allocated to more than one domain) require safe sharing by
setting the semaphore-required configuration for each peripheral.
The RDC configuration information is sent to the fabric ports, memories gaskets,
semaphore controller, and peripherals to control access based on domain assignments.
The fabric uses the domain identifier associated with each port to include this information
along with the bus transaction. When the slave gasket encounters a bus transaction, it
makes a comparison of the transaction domain ID to the RDC-provided list of allowed
domains. If the transaction domain ID is on the list, then access may be permitted.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 37
Resource Domain Controller (RDC)

DEXSC OCRAM

D0 Core

main
fabric TZASC DDRC
DEXSC

switch
D1 Core fabric

SPBA Periph

DSEC AHB Slave

switch CAAM
DEXSC Secure RAM
fabric

D0 Periph

D1 Periph

SEMA42
AIPS-TZ (Shared)

Allowed Gate
Domains Locks

RDC
(D0 TZ
Locked)
Peripheral Permissions

Memory Region Bounds

Master to Domain Assignment

Figure 3-2. Example RDC Connections

For shared peripherals, RDC permits more than one domain access to a single peripheral.
RDC also provides three ways to control synchronized use of shared peripherals. These
methods include hardware-enforced synchronization, software-based semaphores, or no
synchronization. The latter may be suitable for well-tuned multi-core operating systems
that handle synchronization in the core platform, for instance.
For hardware-enforced synchronization, also known as "safe sharing", ownership of the
peripheral must be claimed in the semaphore controller before access is allowed to the
shared peripheral. Each shared peripheral has a corresponding Peripheral Domain Access
Permissions (PDAP) register. When the Semaphore Required (SREQ) bit in a PDAP
register is set, a master cannot access this shared peripheral until obtaining a semaphore.
During the time that the domain has the semaphore in possession, its bus masters have
exclusive access to the peripheral.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

38 NXP Semiconductors
 Chapter 3 Security

When the semaphore is released, then no domain masters have access until the semaphore
is obtained again. When the SREQ bit is set, RDC module does not allow masters to
obtain semaphores of peripherals to which the domain is not allocated; the master must
have designated access in the D-bits of the corresponding PDAP register (e.g. D1R bit set
for Domain 1 access of the shared peripheral). There is a one-to-one mapping between
the semaphore controller gate and the resource domain controller peripheral. The
mapping of PDAP registers and peripherals can be found in the Peripheral Map section of
the RDC chapter.

3.2.2.1 Domain ID
The RDC provides for an isolation of domain resources by use of an identifier called the
Domain ID (DID). A core and its resources including memory, bus masters, and
peripherals are all associated with a single DID. When software or a DMA attempts to
access a peripheral or memory, the corresponding bus transaction includes the DID along
with the other bus control information such as Read, Write, and privilege mode.

3.2.2.2 Resource Assignment

The RDC allows assignment of peripherals and memories to one or more domains while
each bus master or core is placed in one of several domains. The masters are assigned a
domain in the Master Domain Assignment (MDA) register. A peripheral is given R/W
access permissions to each domain in the PDAP register. Memory regions are bound by
address space in start and end registers, i.e. MRSA and MREA. Each memory region is
assigned one or more allowed domains and R/W permissions in the Memory Region
Control (MRC) register. Memory regions must be enabled before the permissions are
active. Otherwise the permissions are not restricted.
The RDC itself should be isolated to ensure that only a trustworthy resource manager can
configure the RDC registers. This process may either be present initially during secure
boot, or during the runtime in the secure world, for example. If the operating system does
not support a runtime trusted execution, then during the secure boot process the RDC
configuration can be locked to prevent further modification after the operating systems
are running.
NOTE
The CCM supports multi-core awareness based on resource
domain assignments programmed into the RDC. Refer to the
CCM chapter regarding the relationship between core resource
domains and their respective CCM resources. Failing to follow
the proper sequence when updating the resource domain
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 39
Resource Domain Controller (RDC)

assignments of the core can result in clocks being inadvertently

gated.

3.2.2.3 Safe Sharing

For shared peripherals, the RDC can be configured to require a domain to obtain a
semaphore lock before access to the peripheral is allowed. This feature helps prevent
collisions from processes on separate cores that may want to use the same peripheral at
the same time. The RDC sends a list of eligible domains to the semaphore module for
each gate/peripheral. The eligible domains are those that are set in the peripheral domain
access permissions (PDAP) registers. There is a one-to-one correspondence between
semaphore gates and peripherals so each gate in the semaphore block represents a
peripheral. The RDC receives semaphore locks from the hardware semaphore module
(SEMA42). A semaphore lock is acquired when a core or bus master from a given
domain requests a lock for a particular gate. The semaphore module compares the
request's domain ID against the list of eligible domain IDs. If the domain ID is on the list
and the lock is available then the lock is set and a signal is sent back to the RDC module
indicating a lock has been acquired for a particular gate and a domain ID the lock belongs
to. The RDC then restricts access to the corresponding peripheral to only transactions
originating from the domain that has the lock. Another domain, though on the shared list
to access the peripheral, must then wait until the lock is released before acquiring the lock
and gaining access to the peripheral. To enable this feature of hardware enforcement for
the semaphore locks, the SREQ bit is set in the RDC resource register.
If the SREQ is set, then when a process determines it needs a shared peripheral, it must
first lock the resource in the semaphore module. Once the resource is locked, the
semaphore module sends a signal to the RDC indicating the domain has access to the
resource. The RDC will then set the access permissions to allow that domain access to the
peripheral.
For a domain to acquire a lock on a peripheral, the domain must have been assigned to
the peripheral in the RDC Peripheral Domain Access Permissions register (PDAP). The
semaphore module only allows safe-sharing locks for those domains that are assigned to
the peripheral. The semaphore module does not consider the access type (Read or Write)
when allowing domains to acquire locks.
The SEMA42 module implements hardware-enforced semaphores as an IPS-mapped
slave peripheral device. The feature set includes:
• Module definition supporting 64 hardware-enforced gates in a multi-processor
configuration, where up to 15 processors can be supported; cpX is meant to represent
core processor X

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

40 NXP Semiconductors
 Chapter 3 Security

• Gates appear as an n-entry byte-size array with read and write accesses (n = 64).
• Processors lock gates by writing "Master_index" to the appropriate gate and
must read back the gate value to verify the lock operation was successful.
The Master_index value for the processors can be found in the Master Index
Allocation table, which can be found in the AIPSTZ block. Also note that
after locking, the gate register contains the master_id value of the locking
processor (in the field GTFSM ), and also the value of the locking domain
(in the field LDOM ).
• Once locked, the gate is unlocked by a write of zeroes from the locking
processor.
• The number of implemented gates is specified by a hardware configuration
define.
• Each hardware gate appears as a 16-state, 4-bit state machine.
• 16-state implementation
if gate = 0x0, then state = unlocked
if gate = 0x1, then state = locked by processor (master_index) 0
if gate = 0x2, then state = locked by processor (master_index) 1
…
if gate = 0xF, then state = locked by processor (master_index) 14
• Uses the logical bus master number (master_index) as a reference attribute
plus the specified data patterns to validate all write operations.
• Once locked, the gate can (and must) be unlocked by a write of zeroes from
the locking processor.
• Secure reset mechanisms are supported to clear the contents of individual gates,
as well as a clear_all capability.
• Memory-mapped IPS slave peripheral platform module
• Interface to the IPS bus for programming-model accesses

3.2.2.4 Resource Domain Control and Security Considerations

Conceptually, the RDC configuration is independent of the processor privilege mode and
security domain. It is intended to allow for isolation between core processing
environments to prevent collisions and increase reliability. Access between resource
domains is mutually exclusive and each domain should be in control of its own privilege
modes and access rights.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 41
Resource Domain Controller (RDC)

However, it is important to realize multi-core processors may have a multiple resource

domains but only one overarching security domain. Chip security controls reside in one
resource domain. In this configuration, a domain can affect at least one level of access
privileges in the other domain. This may be acceptable but clarity and care is needed to
ensure expected functionality.

Figure 3-3. Access Control to Memory

Therefore, access to the security controls should be restricted to the most trustworthy
operating mode of the core and privilege levels should be coordinated to ensure that
shared peripherals and memory regions are accessible by both cores. For instance, if a
memory region is designated for secure accesses then all domain masters that share that
region must have secure privileges.

3.2.2.5 Modes of Operation

The RDC provides access controls to the resource domain subsystem. When the device is
in a low power mode then some memory regions in the subsystem may be powered off.
RDC responds to the impacted memory regions by automatically reconfiguring the
memory regions once power returns and blocking access to those memory regions until
the reconfiguration process is complete.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

42 NXP Semiconductors
 Chapter 3 Security

3.2.2.5.1 Low Power Modes

The RDC loads configuration information for memory regions (MRSA, MRSE, MRC)
into access control mechanisms (gaskets) at the memory interface. The location of this
configuration information may reside inside power domains that lose power during sleep
modes for energy savings. To restore configuration information upon return from sleep
mode, the RDC receives a global power control signal indicating power is restored. The
RDC then automatically reconfigures the memory regions with the configuration
information.
During reconfiguration, access is blocked to the previously powered down memories.
When the RDC completes reconfiguration it issues an interrupt and allows access to the
memory regions. Only the powered down regions are blocked during the reconfiguration.
Memory regions in the "always-on" power domain (still powered during sleep mode)
remain available according to the programmed access rights. If no memory regions were
enabled then the powered down regions are available immediately when power is
restored.
The figure below shows the Global Power Control signal which RDC uses to invalidate
the configuration upon deassertion and to restore the configuration when re-asserted. The
configuration is valid and bus transactions allowed once the memory regions have been
restored.

Higher Power
Memory ON
Global Power
RDC
Control

Configuration Memory Region

Invalid Restoration Interface

System Bus
Memory Regions

Higher Power
Memory

Figure 3-4. Memory Restoration Signaling

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 43
Resource Domain Controller (RDC)

3.2.3 External Signals

RDC has no external signals pinned out.

3.2.4 Programming Interface

This section provides product specific details describing the mapping of resources -
peripherals, bus masters, and memory regions - to corresponding resource domain
controls RDC registers.
The RDC and RDC_SEMA42 register maps are combined in this chapter. The base
address for the one RDC map and two SEMA42 maps are each separated by 4KB. While
there are two SEMA42 submodules and therefore two sets of SEMA42 registers, this
chapter describes one. Please refer to the peripheral memory map for the base addresses
of the RDC and SEMA42 modules.

3.2.4.1 Master Assignment Registers

Table 3-2. Master Assignment Mapping

Master RDC MDA Register
Quad A53 RDC_MDA0
M4 RDC_MDA1
PCIE_CTRL1 RDC_MDA2
SDMA3 (p) RDC_MDA3
VPU Decoders RDC_MDA4
LCDIF RDC_MDA5
CSI-1 RDC_MDA6
SDMA3 (b) RDC_MDA7
Coresight RDC_MDA8
DAP RDC_MDA9
CAAM RDC_MDA10
SDMA1 (p) RDC_MDA11
SDMA1 (b) RDC_MDA12
APBHDMA RDC_MDA13
NAND RDC_MDA14
uSDHC1 RDC_MDA15
uSDHC2 RDC_MDA16

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

44 NXP Semiconductors
 Chapter 3 Security

Table 3-2. Master Assignment Mapping (continued)

Master RDC MDA Register
uSDHC3 RDC_MDA17
GPU RDC_MDA18
USB1 RDC_MDA19
USB2 RDC_MDA20
TESTPORT RDC_MDA21
ENET1_TX RDC_MDA22
ENET1_RX RDC_MDA23
SDMA2 (p) RDC_MDA24
SDMA2 (b) RDC_MDA24
SDMA2 to SPBA2 RDC_MDA24
SDMA3 to SPBA2 RDC_MDA25
SDMA1 to SPBA1 RDC_MDA26

3.2.4.2 Peripheral Mapping

Each peripheral has a corresponding resource domain assignment register in the RDC and
semaphore lock register in the RDC_SEMA42 module. The following table shows
allocation of the RDC_PDAP and RDC_SEMAPHOREx_GATE registers for peripheral
resource domain assignment.
NOTE
Access control of the RDC registers can be programmed using
the respective PDAP register. The default setting of the PDAP
register for the RDC allows access from all domains. Use
caution when restricting access of the RDC registers to avoid
conditions where access to the RDC registers is needed but no
master is assigned to a domain with access rights to the RDC.

Table 3-3. RDC Peripheral Mapping

Peripheral RDC PDAP register RDC_SEMA42 block/gate register
GPIO1 RDC_PDAP00 SEMA42 B1 / G0
GPIO2 RDC_PDAP01 SEMA42 B1 / G1
GPIO3 RDC_PDAP02 SEMA42 B1 / G2
GPIO4 RDC_PDAP03 SEMA42 B1 / G3
GPIO5 RDC_PDAP04 SEMA42 B1 / G4
Reserved RDC_PDAP05 SEMA42 B1 / G5

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 45
Resource Domain Controller (RDC)

Table 3-3. RDC Peripheral Mapping (continued)

Peripheral RDC PDAP register RDC_SEMA42 block/gate register
ANA_TSENSOR RDC_PDAP06 SEMA42 B1 / G6
ANA_OSC RDC_PDAP07 SEMA42 B1 / G7
WDOG1 RDC_PDAP08 SEMA42 B1 / G8
WDOG2 RDC_PDAP09 SEMA42 B1 / G9
WDOG3 RDC_PDAP10 SEMA42 B1 / G10
SDMA3 RDC_PDAP11 SEMA42 B1 / G11
SDMA2 RDC_PDAP12 SEMA42 B1 / G12
GPT1 RDC_PDAP13 SEMA42 B1 / G13
GPT2 RDC_PDAP14 SEMA42 B1 / G14
GPT3 RDC_PDAP15 SEMA42 B1 / G15
Reserved RDC_PDAP16 SEMA42 B1 / G16
ROMCP RDC_PDAP17 SEMA42 B1 / G17
Reserved RDC_PDAP18 SEMA42 B1 / G18
IOMUXC RDC_PDAP19 SEMA42 B1 / G19
IOMUXC_GPR RDC_PDAP20 SEMA42 B1 / G20
OCOTP_CTRL RDC_PDAP21 SEMA42 B1 / G21
ANA_PLL RDC_PDAP22 SEMA42 B1 / G22
SNVS_HP RDC_PDAP23 SEMA42 B1 / G23
CCM RDC_PDAP24 SEMA42 B1 / G24
SRC RDC_PDAP25 SEMA42 B1 / G25
GPC RDC_PDAP26 SEMA42 B1 / G26
SEMAPHORE1 RDC_PDAP27 SEMA42 B1 / G27
SEMAPHORE2 RDC_PDAP28 SEMA42 B1 / G28
RDC RDC_PDAP29 SEMA42 B1 / G29
CSU RDC_PDAP30 SEMA42 B1 / G30
Reserved RDC_PDAP31 SEMA42 B1 / G31
LCDIF RDC_PDAP32 SEMA42 B1 / G32
MIPI_DSI RDC_PDAP33 SEMA42 B1 / G33
CSI RDC_PDAP34 SEMA42 B1 / G34
MIPI_CSI RDC_PDAP35 SEMA42 B1 / G35
USB1 RDC_PDAP36 SEMA42 B1 / G36
Reserved RDC_PDAP37 SEMA42 B1 / G37
PWM1 RDC_PDAP38 SEMA42 B1 / G38
PWM2 RDC_PDAP39 SEMA42 B1 / G39
PWM3 RDC_PDAP40 SEMA42 B1 / G40
PWM4 RDC_PDAP41 SEMA42 B1 / G41
System_Counter_RD RDC_PDAP42 SEMA42 B1 / G42
System_Counter_CMP RDC_PDAP43 SEMA42 B1 / G43
System_Counter_CTRL RDC_PDAP44 SEMA42 B1 / G44

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

46 NXP Semiconductors
 Chapter 3 Security

Table 3-3. RDC Peripheral Mapping (continued)

Peripheral RDC PDAP register RDC_SEMA42 block/gate register
Reserved RDC_PDAP45 SEMA42 B1 / G45
GPT6 RDC_PDAP46 SEMA42 B1 / G46
GPT5 RDC_PDAP47 SEMA42 B1 / G47
GPT4 RDC_PDAP48 SEMA42 B1 / G48
Reserved RDC_PDAP49 SEMA42 B1 / G49
Reserved RDC_PDAP50 SEMA42 B1 / G50
Reserved RDC_PDAP51 SEMA42 B1 / G51
Reserved RDC_PDAP52 SEMA42 B1 / G52
Reserved RDC_PDAP53 SEMA42 B1 / G53
Reserved RDC_PDAP54 SEMA42 B1 / G54
Reserved RDC_PDAP55 SEMA42 B1 / G55
TZASC RDC_PDAP56 SEMA42 B1 / G56
Reserved RDC_PDAP57 SEMA42 B1 / G57
Reserved RDC_PDAP58 SEMA42 B1 / G58
USB2 RDC_PDAP59 SEMA42 B1 / G59
PERFMON1 RDC_PDAP60 SEMA42 B1 / G60
PERFMON2 RDC_PDAP61 SEMA42 B1 / G61
PLATFORM_CTRL RDC_PDAP62 SEMA42 B1 / G62
QoSC RDC_PDAP63 SEMA42 B1 / G63
Reserved RDC_PDAP64 SEMA42 B2 / G0
Reserved RDC_PDAP65 SEMA42 B2 / G1
I2C1 RDC_PDAP66 SEMA42 B2 / G2
I2C2 RDC_PDAP67 SEMA42 B2 / G3
I2C3 RDC_PDAP68 SEMA42 B2 / G4
I2C4 RDC_PDAP69 SEMA42 B2 / G5
UART4 RDC_PDAP70 SEMA42 B2 / G6
Reserved RDC_PDAP71 SEMA42 B2 / G7
Reserved RDC_PDAP72 SEMA42 B2 / G8
Reserved RDC_PDAP73 SEMA42 B2 / G9
MU_A RDC_PDAP74 SEMA42 B2 / G10
MU_B RDC_PDAP75 SEMA42 B2 / G11
SEMAPHORE_HS RDC_PDAP76 SEMA42 B2 / G12
Reserved for SDMA2 internal memory RDC_PDAP77 SEMA42 B2 / G13
SAI1 RDC_PDAP78 SEMA42 B2 / G14
SAI2 RDC_PDAP79 SEMA42 B2 / G15
SAI3 RDC_PDAP80 SEMA42 B2 / G16
Reserved RDC_PDAP81 SEMA42 B2 / G17
SAI5 RDC_PDAP82 SEMA42 B2 / G18
SAI6 RDC_PDAP83 SEMA42 B2 / G19

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 47
Resource Domain Controller (RDC)

Table 3-3. RDC Peripheral Mapping (continued)

Peripheral RDC PDAP register RDC_SEMA42 block/gate register
uSDHC1 RDC_PDAP84 SEMA42 B2 / G20
uSDHC2 RDC_PDAP85 SEMA42 B2 / G21
uSDHC3 RDC_PDAP86 SEMA42 B2 / G22
Reserved RDC_PDAP87 SEMA42 B2 / G23
PCIE_PHY1 RDC_PDAP88 SEMA42 B2 / G24
Reserved for SDMA2 internal memory RDC_PDAP89 SEMA42 B2 / G25
SPBA2 RDC_PDAP90 SEMA42 B2 / G26
QSPI RDC_PDAP91 SEMA42 B2 / G27
Reserved RDC_PDAP92 SEMA42 B2 / G28
SDMA1 RDC_PDAP93 SEMA42 B2 / G29
ENET1 RDC_PDAP94 SEMA42 B2 / G30
Reserved RDC_PDAP95 SEMA42 B2 / G31
Reserved for SDMA internal memory RDC_PDAP96 SEMA42 B2 / G32
SPDIF1 RDC_PDAP97 SEMA42 B2 / G33
eCSPI1 RDC_PDAP98 SEMA42 B2 / G34
eCSPI2 RDC_PDAP99 SEMA42 B2 / G35
eCSPI3 RDC_PDAP100 SEMA42 B2 / G36
MICFIL RDC_PDAP101 SEMA42 B2 / G37
UART1 RDC_PDAP102 SEMA42 B2 / G38
Reserved for SDMA internal registers RDC_PDAP103 SEMA42 B2 / G39
UART3 RDC_PDAP104 SEMA42 B2 / G40
UART2 RDC_PDAP105 SEMA42 B2 / G41
SPDIF2 RDC_PDAP106 SEMA42 B2 / G42
Reserved RDC_PDAP108 SEMA42 B2 / G44
Reserved RDC_PDAP109 SEMA42 B2 / G45
Reserved for SDMA internal registers RDC_PDAP110 SEMA42 B2 / G46
SPBA1 RDC_PDAP111 SEMA42 B2 / G47
module_en_glbl[0] RDC_PDAP112 SEMA42 B2 / G48
module_en_glbl[0] RDC_PDAP113 SEMA42 B2 / G49
CAAM RDC_PDAP114 SEMA42 B2 / G50

3.2.4.3 Memory Region Map

The number of memories with domain isolation support varies per device. The number of
memory regions for a particular memory and the size of those regions varies per memory
gasket. Each region of memory has a set of registers to define the boundaries of the

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

48 NXP Semiconductors
 Chapter 3 Security

region based on start and end addresses, a control register to set the domain access
permissions and enable the region, and a status register to determin if access was denied
to a region.
For this device, refer to the table below to determine the memories with domain support,
the number of regions for each memory, the region resolution, the identifying numbers
for the sets of memory region registers, and the addresses of the RDC registers to access
the sets of Memory Region registers.
Table 3-4. Memory Region Mapping
Memory/Port Number of regions Region resolution Memory region Register address
register set number range
(MREA, MRSA, MRC,
MRVS)
DRAM 8 4 KB 0-7 0x800 - 0x87C
QSPI1 8 4 KB 8 - 15 0x880 - 0x8FC
PCIe1 8 4 KB 16 - 23 0x900 - 0x97C
OCRAM 5 128 B 24 - 28 0x980 - 0x9CC
OCRAM_S 5 128 B 29 - 33 0x9D0 - 0xA1C
TCM 5 128 B 34 - 38 0xA20 - 0xA6C
GIC 4 4 KB 39 - 42 0xA70 - 0xAAC
GPU 8 4 KB 43 - 50 0xAB0 - 0xB2C
VPU 4 4 KB 51 - 54 0xB30 - 0xB6C
DEBUG(DAP) 4 4 KB 55 - 58 0xB70 - 0xBAC
DDRC (REG ) 5 4 KB 59 - 63 0xBB0 - 0xBFC

3.2.5 RDC Memory Map/Register Definition

RDC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0000 Version Information (RDC_VIR) 32 R 0376_E204h 3.2.5.1/60
303D_0024 Status (RDC_STAT) 32 R/W 0000_0100h 3.2.5.2/61
303D_0028 Interrupt and Control (RDC_INTCTRL) 32 R/W 0000_0000h 3.2.5.3/62
303D_002C Interrupt Status (RDC_INTSTAT) 32 R/W See section 3.2.5.4/62
303D_0200 Master Domain Assignment (RDC_MDA0) 32 R/W 0000_0000h 3.2.5.5/63
303D_0204 Master Domain Assignment (RDC_MDA1) 32 R/W 0000_0000h 3.2.5.5/63
303D_0208 Master Domain Assignment (RDC_MDA2) 32 R/W 0000_0000h 3.2.5.5/63
303D_020C Master Domain Assignment (RDC_MDA3) 32 R/W 0000_0000h 3.2.5.5/63
303D_0210 Master Domain Assignment (RDC_MDA4) 32 R/W 0000_0000h 3.2.5.5/63
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 49
Resource Domain Controller (RDC)

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0214 Master Domain Assignment (RDC_MDA5) 32 R/W 0000_0000h 3.2.5.5/63
303D_0218 Master Domain Assignment (RDC_MDA6) 32 R/W 0000_0000h 3.2.5.5/63
303D_021C Master Domain Assignment (RDC_MDA7) 32 R/W 0000_0000h 3.2.5.5/63
303D_0220 Master Domain Assignment (RDC_MDA8) 32 R/W 0000_0000h 3.2.5.5/63
303D_0224 Master Domain Assignment (RDC_MDA9) 32 R/W 0000_0000h 3.2.5.5/63
303D_0228 Master Domain Assignment (RDC_MDA10) 32 R/W 0000_0000h 3.2.5.5/63
303D_022C Master Domain Assignment (RDC_MDA11) 32 R/W 0000_0000h 3.2.5.5/63
303D_0230 Master Domain Assignment (RDC_MDA12) 32 R/W 0000_0000h 3.2.5.5/63
303D_0234 Master Domain Assignment (RDC_MDA13) 32 R/W 0000_0000h 3.2.5.5/63
303D_0238 Master Domain Assignment (RDC_MDA14) 32 R/W 0000_0000h 3.2.5.5/63
303D_023C Master Domain Assignment (RDC_MDA15) 32 R/W 0000_0000h 3.2.5.5/63
303D_0240 Master Domain Assignment (RDC_MDA16) 32 R/W 0000_0000h 3.2.5.5/63
303D_0244 Master Domain Assignment (RDC_MDA17) 32 R/W 0000_0000h 3.2.5.5/63
303D_0248 Master Domain Assignment (RDC_MDA18) 32 R/W 0000_0000h 3.2.5.5/63
303D_024C Master Domain Assignment (RDC_MDA19) 32 R/W 0000_0000h 3.2.5.5/63
303D_0250 Master Domain Assignment (RDC_MDA20) 32 R/W 0000_0000h 3.2.5.5/63
303D_0254 Master Domain Assignment (RDC_MDA21) 32 R/W 0000_0000h 3.2.5.5/63
303D_0258 Master Domain Assignment (RDC_MDA22) 32 R/W 0000_0000h 3.2.5.5/63
303D_025C Master Domain Assignment (RDC_MDA23) 32 R/W 0000_0000h 3.2.5.5/63
303D_0260 Master Domain Assignment (RDC_MDA24) 32 R/W 0000_0000h 3.2.5.5/63
303D_0264 Master Domain Assignment (RDC_MDA25) 32 R/W 0000_0000h 3.2.5.5/63
303D_0268 Master Domain Assignment (RDC_MDA26) 32 R/W 0000_0000h 3.2.5.5/63
303D_0400 Peripheral Domain Access Permissions (RDC_PDAP0) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0404 Peripheral Domain Access Permissions (RDC_PDAP1) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0408 Peripheral Domain Access Permissions (RDC_PDAP2) 32 R/W 0000_00FFh 3.2.5.6/64
303D_040C Peripheral Domain Access Permissions (RDC_PDAP3) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0410 Peripheral Domain Access Permissions (RDC_PDAP4) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0414 Peripheral Domain Access Permissions (RDC_PDAP5) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0418 Peripheral Domain Access Permissions (RDC_PDAP6) 32 R/W 0000_00FFh 3.2.5.6/64
303D_041C Peripheral Domain Access Permissions (RDC_PDAP7) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0420 Peripheral Domain Access Permissions (RDC_PDAP8) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0424 Peripheral Domain Access Permissions (RDC_PDAP9) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0428 Peripheral Domain Access Permissions (RDC_PDAP10) 32 R/W 0000_00FFh 3.2.5.6/64
303D_042C Peripheral Domain Access Permissions (RDC_PDAP11) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0430 Peripheral Domain Access Permissions (RDC_PDAP12) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0434 Peripheral Domain Access Permissions (RDC_PDAP13) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0438 Peripheral Domain Access Permissions (RDC_PDAP14) 32 R/W 0000_00FFh 3.2.5.6/64
303D_043C Peripheral Domain Access Permissions (RDC_PDAP15) 32 R/W 0000_00FFh 3.2.5.6/64
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

50 NXP Semiconductors
 Chapter 3 Security

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0440 Peripheral Domain Access Permissions (RDC_PDAP16) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0444 Peripheral Domain Access Permissions (RDC_PDAP17) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0448 Peripheral Domain Access Permissions (RDC_PDAP18) 32 R/W 0000_00FFh 3.2.5.6/64
303D_044C Peripheral Domain Access Permissions (RDC_PDAP19) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0450 Peripheral Domain Access Permissions (RDC_PDAP20) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0454 Peripheral Domain Access Permissions (RDC_PDAP21) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0458 Peripheral Domain Access Permissions (RDC_PDAP22) 32 R/W 0000_00FFh 3.2.5.6/64
303D_045C Peripheral Domain Access Permissions (RDC_PDAP23) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0460 Peripheral Domain Access Permissions (RDC_PDAP24) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0464 Peripheral Domain Access Permissions (RDC_PDAP25) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0468 Peripheral Domain Access Permissions (RDC_PDAP26) 32 R/W 0000_00FFh 3.2.5.6/64
303D_046C Peripheral Domain Access Permissions (RDC_PDAP27) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0470 Peripheral Domain Access Permissions (RDC_PDAP28) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0474 Peripheral Domain Access Permissions (RDC_PDAP29) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0478 Peripheral Domain Access Permissions (RDC_PDAP30) 32 R/W 0000_00FFh 3.2.5.6/64
303D_047C Peripheral Domain Access Permissions (RDC_PDAP31) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0480 Peripheral Domain Access Permissions (RDC_PDAP32) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0484 Peripheral Domain Access Permissions (RDC_PDAP33) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0488 Peripheral Domain Access Permissions (RDC_PDAP34) 32 R/W 0000_00FFh 3.2.5.6/64
303D_048C Peripheral Domain Access Permissions (RDC_PDAP35) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0490 Peripheral Domain Access Permissions (RDC_PDAP36) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0494 Peripheral Domain Access Permissions (RDC_PDAP37) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0498 Peripheral Domain Access Permissions (RDC_PDAP38) 32 R/W 0000_00FFh 3.2.5.6/64
303D_049C Peripheral Domain Access Permissions (RDC_PDAP39) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04A0 Peripheral Domain Access Permissions (RDC_PDAP40) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04A4 Peripheral Domain Access Permissions (RDC_PDAP41) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04A8 Peripheral Domain Access Permissions (RDC_PDAP42) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04AC Peripheral Domain Access Permissions (RDC_PDAP43) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04B0 Peripheral Domain Access Permissions (RDC_PDAP44) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04B4 Peripheral Domain Access Permissions (RDC_PDAP45) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04B8 Peripheral Domain Access Permissions (RDC_PDAP46) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04BC Peripheral Domain Access Permissions (RDC_PDAP47) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04C0 Peripheral Domain Access Permissions (RDC_PDAP48) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04C4 Peripheral Domain Access Permissions (RDC_PDAP49) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04C8 Peripheral Domain Access Permissions (RDC_PDAP50) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04CC Peripheral Domain Access Permissions (RDC_PDAP51) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04D0 Peripheral Domain Access Permissions (RDC_PDAP52) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04D4 Peripheral Domain Access Permissions (RDC_PDAP53) 32 R/W 0000_00FFh 3.2.5.6/64
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 51
Resource Domain Controller (RDC)

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_04D8 Peripheral Domain Access Permissions (RDC_PDAP54) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04DC Peripheral Domain Access Permissions (RDC_PDAP55) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04E0 Peripheral Domain Access Permissions (RDC_PDAP56) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04E4 Peripheral Domain Access Permissions (RDC_PDAP57) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04E8 Peripheral Domain Access Permissions (RDC_PDAP58) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04EC Peripheral Domain Access Permissions (RDC_PDAP59) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04F0 Peripheral Domain Access Permissions (RDC_PDAP60) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04F4 Peripheral Domain Access Permissions (RDC_PDAP61) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04F8 Peripheral Domain Access Permissions (RDC_PDAP62) 32 R/W 0000_00FFh 3.2.5.6/64
303D_04FC Peripheral Domain Access Permissions (RDC_PDAP63) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0500 Peripheral Domain Access Permissions (RDC_PDAP64) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0504 Peripheral Domain Access Permissions (RDC_PDAP65) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0508 Peripheral Domain Access Permissions (RDC_PDAP66) 32 R/W 0000_00FFh 3.2.5.6/64
303D_050C Peripheral Domain Access Permissions (RDC_PDAP67) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0510 Peripheral Domain Access Permissions (RDC_PDAP68) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0514 Peripheral Domain Access Permissions (RDC_PDAP69) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0518 Peripheral Domain Access Permissions (RDC_PDAP70) 32 R/W 0000_00FFh 3.2.5.6/64
303D_051C Peripheral Domain Access Permissions (RDC_PDAP71) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0520 Peripheral Domain Access Permissions (RDC_PDAP72) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0524 Peripheral Domain Access Permissions (RDC_PDAP73) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0528 Peripheral Domain Access Permissions (RDC_PDAP74) 32 R/W 0000_00FFh 3.2.5.6/64
303D_052C Peripheral Domain Access Permissions (RDC_PDAP75) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0530 Peripheral Domain Access Permissions (RDC_PDAP76) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0534 Peripheral Domain Access Permissions (RDC_PDAP77) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0538 Peripheral Domain Access Permissions (RDC_PDAP78) 32 R/W 0000_00FFh 3.2.5.6/64
303D_053C Peripheral Domain Access Permissions (RDC_PDAP79) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0540 Peripheral Domain Access Permissions (RDC_PDAP80) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0544 Peripheral Domain Access Permissions (RDC_PDAP81) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0548 Peripheral Domain Access Permissions (RDC_PDAP82) 32 R/W 0000_00FFh 3.2.5.6/64
303D_054C Peripheral Domain Access Permissions (RDC_PDAP83) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0550 Peripheral Domain Access Permissions (RDC_PDAP84) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0554 Peripheral Domain Access Permissions (RDC_PDAP85) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0558 Peripheral Domain Access Permissions (RDC_PDAP86) 32 R/W 0000_00FFh 3.2.5.6/64
303D_055C Peripheral Domain Access Permissions (RDC_PDAP87) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0560 Peripheral Domain Access Permissions (RDC_PDAP88) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0564 Peripheral Domain Access Permissions (RDC_PDAP89) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0568 Peripheral Domain Access Permissions (RDC_PDAP90) 32 R/W 0000_00FFh 3.2.5.6/64
303D_056C Peripheral Domain Access Permissions (RDC_PDAP91) 32 R/W 0000_00FFh 3.2.5.6/64
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

52 NXP Semiconductors
 Chapter 3 Security

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0570 Peripheral Domain Access Permissions (RDC_PDAP92) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0574 Peripheral Domain Access Permissions (RDC_PDAP93) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0578 Peripheral Domain Access Permissions (RDC_PDAP94) 32 R/W 0000_00FFh 3.2.5.6/64
303D_057C Peripheral Domain Access Permissions (RDC_PDAP95) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0580 Peripheral Domain Access Permissions (RDC_PDAP96) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0584 Peripheral Domain Access Permissions (RDC_PDAP97) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0588 Peripheral Domain Access Permissions (RDC_PDAP98) 32 R/W 0000_00FFh 3.2.5.6/64
303D_058C Peripheral Domain Access Permissions (RDC_PDAP99) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0590 Peripheral Domain Access Permissions (RDC_PDAP100) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0594 Peripheral Domain Access Permissions (RDC_PDAP101) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0598 Peripheral Domain Access Permissions (RDC_PDAP102) 32 R/W 0000_00FFh 3.2.5.6/64
303D_059C Peripheral Domain Access Permissions (RDC_PDAP103) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05A0 Peripheral Domain Access Permissions (RDC_PDAP104) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05A4 Peripheral Domain Access Permissions (RDC_PDAP105) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05A8 Peripheral Domain Access Permissions (RDC_PDAP106) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05AC Peripheral Domain Access Permissions (RDC_PDAP107) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05B0 Peripheral Domain Access Permissions (RDC_PDAP108) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05B4 Peripheral Domain Access Permissions (RDC_PDAP109) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05B8 Peripheral Domain Access Permissions (RDC_PDAP110) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05BC Peripheral Domain Access Permissions (RDC_PDAP111) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05C0 Peripheral Domain Access Permissions (RDC_PDAP112) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05C4 Peripheral Domain Access Permissions (RDC_PDAP113) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05C8 Peripheral Domain Access Permissions (RDC_PDAP114) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05CC Peripheral Domain Access Permissions (RDC_PDAP115) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05D0 Peripheral Domain Access Permissions (RDC_PDAP116) 32 R/W 0000_00FFh 3.2.5.6/64
303D_05D4 Peripheral Domain Access Permissions (RDC_PDAP117) 32 R/W 0000_00FFh 3.2.5.6/64
303D_0800 Memory Region Start Address (RDC_MRSA0) 32 R/W Undefined 3.2.5.7/65
303D_0804 Memory Region End Address (RDC_MREA0) 32 R/W Undefined 3.2.5.8/67
303D_0808 Memory Region Control (RDC_MRC0) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_080C Memory Region Violation Status (RDC_MRVS0) 32 R/W 0000_0000h
69
303D_0810 Memory Region Start Address (RDC_MRSA1) 32 R/W Undefined 3.2.5.7/65
303D_0814 Memory Region End Address (RDC_MREA1) 32 R/W Undefined 3.2.5.8/67
303D_0818 Memory Region Control (RDC_MRC1) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_081C Memory Region Violation Status (RDC_MRVS1) 32 R/W 0000_0000h
69
303D_0820 Memory Region Start Address (RDC_MRSA2) 32 R/W Undefined 3.2.5.7/65
303D_0824 Memory Region End Address (RDC_MREA2) 32 R/W Undefined 3.2.5.8/67
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 53
Resource Domain Controller (RDC)

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0828 Memory Region Control (RDC_MRC2) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_082C Memory Region Violation Status (RDC_MRVS2) 32 R/W 0000_0000h
69
303D_0830 Memory Region Start Address (RDC_MRSA3) 32 R/W Undefined 3.2.5.7/65
303D_0834 Memory Region End Address (RDC_MREA3) 32 R/W Undefined 3.2.5.8/67
303D_0838 Memory Region Control (RDC_MRC3) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_083C Memory Region Violation Status (RDC_MRVS3) 32 R/W 0000_0000h
69
303D_0840 Memory Region Start Address (RDC_MRSA4) 32 R/W Undefined 3.2.5.7/65
303D_0844 Memory Region End Address (RDC_MREA4) 32 R/W Undefined 3.2.5.8/67
303D_0848 Memory Region Control (RDC_MRC4) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_084C Memory Region Violation Status (RDC_MRVS4) 32 R/W 0000_0000h
69
303D_0850 Memory Region Start Address (RDC_MRSA5) 32 R/W Undefined 3.2.5.7/65
303D_0854 Memory Region End Address (RDC_MREA5) 32 R/W Undefined 3.2.5.8/67
303D_0858 Memory Region Control (RDC_MRC5) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_085C Memory Region Violation Status (RDC_MRVS5) 32 R/W 0000_0000h
69
303D_0860 Memory Region Start Address (RDC_MRSA6) 32 R/W Undefined 3.2.5.7/65
303D_0864 Memory Region End Address (RDC_MREA6) 32 R/W Undefined 3.2.5.8/67
303D_0868 Memory Region Control (RDC_MRC6) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_086C Memory Region Violation Status (RDC_MRVS6) 32 R/W 0000_0000h
69
303D_0870 Memory Region Start Address (RDC_MRSA7) 32 R/W Undefined 3.2.5.7/65
303D_0874 Memory Region End Address (RDC_MREA7) 32 R/W Undefined 3.2.5.8/67
303D_0878 Memory Region Control (RDC_MRC7) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_087C Memory Region Violation Status (RDC_MRVS7) 32 R/W 0000_0000h
69
303D_0880 Memory Region Start Address (RDC_MRSA8) 32 R/W Undefined 3.2.5.7/65
303D_0884 Memory Region End Address (RDC_MREA8) 32 R/W Undefined 3.2.5.8/67
303D_0888 Memory Region Control (RDC_MRC8) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_088C Memory Region Violation Status (RDC_MRVS8) 32 R/W 0000_0000h
69
303D_0890 Memory Region Start Address (RDC_MRSA9) 32 R/W Undefined 3.2.5.7/65
303D_0894 Memory Region End Address (RDC_MREA9) 32 R/W Undefined 3.2.5.8/67
303D_0898 Memory Region Control (RDC_MRC9) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_089C Memory Region Violation Status (RDC_MRVS9) 32 R/W 0000_0000h
69
303D_08A0 Memory Region Start Address (RDC_MRSA10) 32 R/W Undefined 3.2.5.7/65
303D_08A4 Memory Region End Address (RDC_MREA10) 32 R/W Undefined 3.2.5.8/67
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

54 NXP Semiconductors
 Chapter 3 Security

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_08A8 Memory Region Control (RDC_MRC10) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_08AC Memory Region Violation Status (RDC_MRVS10) 32 R/W 0000_0000h
69
303D_08B0 Memory Region Start Address (RDC_MRSA11) 32 R/W Undefined 3.2.5.7/65
303D_08B4 Memory Region End Address (RDC_MREA11) 32 R/W Undefined 3.2.5.8/67
303D_08B8 Memory Region Control (RDC_MRC11) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_08BC Memory Region Violation Status (RDC_MRVS11) 32 R/W 0000_0000h
69
303D_08C0 Memory Region Start Address (RDC_MRSA12) 32 R/W Undefined 3.2.5.7/65
303D_08C4 Memory Region End Address (RDC_MREA12) 32 R/W Undefined 3.2.5.8/67
303D_08C8 Memory Region Control (RDC_MRC12) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_08CC Memory Region Violation Status (RDC_MRVS12) 32 R/W 0000_0000h
69
303D_08D0 Memory Region Start Address (RDC_MRSA13) 32 R/W Undefined 3.2.5.7/65
303D_08D4 Memory Region End Address (RDC_MREA13) 32 R/W Undefined 3.2.5.8/67
303D_08D8 Memory Region Control (RDC_MRC13) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_08DC Memory Region Violation Status (RDC_MRVS13) 32 R/W 0000_0000h
69
303D_08E0 Memory Region Start Address (RDC_MRSA14) 32 R/W Undefined 3.2.5.7/65
303D_08E4 Memory Region End Address (RDC_MREA14) 32 R/W Undefined 3.2.5.8/67
303D_08E8 Memory Region Control (RDC_MRC14) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_08EC Memory Region Violation Status (RDC_MRVS14) 32 R/W 0000_0000h
69
303D_08F0 Memory Region Start Address (RDC_MRSA15) 32 R/W Undefined 3.2.5.7/65
303D_08F4 Memory Region End Address (RDC_MREA15) 32 R/W Undefined 3.2.5.8/67
303D_08F8 Memory Region Control (RDC_MRC15) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_08FC Memory Region Violation Status (RDC_MRVS15) 32 R/W 0000_0000h
69
303D_0900 Memory Region Start Address (RDC_MRSA16) 32 R/W Undefined 3.2.5.7/65
303D_0904 Memory Region End Address (RDC_MREA16) 32 R/W Undefined 3.2.5.8/67
303D_0908 Memory Region Control (RDC_MRC16) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_090C Memory Region Violation Status (RDC_MRVS16) 32 R/W 0000_0000h
69
303D_0910 Memory Region Start Address (RDC_MRSA17) 32 R/W Undefined 3.2.5.7/65
303D_0914 Memory Region End Address (RDC_MREA17) 32 R/W Undefined 3.2.5.8/67
303D_0918 Memory Region Control (RDC_MRC17) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_091C Memory Region Violation Status (RDC_MRVS17) 32 R/W 0000_0000h
69
303D_0920 Memory Region Start Address (RDC_MRSA18) 32 R/W Undefined 3.2.5.7/65
303D_0924 Memory Region End Address (RDC_MREA18) 32 R/W Undefined 3.2.5.8/67
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 55
Resource Domain Controller (RDC)

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0928 Memory Region Control (RDC_MRC18) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_092C Memory Region Violation Status (RDC_MRVS18) 32 R/W 0000_0000h
69
303D_0930 Memory Region Start Address (RDC_MRSA19) 32 R/W Undefined 3.2.5.7/65
303D_0934 Memory Region End Address (RDC_MREA19) 32 R/W Undefined 3.2.5.8/67
303D_0938 Memory Region Control (RDC_MRC19) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_093C Memory Region Violation Status (RDC_MRVS19) 32 R/W 0000_0000h
69
303D_0940 Memory Region Start Address (RDC_MRSA20) 32 R/W Undefined 3.2.5.7/65
303D_0944 Memory Region End Address (RDC_MREA20) 32 R/W Undefined 3.2.5.8/67
303D_0948 Memory Region Control (RDC_MRC20) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_094C Memory Region Violation Status (RDC_MRVS20) 32 R/W 0000_0000h
69
303D_0950 Memory Region Start Address (RDC_MRSA21) 32 R/W Undefined 3.2.5.7/65
303D_0954 Memory Region End Address (RDC_MREA21) 32 R/W Undefined 3.2.5.8/67
303D_0958 Memory Region Control (RDC_MRC21) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_095C Memory Region Violation Status (RDC_MRVS21) 32 R/W 0000_0000h
69
303D_0960 Memory Region Start Address (RDC_MRSA22) 32 R/W Undefined 3.2.5.7/65
303D_0964 Memory Region End Address (RDC_MREA22) 32 R/W Undefined 3.2.5.8/67
303D_0968 Memory Region Control (RDC_MRC22) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_096C Memory Region Violation Status (RDC_MRVS22) 32 R/W 0000_0000h
69
303D_0970 Memory Region Start Address (RDC_MRSA23) 32 R/W Undefined 3.2.5.7/65
303D_0974 Memory Region End Address (RDC_MREA23) 32 R/W Undefined 3.2.5.8/67
303D_0978 Memory Region Control (RDC_MRC23) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_097C Memory Region Violation Status (RDC_MRVS23) 32 R/W 0000_0000h
69
303D_0980 Memory Region Start Address (RDC_MRSA24) 32 R/W Undefined 3.2.5.7/65
303D_0984 Memory Region End Address (RDC_MREA24) 32 R/W Undefined 3.2.5.8/67
303D_0988 Memory Region Control (RDC_MRC24) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_098C Memory Region Violation Status (RDC_MRVS24) 32 R/W 0000_0000h
69
303D_0990 Memory Region Start Address (RDC_MRSA25) 32 R/W Undefined 3.2.5.7/65
303D_0994 Memory Region End Address (RDC_MREA25) 32 R/W Undefined 3.2.5.8/67
303D_0998 Memory Region Control (RDC_MRC25) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_099C Memory Region Violation Status (RDC_MRVS25) 32 R/W 0000_0000h
69
303D_09A0 Memory Region Start Address (RDC_MRSA26) 32 R/W Undefined 3.2.5.7/65
303D_09A4 Memory Region End Address (RDC_MREA26) 32 R/W Undefined 3.2.5.8/67
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

56 NXP Semiconductors
 Chapter 3 Security

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_09A8 Memory Region Control (RDC_MRC26) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_09AC Memory Region Violation Status (RDC_MRVS26) 32 R/W 0000_0000h
69
303D_09B0 Memory Region Start Address (RDC_MRSA27) 32 R/W Undefined 3.2.5.7/65
303D_09B4 Memory Region End Address (RDC_MREA27) 32 R/W Undefined 3.2.5.8/67
303D_09B8 Memory Region Control (RDC_MRC27) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_09BC Memory Region Violation Status (RDC_MRVS27) 32 R/W 0000_0000h
69
303D_09C0 Memory Region Start Address (RDC_MRSA28) 32 R/W Undefined 3.2.5.7/65
303D_09C4 Memory Region End Address (RDC_MREA28) 32 R/W Undefined 3.2.5.8/67
303D_09C8 Memory Region Control (RDC_MRC28) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_09CC Memory Region Violation Status (RDC_MRVS28) 32 R/W 0000_0000h
69
303D_09D0 Memory Region Start Address (RDC_MRSA29) 32 R/W Undefined 3.2.5.7/65
303D_09D4 Memory Region End Address (RDC_MREA29) 32 R/W Undefined 3.2.5.8/67
303D_09D8 Memory Region Control (RDC_MRC29) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_09DC Memory Region Violation Status (RDC_MRVS29) 32 R/W 0000_0000h
69
303D_09E0 Memory Region Start Address (RDC_MRSA30) 32 R/W Undefined 3.2.5.7/65
303D_09E4 Memory Region End Address (RDC_MREA30) 32 R/W Undefined 3.2.5.8/67
303D_09E8 Memory Region Control (RDC_MRC30) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_09EC Memory Region Violation Status (RDC_MRVS30) 32 R/W 0000_0000h
69
303D_09F0 Memory Region Start Address (RDC_MRSA31) 32 R/W Undefined 3.2.5.7/65
303D_09F4 Memory Region End Address (RDC_MREA31) 32 R/W Undefined 3.2.5.8/67
303D_09F8 Memory Region Control (RDC_MRC31) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_09FC Memory Region Violation Status (RDC_MRVS31) 32 R/W 0000_0000h
69
303D_0A00 Memory Region Start Address (RDC_MRSA32) 32 R/W Undefined 3.2.5.7/65
303D_0A04 Memory Region End Address (RDC_MREA32) 32 R/W Undefined 3.2.5.8/67
303D_0A08 Memory Region Control (RDC_MRC32) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A0C Memory Region Violation Status (RDC_MRVS32) 32 R/W 0000_0000h
69
303D_0A10 Memory Region Start Address (RDC_MRSA33) 32 R/W Undefined 3.2.5.7/65
303D_0A14 Memory Region End Address (RDC_MREA33) 32 R/W Undefined 3.2.5.8/67
303D_0A18 Memory Region Control (RDC_MRC33) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A1C Memory Region Violation Status (RDC_MRVS33) 32 R/W 0000_0000h
69
303D_0A20 Memory Region Start Address (RDC_MRSA34) 32 R/W Undefined 3.2.5.7/65
303D_0A24 Memory Region End Address (RDC_MREA34) 32 R/W Undefined 3.2.5.8/67
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 57
Resource Domain Controller (RDC)

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0A28 Memory Region Control (RDC_MRC34) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A2C Memory Region Violation Status (RDC_MRVS34) 32 R/W 0000_0000h
69
303D_0A30 Memory Region Start Address (RDC_MRSA35) 32 R/W Undefined 3.2.5.7/65
303D_0A34 Memory Region End Address (RDC_MREA35) 32 R/W Undefined 3.2.5.8/67
303D_0A38 Memory Region Control (RDC_MRC35) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A3C Memory Region Violation Status (RDC_MRVS35) 32 R/W 0000_0000h
69
303D_0A40 Memory Region Start Address (RDC_MRSA36) 32 R/W Undefined 3.2.5.7/65
303D_0A44 Memory Region End Address (RDC_MREA36) 32 R/W Undefined 3.2.5.8/67
303D_0A48 Memory Region Control (RDC_MRC36) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A4C Memory Region Violation Status (RDC_MRVS36) 32 R/W 0000_0000h
69
303D_0A50 Memory Region Start Address (RDC_MRSA37) 32 R/W Undefined 3.2.5.7/65
303D_0A54 Memory Region End Address (RDC_MREA37) 32 R/W Undefined 3.2.5.8/67
303D_0A58 Memory Region Control (RDC_MRC37) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A5C Memory Region Violation Status (RDC_MRVS37) 32 R/W 0000_0000h
69
303D_0A60 Memory Region Start Address (RDC_MRSA38) 32 R/W Undefined 3.2.5.7/65
303D_0A64 Memory Region End Address (RDC_MREA38) 32 R/W Undefined 3.2.5.8/67
303D_0A68 Memory Region Control (RDC_MRC38) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A6C Memory Region Violation Status (RDC_MRVS38) 32 R/W 0000_0000h
69
303D_0A70 Memory Region Start Address (RDC_MRSA39) 32 R/W Undefined 3.2.5.7/65
303D_0A74 Memory Region End Address (RDC_MREA39) 32 R/W Undefined 3.2.5.8/67
303D_0A78 Memory Region Control (RDC_MRC39) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A7C Memory Region Violation Status (RDC_MRVS39) 32 R/W 0000_0000h
69
303D_0A80 Memory Region Start Address (RDC_MRSA40) 32 R/W Undefined 3.2.5.7/65
303D_0A84 Memory Region End Address (RDC_MREA40) 32 R/W Undefined 3.2.5.8/67
303D_0A88 Memory Region Control (RDC_MRC40) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A8C Memory Region Violation Status (RDC_MRVS40) 32 R/W 0000_0000h
69
303D_0A90 Memory Region Start Address (RDC_MRSA41) 32 R/W Undefined 3.2.5.7/65
303D_0A94 Memory Region End Address (RDC_MREA41) 32 R/W Undefined 3.2.5.8/67
303D_0A98 Memory Region Control (RDC_MRC41) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0A9C Memory Region Violation Status (RDC_MRVS41) 32 R/W 0000_0000h
69
303D_0AA0 Memory Region Start Address (RDC_MRSA42) 32 R/W Undefined 3.2.5.7/65
303D_0AA4 Memory Region End Address (RDC_MREA42) 32 R/W Undefined 3.2.5.8/67
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

58 NXP Semiconductors
 Chapter 3 Security

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0AA8 Memory Region Control (RDC_MRC42) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0AAC Memory Region Violation Status (RDC_MRVS42) 32 R/W 0000_0000h
69
303D_0AB0 Memory Region Start Address (RDC_MRSA43) 32 R/W Undefined 3.2.5.7/65
303D_0AB4 Memory Region End Address (RDC_MREA43) 32 R/W Undefined 3.2.5.8/67
303D_0AB8 Memory Region Control (RDC_MRC43) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0ABC Memory Region Violation Status (RDC_MRVS43) 32 R/W 0000_0000h
69
303D_0AC0 Memory Region Start Address (RDC_MRSA44) 32 R/W Undefined 3.2.5.7/65
303D_0AC4 Memory Region End Address (RDC_MREA44) 32 R/W Undefined 3.2.5.8/67
303D_0AC8 Memory Region Control (RDC_MRC44) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0ACC Memory Region Violation Status (RDC_MRVS44) 32 R/W 0000_0000h
69
303D_0AD0 Memory Region Start Address (RDC_MRSA45) 32 R/W Undefined 3.2.5.7/65
303D_0AD4 Memory Region End Address (RDC_MREA45) 32 R/W Undefined 3.2.5.8/67
303D_0AD8 Memory Region Control (RDC_MRC45) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0ADC Memory Region Violation Status (RDC_MRVS45) 32 R/W 0000_0000h
69
303D_0AE0 Memory Region Start Address (RDC_MRSA46) 32 R/W Undefined 3.2.5.7/65
303D_0AE4 Memory Region End Address (RDC_MREA46) 32 R/W Undefined 3.2.5.8/67
303D_0AE8 Memory Region Control (RDC_MRC46) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0AEC Memory Region Violation Status (RDC_MRVS46) 32 R/W 0000_0000h
69
303D_0AF0 Memory Region Start Address (RDC_MRSA47) 32 R/W Undefined 3.2.5.7/65
303D_0AF4 Memory Region End Address (RDC_MREA47) 32 R/W Undefined 3.2.5.8/67
303D_0AF8 Memory Region Control (RDC_MRC47) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0AFC Memory Region Violation Status (RDC_MRVS47) 32 R/W 0000_0000h
69
303D_0B00 Memory Region Start Address (RDC_MRSA48) 32 R/W Undefined 3.2.5.7/65
303D_0B04 Memory Region End Address (RDC_MREA48) 32 R/W Undefined 3.2.5.8/67
303D_0B08 Memory Region Control (RDC_MRC48) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0B0C Memory Region Violation Status (RDC_MRVS48) 32 R/W 0000_0000h
69
303D_0B10 Memory Region Start Address (RDC_MRSA49) 32 R/W Undefined 3.2.5.7/65
303D_0B14 Memory Region End Address (RDC_MREA49) 32 R/W Undefined 3.2.5.8/67
303D_0B18 Memory Region Control (RDC_MRC49) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0B1C Memory Region Violation Status (RDC_MRVS49) 32 R/W 0000_0000h
69
303D_0B20 Memory Region Start Address (RDC_MRSA50) 32 R/W Undefined 3.2.5.7/65
303D_0B24 Memory Region End Address (RDC_MREA50) 32 R/W Undefined 3.2.5.8/67
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 59
Resource Domain Controller (RDC)

RDC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0B28 Memory Region Control (RDC_MRC50) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0B2C Memory Region Violation Status (RDC_MRVS50) 32 R/W 0000_0000h
69
303D_0B30 Memory Region Start Address (RDC_MRSA51) 32 R/W Undefined 3.2.5.7/65
303D_0B34 Memory Region End Address (RDC_MREA51) 32 R/W Undefined 3.2.5.8/67
303D_0B38 Memory Region Control (RDC_MRC51) 32 R/W 0000_00FFh 3.2.5.9/68
3.2.5.10/
303D_0B3C Memory Region Violation Status (RDC_MRVS51) 32 R/W 0000_0000h
69

3.2.5.1 Version Information (RDC_VIR)

The VIR provides version information including the number of domains, number of
master slots, number of peripheral slots, and number of memory regions.
Address: 303D_0000h base + 0h offset = 303D_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R NRGN NPER NMSTR NDID

Reserved
W

Reset 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0

RDC_VIR field descriptions

Field Description
31–28 This field is reserved.
Reserved
27–20 Number of Memory Regions
NRGN
Indicates the number of memory regions in this instance of the RDC.
19–12 Number of Peripherals
NPER
Indicates the number of peripherals that can be isolated or safe-shared.
11–4 Number of Masters
NMSTR
Indicates the number of masters supported by this instance of RDC.
NDID Number of Domains

Indicates the number of domain IDs supported by this instance of the RDC. For example, value '0010'
means the actual number of domains is 2.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

60 NXP Semiconductors
 Chapter 3 Security

3.2.5.2 Status (RDC_STAT)

Address: 303D_0000h base + 24h offset = 303D_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PDS Reserved DID
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

RDC_STAT field descriptions

Field Description
31–9 This field is reserved.
Reserved
8 Power Domain Status
PDS
Indicates if the "Power Down" memory regions are powered and available. Power Down memory regions
are only those memory regions susceptible to power outage for power savings are unavailable if this is
zero. "Always-On" memory regions remain available. Always On memory regions are those regions that
are not powered down unless the entire SoC is powered down. This signal remains low until all access
controls have been restored to the domain.

0 Power Down Domain is OFF

1 Power Down Domain is ON
7–4 This field is reserved.
Reserved
DID Domain ID

The Domain ID of the core or bus master that is reading this. The value is different for requests from
different domains.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 61
Resource Domain Controller (RDC)

3.2.5.3 Interrupt and Control (RDC_INTCTRL)

Address: 303D_0000h base + 28h offset = 303D_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RCI_EN
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDC_INTCTRL field descriptions

Field Description
31–1 This field is reserved.
Reserved
0 Restoration Complete Interrupt
RCI_EN
Interrupt generated when the RDC has completed restoring state to a recently re-powered memory
regions.

0 Interrupt Disabled
1 Interrupt Enabled

3.2.5.4 Interrupt Status (RDC_INTSTAT)

Indication of Interrupt Pending for State Restoration
Address: 303D_0000h base + 2Ch offset = 303D_002Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R INT
Reserved
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

62 NXP Semiconductors
 Chapter 3 Security

RDC_INTSTAT field descriptions

Field Description
31–1 This field is reserved.
Reserved
0 Interrupt Status
INT
Indicates state of interrupt signal for state restoration. This is that status of the interrupt enabled in
RDC_INTCTRL. Write one to interrupt status to clear it.

0 No Interrupt Pending
1 Interrupt Pending

3.2.5.5 Master Domain Assignment (RDC_MDAn)

Address: 303D_0000h base + 200h offset + (4d × i), where i=0d to 26d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
LCK Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved DID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDC_MDAn field descriptions

Field Description
31 Assignment Lock
LCK
0 Not Locked
1 Locked
30–2 This field is reserved.
Reserved
DID Domain ID

Indicates the domain to which the Master is assigned

00 Master assigned to Processing Domain 0

01 Master assigned to Processing Domain 1
10 Master assigned to Processing Domain 2
11 Master assigned to Processing Domain 3

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 63
Resource Domain Controller (RDC)

3.2.5.6 Peripheral Domain Access Permissions (RDC_PDAPn)

Address: 303D_0000h base + 400h offset + (4d × i), where i=0d to 117d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SRE
LCK Reserved
W Q
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved D3R D3W D2R D2W D1R D1W D0R D0W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

RDC_PDAPn field descriptions

Field Description
31 Peripheral Permissions Lock
LCK
When set prevents further modification of the Peripheral Domain Access Permissions (sticky bit until reset)

0 Not Locked
1 Locked
30 Semaphore Required
SREQ
When set the hardware semaphore state enforces the semaphore lock. If a domain has access
permissions and a semaphore has locked a shared peripheral then only the domain holding the
semaphore signal can access this peripheral.

0 Semaphores have no effect

1 Semaphores are enforced
29–8 This field is reserved.
Reserved
7 Domain 3 Read Access
D3R
0 No Read Access
1 Read Access Allowed
6 Domain 3 Write Access
D3W
0 No Write Access
1 Write Access Allowed
5 Domain 2 Read Access
D2R
0 No Read Access
1 Read Access Allowed
4 Domain 2 Write Access
D2W
0 No Write Access
1 Write Access Allowed
3 Domain 1 Read Access
D1R
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

64 NXP Semiconductors
 Chapter 3 Security

RDC_PDAPn field descriptions (continued)

Field Description
0 No Read Access
1 Read Access Allowed
2 Domain 1 Write Access
D1W
0 No Write Access
1 Write Access Allowed
1 Domain 0 Read Access
D0R
0 No Read Access
1 Read Access Allowed
0 Domain 0 Write Access
D0W
0 No Write Access
1 Write Access Allowed

3.2.5.7 Memory Region Start Address (RDC_MRSAn)

NOTE
The DDR space is 33-bit width. The RDC memory region
registers are 32-bit width. The RDC configuration is the most
significant bits in the DDR address space (32:1). To set the start
address for this configuration, the MRSA value should be
shifted 1-bit and added to the DDR base address. The example
below illustrates how to calculate the proper start and end
address value. Please refer to the Memory Map for the actual
DDR base address.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 65
Resource Domain Controller (RDC)

Start Address: 0x5000_0000

End Address: 0xAE00_0000
DDR Base Address: 0x4000_0000

Calculating MRSA value:

0x5000_0000 - 0x4000_0000 = 0x1000_0000 // Desired Start - DDR Base
0x1000_0000 / 2 = 0x800_0000 // Right-shift 1 bit
MRSA Value: 0x800_0000

Calculating MREA value:

0xAE00_0000 - 0x4000_0000 = 0x6E00_0000 // Desired End - DDR Base
0x6E00_0000 / 2 = 0x3700_0000 // Right-shift 1 bit
MREA Value: 0x3700_0000

Figure 3-5. Calculating Address Value Example

Address: 303D_0000h base + 800h offset + (16d × i), where i=0d to 51d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
SADR Reserved
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:
• x = Undefined at reset.

RDC_MRSAn field descriptions

Field Description
31–7 Start address for memory region
SADR
Lower bound (inclusive) modulo the defined granularity byte size of a region. The region size (granularity)
is defined for each Memory/Port in the Memory Region Map section. Region boundaries are aligned to the
minimum possible region size for the Memory/Port.
Reserved This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

66 NXP Semiconductors
 Chapter 3 Security

3.2.5.8 Memory Region End Address (RDC_MREAn)

NOTE
The DDR space is 33-bit width. The RDC memory region
registers are 32-bit width. The RDC configuration is the most
significant bits in the DDR address space (32:1). To set the start
address for this configuration, the MRSA value should be
shifted 1-bit and added to the DDR base address. The example
below illustrates how to calculate the proper start and end
address value. Please refer to the Memory Map for the actual
DDR base address.

Start Address: 0x5000_0000

End Address: 0xAE00_0000
DDR Base Address: 0x4000_0000

Calculating MRSA value:

0x5000_0000 - 0x4000_0000 = 0x1000_0000 // Desired Start - DDR Base
0x1000_0000 / 2 = 0x800_0000 // Right-shift 1 bit
MRSA Value: 0x800_0000

Calculating MREA value:

0xAE00_0000 - 0x4000_0000 = 0x6E00_0000 // Desired End - DDR Base
0x6E00_0000 / 2 = 0x3700_0000 // Right-shift 1 bit
MREA Value: 0x3700_0000

Figure 3-6. Calculating Address Value Example

Address: 303D_0000h base + 804h offset + (16d × i), where i=0d to 51d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
EADR Reserved
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:
• x = Undefined at reset.

RDC_MREAn field descriptions

Field Description
31–7 Upper bound for memory region
EADR
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 67
Resource Domain Controller (RDC)

RDC_MREAn field descriptions (continued)

Field Description
Upper bound (exclusive) modulo the defined granularity byte size of a region. The region size (granularity)
is defined for each Memory/Port in the Memory Region Map section. Region boundaries are aligned to the
minimum possible region size for the Memory/Port.
Reserved This field is reserved.

3.2.5.9 Memory Region Control (RDC_MRCn)

Address: 303D_0000h base + 808h offset + (16d × i), where i=0d to 51d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
LCK ENA Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved D3R D3W D2R D2W D1R D1W D0R D0W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

RDC_MRCn field descriptions

Field Description
31 Region Lock
LCK
Locks all region fields from further modification except ENA, which can be set but not reset after LCK is
set. LCK is a sticky bit.

0 No Lock. All fields in this register may be modified.

1 Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
30 Region Enable
ENA
Activates the memory region. If the region is not activated then the permissions and address boundaries
have not affect and the region will be fully accessible.

0 Memory region is not defined or restricted.

1 Memory boundaries, domain permissions and controls are in effect.
29–8 This field is reserved.
Reserved
7 Domain 3 Read Access to Region
D3R
0 Processing Domain 3 does not have Read access to the memory region
1 Processing Domain 3 has Read access to the memory region
6 Domain 3 Write Access to Region
D3W
0 Processing Domain 3 does not have Write access to the memory region
1 Processing Domain 3 has Read access to the memory region
5 Domain 2 Read Access to Region
D2R
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

68 NXP Semiconductors
 Chapter 3 Security

RDC_MRCn field descriptions (continued)

Field Description
0 Processing Domain 2 does not have Read access to the memory region
1 Processing Domain 2 has Read access to the memory region
4 Domain 2 Write Access to Region
D2W
0 Processing Domain 2 does not have Write access to the memory region
1 Processing Domain 2 has Write access to the memory region
3 Domain 1 Read Access to Region
D1R
0 Processing Domain 1 does not have Read access to the memory region
1 Processing Domain 1 has Read access to the memory region
2 Domain 1 Write Access to Region
D1W
0 Processing Domain 1 does not have Write access to the memory region
1 Processing Domain 1 has Write access to the memory region
1 Domain 0 Read Access to Region
D0R
0 Processing Domain 0 does not have Read access to the memory region
1 Processing Domain 0 has Read access to the memory region
0 Domain 0 Write Access to Region
D0W
0 Processing Domain 0 does not have Write access to the memory region
1 Processing Domain 0 has Write access to the memory region

3.2.5.10 Memory Region Violation Status (RDC_MRVSn)

Address: 303D_0000h base + 80Ch offset + (16d × i), where i=0d to 51d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R VADR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R VADR AD VDID
Reserved
W w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDC_MRVSn field descriptions

Field Description
31–5 Violating Address
VADR
The address of the denied access. The first access violation is captured. Subsequent violations are
ignored until the status register is cleared. Contents are cleared upon reading the register. Clearing of
contents occurs only when the status is read by the memory region's associated domain ID (s).

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 69
Resource Domain Controller (RDC)

RDC_MRVSn field descriptions (continued)

Field Description
4 Access Denied
AD
Access to a memory region denied. This bit is cleared when this bit is written by one of the allowed
domains.
3–2 This field is reserved.
Reserved
VDID Violating Domain ID

The domain ID of the denied access. The first access violation is captured. Subsequent violations are
ignored until the status register is cleared. Contents are cleared upon reading the register.

00 Processing Domain 0
01 Processing Domain 1
10 Processing Domain 2
11 Processing Domain 3

3.2.6 RDC SEMA42 Memory Map/Register Definition

Only Supervisor Mode accesses are allowed on these registers. User accesses generate an
error termination.
RDC_SEMAPHORE memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303B_0000 Gate Register (RDC_SEMAPHORE1_GATE0) 8 R/W 00h 3.2.6.1/74
303B_0001 Gate Register (RDC_SEMAPHORE1_GATE1) 8 R/W 00h 3.2.6.1/74
303B_0002 Gate Register (RDC_SEMAPHORE1_GATE2) 8 R/W 00h 3.2.6.1/74
303B_0003 Gate Register (RDC_SEMAPHORE1_GATE3) 8 R/W 00h 3.2.6.1/74
303B_0004 Gate Register (RDC_SEMAPHORE1_GATE4) 8 R/W 00h 3.2.6.1/74
303B_0005 Gate Register (RDC_SEMAPHORE1_GATE5) 8 R/W 00h 3.2.6.1/74
303B_0006 Gate Register (RDC_SEMAPHORE1_GATE6) 8 R/W 00h 3.2.6.1/74
303B_0007 Gate Register (RDC_SEMAPHORE1_GATE7) 8 R/W 00h 3.2.6.1/74
303B_0008 Gate Register (RDC_SEMAPHORE1_GATE8) 8 R/W 00h 3.2.6.1/74
303B_0009 Gate Register (RDC_SEMAPHORE1_GATE9) 8 R/W 00h 3.2.6.1/74
303B_000A Gate Register (RDC_SEMAPHORE1_GATE10) 8 R/W 00h 3.2.6.1/74
303B_000B Gate Register (RDC_SEMAPHORE1_GATE11) 8 R/W 00h 3.2.6.1/74
303B_000C Gate Register (RDC_SEMAPHORE1_GATE12) 8 R/W 00h 3.2.6.1/74
303B_000D Gate Register (RDC_SEMAPHORE1_GATE13) 8 R/W 00h 3.2.6.1/74
303B_000E Gate Register (RDC_SEMAPHORE1_GATE14) 8 R/W 00h 3.2.6.1/74
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

70 NXP Semiconductors
 Chapter 3 Security

RDC_SEMAPHORE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303B_000F Gate Register (RDC_SEMAPHORE1_GATE15) 8 R/W 00h 3.2.6.1/74
303B_0010 Gate Register (RDC_SEMAPHORE1_GATE16) 8 R/W 00h 3.2.6.1/74
303B_0011 Gate Register (RDC_SEMAPHORE1_GATE17) 8 R/W 00h 3.2.6.1/74
303B_0012 Gate Register (RDC_SEMAPHORE1_GATE18) 8 R/W 00h 3.2.6.1/74
303B_0013 Gate Register (RDC_SEMAPHORE1_GATE19) 8 R/W 00h 3.2.6.1/74
303B_0014 Gate Register (RDC_SEMAPHORE1_GATE20) 8 R/W 00h 3.2.6.1/74
303B_0015 Gate Register (RDC_SEMAPHORE1_GATE21) 8 R/W 00h 3.2.6.1/74
303B_0016 Gate Register (RDC_SEMAPHORE1_GATE22) 8 R/W 00h 3.2.6.1/74
303B_0017 Gate Register (RDC_SEMAPHORE1_GATE23) 8 R/W 00h 3.2.6.1/74
303B_0018 Gate Register (RDC_SEMAPHORE1_GATE24) 8 R/W 00h 3.2.6.1/74
303B_0019 Gate Register (RDC_SEMAPHORE1_GATE25) 8 R/W 00h 3.2.6.1/74
303B_001A Gate Register (RDC_SEMAPHORE1_GATE26) 8 R/W 00h 3.2.6.1/74
303B_001B Gate Register (RDC_SEMAPHORE1_GATE27) 8 R/W 00h 3.2.6.1/74
303B_001C Gate Register (RDC_SEMAPHORE1_GATE28) 8 R/W 00h 3.2.6.1/74
303B_001D Gate Register (RDC_SEMAPHORE1_GATE29) 8 R/W 00h 3.2.6.1/74
303B_001E Gate Register (RDC_SEMAPHORE1_GATE30) 8 R/W 00h 3.2.6.1/74
303B_001F Gate Register (RDC_SEMAPHORE1_GATE31) 8 R/W 00h 3.2.6.1/74
303B_0020 Gate Register (RDC_SEMAPHORE1_GATE32) 8 R/W 00h 3.2.6.1/74
303B_0021 Gate Register (RDC_SEMAPHORE1_GATE33) 8 R/W 00h 3.2.6.1/74
303B_0022 Gate Register (RDC_SEMAPHORE1_GATE34) 8 R/W 00h 3.2.6.1/74
303B_0023 Gate Register (RDC_SEMAPHORE1_GATE35) 8 R/W 00h 3.2.6.1/74
303B_0024 Gate Register (RDC_SEMAPHORE1_GATE36) 8 R/W 00h 3.2.6.1/74
303B_0025 Gate Register (RDC_SEMAPHORE1_GATE37) 8 R/W 00h 3.2.6.1/74
303B_0026 Gate Register (RDC_SEMAPHORE1_GATE38) 8 R/W 00h 3.2.6.1/74
303B_0027 Gate Register (RDC_SEMAPHORE1_GATE39) 8 R/W 00h 3.2.6.1/74
303B_0028 Gate Register (RDC_SEMAPHORE1_GATE40) 8 R/W 00h 3.2.6.1/74
303B_0029 Gate Register (RDC_SEMAPHORE1_GATE41) 8 R/W 00h 3.2.6.1/74
303B_002A Gate Register (RDC_SEMAPHORE1_GATE42) 8 R/W 00h 3.2.6.1/74
303B_002B Gate Register (RDC_SEMAPHORE1_GATE43) 8 R/W 00h 3.2.6.1/74
303B_002C Gate Register (RDC_SEMAPHORE1_GATE44) 8 R/W 00h 3.2.6.1/74
303B_002D Gate Register (RDC_SEMAPHORE1_GATE45) 8 R/W 00h 3.2.6.1/74
303B_002E Gate Register (RDC_SEMAPHORE1_GATE46) 8 R/W 00h 3.2.6.1/74
303B_002F Gate Register (RDC_SEMAPHORE1_GATE47) 8 R/W 00h 3.2.6.1/74
303B_0030 Gate Register (RDC_SEMAPHORE1_GATE48) 8 R/W 00h 3.2.6.1/74
303B_0031 Gate Register (RDC_SEMAPHORE1_GATE49) 8 R/W 00h 3.2.6.1/74
303B_0032 Gate Register (RDC_SEMAPHORE1_GATE50) 8 R/W 00h 3.2.6.1/74
303B_0033 Gate Register (RDC_SEMAPHORE1_GATE51) 8 R/W 00h 3.2.6.1/74
303B_0034 Gate Register (RDC_SEMAPHORE1_GATE52) 8 R/W 00h 3.2.6.1/74
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 71
Resource Domain Controller (RDC)

RDC_SEMAPHORE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303B_0035 Gate Register (RDC_SEMAPHORE1_GATE53) 8 R/W 00h 3.2.6.1/74
303B_0036 Gate Register (RDC_SEMAPHORE1_GATE54) 8 R/W 00h 3.2.6.1/74
303B_0037 Gate Register (RDC_SEMAPHORE1_GATE55) 8 R/W 00h 3.2.6.1/74
303B_0038 Gate Register (RDC_SEMAPHORE1_GATE56) 8 R/W 00h 3.2.6.1/74
303B_0039 Gate Register (RDC_SEMAPHORE1_GATE57) 8 R/W 00h 3.2.6.1/74
303B_003A Gate Register (RDC_SEMAPHORE1_GATE58) 8 R/W 00h 3.2.6.1/74
303B_003B Gate Register (RDC_SEMAPHORE1_GATE59) 8 R/W 00h 3.2.6.1/74
303B_003C Gate Register (RDC_SEMAPHORE1_GATE60) 8 R/W 00h 3.2.6.1/74
303B_003D Gate Register (RDC_SEMAPHORE1_GATE61) 8 R/W 00h 3.2.6.1/74
303B_003E Gate Register (RDC_SEMAPHORE1_GATE62) 8 R/W 00h 3.2.6.1/74
303B_003F Gate Register (RDC_SEMAPHORE1_GATE63) 8 R/W 00h 3.2.6.1/74
303B_0042 Reset Gate Write (RDC_SEMAPHORE1_RSTGT_W) 16 R/W 0000h 3.2.6.2/75
303B_0042 Reset Gate Read (RDC_SEMAPHORE1_RSTGT_R) 16 R/W 0000h 3.2.6.3/76
303C_0000 Gate Register (RDC_SEMAPHORE2_GATE0) 8 R/W 00h 3.2.6.1/74
303C_0001 Gate Register (RDC_SEMAPHORE2_GATE1) 8 R/W 00h 3.2.6.1/74
303C_0002 Gate Register (RDC_SEMAPHORE2_GATE2) 8 R/W 00h 3.2.6.1/74
303C_0003 Gate Register (RDC_SEMAPHORE2_GATE3) 8 R/W 00h 3.2.6.1/74
303C_0004 Gate Register (RDC_SEMAPHORE2_GATE4) 8 R/W 00h 3.2.6.1/74
303C_0005 Gate Register (RDC_SEMAPHORE2_GATE5) 8 R/W 00h 3.2.6.1/74
303C_0006 Gate Register (RDC_SEMAPHORE2_GATE6) 8 R/W 00h 3.2.6.1/74
303C_0007 Gate Register (RDC_SEMAPHORE2_GATE7) 8 R/W 00h 3.2.6.1/74
303C_0008 Gate Register (RDC_SEMAPHORE2_GATE8) 8 R/W 00h 3.2.6.1/74
303C_0009 Gate Register (RDC_SEMAPHORE2_GATE9) 8 R/W 00h 3.2.6.1/74
303C_000A Gate Register (RDC_SEMAPHORE2_GATE10) 8 R/W 00h 3.2.6.1/74
303C_000B Gate Register (RDC_SEMAPHORE2_GATE11) 8 R/W 00h 3.2.6.1/74
303C_000C Gate Register (RDC_SEMAPHORE2_GATE12) 8 R/W 00h 3.2.6.1/74
303C_000D Gate Register (RDC_SEMAPHORE2_GATE13) 8 R/W 00h 3.2.6.1/74
303C_000E Gate Register (RDC_SEMAPHORE2_GATE14) 8 R/W 00h 3.2.6.1/74
303C_000F Gate Register (RDC_SEMAPHORE2_GATE15) 8 R/W 00h 3.2.6.1/74
303C_0010 Gate Register (RDC_SEMAPHORE2_GATE16) 8 R/W 00h 3.2.6.1/74
303C_0011 Gate Register (RDC_SEMAPHORE2_GATE17) 8 R/W 00h 3.2.6.1/74
303C_0012 Gate Register (RDC_SEMAPHORE2_GATE18) 8 R/W 00h 3.2.6.1/74
303C_0013 Gate Register (RDC_SEMAPHORE2_GATE19) 8 R/W 00h 3.2.6.1/74
303C_0014 Gate Register (RDC_SEMAPHORE2_GATE20) 8 R/W 00h 3.2.6.1/74
303C_0015 Gate Register (RDC_SEMAPHORE2_GATE21) 8 R/W 00h 3.2.6.1/74
303C_0016 Gate Register (RDC_SEMAPHORE2_GATE22) 8 R/W 00h 3.2.6.1/74
303C_0017 Gate Register (RDC_SEMAPHORE2_GATE23) 8 R/W 00h 3.2.6.1/74
303C_0018 Gate Register (RDC_SEMAPHORE2_GATE24) 8 R/W 00h 3.2.6.1/74
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

72 NXP Semiconductors
 Chapter 3 Security

RDC_SEMAPHORE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303C_0019 Gate Register (RDC_SEMAPHORE2_GATE25) 8 R/W 00h 3.2.6.1/74
303C_001A Gate Register (RDC_SEMAPHORE2_GATE26) 8 R/W 00h 3.2.6.1/74
303C_001B Gate Register (RDC_SEMAPHORE2_GATE27) 8 R/W 00h 3.2.6.1/74
303C_001C Gate Register (RDC_SEMAPHORE2_GATE28) 8 R/W 00h 3.2.6.1/74
303C_001D Gate Register (RDC_SEMAPHORE2_GATE29) 8 R/W 00h 3.2.6.1/74
303C_001E Gate Register (RDC_SEMAPHORE2_GATE30) 8 R/W 00h 3.2.6.1/74
303C_001F Gate Register (RDC_SEMAPHORE2_GATE31) 8 R/W 00h 3.2.6.1/74
303C_0020 Gate Register (RDC_SEMAPHORE2_GATE32) 8 R/W 00h 3.2.6.1/74
303C_0021 Gate Register (RDC_SEMAPHORE2_GATE33) 8 R/W 00h 3.2.6.1/74
303C_0022 Gate Register (RDC_SEMAPHORE2_GATE34) 8 R/W 00h 3.2.6.1/74
303C_0023 Gate Register (RDC_SEMAPHORE2_GATE35) 8 R/W 00h 3.2.6.1/74
303C_0024 Gate Register (RDC_SEMAPHORE2_GATE36) 8 R/W 00h 3.2.6.1/74
303C_0025 Gate Register (RDC_SEMAPHORE2_GATE37) 8 R/W 00h 3.2.6.1/74
303C_0026 Gate Register (RDC_SEMAPHORE2_GATE38) 8 R/W 00h 3.2.6.1/74
303C_0027 Gate Register (RDC_SEMAPHORE2_GATE39) 8 R/W 00h 3.2.6.1/74
303C_0028 Gate Register (RDC_SEMAPHORE2_GATE40) 8 R/W 00h 3.2.6.1/74
303C_0029 Gate Register (RDC_SEMAPHORE2_GATE41) 8 R/W 00h 3.2.6.1/74
303C_002A Gate Register (RDC_SEMAPHORE2_GATE42) 8 R/W 00h 3.2.6.1/74
303C_002B Gate Register (RDC_SEMAPHORE2_GATE43) 8 R/W 00h 3.2.6.1/74
303C_002C Gate Register (RDC_SEMAPHORE2_GATE44) 8 R/W 00h 3.2.6.1/74
303C_002D Gate Register (RDC_SEMAPHORE2_GATE45) 8 R/W 00h 3.2.6.1/74
303C_002E Gate Register (RDC_SEMAPHORE2_GATE46) 8 R/W 00h 3.2.6.1/74
303C_002F Gate Register (RDC_SEMAPHORE2_GATE47) 8 R/W 00h 3.2.6.1/74
303C_0030 Gate Register (RDC_SEMAPHORE2_GATE48) 8 R/W 00h 3.2.6.1/74
303C_0031 Gate Register (RDC_SEMAPHORE2_GATE49) 8 R/W 00h 3.2.6.1/74
303C_0032 Gate Register (RDC_SEMAPHORE2_GATE50) 8 R/W 00h 3.2.6.1/74
303C_0033 Gate Register (RDC_SEMAPHORE2_GATE51) 8 R/W 00h 3.2.6.1/74
303C_0034 Gate Register (RDC_SEMAPHORE2_GATE52) 8 R/W 00h 3.2.6.1/74
303C_0035 Gate Register (RDC_SEMAPHORE2_GATE53) 8 R/W 00h 3.2.6.1/74
303C_0036 Gate Register (RDC_SEMAPHORE2_GATE54) 8 R/W 00h 3.2.6.1/74
303C_0037 Gate Register (RDC_SEMAPHORE2_GATE55) 8 R/W 00h 3.2.6.1/74
303C_0038 Gate Register (RDC_SEMAPHORE2_GATE56) 8 R/W 00h 3.2.6.1/74
303C_0039 Gate Register (RDC_SEMAPHORE2_GATE57) 8 R/W 00h 3.2.6.1/74
303C_003A Gate Register (RDC_SEMAPHORE2_GATE58) 8 R/W 00h 3.2.6.1/74
303C_003B Gate Register (RDC_SEMAPHORE2_GATE59) 8 R/W 00h 3.2.6.1/74
303C_003C Gate Register (RDC_SEMAPHORE2_GATE60) 8 R/W 00h 3.2.6.1/74
303C_003D Gate Register (RDC_SEMAPHORE2_GATE61) 8 R/W 00h 3.2.6.1/74
303C_003E Gate Register (RDC_SEMAPHORE2_GATE62) 8 R/W 00h 3.2.6.1/74
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 73
Resource Domain Controller (RDC)

RDC_SEMAPHORE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303C_003F Gate Register (RDC_SEMAPHORE2_GATE63) 8 R/W 00h 3.2.6.1/74
303C_0042 Reset Gate Write (RDC_SEMAPHORE2_RSTGT_W) 16 R/W 0000h 3.2.6.2/75
303C_0042 Reset Gate Read (RDC_SEMAPHORE2_RSTGT_R) 16 R/W 0000h 3.2.6.3/76

3.2.6.1 Gate Register (RDC_SEMAPHOREx_GATEn)

Each semaphore gate is implemented in a 4-bit finite state machine, right-justified in a
byte data structure. The hardware uses the logical bus master number (master_index) in
conjunction with the data patterns to validate all attempted write operations. Only
processor bus masters can modify the gate registers. Once locked, a gate can (and must)
be opened (unlocked) by the locking processor core.
Multiple gate values can be read in a single access, but only a single gate can be updated
via a write operation at a time. Attempted writes with a data value that is neither the
unlock value nor the appropriate lock value (master_index + 1) are simply treated as "no
operation" and do not affect any gate state. Attempts to write multiple gates in a single
aligned access with a size larger than an 8-bit (byte) reference generate an error
termination and do not allow any gate state changes. Processor dex values can be found
in AIPSTZ Memory Map/Register Definition.
Address: Base address + 0h offset + (1d × i), where i=0d to 63d
Bit 7 6 5 4 3 2 1 0

Read 0 LDOM
GTFSM
Write
Reset 0 0 0 0 0 0 0 0

RDC_SEMAPHOREx_GATEn field descriptions

Field Description
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5–4 Read-only bits. They indicate which domain had currently locked the gate.
LDOM
00 The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
01 The gate has been locked by domain 1.
10 The gate has been locked by domain 2.
11 The gate has been locked by domain 3.
GTFSM Gate Finite State Machine.

The state of the gate reflects the last processor that locked it, which can be useful during system debug.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

74 NXP Semiconductors
 Chapter 3 Security

RDC_SEMAPHOREx_GATEn field descriptions (continued)

Field Description
The hardware gate is maintained in a 16-state implementation, defined as:

0000 The gate is unlocked (free).

0001 The gate has been locked by processor with master_index = 0.
0010 The gate has been locked by processor with master_index = 1.
0011 The gate has been locked by processor with master_index = 2.
0100 The gate has been locked by processor with master_index = 3.
0101 The gate has been locked by processor with master_index = 4.
0110 The gate has been locked by processor with master_index = 5.
0111 The gate has been locked by processor with master_index = 6.
1000 The gate has been locked by processor with master_index = 7.
1001 The gate has been locked by processor with master_index = 8.
1010 The gate has been locked by processor with master_index = 9.
1011 The gate has been locked by processor with master_index = 10.
1100 The gate has been locked by processor with master_index = 11.
1101 The gate has been locked by processor with master_index = 12.
1110 The gate has been locked by processor with master_index = 13.
1111 The gate has been locked by processor with master_index = 14.

3.2.6.2 Reset Gate Write (RDC_SEMAPHOREx_RSTGT_W)

Although the intent of the hardware gate implementation specifies a protocol where the
locking processor must unlock the gate, it is recognized that system operation may
require a reset function to re-initialize the state of any gate(s) without requiring a system-
level reset.
To support this special gate reset requirement, the RDC Semaphores module implements
a "secure" reset mechanism that allows a hardware gate (or all the gates) to be initialized
by following a specific dual-write access pattern. Using a technique similar to that
required for the servicing of a software watchdog timer, the secure gate reset requires two
consecutive writes with predefined data patterns from the same processor to force the
clearing of the specified gate(s). The required access pattern is:
1. A processor performs a 16-bit write to the RDC_SEMA42RSTGT memory location.
The least significant byte (RDC_SEMA42RSTGT[RSTGDP]) must be 0xE2; the
most significant byte is a "don't_care" for this reference.
2. The same processor then performs a second 16-bit write to the
RDC_SEMA42RSTGT location. For this write, the lower byte
(RDC_SEMA42RSTGT[RSTGDP]) is the logical complement of the first data
pattern (0x1D) and the upper byte (RDC_SEMA42RSTGT[RSTGTN]) specifies the
gate(s) to be reset. This gate field can specify a single gate be cleared, or else that all
gates are to be cleared. If the same processor writes incorrect data on the second

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 75
Resource Domain Controller (RDC)

access or another processor performs the second write access, the special gate reset
sequence is aborted and no error signal will be asserted.
3. Reads of the RDC_SEMA42RSTGT location return information on the 2-bit state
machine (RDC_SEMA42RSTGT[RSTGSM]) that implements this function, the bus
master performing the reset (RDC_SEMA42RSTGT[RSTGMS]), and the gate
number(s) last cleared (RDC_SEMA42RSTGT[RSTGTN]). Reads of the
RDC_SEMA42RSTGT register do not affect the secure reset finite state machine in
any manner.
Address: Base address + 42h offset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read 0
RSTGTN
Write RSTGDP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDC_SEMAPHOREx_RSTGT_W field descriptions

Field Description
15–8 Reset Gate Number. This 8-bit field specifies the specific hardware gate to be reset. This field is updated
RSTGTN by the second write.
This field contains the hexidecimal value of the gate number. If RSTGTN < 64, then reset the single gate
defined by RSTGTN, else reset all the gates.
RSTGDP Reset Gate Data Pattern. This write-only field is accessed with the specified data patterns on the two
consecutive writes to enable the gate reset mechanism. For the first write, RSTGDP = 0xE2 while the
second write requires RSTGDP = 0x1D.

3.2.6.3 Reset Gate Read (RDC_SEMAPHOREx_RSTGT_R)

Although the intent of the hardware gate implementation specifies a protocol where the
locking processor must unlock the gate, it is recognized that system operation may
require a reset function to re-initialize the state of any gate(s) without requiring a system-
level reset.
To support this special gate reset requirement, the RDC Semaphores module implements
a "secure" reset mechanism that allows a hardware gate (or all the gates) to be initialized
by following a specific dual-write access pattern. Using a technique similar to that
required for the servicing of a software watchdog timer, the secure gate reset requires two
consecutive writes with predefined data patterns from the same processor to force the
clearing of the specified gate(s). The required access pattern is:
1. A processor performs a 16-bit write to the RDC_SEMA42RSTGT memory location.
The least significant byte (RDC_SEMA42RSTGT[RSTGDP]) must be 0xE2; the
most significant byte is a "don't_care" for this reference.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

76 NXP Semiconductors
 Chapter 3 Security

2. The same processor then performs a second 16-bit write to the

RDC_SEMA42RSTGT location. For this write, the lower byte
(RDC_SEMA42RSTGT[RSTGDP]) is the logical complement of the first data
pattern (0x1D) and the upper byte (RDC_SEMA42RSTGT[RSTGTN]) specifies the
gate(s) to be reset. This gate field can specify a single gate be cleared, or else that all
gates are to be cleared. If the same processor writes incorrect data on the second
access or another processor performs the second write access, the special gate reset
sequence is aborted and no error signal will be asserted.
3. Reads of the RDC_SEMA42RSTGT location return information on the 2-bit state
machine (RDC_SEMA42RSTGT[RSTGSM]) that implements this function, the bus
master performing the reset (RDC_SEMA42RSTGT[RSTGMS]), and the gate
number(s) last cleared (RDC_SEMA42RSTGT[RSTGTN]). Reads of the
RDC_SEMA42RSTGT register do not affect the secure reset finite state machine in
any manner.
Address: Base address + 42h offset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read 0 RSTGSM RSTGMS

RSTGTN
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDC_SEMAPHOREx_RSTGT_R field descriptions

Field Description
15–8 Reset Gate Number. This 8-bit field specifies the specific hardware gate to be reset. This field is updated
RSTGTN by the second write.
This field contains the hexidecimal value of the gate number. If RSTGTN < 64, then reset the single gate
defined by RSTGTN, else reset all the gates.
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5–4 Reset Gate Finite State Machine. Reads of the RDC_SEMA42RSTGT register return the encoded state
RSTGSM machine value. Note the RSTGSM = 10 state is valid for only a single machine cycle, so it is impossible
for a read to return this value. The reset state machine is maintained in a 2-bit, 3-state implementation,
defined as:

00 Idle, waiting for the first data pattern write.

01 Waiting for the second data pattern write.
10 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is
performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state
persists for only one clock cycle. Software will never be able to observe this state.
11 This state encoding is never used and therefore reserved.
RSTGMS Reset Gate Bus Master. This 4-bit read-only field records the logical number of the bus master performing
the gate reset function. The reset function requires that the two consecutive writes to this register must be
initiated by the same bus master to succeed. This field is updated each time a write to this register occurs.
The association between system bus master port numbers, the associated bus master device, and the
logical processor number is SoC-specific.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 77
Resource Domain Controller (RDC)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

78 NXP Semiconductors
Chapter 4
ARM Platform and Debug

4.1 ARM Cortex A53 Platform (A53)

4.1.1 Overview
The Cortex-A53 cluster is a mid-range, low-power processor that implements the
ARMv8-A architecture. The Cortex-A53 cluster has four cores, each with an L1 memory
system and a single shared L2 cache that has a set of additional functions, which are
included in a single APR region.
The core supports debug through real-time trace via ETM, and static debug via JTAG.
The core platform supports static debug through the debug logic to SoC. This includes
the capability of real-time trace via ARM's CoreSight ETM modules. The CTI and CTM
modules allow cross-triggering of internal and external trigger sources.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 79
ARM Cortex A53 Platform (A53)

Quad A53
Cortex
Cortex A53
A53 Counter
CortexMPCore
A53
CortexMPCore
A53
MPCore
MPCore CPU0
CPU0
Timer events
CPU0
CPU0 Neon Interrupts
I$ I$
Neon
Neon
I$ 32K D$
Neon
I$ I$32K
I$32K D$
I$32K32K D$ 32K
I$ 32K D$ 32K
32K 32K
32K 32K Clocks
Resets
Snoop Control Unit
(SCU) Config

L2 Cache
(512KB) APB
ATB
CTM

ACE master
Interface

Figure 4-1. Cortex-A53 Block Diagram

4.1.1.1 Features
• 4x cores
• L1 instruction cache 32K with parity
• L1 data cache 32K with SECDED
• Advanced SIMD (NEON) per core
• Crypto extension per core
• CPU cache protection per core
• AMBA 4 ACE interface
• No ACP is included
• utilizes the ARMv8 debug map
• 512KB of L2 Cache
• 512KB with Single-bit Error Correct and Double-bit Error Detect (SECDED)
• Input latency 2 cycles
• Output latency 2 cycles
• SCU-L2 cache protection

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

80 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.1.2 Configuration
The configuration of the bus, cores and memory are detailed in the features and sections
below. The core revision is r0p4-51rel0.

4.1.3 Performance
This section will discuss power and clocking performance of the Cortex-A53 Platform.

4.1.3.1 Power
There are several power states supported by the A53 Core Complex. Supported primary
states are listed below:
• Run – At least one of 4 cores is running. The other cores may either be running,
clock gated, or powered down.
• L2 only coherent – The L2 is powered up and servicing snoops. The cores are
stopped (either powered down or clock gated). In this state the cache is retained
coherent to the system.
• L2 only non-coherent – Both cores are stopped and powered down, the logic in the
L2 controller are retaining the arrays only. In this state the L2 is not coherent, and as
a result, the other AP cores must also be stopped.
• Cluster Off – The L2 has been flushed from the L2 only coherent state, using the
HW flush mechanism (no core required). Then the cluster is fully powered off
including the L2 arrays.
The power supply for the cluster is separated into two regions. The first is the control
domain and second is for the remainder of the cluster (core and cluster domains). These
regions are listed below:
• Control domain – The AON control domain contains the controls for powering up
and down the rest of the core. The control domain is always powered on first and
powered off last.
• Core domains – The core domains contains the whole core. The supply for the core
domains is the same as the cluster domain, but require separate power down
switches.
• Cluster domain – The cluster domain contains the rest of the cluster outside of the
cores, which includes the shared logic of the L2 memory. The supply for the cluster
power domain is the same as the core domains, but does not require power switches
as it's shut down externally.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 81
ARM Cortex A53 Platform (A53)

Isolation cells are required between each of these domains and is controlled by the signals
on the control domain. These cells are necessary to force the output signal to be isolated
to null values when the local power shuts down.

4.1.3.2 Clocking
The A53 platform is provided a main processor clock that supplies the component clocks
to the cluster components, including CoreSight debug components. The maximum
frequency targets are specified in the chip datasheet.
The cores are intended to support up to 1.5 GHz dependent on forward bias within the
operating temperature range. Please see the datasheet for more information. The clocks
are described in the table below:
Table 4-1. A53 Clocks
Clock Signal Clock Name Frequency Description
Main Clock CLKIN Target Main input clock.
APB Clock PCLKENDBG CLKIN/4 APB clock controls the timing on the debug port.
Fixed frequency ratio to main frequency.
ACE Bus Clock ACLKENM CLKIN/2 ACE Interface bus clock. Controls the timing on
the interface to CCI, but is not synchronous to
CCI. Frequency is fixed ratio.
ATB Clock ATCLKEN CLKIN/4 ATB clock provides the clocks or outgoing trace.
This clock needs to be reasonably high to enable
sending samples out, but also needs to be the
same as CNTCLKEN. Link to same signal as
CNTCLKEN (1:4 core frequency fixed ratio).
Input Counter Clock CNTCLKEN CLKIN/4 Input counter clock. Timing is identical to debug
port. The frequency is a fixed ratio (1:4) with the
core clock. The same signal may be used for
both inputs.

4.1.4 Platform sub-blocks

The sections below discuss the high-level overview of the ARM® Cortex®-A53 Platform
components.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

82 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.1.4.1 ARM Cortex-A53 MPCore Processor

The information presented in this section focuses on the design aspects of the ARM
Cortex-A53 MPCore in the AP subsystem. The Cortex-A53 processor is a mid-range,
low-power processor that implements the ARMv8-A architecture. The A53 complex has
four cores, each with an L1 memory system and a single shared L2 cache.
The ARM Cortex-A53 MPCore processor consists of:
• Tightly-coupled L2 cache and an integrated Snoop Control Unit (SCU), connecting
the four cores within the cluster providing cluster memory coherency, and a
configurable coherent external interface supporting AMBA4 bus architecture.
• The Cortex-A53 implements the ARM Generic Interrupt Controller v3 (GICv3)
architecture.

4.1.4.2 Advanced SIMD (Neon)

The Cortex-A53 processor supports the Advanced SIMD and Scalar Floating-point
instructions in the A64 instruction set, and the Advanced SIMD and VFP instructions in
the A32 and T32 instruction sets.
The ARMv8 architecture eliminates the concept of version numbers for Advanced SIMD
and Floating-point in the AArch64 execution state.

4.1.4.3 Generic Interrupt Controller (GIC)

The Generic Interrupt Controller (GIC) supports and manages interrupts in the cluster.
The GIC provides registers for managing:
• Interrupt sources
• Interrupt behavior
• Interrupt routing to one or more cores
The Cortex-A53 processor implements the GIC CPU interface as described in the
Generic Interrupt Controller (GICv4) architecture. This interfaces with an external GICv3
or GICv4 interrupt distributor component within the system. The GICv4 architecture
supports:
• Two security states
• Interrupt virtualization
• Software-generated Interrupts (SGIs)
• Message Based Interrupts
• System register access
• Memory-mapped register access
• Interrupt masking and prioritization

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 83
ARM Cortex A53 Platform (A53)

• Cluster environments
• Wake-up events in power management environments
The GIC includes interrupt grouping functionality that supports:
• Signaling interrupt groups to the target core using either the IRQ or the FIQ
exception request, based on software configuration
• A unified scheme for handling the priority of Group 0 and Group 1 interrupts.

4.1.4.4 L1 Cache
The L1 instruction memory system has the following features:
• 32KB Instruction Cache
• Instruction side cache line length of 64 bytes
• 2-way set associative L1 Instruction cache
• 128-bit read interface to the L2 memory system
• 32KB Data Cache
• Data side cache line length of 64 bytes
• 4-way set associative L1 Data cache
• 256-bit write interface to the L2 memory system
• 128-bit read interface to the L2 memory system
• Read buffer that services the Data Cache Unit (DCU), the Instruction Fetch Unit
(IFU) and the TLB
• 64-bit read path from the data L1 memory system to the datapath
• 128-bit write path from the datapath to the L1 memory system
• Support for three outstanding data cache misses
• Merging store buffer capability. This handles writes to:
• Device memory
• Normal Cacheable memory
• Normal Non-cacheable memory
• Data side prefetch engine

4.1.4.5 L2 Cache
The L2 cache consists of an integrated Snoop Control Unit (SCU), connecting four cores
within the A53 cluster. The SCU also has duplicate copies of the L1 Data cache tags for
coherency support. The L2 memory system interfaces to the external memory system
through an AMBA 128-bit bus. The tightly-coupled L2 cache includes the following
features:
• 1MB shared cache size
• AMBA 4 ACE Interface
• Fixed line length of 64 bytes
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
84 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• Physically indexed and tagged cache

• 16-way set-associative cache structure
• No ACP support
• ECC/parity support

4.2 ARM Cortex M4 Platform (M4)

4.2.1 Overview
The Cortex-M4 implements the ARMv7- ME instruction set architecture (ISA) and adds
significant capabilities with DSP and SIMD extensions. The ARM Cortex-M4 core
provides additional general processing capability to the SoC with lower power and fast
interrupt response time.
The Cortex-M4 also includes a single-precision floating-point unit (FPU) and two 32-bit
system bus interfaces. The Cortex-M4 implementation includes two tightly coupled local
memories, two cache memories connected to bus interfaces, 64-bit system bus
interconnect, and supports a 32-byte cache line size.

4.2.1.1 Block Diagram

The block diagram details the ARM Cortex-M4 core and platform.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 85
ARM Cortex M4 Platform (M4)

M4 Platform
Timer events
Counter
Cortex M4 CPU

Interrupts NVIC FPU MPU

Clocks
Resets MMCAU MCM
Config
LMEM
APB code TCM sys TCM Sys$ Code$
128 KB 128 KB 16 KB 16 KB
ATB
CTM

Private Peripheral
System Bus
(icode, dcode)

Bus (PPB)
Code Bus

Figure 4-2. Cortex-M4 Platform Block Diagram

4.2.1.2 Features
The features of the Cortex-M4 platform are detailed below:
• 1x Cortex-M4 processor
• AHB LMEM (Local Memory Controller) including controllers for TCM and cache
memories
• 256 KB TCM (128 KB TCMU, 128 KB TCML)
• 16 KB Code Bus Cache
• 16 KB System Bus Cache
• ECC for TCM memories and parity for code and system caches (see LMEM and
MCM for more information)
• Integrated Nested Vector Interrupt Controller (NVIC)
• Wakeup Interrupt Controller (WIC)
• FPU (Floating Point Unit)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

86 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• Core MPU (Memory Protection Unit)

• Support for exclusive access on the system bus
• MMCAU (Crypto Acceleration Unit)
• MCM (Miscellaneous Control Module)

4.2.2 Configuration
The configuration of the bus, core, and memory are detailed in the features and sections
below.
Table 4-2. Cortex-M4 Configuration
Parameter Description Setting
NUM_IRQ Number of Interrupts 128
LVL_WIDTH (translates to 2n Number of interrupt priority bits 4
levels)
MPU_PRESENT Exclude (0) or include (1) optional ARM MPU 1
DEBUG_LVL Level of debug support 3
TRACE_LVL Level of trace support 2
0 = No Trace
1 = ITM and DWT
2 = ITM, DWT, and ETM
3 = ITM, DWT, ETM, and HTM
RESET_ALL_REGS Select whether all registers are reset (1) 1
JTAG_PRESENT SWJ-DP (1) 1
SW-DP (0)
CLKGATE_PRESENT Disable (0) or enable (1) instantiation of architectural clock 1
gates at all levels
WIC_PRESENT Exclude (0) or include (1) optional ARM provided WIC 1
WIC_LINES Select number of interrupts and/or events that WIC is NUM_IRQ+3
sensitive to
FPU_PRESENT Exclude (0) or include (1) Floating Point Unit (FPU) 1
BB_PRESENT Exclude (0) or include (1) Bit Banding logic 0
CONST_AHB_CTRL Specifies whether the external AHB-Lite buses maintain 0
control information during wait stated transfers

4.2.3 Performance
This section will discuss power and clocking performance of the Cortex-M4 Platform.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 87
ARM Cortex M4 Platform (M4)

4.2.3.1 Power
There are several power states supported by the Cortex-M4. Supported primary core
states are listed below:
• Run - Normal run state. CM4 Platform, TCM and cache memories on nominal
voltage.
• Sleep – Wait power state. Depending on power state, CM4 Platform, TCM and cache
memories can either be in nominal or low-voltage. State recovery through NVIC.
NVIC clock is still running in this state.
• Deep Sleep – Stop power state. Depending on power state, CM4 Platform, TCM and
cache memories can either be in nominal or low-voltage. State recovery through
AWIC. Clocks can be completely stopped in this state.

4.2.3.2 Clocking
The M4 platform is provided a main processor clock that supplies the component clocks
to the cluster components. The maximum frequency targets are specified in the chip
datasheet. Please see the datasheet for more information. The clocks are described in the
table below:
Table 4-3. CM4 Clocks
Clock Signal Clock Name Target Frequency Description
Core gated clock cm4_hclk 400 MHz Cortex-M4 core clock.
Core Free-Running Clock cm4_fclk 400 MHz CM4 NVIC and timer clock
TCM Controller Clock cm4_tcmc_hclk 400 MHz CM4 platform TCM controller
clock
Platform Clock hclk 400 MHz CM4 platform AXBS fabric
and bus masters.
Synchronous to the core
clock.
Bus Clock ipg_clk 133 MHz Clock for bus slaves and
peripherals. Synchronous to
the system clock.

4.2.4 Platform sub-blocks

The sections below discuss the high-level overview of the ARM® Cortex®-M4 Platform
components.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

88 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.2.4.1 ARM Cortex-M4 Processor

The Cortex-M4 processor is a low-power processor that features low gate count, low
interrupt latency, and low-cost debug. The Cortex-M4 includes floating point arithmetic
functionality. The processor is intended for deeply embedded applications that require
fast interrupt response features.
The ARM Cortex-M4 processor consists of:
• A processor core
• A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor
core to achieve low-latency interrupt processing
• Multiple high-performance bus interfaces
• A low-cost debug solution with the optional ability to:
• Implement breakpoints and code patches
• Implement watchpoints, tracing, and system profiling
• Support printf() style debugging
• Bridge to a Trace Port Analyzer (TPA)
• Memory Protection Unit (MPU)
• Floating Point Unit (FPU)
• Miscellaneous Control Module (MCM)
• The Cortex-M4 implements the ARM the ARMv7-M architecture.

4.2.4.2 Nested Vectored Interrupt Controller (NVIC)

The M4 platform includes a Nested Vectored Interrupt Controller (NVIC) that is closely
integrated with the processor core to achieve low-latency interrupt processing. The
platform supports 16 priority levels for interrupts. The NVIC IPR registers will define 4
bits per IRQ.
NOTE
M4_NMI is Non-maskable Interrupt of M4 with fixed priority.
It is available by selecting ALT1 mux_mode for pad
GPIO1_IO05. Refer to ARM official document CortexTM-M4
Devices Generic User Guide for more details.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 89
ARM Cortex M4 Platform (M4)

4.2.4.3 Floating Point Unit (FPU)

The Cortex-M4 platform supports Floating Point Unit (FPU). The FPU implements the
single precision variant of the ARMv7-M Floating-Point Extension (FPv4-SP), which
supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square root operations. FPU also provides conversions between fixed-point and floating-
point data formats, and floating-point constant instructions.
The FPU provides floating-point computation functionality that is compliant with the
ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred
to as the IEEE 754 standard. The FPU contains 32 single-precision extension registers,
which you can also access as 16 doubleword registers for load, store, and move
operations.

4.2.4.4 Memory Protection Unit (MPU)

The Cortex-M4 platform supports Memory Protection Unit (MPU). The MPU enforces
privilege rules, separates processes, and enforces access rules to memory, and supports
the standard ARMv7 Protected Memory System Architecture model. The MPU provides
full support for:
• Protection regions
• Overlapping protection regions, with ascending region priority:
7 = highest priority
0 = lowest priority
• Access permissions
• Exporting memory attributes to the system
MPU mismatches and permission violations invoke the programmable-priority
MemManage fault handler. You can use the MPU to:
• Enforce privilege rules
• Separate processes
• Enforce access rules

4.2.4.5 Tightly-Coupled Memory (TCM)

The Cortex-M4 uses Tightly-Coupled Memory (TCM) to perform low-latency memory
operations including speculative read accesses. The TCM is split between upper and
lower regions with each TCM interface operating independently of each other.
The Cortex-M4 supports 32-bit ECC error detection and correction for the TCM
memories. TCM ECC can indicate to the processor that an access must be retried to
return the corrected data.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

90 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Because AHB-Lite does not support write data strobes when accessing AHB-Lite slaves
from an AXI master, care must be taken not to generate transactions that have partial
strobes. Make sure to not have unaligned accessing to TCM from an AXI master. For
example, when writing data to TCM from A53, ensure every write strobe address is 64bit
aligned. When the MMU is enabled, the TCM memory range must have the
MT_DEVICE_NGNRNE type attribute set. This will avoid A53 sparse writes to the
TCM memory region.

4.2.5 Local Memory Controller (LMEM)

The Local Memory Controller provides the Arm®Cortex-M4™ processor with tightly-
coupled processor-local memories and bus paths to all slave memory spaces.

4.2.5.1 LMEM Block Diagram

The Cortex-M4 processor has a modified 32-bit Harvard bus architecture. Using a 32-bit
address space, low-order addresses (0x0000_0000 through 0x1FFF_FFFF) use the
Processor Code (PC) bus, and high-order addresses (0x2000_0000 through
0xFFFF_FFFF) use the Processor System (PS) bus. As the bus names imply, normal
operation has code accesses on the PC bus and data accesses on the PS bus.
This device has been augmented with tightly-coupled memories for the PC and PS buses.
The memories include RAMs and caches. These local memories provide zero wait state
access to RAM and cacheable address spaces.
The local memory controller includes four memory controllers and their attached
memories:
• SRAM lower (SRAM_L) controller via the PC bus
• SRAM upper (SRAM_U) controller via the PS bus
• Cache memory controller via the PC bus
• Cache memory controller via the PS bus

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 91
ARM Cortex M4 Platform (M4)

SRAM upper Cache tag arrays Cache data arrays

LMEM

Cache I&D code bus Code cache

controller
Processor Code (PC) bus LMEM

Crossbar switch
Cortex-M4 core

controller CCM bus

Backdoor port

CSM bus
Cache system bus System cache
Processor System (PS) bus
controller

SRAM lower Cache tag arrays Cache data arrays

Figure 4-3. Local memory controller block diagram

NOTE
The SRAM and cache controllers reside within the LMEM, but
the single-port synchronous RAM arrays used by these
controllers are external.
The LMEM contains address decode logic for the PC and PS buses. This logic routes the
core's accesses to the various system resources. The address spaces are device-specific
and are specified in the device's Chip Configuration chapter.

4.2.5.2 Cache features

A cache is a block of high-speed memory locations containing address information
(commonly known as a tag) and the associated data. The purpose is to decrease the
average time of a memory access. Caches operate on two principles of locality:
• Spatial locality — An access to one location is likely to be followed by accesses
from adjacent locations (for example, sequential instruction execution or usage of a
data structure).
• Temporal locality — An access to an area of memory is likely to be repeated within a
short time period (for example, execution of a code loop).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

92 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

To minimize the quantity of control information stored, the spatial locality property is
used to group several locations together under the same tag. This logical block is
commonly known as a cache line.
When data is loaded into a cache, access times for subsequent loads and stores are
reduced, resulting in overall performance benefits. An access to information already in a
cache is known as a cache hit, and other accesses are called cache misses.
Normally, caches are self-managing, with the updates occurring automatically. Whenever
the processor wants to access a cacheable location, the cache is checked. If the access is a
cache hit, the access occurs immediately. Otherwise, a location is allocated and the cache
line is loaded from memory. Different cache topologies and access policies are possible.
However, they must comply with the memory coherency model of the underlying
architecture.
Caches introduce a number of potential problems, mainly because of:
• memory accesses occurring at times other than when the programmer would
normally expect them,
• the existence of multiple physical locations where a data item can be held.
The local memory controller supports three modes of operation:
1. Write-through — access to address spaces with this cache mode are cacheable.
• A read miss on the input bus causes a line read on the output bus of a 32-byte-
aligned memory address containing the desired address. This miss data is loaded
into the cache and is marked as valid and not modified.
• A write-through read hit to a valid cache location returns data from the cache
with no output bus access.
• A write-through write miss bypasses the cache and writes to the output bus (no
allocate on write miss policy for write-through mode spaces).
• A write-through write hit updates the cache hit data and writes to the output bus.
2. Write-back — access to address spaces with this cache mode are cacheable.
• A write-back read miss on the input bus will cause a line read on the output bus
of a 32-byte-aligned memory address containing the desired address. This miss
data is loaded into the cache and marked as valid and not modified.
• A write-back read hit to a valid cache location will return data from the cache
with no output bus access.
• A write-back write miss will do a "read-to-write" (allocate on write miss policy
for write-back mode spaces). A line read on the output bus of a 16 byte aligned
memory address containing the desired write address is performed. This miss
data is loaded into the cache and marked as valid and modified; and the write
data will then update the appropriate cache data locations.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 93
ARM Cortex M4 Platform (M4)

3. Non-cacheable — access to address spaces with this cache mode are not cacheable.
These accesses bypass the cache and access the output bus.

4.2.5.3 LMEM Function

The LMEM receives the following requests:
• Core master bus requests on the Processor Code (PC) bus,
• Core master bus requests on the Processor System (PS) bus, and
• SRAM controller requests from all other bus masters on the backdoor port.
The LMEM address decode logic routes these accesses and also provides any crossbar
switch slave target logic. Finally, the Local Memory controller provides the needed MPU
connections for checking all SRAM controller and cacheable accesses.
The programming model for the Code and System Caches is accessed via the core's
Private Peripheral Bus (PPB).

4.2.5.3.1 Processor Code accesses

Processor Code accesses are routed to the SRAM_L if they are mapped to that space. All
other PC accesses are routed to the Code Cache Memory Controller. This controller then
processes the cacheable accesses as needed, while bypassing the non-cacheable, cache
write-through, cache miss, and cache maintenance accesses to the CCM bus and the
crossbar switch using the Master0 port.

4.2.5.3.2 Processor System accesses

Processor System accesses are routed to the SRAM_U if they are mapped to that space.
All other PS accesses are routed to the PS Cache Memory Controller. This controller then
processes the cacheable accesses as needed, while bypassing the non-cacheable, cache
write-through, cache miss, and cache maintenance accesses to the CCM bus and the
crossbar switch using the Master1 port.

4.2.5.3.3 Backdoor port accesses

All LMEM backdoor port accesses are for the SRAM controller. These accesses go to the
SRAM_L or the SRAM_U depending on their specific address.

4.2.5.3.4 SRAM Function

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

94 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.2.5.3.4.1 SRAM Configuration

The figure below shows how the SRAM controller is configured.

Cache Cache
Tag Arrays Data Arrays

Code Cache
Backdoor S0 Slave Port

M0 Master Port
Frontdoor
SRAM_U
Code bus LMEM
Controller SRAM Controller
System bus SRAM_L

M1 Master Port

System Cache

Cache Cache
Tag Arrays Data Arrays

Figure 4-4. SRAM Configuration

4.2.5.3.4.2 SRAM Arrays

The on-chip SRAM is split into two logical arrays, SRAM_L and SRAM_U.
From equal-sized memories, valid address ranges for SRAM_L and SRAM_U are then
defined as:
• SRAM_U = 0x2000_0000 - (0x2000_0000 + SRAM_size/2)

4.2.5.3.4.3 SRAM accesses

The SRAM is split into two logical arrays that are 64-bits wide:
• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor
port.
• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the
backdoor port.
The backdoor port makes the SRAM accessible to the non-core bus masters (such as
DMA).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 95
ARM Cortex M4 Platform (M4)

The figure below illustrates the SRAM accesses within the device.

SRAM_L

Frontdoor
Backdoor
SRAM controller

SRAM_U

Figure 4-5. SRAM access diagram

The following simultaneous accesses can be made to different logical halves of the
SRAM:
• Core code and core system
• Core code and non-core master
• Core system and non-core master
NOTE
Two non-core masters cannot access SRAM simultaneously.
The required arbitration and serialization is provided by the
crossbar switch. The SRAM_{L,U} arbitration is controlled by
the SRAM controller based on the configuration bits in the
MCM module.

4.2.5.3.5 Cache Function

The caches on this device are structured as follows. Both caches have a 2-way set-
associative cache structure with a total size of 32 KBytes. The caches have a 32-bit
address, 64-bit data paths and a 32-byte line size. The cache tags and data storage use
single-port, synchronous RAMs.
For these 16-KByte caches, each cache TAG function uses two 256 x 22-bit RAM arrays
and the cache DATA function uses two 1024 x 32-bit RAM arrays. The cache TAG
entries store 20 bits of upper address as well as a modified and valid bit per cache line.
The cache DATA entries store eight byes of code or data.
All normal cache accesses use physical addresses. This leads to the following cache
address use:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

96 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

CACHE - 16 KByte size = (256 sets) x (32-byte lines) x (2-way set associative)
TAG:

DATA
• address[31:13] not used
• address[12:5] used to select one of 256 sets
• address[4:2] used to select one of eight 32-bit words within a set
• address[1:0] used to select the byte within the 32-bit word

4.2.5.3.6 Cache Control

The Code and System Caches are disabled at reset. Cache tag and data arrays are not
cleared at reset. Therefore, to enable the caches, cache commands must be done to clear
and initialize the required tag array bits and to configure and enable the caches.

4.2.5.3.6.1 Cache set commands

The cache set commands may operate on:
• all of way 0,
• all of way 1, or
• all of both ways (complete cache).
Cache set commands are initiated using the upper bits in the CCR register. Cache set
commands perform their operation on the cache independent of the cache enable bit,
CCR[ENCACHE].
A cache set command is initiated by setting the CCR[GO] bit. This bit also acts as a busy
bit for set commands. It stays set while the command is active and is cleared by the
hardware when the set command completes.
Supported cache set commands are given in the table below. Set commands work as
follows:
• Invalidate − Unconditionally clear valid and modify bits of a cache entry.
• Push − Push a cache entry if it is valid and modified, then clear the modify bit. If
entry not valid or not modified, leave as is.
• Clear − Push a cache entry if it is valid and modified, then clear the valid and modify
bits. If entry not valid or not modified, clear the valid bit.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 97
ARM Cortex M4 Platform (M4)

Table 4-4. Cache Set Commands

CCR[27:24] Command
PUSH INVW1 PUSH INVW0
W1 W0
0 0 0 0 NOP
0 0 0 1 Invalidate all way 0
0 0 1 0 Push all way 0
0 0 1 1 Clear all way 0
0 1 0 0 Invalidate all way 1
0 1 0 1 Invalidate all way 1; invalidate all way 0 (invalidate cache)
0 1 1 0 Invalidate all way 1; push all way 0
0 1 1 1 Invalidate all way 1; clear all way 0
1 0 0 0 Push all way 1
1 0 0 1 Push all way 1; invalidate all way 0
1 0 1 0 Push all way 1; push all way 0 (push cache)
1 0 1 1 Push all way 1; clear all way 0
1 1 0 0 Clear all way 1
1 1 0 1 Clear all way 1; invalidate all way 0
1 1 1 0 Clear all way 1; push all way 0
1 1 1 1 Clear all way 1; clear all way 0 (clear cache)

After a reset, complete an invalidate cache command before using the cache. It is possible
to combine the cache invalidate command with the cache enable. That is, setting CCR to
0x8500_0003 will invalidate the cache and enable the cache and write buffer.

4.2.5.3.6.2 Cache line commands

Cache line commands operate on a single line in the cache at a time. Cache line
commands can be performed using a physical or cache address.
• A cache address consists of a set address and a way select. The line command acts on
the specified cache line.
• Cache line commands with physical addresses first search both ways of the cache set
specified by bits [11:4] of the physical address. If they hit, the commands perform
their action on the hit way.
Cache line commands are specified using the upper bits in the CLCR register. Cache line
commands perform their operation on the cache independent of the cache enable bit
(CCR[ENCACHE]). Using a cache address, the command can be completely specified
using the CLCR register. Using a physical address, the command must also use the
CSAR register to specify the physical address.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

98 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

A line cache command is initiated by setting the line command go bit (CLCR[LGO] or
CSAR[LGO]). This bit also acts a a busy bit for line commands. It stays set while the
command is active and is cleared by the hardware when the command completes.
The CLCR[27:24] bits select the line command as follows:
Table 4-5. Cache Line Commands
CLCR[27:24] Command
LACC LADSEL LCMD
0 0 00 Search by cache address and way
0 0 01 Invalidate by cache address and way
0 0 10 Push by cache address and way
0 0 11 Clear by cache address and way
0 1 00 Search by physical address
0 1 01 Invalidate by physical address
0 1 10 Push by physical address
0 1 11 Clear by physical address
1 0 00 Write by cache address and way
1 0 01 Reserved, NOP
1 0 10 Reserved, NOP
1 0 11 Reserved, NOP
1 1 xx Reserved, NOP

4.2.5.3.6.2.1 Executing a series of line commands using cache addresses

A series of line commands with incremental cache addresses can be performed by just
writing to the CLCR.
• Place the command in CLCR[27:24],
• Set the way (CLCR[WSEL]) and tag/data (CLCR[TDSEL]) controls as needed,
• Place the cache address in CLCR[CACHEADDR], and
• Set the line command go bit (CLCR[LGO]).
When one line command completes, initiate the next command by following these steps:
• Increment the cache address (at bit 2 to step through data or at bit 4 to step through
lines), and
• Set the line command go bit (CLCR[LGO]).

4.2.5.3.6.2.2 Executing a series of line commands using physical addresses

Perform a series of line commands with incremental physical addresses using the
following steps:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 99
ARM Cortex M4 Platform (M4)

• Write to the CLCR.

• Place the command in CLCR[27:24]
• Set the tag/data (CLCR[TDSEL]) control
• Place the physical address in CSAR[PHYADDR] and set the line command go bit
(CSAR[LGO]).
When one line command completes, initiate the next command by following these steps:
• Increment the physical address (at bit 2 to step through data or at bit 4 to step through
lines), and
• Set the line command go bit (CSAR[LGO]).
The line command go bit is shared between the CLCR and CSAR registers, so that the
above steps can be completed in a single write to the CSAR register.

4.2.5.3.6.2.3 Line command results

At completion of a line command, the CLCR register contains information on the initial
state of the line targeted by the command. For line commands with cache addresses, this
information is read before the line command action is performed from the targeted cache
line. For line commands with physical addresses, this information is read on a hit before
the line command action is performed from the hit cache line or has initial valid bit
cleared if the command misses. In general, if the valid indicator (CLCR[LCIVB] is
cleared, the targeted line was invalid at the start of the line command and no line
operation was performed.
Table 4-6. Line command results
CLCR[22:20] For cache address commands For physical address commands
LCWA LCIMB LCIVB
Y
0 0 0 Way 0 line was invalid No hit
0 0 1 Way 0 valid, not modified Way 0 valid, not modified
0 1 0 Way 0 line was invalid No hit
0 1 1 Way 0 valid and modified Way 0 valid and modified
1 0 0 Way 1 line was invalid No hit
1 0 1 Way 1 valid, not modified Way 1 valid, not modified
1 1 0 Way 1 line was invalid No hit
1 1 1 Way 1 valid and modified Way 1 valid and modified

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

100 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

At completion of a line command other than a write, the CCVR (Cache R/W Value
Register) contains information on the initial state of the line tag or data targeted by the
command. For line commands, CLCR[TDSEL] selects between tag and data. If the line
command used a physical address and missed, the data is don't care. For write commands,
the CCVR holds the write data.

4.2.6 Miscellaneous Control Module (MCM)

The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control
functions.

4.2.6.1 MCM features

The MCM includes the following features:
• Program-visible information on the platform configuration and revision

4.2.6.2 MCM Interrupts

The MCM generates the following interrupt requests:
• Normal interrupt

4.2.6.2.1 Normal interrupt

The MCM's normal interrupt is generated if any of the following is true:
• ISCR[ETBI] is set, when
• The ETB counter is enabled, ETBCC[CNTEN] = 1
• The ETB count expires
• The response to counter expiration is a normal interrupt, ETBCC[RSPT] = 01

4.2.7 LMEM Memory Map/Register Definition

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 101
ARM Cortex M4 Platform (M4)

LMEM memory map

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
E008_2000 Cache control register (LMEM_PCCCR) 32 R/W 0000_0000h 4.2.7.1/102
E008_2004 Cache line control register (LMEM_PCCLCR) 32 R/W 0000_0000h 4.2.7.2/103
E008_2008 Cache search address register (LMEM_PCCSAR) 32 R/W 0000_0000h 4.2.7.3/106
E008_200C Cache read/write value register (LMEM_PCCCVR) 32 R/W 0000_0000h 4.2.7.4/107
E008_2800 Cache control register (LMEM_PSCCR) 32 R/W 0000_0000h 4.2.7.5/107
E008_2804 Cache line control register (LMEM_PSCLCR) 32 R/W 0000_0000h 4.2.7.6/109
E008_2808 Cache search address register (LMEM_PSCSAR) 32 R/W 0000_0000h 4.2.7.7/111
E008_280C Cache read/write value register (LMEM_PSCCVR) 32 R/W 0000_0000h 4.2.7.8/112

4.2.7.1 Cache control register (LMEM_PCCCR)

Address: E008_2000h base + 0h offset = E008_2000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0
PUSHW1

PUSHW0
INVW1

INVW0

GO
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ENWRBUF

ENCACHE
R 0
PCCR3

PCCR2
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMEM_PCCCR field descriptions

Field Description
31 Initiate Cache Command
GO
Setting this bit initiates the cache command indicated by bits 27-24. Reading this bit indicates if a
command is active

NOTE: This bit stays set until the command completes. Writing zero has no effect.

0 Write: no effect. Read: no cache command active.

1 Write: initiate command indicated by bits 27-24. Read: cache command active.
30–28 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
27 Push Way 1
PUSHW1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

102 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

LMEM_PCCCR field descriptions (continued)

Field Description
0 No operation
1 When setting the GO bit, push all modified lines in way 1
26 Invalidate Way 1
INVW1

NOTE: If the PUSHW1 and INVW1 bits are set, then after setting the GO bit, push all modified lines in
way 1 and invalidate all lines in way 1 (clear way 1).

0 No operation
1 When setting the GO bit, invalidate all lines in way 1
25 Push Way 0
PUSHW0
0 No operation
1 When setting the GO bit, push all modified lines in way 0
24 Invalidate Way 0
INVW0

NOTE: If the PUSHW0 and INVW0 bits are set, then after setting the GO bit, push all modified lines in
way 0 and invalidate all lines in way 0 (clear way 0).

0 No operation
1 When setting the GO bit, invalidate all lines in way 0.
23–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
3 Forces no allocation on cache misses (must also have ACCR2 asserted)
PCCR3
2 Forces all cacheable spaces to write through
PCCR2
1 Enable Write Buffer
ENWRBUF
0 Write buffer disabled
1 Write buffer enabled
0 Cache enable
ENCACHE
0 Cache disabled
1 Cache enabled

4.2.7.2 Cache line control register (LMEM_PCCLCR)

This register defines specific line-sized cache operations to be performed using a specific
cache line address or a physical address.
If a physical address is specified, both ways of the cache are searched, and the command
is only performed on the way which hits.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 103
ARM Cortex M4 Platform (M4)

Address: E008_2000h base + 4h offset = E008_2004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LCWAY

LCIMB

LCIVB
R 0 0 0

LADSEL

TDSEL
LACC
LCMD

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0
WSEL

CACHEADDR LGO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMEM_PCCLCR field descriptions

Field Description
31–28 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
27 Line access type
LACC
0 Read
1 Write
26 Line Address Select
LADSEL
When using the cache address, the way must also be specified in CLCR[WSEL].
When using the physical address, both ways are searched and the command is performed only if a hit.

0 Cache address
1 Physical address
25–24 Line Command
LCMD
00 Search and read or write
01 Invalidate
10 Push
11 Clear

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

104 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

LMEM_PCCLCR field descriptions (continued)

Field Description
23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
22 Line Command Way
LCWAY
Indicates the way used by the line command.
21 Line Command Initial Modified Bit
LCIMB
If command used cache address and way, then this bit shows the initial state of the modified bit
If command used physical address and a hit, then this bit shows the initial state of the modified bit. If a
miss, this bit reads zero.
20 Line Command Initial Valid Bit
LCIVB
If command used cache address and way, then this bit shows the initial state of the valid bit
If command used physical address and a hit, then this bit shows the initial state of the valid bit. If a miss,
this bit reads zero.
19–17 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
16 Tag/Data Select
TDSEL
Selects tag or data for search and read or write commands.

0 Data
1 Tag
15 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
14 Way select
WSEL
Selects the way for line commands.

0 Way 0
1 Way 1
13 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
12–2 Cache address
CACHEADDR
CLCR[11:4] bits are used to access the tag arrays
CLCR[11:2] bits are used to access the data arrays
1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Initiate Cache Line Command
LGO
Setting this bit initiates the cache line command indicated by bits 27-24. Reading this bit indicates if a line
command is active

NOTE: This bit stays set until the command completes. Writing zero has no effect.

NOTE: This bit is shared with CSAR[LGO]

0 Write: no effect. Read: no line command active.

1 Write: initiate line command indicated by bits 27-24. Read: line command active.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 105
ARM Cortex M4 Platform (M4)

4.2.7.3 Cache search address register (LMEM_PCCSAR)

The CSAR register is used to define the explicit cache address or the physical address for
line-sized commands specified in the CLCR[LADSEL] bit.
Address: E008_2000h base + 8h offset = E008_2008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
PHYADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
PHYADDR LGO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMEM_PCCSAR field descriptions

Field Description
31–2 Physical Address
PHYADDR
PHYADDR represents bits [31:2] of the system address.
CSAR[31:12] bits are used for tag compare
CSAR[11:4] bits are used to access the tag arrays
CSAR[11:2] bits are used to access the data arrays
1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Initiate Cache Line Command
LGO
Setting this bit initiates the cache line command indicated by bits 27-24. Reading this bit indicates if a line
command is active

NOTE: This bit stays set until the command completes. Writing zero has no effect.

NOTE: This bit is shared with CLCR[LGO]

0 Write: no effect. Read: no line command active.

1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

106 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.2.7.4 Cache read/write value register (LMEM_PCCCVR)

The CCVR register is used to source write data or return read data for the commands
specified in the CLCR register.
Address: E008_2000h base + Ch offset = E008_200Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMEM_PCCCVR field descriptions

Field Description
DATA Cache read/write Data

For tag search, read or write:

• CCVR[31:12] bits are used for tag array R/W value
• CCVR[11:4] bits are used for tag set address on reads; unused on writes
• CCVR[3:2] bits are reserved

For data search, read or write:

• CCVR[31:0] bits are used for data array R/W value

4.2.7.5 Cache control register (LMEM_PSCCR)

Address: E008_2000h base + 800h offset = E008_2800h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0
PUSHW1

PUSHW0
INVW1

INVW0

GO
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENWRBUF

ENCACHE

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 107
ARM Cortex M4 Platform (M4)

LMEM_PSCCR field descriptions

Field Description
31 Initiate Cache Command
GO
Setting this bit initiates the cache command indicated by bits 27-24. Reading this bit indicates if a
command is active

NOTE: This bit stays set until the command completes. Writing zero has no effect.

0 Write: no effect. Read: no cache command active.

1 Write: initiate command indicated by bits 27-24. Read: cache command active.
30–28 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
27 Push Way 1
PUSHW1
0 No operation
1 When setting the GO bit, push all modified lines in way 1
26 Invalidate Way 1
INVW1

NOTE: If the PUSHW1 and INVW1 bits are set, then after setting the GO bit, push all modified lines in
way 1 and invalidate all lines in way 1 (clear way 1).

0 No operation
1 When setting the GO bit, invalidate all lines in way 1
25 Push Way 0
PUSHW0
0 No operation
1 When setting the GO bit, push all modified lines in way 0
24 Invalidate Way 0
INVW0

NOTE: If the PUSHW0 and INVW0 bits are set, then after setting the GO bit, push all modified lines in
way 0 and invalidate all lines in way 0 (clear way 0).

0 No operation
1 When setting the GO bit, invalidate all lines in way 0.
23–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 Enable Write Buffer
ENWRBUF
0 Write buffer disabled
1 Write buffer enabled
0 Cache enable
ENCACHE
0 Cache disabled
1 Cache enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

108 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.2.7.6 Cache line control register (LMEM_PSCLCR)

This register defines specific line-sized cache operations to be performed using a specific
cache line address or a physical address.
If a physical address is specified, both ways of the cache are searched, and the command
is only performed on the way which hits.
Address: E008_2000h base + 804h offset = E008_2804h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LCWAY

LCIMB

LCIVB
R 0 0 0
LADSEL

TDSEL
LACC

LCMD

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0
WSEL

CACHEADDR LGO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMEM_PSCLCR field descriptions

Field Description
31–28 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
27 Line access type
LACC
0 Read
1 Write
26 Line Address Select
LADSEL
When using the cache address, the way must also be specified in CLCR[WSEL].
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 109
ARM Cortex M4 Platform (M4)

LMEM_PSCLCR field descriptions (continued)

Field Description
When using the physical address, both ways are searched and the command is performed only if a hit.

0 Cache address
1 Physical address
25–24 Line Command
LCMD
00 Search and read or write
01 Invalidate
10 Push
11 Clear
23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
22 Line Command Way
LCWAY
Indicates the way used by the line command.
21 Line Command Initial Modified Bit
LCIMB
If command used cache address and way, then this bit shows the initial state of the modified bit
If command used physical address and a hit, then this bit shows the initial state of the modified bit. If a
miss, this bit reads zero.
20 Line Command Initial Valid Bit
LCIVB
If command used cache address and way, then this bit shows the initial state of the valid bit
If command used physical address and a hit, then this bit shows the initial state of the valid bit. If a miss,
this bit reads zero.
19–17 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
16 Tag/Data Select
TDSEL
Selects tag or data for search and read or write commands.

0 Data
1 Tag
15 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
14 Way select
WSEL
Selects the way for line commands.

0 Way 0
1 Way 1
13 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
12–2 Cache address
CACHEADDR
CLCR[11:4] bits are used to access the tag arrays
CLCR[11:2] bits are used to access the data arrays
1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

110 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

LMEM_PSCLCR field descriptions (continued)

Field Description
0 Initiate Cache Line Command
LGO
Setting this bit initiates the cache line command indicated by bits 27-24. Reading this bit indicates if a line
command is active

NOTE: This bit stays set until the command completes. Writing zero has no effect.

NOTE: This bit is shared with CSAR[LGO]

0 Write: no effect. Read: no line command active.

1 Write: initiate line command indicated by bits 27-24. Read: line command active.

4.2.7.7 Cache search address register (LMEM_PSCSAR)

The CSAR register is used to define the explicit cache address or the physical address for
line-sized commands specified in the CLCR[LADSEL] bit.
Address: E008_2000h base + 808h offset = E008_2808h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
PHYADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
PHYADDR LGO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMEM_PSCSAR field descriptions

Field Description
31–2 Physical Address
PHYADDR
PHYADDR represents bits [31:2] of the system address.
CSAR[31:12] bits are used for tag compare
CSAR[11:4] bits are used to access the tag arrays
CSAR[11:2] bits are used to access the data arrays
1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Initiate Cache Line Command
LGO
Setting this bit initiates the cache line command indicated by bits 27-24. Reading this bit indicates if a line
command is active

NOTE: This bit stays set until the command completes. Writing zero has no effect.

NOTE: This bit is shared with CLCR[LGO]

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 111
ARM Cortex M4 Platform (M4)

LMEM_PSCSAR field descriptions (continued)

Field Description
0 Write: no effect. Read: no line command active.
1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.

4.2.7.8 Cache read/write value register (LMEM_PSCCVR)

The CCVR register is used to source write data or return read data for the commands
specified in the CLCR register.
Address: E008_2000h base + 80Ch offset = E008_280Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMEM_PSCCVR field descriptions

Field Description
DATA Cache read/write Data

For tag search, read or write:

• CCVR[31:12] bits are used for tag array R/W value
• CCVR[11:4] bits are used for tag set address on reads; unused on writes
• CCVR[3:2] bits are reserved

For data search, read or write:

• CCVR[31:0] bits are used for data array R/W value

4.2.8 MCM Memory Map/Register Definition

MCM memory map

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Crossbar Switch (AXBS) Slave Configuration
E008_0008 16 R 0002h 4.2.8.1/113
(MCM_PLASC)
Crossbar Switch (AXBS) Master Configuration
E008_000A 16 R 0003h 4.2.8.2/113
(MCM_PLAMC)
E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) 32 R/W 0000_0000h 4.2.8.3/114
E008_0020 Fault address register (MCM_FADR) 32 R Undefined 4.2.8.4/114
E008_0024 Fault attributes register (MCM_FATR) 32 R Undefined 4.2.8.5/115
E008_0028 Fault data register (MCM_FDR) 32 R Undefined 4.2.8.6/117

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

112 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.2.8.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)

PLASC is a 16-bit read-only register identifying the presence/absence of bus slave

connections to the device’s crossbar switch.
Address: E008_0000h base + 8h offset = E008_0008h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read 0 ASC

Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

MCM_PLASC field descriptions

Field Description
15–8 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's
slave input port.

0 A bus slave connection to AXBS input port n is absent

1 A bus slave connection to AXBS input port n is present

4.2.8.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)

PLAMC is a 16-bit read-only register identifying the presence/absence of bus master

connections to the device's crossbar switch.
Address: E008_0000h base + Ah offset = E008_000Ah

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read 0 AMC

Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

MCM_PLAMC field descriptions

Field Description
15–8 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
port.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 113
ARM Cortex M4 Platform (M4)

MCM_PLAMC field descriptions (continued)

Field Description
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present

4.2.8.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)

The PLACR register selects the arbitration policy for the crossbar masters.
Address: E008_0000h base + Ch offset = E008_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MCM_PLACR field descriptions

Field Description
31–9 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
Reserved This field is reserved.

4.2.8.4 Fault address register (MCM_FADR)

When a properly-enabled cache write buffer error interrupt event is detected, the faulting
address is captured in the MCM_FADR register. The MCM logic supports capturing a
single cache write buffer bus error event; if a subsequent error is detected before the
captured error information has been read from the corresponding registers and the
MCM_ISCR[CWBER] indicator cleared, the MCM_FATR[BEOVR] flag is set.
However, no additional information is captured.
The bits in this register are set by hardware and signaled by the assertion of
MCM_ISCR[CWBER]. Attempted writes to this location are terminated with an error.
Address: E008_0000h base + 20h offset = E008_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ADDRESS
W

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

114 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

* Notes:
• x = Undefined at reset.

MCM_FADR field descriptions

Field Description
ADDRESS Fault address

4.2.8.5 Fault attributes register (MCM_FATR)

When a properly-enabled cache write buffer error interrupt event is detected, the faulting
attributes are captured in the MCM_FATR register.
The bits in this register are set by hardware and signaled by the assertion of
MCM_ISCR[CWBER]. Attempted writes to this location are terminated with an error.
Address: E008_0000h base + 24h offset = E008_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BEOVR

R 0

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BEWT

BEMD

BEDA

R 0 BEMN 0 BESZ 0

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:
• x = Undefined at reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 115
ARM Cortex M4 Platform (M4)

MCM_FATR field descriptions

Field Description
31 Bus error overrun
BEOVR
Indicates if anothercache write buffer bus error is detected before system software has retrieved all the
error information from the original event, this overrun flag is set. The window of time is defined from the
detection of the original cache write buffer error termination until the MCM_ISCR[CWBER] is written with a
1 to clear it and rearm the capture logic. This bit is set by the hardware and cleared whenever software
writes a 1 to the CWBER bit.

0 No bus error overrun

1 Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to
reflect this new bus error.
30–12 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
11–8 Bus error master number
BEMN
Crossbar switch bus master number of the captured cache write buffer bus error. For this device, this
value is always 0x1.
7 Bus error write
BEWT
Indicates the type of system bus access when the error was detected. Since this logic is monitoring data
transfers from the cache write buffer, this bit is always a logical one, signaling a write operation.

0 Read access
1 Write access
6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5–4 Bus error size
BESZ
Indicates the size of the cache write buffer access when the error was detected.

00 8-bit access
01 16-bit access
10 32-bit access
11 Reserved
3–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 Bus error privilege level
BEMD
Indicates the privilege level of the cache write buffer access when the error was detected.

0 User mode
1 Supervisor/privileged mode
0 Bus error access type
BEDA
Indicates the type of cache write buffer access when the error was detected. This attribute is always a
logical one signaling a data reference.

0 Instruction
1 Data

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

116 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.2.8.6 Fault data register (MCM_FDR)

When a properly-enabled cache write buffer error interrupt event is detected, the faulting
data is captured in the MCM_FDR register.
The bits in this register are set by hardware and signaled by the assertion of
MCM_ISCR[CWBER]. For byte and halfword writes, only the accessed byte lanes
contain valid data; the contents of the other bytes are undefined. Attempted writes to this
location are terminated with an error.
Address: E008_0000h base + 28h offset = E008_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R DATA
W

Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:
• x = Undefined at reset.

MCM_FDR field descriptions

Field Description
DATA Fault data

4.3 Messaging Unit (MU)

4.3.1 Overview
The Messaging Unit module enables two processors within the SoC to communicate and
coordinate by passing messages (e.g. data, status and control) through the MU interface.
The MU also provides the ability for one processor to signal the other processor using
interrupts.
Because the MU manages the messaging between processors, the MU uses different
clocks (from each side of the different peripheral buses). Therefore, the MU must
synchronize the accesses from one side to the other. The MU accomplishes
synchronization using two sets of matching registers (Processor A-facing, Processor B-
facing).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 117
Messaging Unit (MU)

Processor A Processor B

Messaging Unit (MU)

Processor A side Processor B side

TX / RX TX / RX
Registers Registers

Status and Status and

Processor A Processor B
Control Control
Peripheral Peripheral
Bus Registers Registers Bus

Sync and Sync and

Control Control
Registers Registers

Generate Generate
Interrupts Interrupts
Interrupts to Interrupts to
Processor A Processor B
interrupt interrupt
controller controller

Figure 4-6. MU Block Diagram

4.3.1.1 Features
The MU includes the following features:
• Messaging control by interrupts or by polling
• The Processor B can take the Processor A out of low-power modes by asserting one
of the above twelve interrupts to the Processor A and vice versa
• Symmetrical processor interfaces with each side supporting the following:
• Four general-purpose interrupt requests reflected to the other side
• Three general-purpose flags reflected to the other side
• Four receive registers with maskable interrupt
• Four transmit registers with maskable interrupt

4.3.1.2 Modes of Operation

The MU supports the modes described in the indicated sections:
• Operating Modes
• Low Power Modes

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

118 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.2 Functional Description

Table 4-7. Major Features of the MU
Major Feature Description
Interprocessor Interrupts • The MU has 12 interrupt sources on each side (Processor A-side, Processor B-
side) that are used for signaling the other processor. The interrupts can be used
for notification of RX/TX events and general-purpose signaling between the
processors.
MU Reset • The Processor A can issue a reset to the entire MU, using a control bit (MUR) in
the Processor A Control Register (ACR).
• The MUR bit is a self-clearing bit.
Processor B Boot Configuration • The Boot Source for Processor B can be configured with the BBOOT bits in the
ACR register.
• Boot Source Options are:
• DMEM Base Address
• IMEM Base Address
• Address 0x00
• The value at reset is loaded from Flash IFR
Processor B Reset Hold • Processor B can be held in reset following any reset event. This is done by
setting the BRSTH bit in the ACR register.
• Processor B will be released from reset when this bit is cleared.
• The value at reset is loaded from Flash IFR.
Processor A/B Clock Enable • The Processor A/B platform clock can be enabled to continue running when
Processor A/B enters Stop Mode, until Processor B/A also enters Stop Mode.
This allows Processor B/A to continue accessing peripherals on Processor A/B's
AIPS bus even when it has entered a Stop Mode.
Status and Control Communications • The MU provides a way for the two cores to communicate using the status and
between Cores control registers present on both the Processor B and Processor A sides of the
MU.
• The status register of one MU side reflects the status of the other MU side.
• The control register is used for control operations, such as enabling an interrupt
and sending an interrupt to the other processor.
Synchronized Message Transfers • The transfer of data messages between cores uses transmit empty and receive
between Cores full flags provided on both sides of the MU.
• The update of these transmit and receive flags is accomplished using a
synchronization mechanism. There is inherent latency between updating the flag
on one side and reflecting its status on other side. For more about latency, see
Event Update Timing
Accessing Shared Memory Directly • For sending data or messages from one MU-side to the other MU-side, the MU
and Avoiding Collisions provides 4 transmit registers and 4 receive registers on each side of the MU.
• The Processor A or Processor B can access shared memory resources of the
SoC directly. However, to avoid simultaneous access to shared memory by both
cores, the MU provides a method (to prevent simultaneous access) using
interrupts and transmit-receive registers for both processors.
Support for Different Clocks in the • The heart of the MU module is the event control mechanism, which synchronizes
Two Cores the access of one MU-side to the other MU-side, because these two MU-sides
can operate using different clocks.
• Formulated event update latency.
Memory-Mapped Registers • The MU is connected as a peripheral under the Peripheral bus on both sides—on
the Processor A-side, the Processor A Peripheral Bus, and on the Processor B-
side, the Processor B Peripheral Bus.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 119
Messaging Unit (MU)

4.3.2.1 Processor A Side Memory-Mapping

The messaging, control, and status registers of the Processor A-side for the MU are
mapped to the Processor A memory as a regular peripheral. The Peripheral bus data bus
is 32 bits wide inside the MU module.

4.3.2.2 Processor B Side Memory-Mapping

The messaging, control, and status registers of the Processor B-side for the MU are
mapped to the Processor B memory as a regular peripheral. The Peripheral bus data bus is
32 bits wide inside the MU module.

4.3.2.3 MU Messaging
The MU provides 32-bit status and control registers to the Processor B and Processor A
sides for control operations (such as interrupts and reset), and for status checking of the
other MU-side.
For messaging, the MU has four, 32-bit write-only transmit registers and four, 32-bit
read-only receive registers on the Processor B and Processor A-sides. These registers are
used for sending messages to each other. These messages can be also be controlled using
the 3 general purpose flags provided in the control and status registers of either MU-side.

4.3.2.3.1 Programmer Model

The messaging logic is used in conjunction with external memory. You have various
messaging methods, which you can use to implement a messaging protocol. Some of
these messages could mean “I have just written a message of N words, starting at offset X
in the memory,” or “I have just finished reading the previous data block that was sent.”
Having the messaging logic independent from the memory array does not restrict you to a
predefined hardware protocol. On the other hand, the software needed to manage the
messaging is short and straightforward.
Most of the messaging mechanisms are symmetric; they are duplicated and are available
on both the Processor B-side and the Processor A-side. The messaging mechanisms are:
• Four, 32-bit write-only transmit registers, which are each reflected in four, read-only
receive registers in the other processor’s side. You can use these registers to transfer
32-bit word messages or frame information of messages written to the shared
memory (number of words, initial address, and message type code).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

120 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• A write to a transmit register on the transmitter side clears a “transmitter empty” bit
in the Status Register on the transmitter side, and sets a “receiver full” bit in the
Status Register on the receiver side. The setting of the bit at the receiver side can
optionally trigger an interrupt at the receiver side (maskable receive interrupt).
• A read of one of the receive registers at the receiver side clears the “receiver full” bit
in the Status Register at the receiver side, and sets the “transmitter empty” bit in the
Status Register on the transmitter side. The setting of the “transmitter empty” bit can
optionally trigger an interrupt at the transmitter side (maskable transmit interrupt).
• Four general purpose flags are reflected in the Status Register on the receiver side
• A read/write access to any reserved location and a write to a read-only register on the
Processor A-side of the MU will generate a module transfer error acknowledge to the
Processor A.
• A read/write access to any reserved location and write to a read-only register on the
Processor B-side of the MU will generate a module transfer error acknowledge to the
Processor B.

4.3.2.3.2 Messaging Examples

The following are messaging examples:
• Passing short messages: Transmit register(s) can be used to pass short messages
from one to four words in length. For example, when a four-word message is desired,
only one of the registers needs to have its corresponding interrupt enable bit set at the
receiver side; the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other register (which
triggers an interrupt at the receiver side).
• Passing frame information: Transmit registers can be used to pass frame
information for long messages written to the shared system (SDRAM and
SyncFLASH). Such frame information normally includes a start address, number of
words, and perhaps a message type code.
• Passing event notices and requests: Events and requests that do not include data
words can be signaled from the Processor B to the Processor A using the general
interrupts, such as acknowledging that a long message was read from the shared
system memory.
• Passing fixed length data: Formatted data with a fixed length can be written in
predetermined locations in the shared memory. A processor can use a general
interrupt (Processor A or Processor B) to signal the other processor that the data is
ready.
• Passing announcements: The three flags can be used by a processor to announce its
current program state or other billboard messages to the other processor.
Figure 4-7 shows the MU registers schematic.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 121
Messaging Unit (MU)

Processor Other
Processor
Messaging Unit (MU)

xCR xSR

xSR xCR

xRR0-3 xTR0-3

xTR0-3 xRR0-3

Figure 4-7. MU Registers

4.3.2.4 Operating Modes

This section describes all functional operation modes of the module.

4.3.2.5 Low Power Modes

This section describes the low power operating modes of the MU module.

4.3.2.5.1 Low Power Clocks and Synchronization

The Processor B and the Processor A clocks operate at different frequencies and from
different sources. The MU design does not assume any frequency relationship between
the Processor A and the Processor B clocks. Be aware, however, that the frequency
relationship affects the MU’s throughput performance.
• The data buffers and control logic of each MU-side operate with its corresponding
clock.

4.3.2.5.2 Processor Low Power Modes

The Processors have four power modes:
• Run
• WAIT
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
122 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• STOP
• DSM
The Processor can be awakened from a low-power mode by any enabled Processor side
MU interrupt, as reflected in the xSR “status” register (RF0–3, TE0–3, GIP0–3 bits are
set) and enabled in the xCR control register. Using these bits, the Processor can actively
control when to wake the other Processor.
While the Processor is in STOP mode (such that the xSR register bits cannot be updated
with events), special logic drives the enabled Processor interrupts directly from the other
Processor-side (instead of from the xSR register).
While the Processor is in STOP mode, the asynchronous Processor interrupt will be
asserted to wake the Processor:
• If any transmit data register of the other Processor-side is full, because of a write to it
(transmit data register); that is, its “empty” bit in the xSR register is cleared while its
corresponding receive interrupt is enabled on the Processor-side.
• If any receive data register of the other Processor-side is empty, because of a read on
the other Processor -side; that is, its “full” bit in the xSR register is cleared while its
corresponding transmit interrupt is enabled on the Processor-side.
• If any general purpose interrupt is set in the xCR register while the corresponding
interrupt is enabled on the Processor-side.
• If the other Processor issues a non-maskable interrupt to the Processor.
The logic enables the other Processor to operate independently while the Processor is in
any power mode (including STOP). However, the Processor power mode change protocol
should be handled with care regarding:
• The interrupts that are enabled on the Processor-side
• The events that could be triggered by the other Processor-side
• The compatibility with the other Processor protocol of entering STOP mode
If the Processor is in STOP mode and an event on the other Processor is triggered, the EP
bit (in the xSR register) will remain high until the Processor wakes up.
Before entering STOP mode, the Processor programmer should verify that the EP bit (in
the xSR register) is cleared. This check is needed to ensure that all pending updates from
the Processor, including the power mode change when STOP or WAIT is executed, will
be updated in the xSR register.
• If the other Processor is in STOP mode or DSM mode, the EP bit (in the xSR
register) may be stuck high; in this case, the Processor need not check the EP bit
before entering STOP mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 123
Messaging Unit (MU)

4.3.2.6 Event Update Timing

Each processor’s MU messaging side (Processor B or Processor A) has a hardware
mechanism to send “event update requests” to the other processor’s side. An “event” is
considered when any information change should be reflected at the Status Register of the
receiving processor. The event update latency is the delay between the event being ready
at one processor and the resulting update at the Status Register of the other processor.
• The minimum event latency is “1 clock of the sending side” + “2 1/2 clocks of the
receiving side”. The minimum case is if there is no event pending when the new
event occurs.
• The maximum event latency is “6 clocks of the sending side” + “6 1/2 clocks of the
receiving side.” The maximum case is if the event occurred just after a previous
event was sent to the other side. The event update latency will vary between the
above-mentioned minimum and maximum latencies, depending on the time at which
the subsequent event is triggered.

4.3.2.7 Interrupts
The MU controls the Processor B interrupt requests to the Processor A, and the Processor
A interrupt requests to the Processor B. This section describes all the interrupts that the
module generates.

4.3.2.7.1 Interrupts to the Processors

There are 12 interrupt sources from the MU to the Processors:
• Four receive interrupts (asserted when the Processors receive full bits are set and
enabled in the xCR register) for each of the receive registers
• Four transmit interrupts (asserted when the Processor transmit empty bits are set and
enabled in the xCR register) for each of the transmit registers
• Four general purpose interrupts (asserted when the GIP bits are set and enabled in the
xCR register)
All the interrupts are maskable in the Processor Control Register (xCR). The MU does
not assume any internal priority of these interrupts. Multiple interrupts (for example,
Receive 0 and Receive 1 interrupts or any of the transmit and general purpose interrupts)
can be asserted at one time. The priority of these interrupts should be resolved by the
interrupt controller at the chip level.
The General Purpose Interrupt Pending bits (GIP0, GIP1, GIP2, and GIP3) should be
cleared by the software (as part of the interrupt service routine) to de-assert the request to
the interrupt controller.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

124 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.2.7.2 General Purpose Interrupt Clearing Sequence

When a Processor writes to the general interrupt bit (GIR), the write event is
synchronized to the other Processor clock to set the general interrupt request pending bit
(GIP). When the GIP bit is set, and if the general purpose interrupt is enabled on the
transmitting Processor side (GIE bit is set), then the receiving Processor general purpose
interrupt is issued to the transmitting Processor. The transmitting Processor clears this
interrupt by writing a “1” on the GIP bit. The interrupt is de-asserted as soon as the GIP
bit is written. The write event of the GIP bit is synchronized to the other Processor clock.
The synchronized signal clears the GIR bit. The software should not write the GIR bit
again until the GIR bit is cleared.

4.3.2.8 Interrupt Messaging Protocols

4.3.2.8.1 Messaging Protocols using Interrupts

The example below describes a four-word messaging sequence sent by the Processor to
the other Processor.
In this example, the first, second, and third receive interrupts are disabled, and the fourth
receive interrupt is enabled. We write registers sequentially for n = 0, 1, 2, 3. For n = 0, 1,
2, the interrupts are disabled, therefore no interrupt will go to the other core (although
interrupt conditions occur). For n = 3, the interrupt is enabled, and the last Receive
Interrupt request is generated.
1. Write Sequence
• The Processor writes the message information sequentially to its Transmit
Registers 0, 1, 2.
• When the write to the Transmit Register 3 occurs, the RF3 bit of the xSR is set
after synchronization, and it immediately trigger the Receive 3 interrupt to the
other Processor.
2. Read Sequence
• The other Processor receives the Receive 3 interrupt and starts reading the
message transferred from the receive registers.
• After Receive Register 3 is read, the interrupt bit is cleared.
Figure 4-8 shows the programmer’s model of a messaging protocol using transmit and
receive registers. Use Table 4-8 and Figure 4-8 to understand the generalized protocol
sequence.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 125
Messaging Unit (MU)

Table 4-8. Interrupt Messaging Protocol (Generalized)

Sequence Action Description
1 Processor A Data write A data write to the ATRn register by Processor A is
immediately reflected in the Processor B BRRn register.
2 Clear Tx Empty bit and Set Rx Full The data write to the ATRn register
bit • Clears the transmitter empty bit (TEn) in the Processor
A Transmit Status Register
• Sets the receiver full bit (RFn) in the Processor B
Receive Status Register
3 Generate Receive Interrupt request The setting of the receiver full bit (RFn) in the Receive Status
Register generates a Receive Interrupt request to Processor
B.
4 Processor B Data read After receiving the Receive Interrupt request, Processor B
performs a data read of the BRRn register.
5 Clear Rx Full bit and Set Tx Empty Reading the data out of the BRRn register
bit • Clears the receiver full bit (RFn) in the Processor B
Receive Status Register
• Sets the transmitter empty bit (TEn) in the Processor A
Transmit Status Register
6 Generate Transmit Interrupt request The setting of the transmitter empty bit (TEn) in the Transmit
Status Register generates a Transmit Interrupt request to
Processor A.

Processor A Processor B

Messaging Unit (MU)

Data write Transmitter side Receiver side Data read

Registers
Registers

1 4

Tx Status Rx Status
2 5
read from 4th TEn clear
RFn write from 4th
set Rx Full
Tx Empty
receive register set clear transmit register
triggers interrupt triggers interrupt

Tx Control Rx Control

6 TIEn Interrupt Interrupt RIEn 3

Enable Enable
Transmit Receive
interrupt interrupt
request request

Figure 4-8. Messaging Model Using Transmit and Receive Registers

NOTE
The Transmit registers can be used to pass frame information
on long messages written to the shared memory. Such frame

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

126 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

information would typically include an initial address, number

of words, and perhaps a message type code.
The messaging hardware can be used by software to implement messaging protocols for a
wide array of message types. Full support is given for both interrupt and polling
management schemes.

4.3.2.8.2 Messaging Protocols using Event Interrupts

Events and requests that do not include data words can be signaled from the Processor B
to the Processor A using the two general interrupts.
Formatted data with a fixed length can be written in predetermined locations in the shared
memory. A processor can use a general purpose interrupt to signal the other processor
that the data is ready.
The three flags can be used by a processor to announce to the other processor the
program state it is currently in, or to announce similar messages.
Table 4-9 and Figure 4-9 describe the event sequence when the Processor triggers an
interrupt.
Table 4-9. Interrupt Messaging Protocol (Generalized)
Sequence Action Description
1 Processor A sets General Interrupt Processor A sets its associated General Interrupt request bit
request bit (GIRn = 1) in the control register (ACR).
2 General Interrupt Request Pending The General Interrupt Request Pending status bit (GIPn) in
status bit is set the status register (BSR) is set to "1"
3 General Interrupt request to Setting the GIPn bit generates the General Interrupt request
Processor B is generated to Processor B (Interrupt Request Enable bit, GIEn, must be
set for Processor B)
4 Processor B reads status register The Processor B reads the GIPn bit in the BSR register.
5 Processor B services the interrupt -
6 Processor B sets GIPn bit to clear The Processor B writes "1" to the corresponding GIPn bit to
interrupt clear the interrupt
7 GIRn bit is cleared Setting the GIPn bit to "1" clears the General Interrupt request
bit (GIRn) in the Processor A control register (ACR).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 127
Messaging Unit (MU)

Processor A Processor B

Messaging Unit (MU)

4
Control Status Read GIPn bit
Services
5
Interrupt
1 GIRn 2 GIPn
set set int pend 6
int req 7 clear Write "1" to clear

General Purpose
ACR BSR
Interrupt Request
Register Register
OR'd with other
requests
Control

Interrupt 3 General Purpose

GIEn
Enable Interrupt Request

BCR
Register

Figure 4-9. Messaging Model Using a General Purpose Interrupt

4.3.2.9 Exclusive Access to Shared Memory

You can use the MU to signal one processor about its current access to the shared
memory, so that the data is not overwritten by the other processor during the exclusive
memory access period.
The following tables describe the signaling protocol that the Processor A uses to inform
the Processor B about its current access (write) to the shared memory, assuming that the
set of bits and registers (GIR0 bit, BRR0 register, BTR0 register, GIR0 bit, ARR0
register, ATR0 register) are reserved to support exclusive access to the shared memory
protocol.
Table 4-10. How the Processor A Performs an Exclusive Access to Shared Memory
Sequence Action Description
1 Processor A sends GIRn request to When the Processor A wants to perform an exclusive access
Processor B using Processor A to the shared memory, the Processor A sends an GIR0
control register request to the Processor B.
2 Processor A sends an exclusive- The Processor A will send an exclusive-access request
access request using a transmit data (command, location, and length of target access) to
register (ATRn) Processor B using a selected transmit data register (ATR0).
3 Processor A waits for a dedicated The Processor A waits for a dedicated interrupt (as an
interrupt from Processor B acknowledgement) triggered by the Processor B before
proceeding.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

128 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Table 4-10. How the Processor A Performs an Exclusive Access to Shared Memory
(continued)
Sequence Action Description
4 Processor A accesses shared After receiving a dedicated interrupt from the Processor B,
memory Processor A proceeds.

Table 4-11. How the Processor B Scans for Transaction Information

Sequence Action Description
1 Processor B receives an interrupt -
from a receive data register (BRRn)
2 Processor B reads the receive data -
register (BRRn)
3 Processor B scans the receive data For transaction information (whether Processor A has
register contents requested an exclusive-access)

Table 4-12. How the Processor B Accepts Exclusive Access by Processor A

Sequence Action Description
1 Processor B triggers a dedicated Processor B acknowledges the Processor A request by
interrupt triggering a dedicated interrupt (ack) to the Processor A.
2 Processor B sends a code message Along with the acknowledge interrupt, the Processor B sends
to Processor A a code message to the Processor A through the selected
transmit register (BTRn). The message informs the Processor
A that it can exclusively access the shared memory.

Table 4-13. How the Processor B Rejects Exclusive Access by Processor A

Sequence Action Description
1 Processor B ignores Processor A If the Processor B does not want to give go-ahead permission
request for exclusive access to the Processor A, Processor B ignores the exclusive access
request.

4.3.2.10 Packet Data Transfers

The following example describes the packet transfer sequence between the Processor B
and Processor A subsystems:
Table 4-14. Packet Data Transfer Sequence
Action Sequence Description
Processor B requests DMA 1 The Processor B sends a DMA request to initiate the packet data
transfer

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 129
Messaging Unit (MU)

Table 4-14. Packet Data Transfer Sequence (continued)

Action Sequence Description
DMA data transfer 2 DMA acknowledges.
3 DMA starts transferring data from the specified Processor B location
to the specified shared memory
4 DMA interrupts the Processor B to signal that the packet transfer
has finished.
Processor B informs Processor A 5 Using an MU Processor B-side transmit register, the Processor B
that data is in shared memory sends a packet information message to the Processor A to inform
the Processor A of the arrival of new packet data that is stored in
shared memory . The message contains the command, location,
and length of packet data information.
Processor A receives interrupt 6 The Processor A receives an interrupt (assuming its corresponding
Processor A MU-side receive interrupt is enabled), and the pending
processing task becomes active and processes packet data from
memory.
Processor A reads data, writes data 7 The Processor A reads or processes packet data from shared
memory.
8 The Processor A writes the result from packet processing to a
separate buffer.
Processor A informs Processor B 9 After the processing of the packet data finishes, the Processor A
that transfer is finished informs the Processor B (using the MU Processor A-side transmit
register, ATRn).
Processor A sends interrupt to 10 The Processor B receives the next interrupt from the Processor A, in
Processor B (request for more data) which the Processor A requests more packet data.

4.3.2.11 MU Resets
The MU has two sources of reset, and each reset has a different function from the MU or
system perspective.
• One asynchronous system that is connected to both sides of the MU interface.
• One programmable hardware reset (MUR bit) in the ACR register (on the Processor
A-side).
Table 4-15. MU programmable resets
Reset Description
Processor A MU reset • Processor A MU Reset bit (MUR) of the ACR register
• The MUR reset affects the messaging section on both the Processor A and the
Processor B sides. The MUR reset causes all control and status registers to
return to their default values and all internal states to be cleared.
• It is up to the Processor A software to decide whether to use the MUR reset or
not.
• The instruction immediately following assertion of the MUR bit should not write to
MU registers. Such a write may be overwritten by the reset sequence and the
register will remain with the reset value. You should wait at least one instruction
(after assertion of the MUR bit) before attempting a write to MU registers.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

130 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

After issuing MUR bit reset events, the Processor A programmer can verify that the reset
sequence on the Processor B-side has ended, by checking the RS bit in the ASR register.
NOTE
MUR bit assertion is a delicate operation because it affects the
other side’s registers asynchronously. MUR bit assertion may
cause unpredictable behavior if, for example, the Processor B is
concurrently testing an MU register bit (TE bit in Processor B
SR register). Before asserting the MUR bit, you should verify
that the Processor B is not presently engaged in an MU
signalling activity.

4.3.3 Software Restrictions

This section describes certain software restrictions when accessing the MU.

4.3.3.1 General Restrictions

This section lists the restrictions that apply to both the sides (Processor A, Processor B)
of the MU.

4.3.3.1.1 Write-After-Write to a Transmit Register

A write to a transmit register signals the receiver side that data is ready for retrieval.
• Writing to the transmit register again without verifying that the data was retrieved is
prohibited, because the transmitter side has no way of knowing the exact time that
the receiver will attempt to retrieve the data.
• Before attempting to write the transmit register again, the transmitter side should
wait for a “Transmitter Empty” interrupt, or should poll the “Transmitter Empty” bit
in the Status Register.
• Failure to follow this restriction may result in the wrong data being read on the
receiver side of the MU.

4.3.3.1.2 Read-After-Read from a Receive Register

A read of a receive register signals the transmitter side that data can be written to that
register. In the same way, the receiver processor should not read a receive register before
receiving a “Receiver Full” interrupt or polling the “Receiver Full” bit in the Status
Register.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 131
Messaging Unit (MU)

• Reading the receive register again without verifying that the data was written is
prohibited, because the receiver side has no way of knowing the exact time that the
transmitter will attempt to write the data.
• Before attempting to read the receive register again, the receiver side should wait for
a “Receiver Full” interrupt, or should poll the “Receiver Full” bit in the Status
Register.
• Failure to follow this restriction may result in the wrong data being written on the
transmitter side of the MU.

4.3.3.2 Processor Restrictions

This section lists the restrictions that apply each side of the processor in the MU.

4.3.3.2.1 Before Entering Low Power Mode

Before entering Low Power mode, the Processor should verify that the Processor Event
Pending (EP) bit in the Status Register is cleared.
• If the Event Pending bit (EP) is still set to “1”, then the Processor should wait and
poll the EP bit until it is cleared, before executing the LPM instruction.
• Note that if the other Processor is in Low Power mode (programmed for clock gating
in CCM), the EP bit may be stuck high. In this case, the other Processor clock must
be turned ON to get the EP bit cleared before the Processor can enter Low Power
mode.
• To discover which power mode the other Processor is in, the Processor can check the
PM bits in the xSR register.

4.3.3.2.2 Before Setting a General Interrupt Request Bit (GIR0–3)

Before setting a General Interrupt Request bit (GIR0–3), you must verify that the GIRn
bit is cleared, which means that a general interrupt is not pending. Generally, setting the
GIRn bit while the bit is set to “1” will be ignored, but in some cases it may issue a
second interrupt. This restriction is meant to prevent this indeterministic behavior.

4.3.3.2.3 Reset Bit Restrictions

The reset bit (MUR, HR) restrictions are:
• Before asserting the MUR bit in the ACR register, verify that the Processor B-side is
not engaged in some MU activity.
• Do not write to an MU register in the instruction immediately after the assertion of
the MUR bit in the ACR register, because the written data can be overridden by the
reset value.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

132 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.4 MU Processor A-side Memory Map/Register Definition

This section contains the detailed register descriptions for the Processor A-side MU
registers.
MUA memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30AA_0000 Processor A Transmit Register 0 (MUA_ATR0) 32 R/W 0000_0000h 4.3.4.1/133
30AA_0004 Processor A Transmit Register 1 (MUA_ATR1) 32 R/W 0000_0000h 4.3.4.2/134
30AA_0008 Processor A Transmit Register 2 (MUA_ATR2) 32 R/W 0000_0000h 4.3.4.3/135
30AA_000C Processor A Transmit Register 3 (MUA_ATR3) 32 R/W 0000_0000h 4.3.4.4/135
30AA_0010 Processor A Receive Register 0 (MUA_ARR0) 32 R 0000_0000h 4.3.4.5/136
30AA_0014 Processor A Receive Register 1 (MUA_ARR1) 32 R 0000_0000h 4.3.4.6/137
30AA_0018 Processor A Receive Register 2 (MUA_ARR2) 32 R 0000_0000h 4.3.4.7/137
30AA_001C Processor A Receive Register 3 (MUA_ARR3) 32 R 0000_0000h 4.3.4.8/138
30AA_0020 Processor A Status Register (MUA_ASR) 32 R/W 00F0_0080h 4.3.4.9/139
4.3.4.10/
30AA_0024 Processor A Control Register (MUA_ACR) 32 R/W 0000_0000h
142

4.3.4.1 Processor A Transmit Register 0 (MUA_ ATR0)

Use Processor A Transmit Register 0 (ATR0, 32-bit, write-only) to transmit a message or

data to the Processor B.
• You can only write to the ATR0 register when the TE0 bit in ASR register is set to
“1”.
• Reading the ATR0 register returns all zeros.
Address: 30AA_0000h base + 0h offset = 30AA_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ATR0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUA_ATR0 field descriptions

Field Description
ATR0
Processor A Transmit Register 0. (Write-only)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 133
Messaging Unit (MU)

MUA_ATR0 field descriptions (continued)

Field Description
• Data written to the ATR0 register is reflected on the Processor B-side in the Processor B Receive
Register 0 (BRR0). The ATR0 and BRR0 registers are not double-buffered—a write to the ATR0
register overrides the data readable at the BRR0 register.
• A write to the transmit register clears a “transmitter empty” bit (TE0) in the Processor A Status
Register (ASR) on the transmitter side, and sets a “receiver full” bit (RF0) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 0 on the Processor B-side).
• Any write to the ATR0 register will update all status information.

4.3.4.2 Processor A Transmit Register 1 (MUA_ATR1)

Use Processor A Transmit Register 1 (ATR1, 32-bit, write-only) to transmit a message or

data to the Processor B.
• You can only write to the ATR1 register when the TE1 bit in ASR register is set to
“1”.
• Reading the ATR1 register returns all zeros.
Address: 30AA_0000h base + 4h offset = 30AA_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ATR1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUA_ATR1 field descriptions

Field Description
ATR1
Processor A Transmit Register 1. (Write-only)
• Data written to the ATR1 register is reflected on the Processor B-side in the Processor B Receive
Register 1 (BRR1). The ATR1 and BRR1 registers are not double-buffered—a write to the ATR1
register overrides the data readable at the BRR1 register.
• A write to the transmit register clears a “transmitter empty” bit (TE1) in the Processor A Status
Register (ASR) on the transmitter side, and sets a “receiver full” bit (RF1) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 1 on the Processor B-side).
• Any write to the ATR1 register will update all status information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

134 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.4.3 Processor A Transmit Register 2 (MUA_ATR2)

Use Processor A Transmit Register 2 (ATR2, 32-bit, write-only) to transmit a message or

data to the Processor B.
• You can only write to the ATR2 register when the TE2 bit in ASR register is set to
“1”.
• Reading the ATR2 register returns all zeros.
Address: 30AA_0000h base + 8h offset = 30AA_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ATR2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUA_ATR2 field descriptions

Field Description
ATR2
Processor A Transmit Register 2. (Write-only)
• Data written to the ATR2 register is reflected on the Processor B-side in the Processor B Receive
Register 2 (BRR2). The ATR2 and BRR2 registers are not double-buffered—a write to the ATR2
register overrides the data readable at the BRR2 register.
• A write to the transmit register clears a “transmitter empty” bit (TE2) in the Processor A Status
Register (ASR) on the transmitter side, and sets a “receiver full” bit (RF2) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 2 on the Processor B-side).
• Any write to the ATR2 register will update all status information.

4.3.4.4 Processor A Transmit Register 3 (MUA_ATR3)

Use Processor A Transmit Register 3 (ATR3, 32-bit, write-only) to transmit a message or

data to the Processor B.
• You can only write to the ATR3 register when the TE3 bit in ASR register is set to
“1”.
• Reading the ATR3 register returns all zeros.
Address: 30AA_0000h base + Ch offset = 30AA_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ATR3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 135
Messaging Unit (MU)

MUA_ATR3 field descriptions

Field Description
ATR3
Processor A Transmit Register 3. (Write-only)
• Data written to the ATR3 register is reflected on the Processor B-side in the Processor B Receive
Register 3 (BRR3). The ATR3 and BRR3 registers are not double-buffered—a write to the ATR3
register overrides the data readable at the BRR3 register.
• A write to the transmit register clears a “transmitter empty” bit (TE3) in the Processor A Status
Register (ASR) on the transmitter side, and sets a “receiver full” bit (RF3) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 3 on the Processor B-side).
• Any write to the ATR3 register will update all status information.

4.3.4.5 Processor A Receive Register 0 (MUA_ARR0)

Use Processor A Receive Register 0 (ARR0, 32-bit, read-only) to receive a message or

data from the Processor B.
• Data written to the BTR0 register is immediately reflected in the ARR0 register.
• You can only read the ARR0 register when the RF0 bit in the ASR register is set to
“1”.
• Writing to the ARR0 register generates an error response to the Processor A.
Address: 30AA_0000h base + 10h offset = 30AA_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ARR0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUA_ARR0 field descriptions

Field Description
ARR0
Processor A Receive Register 0. (Read-only)
• Reflects the data written to Processor B Transmit Register 0 (BTR0).
• Reading the ARR0 register clears the “receiver full” bit (RF0) in the Processor A Status Register
(ASR) on the receiver side, and sets the “transmitter empty” bit (TE0) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 0 on the Processor B-side).
• Any read of the ARR0 register will update all status information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

136 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.4.6 Processor A Receive Register 1 (MUA_ARR1)

Use Processor A Receive Register 1 (ARR1, 32-bit, read-only) to receive a message or

data from the Processor B.
• Data written to the BTR1 register is immediately reflected in the ARR1 register.
• You can only read the ARR1 register when the RF1 bit in the ASR register is set to
“1”.
• Writing to the ARR1 register generates an error response to the Processor A.
Address: 30AA_0000h base + 14h offset = 30AA_0014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ARR1
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUA_ARR1 field descriptions

Field Description
ARR1
Processor A Receive Register 1. (Read-only)
• Reflects the data written to Processor B Transmit Register 1 (BTR1).
• Reading the ARR1 register clears the “receiver full” bit (RF1) in the Processor A Status Register
(ASR) on the receiver side, and sets the “transmitter empty” bit (TE1) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 1 on the Processor B-side).
• Any read of the ARR1 register will update all status information.

4.3.4.7 Processor A Receive Register 2 (MUA_ARR2)

Use Processor A Receive Register 2 (ARR2, 32-bit, read-only) to receive a message or

data from the Processor B.
• Data written to the BTR2 register is immediately reflected in the ARR2 register.
• You can only read the ARR2 register when the RF2 bit in the ASR register is set to
“1”.
• Writing to the ARR2 register generates an error response to the Processor A.
Address: 30AA_0000h base + 18h offset = 30AA_0018h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ARR2
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 137
Messaging Unit (MU)

MUA_ARR2 field descriptions

Field Description
ARR2
Processor A Receive Register 2. (Read-only)
• Reflects the data written to Processor B Transmit Register 1 (BTR2).
• Reading the ARR2 register clears the “receiver full” bit (RF2) in the Processor A Status Register
(ASR) on the receiver side, and sets the “transmitter empty” bit (TE2) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 2 on the Processor B-side).
• Any read of the ARR2 register will update all status information.

4.3.4.8 Processor A Receive Register 3 (MUA_ARR3)

Use Processor A Receive Register 3 (ARR3, 32-bit, read-only) to receive a message or

data from the Processor B.
• Data written to the BTR3 register is immediately reflected in the ARR3 register.
• You can only read the ARR3 register when the RF3 bit in the ASR register is set to
“1”.
• Writing to the ARR3 register generates an error response to the Processor A.
Address: 30AA_0000h base + 1Ch offset = 30AA_001Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ARR3
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUA_ARR3 field descriptions

Field Description
ARR3
Processor A Receive Register 3. (Read-only)
• Reflects the data written to Processor B Transmit Register 3 (BTR3).
• Reading the ARR3 register clears the “receiver full” bit (RF3) in the Processor A Status Register
(ASR) on the receiver side, and sets the “transmitter empty” bit (TE3) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 3 on the Processor B-side).
• Any read of the ARR3 register will update all status information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

138 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.4.9 Processor A Status Register (MUA_ASR)

Use the Processor A Status Register (ASR, 32-bit, read-write) to show interrupt status
from the Processor B, general purpose flags, and to set dual function control-status bits.
• Some dual-purpose bits are set by the MU logic, and cleared by the Processor A-side
programmer
• Other dual-purpose bits are set by the Processor A-side programmer, and cleared by
the MU logic.
Address: 30AA_0000h base + 20h offset = 30AA_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GIPn RFn TEn Reserved

Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
BRDIP

Reserved FUP BRS Reserved EP Fn

Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

MUA_ASR field descriptions

Field Description
31–28
GIPn For n = {0, 1, 2, 3} Processor A General Interrupt Request n Pending. (Read-Write)
• GIPn bit signals the Processor A that the GIRn bit in the BCR register on the Processor B-side was
set from “0” to “1”. If the GIEn bit in the ACR register is set to “1”, a General Interrupt n request is
issued.
• The GIPn bit is cleared by writing it back as “1”. Writing “0”, or writing “1” when the GIPn bit is
cleared is ignored. Use this feature in the interrupt routine, where the GIPn bit is cleared in order to
de-assert the interrupt request source at the interrupt controller. The proper bit clearing sequence is:
clear an Processor A register, set the desired bit in it (Processor A register), and write it to the ASR
register, thus clearing the GIPn bit.
• GIPn bit is cleared when the MU is reset.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 139
Messaging Unit (MU)

MUA_ASR field descriptions (continued)

Field Description
0 Processor A general purpose interrupt n is not pending. (default)
1 Processor A general purpose interrupt n is pending.
27–24
RFn For n = {0, 1, 2, 3} Processor A Receive Register n Full. (Read-only)
• The RFn bit is set to “1” when the BTRn register is written on the Processor B-side.
• After the RFn bit is set to “1”, the RFn bit signals the Processor A-side that new data is ready to be
read by the Processor A in the ARRn register, and a Receive n interrupt is issued on the Processor
A-side (if the RIEn bit in the ACR register has been set to “1”).
• RFn bit is cleared when the ARRn register is read, and when the MU is reset.

0 ARRn register is not full (default).

1 ARRn register has received data from BTRn register and is ready to be read by the Processor A.
23–20
TEn For n = {0, 1, 2, 3} Processor A Transmit Register n Empty. (Read-only)
• The TEn bit is set to “1” after the BRRn register is read on the Processor B-side.
• After the TEn bit is set to “1”, the TEn bit signals the Processor A-side that the ATRn register is
ready to be written on the Processor A-side, and a Transmit n interrupt is issued on the Processor
A-side (if the TEn bit in the ACR register is set to “1”).
• TEn bit is cleared after the ATRn register is written on the Processor A-side.
• TEn bit is set to “1” when the MU is reset.

0 ATRn register is not empty.

1 ATRn register is empty (default).
19–10 This field is reserved.
- Reserved.
9
BRDIP Processor B Reset De-asserted Interrupt Pending. (Read-Write)
• BRDIP bit signals the Processor A-side that the Processor B-side has come out of reset.
• BRDIP bit is set to “1” after the MU Processor B-side comes out of reset, after synchronization. The
interrupt generated by a Processor B-side reset de-assertion is ORed with the Processor A general
purpose interrupt 3. The Processor A general purpose interrupt 3 is issued when the Processor B-
side comes out of reset (if the interrupt is enabled).
• To clear the BRDIP bit, write “1”, which also clears general purpose interrupt 3.
• When Processor A-side of MU comes out of reset BRDIP bit has value “0”(default).Then Processor
A sees the status of Processor B-side and if Processor B-side has come out of reset then BRDIP bit
goes high.This takes 5-6 clock cycles.And if you read BRDIP bit now you will see it as high although
its reset value was "0".

0 The Processor A general purpose interrupt 3, because of a Processor B-side reset de-assertion, is
cleared (default).
1 The Processor B-side is out of reset.
8
FUP Processor A Flags Update Pending. (Read-only)
• FUP bit is set to “1” when the Processor A-side sends a Flags Update request to the Processor B-
side.
• A Flags Update request is generated when the ABF[2:0] bits of the ACR register change. No flag
update changes are allowed while the FUP bit is set to “1”. Any write to the ABF[2:0] bits, while the
FUP bit is set to “1”, will not generate a Flags Update event, and the ABF[2:0] bits will stay
unchanged.
• FUP bit is cleared when this Flags Update request is internally acknowledged (that the flag is
updated) from the MU Processor B-side, and during MU reset.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

140 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

MUA_ASR field descriptions (continued)

Field Description
0 No flags updated, initiated by the Processor A, in progress (default)
1 Processor A initiated flags update, processing
7
BRS Processor B-side Reset State. (Read-only)
• BRS bit indicates if the Processor B-side of the MU is in a reset state or not.
• If the BRS bit is set to “1”, then the Processor B-side of the MU is still in the reset state.
• If the BRS bit is cleared, then the Processor B-side of the MU are out of reset.
• The BRS bit is set to “1” during: a Processor B system reset, or an MU reset (caused by setting the
MUR bit at the ACR register).
• The BRS bit is cleared when the reset sequence on the Processor B-side of the MU ends. After
issuing any of the reset events mentioned previously, you should verify that the BRS bit is cleared
before starting any accesses.
• When Processor A side of MU comes out of reset BRS bit has value “1”(default).Then Processor A
sees the status of Processor B-side and if Processor B-side has come out of reset then BRS bit
goes low.This takes 5-6 clock cycles.And if you read BRS bit now you will see it as low although its
reset value was "1" .

0 The Processor B-side of the MU is not in reset.

1 The Processor B-side of the MU is in reset.
6–5 This field is reserved.
- Reserved
4
EP Processor A-Side Event Pending. (Read-only)
• EP bit is set to “1” when the Processor A-side mechanism sends an event update request to the
Processor B-side.
• EP bit is cleared when the event update acknowledge is received. An “event” is any hardware
message that is reflected in the BSR register on the Processor B-side (for example, “transmit
register 0 written”). During normal operations, you do not have to deal with the state of the EP bit
because the event update mechanism works automatically.
• To ensure events have been posted to Processor B before entering STOP mode, you should verify
that the EP bit is cleared. If EP bit is set to “1”, you should wait and continue to poll it (EP bit) before
entering STOP mode.
• Reading the ASR register (to check the EP bit) should be the last access to the MU that should be
performed before entering STOPor WAIT modes; otherwise, the EP bit may be set by subsequent
additional actions.
• The EP bit is cleared when the MU resets.

0 The Processor A-side event is not pending (default).

1 The Processor A-side event is pending.
3 This field is reserved.
- Reserved.
Fn
For n = {0, 1, 2} Processor A-Side Flag n. (Read-only)
• Fn bit is the Processor A-side flag that reflects the values written to the BAFn bit in the Processor B
control register.
• Every time that the BAFn bit is written, the BAFn bit write event updates the Fn bit after the event
update latency, which is measured in terms of the number of clocks of the Processor B and the
Processor A.

0 BAFn bit in BCR register is written 0 (default).

1 BAFn bit in BCR register is written 1.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 141
Messaging Unit (MU)

4.3.4.10 Processor A Control Register (MUA_ACR)

Use the Processor A Control Register (ACR, 32-bit, read-write) to enable the MU
interrupts on the Processor A-side, and trigger events and interrupts on the Processor B-
side (general purpose interrupt, flag update).
For the fields GIEn, RIEn, TIEn and GIRn, n=0 corresponds to the high order bit and n=3
corresponds to the low order bit.
Address: 30AA_0000h base + 24h offset = 30AA_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GIEn RIEn TIEn GIRn

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
BRDIE

Reserved MUR BHR ABFn

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUA_ACR field descriptions

Field Description
31–28
GIEn For n = {0, 1, 2, 3} Processor A General Purpose Interrupt Enable n. (Read-Write) When GIEn=0
corresponds to the high order bit and GIE3 corresponds to the low order bit.
• GIEn bit enables Processor A General Interrupt n.
• If GIEn bit is set to “1” (enabled), then a General Interrupt n request is issued when the GIPn bit in
the ASR register is set to “1”.
• If GIEn is cleared (disabled), then the value of the GIPn bit is ignored and no General Interrupt n
request will be issued.
• GIEn bit is cleared when the MU resets.

0 Disables Processor A General Interrupt n. (default)

1 Enables Processor A General Interrupt n.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

142 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

MUA_ACR field descriptions (continued)

Field Description
27–24
RIEn For n = {0, 1, 2, 3} Processor A Receive Interrupt Enable n. (Read-Write)
• RIEn bit enables Processor A Receive Interrupt n.
• If RIEn bit is set to “1” (enabled), then an Processor A Receive Interrupt n request is issued when
the RFn bit in the ASR register is set to “1”.
• If RIEn bit is cleared (disabled), then the value of the RFn bit is ignored and no Processor A Receive
Interrupt n request will be issued.
• RIEn bit is cleared when the MU resets.

0 Disables Processor A Receive Interrupt n. (default)

1 Enables Processor A Receive Interrupt n.
23–20
TIEn For n = {0, 1, 2, 3} Processor A Transmit Interrupt Enable n. (Read-Write)
• TIEn bit enables Processor A Transmit Interrupt n.
• If TIEn bit is set to “1” (enabled), then an Processor A Transmit Interrupt n request is issued when
the TEn bit in the ASR register is set to “1”.
• If TIEn bit is cleared (disabled), then the value of the TEn bit is ignored and no Processor A Transmit
Interrupt n request will be issued.
• TIEn bit is cleared when the MU resets.

0 Disables Processor A Transmit Interrupt n. (default)

1 Enables Processor A Transmit Interrupt n.
19–16
GIRn For n = {0, 1, 2, 3} Processor A General Purpose Interrupt Request n. (Read-Write)
• Writing “1” to the GIRn bit sets the GIPn bit in the BSR register on the Processor B-side. If the GIEn
bit in the BCR register is set to “1” on the Processor B-side, a General Purpose Interrupt n request is
triggered.
• The GIRn bit is cleared if the GIPn bit (in the BSR register on the Processor B-side) is cleared by
writing it (GIPn bit) as “1”, thereby signalling the Processor A that the interrupt was accepted
(cleared by the software). The GIPn bit cannot be written as “0” on the Processor A-side.
• To ensure proper operations, you must verify that the GIRn bit is cleared (meaning that there is no
pending interrupt) before setting it (GIRn bit).
• GIRn bit is cleared when the MU resets.

0 Processor A General Interrupt n is not requested to the Processor B (default).

1 Processor A General Interrupt n is requested to the Processor B.
15–7 This field is reserved.
- Reserved.
6
BRDIE Processor B Reset De-assertion Interrupt Enable. (Read-Write)
• BRDIE bit enables Processor A General Interrupt 3.
• If BRDIE bit is set to “1”, then General Interrupt 3 request is issued to the Processor A when the
BRDIP bit in the ASR register is set to “1”.
• If BRDIE is cleared, then the value of the BRDIP bit is ignored and no General Interrupt 3 request
will be issued.
• The BRDIE bit is cleared when the MU resets.

0 Disables the Processor A General Purpose Interrupt 3 request due to the Processor B reset de-
assertion to the Processor A. Processor B reset deassertion causes Processor B and MU-Processor B
side to come out of reset thus setting BRDIP bit to “1”.
1 Enables Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion
to the Processor A.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 143
Messaging Unit (MU)

MUA_ACR field descriptions (continued)

Field Description
5
MUR Processor A MU Reset.
• Setting MUR bit to “1” resets both the Processor B and the Processor A sides of the MU module,
forcing all control and status registers to return to their default values (except the BHR bit in the ACR
register and BHRM bit in BCR register), and all internal states to be cleared.
• Before setting the MUR bit to “1”, it is advisable to interrupt the Processor B, because setting the
MUR bit may affect the ongoing Processor B program.
• After setting the MUR bit, you should monitor the value of the BRS bit in the ASR register to know
when the reset sequence on the Processor B-side has ended.
• MUR bit can only be written as “1”.
• MUR bit is always read as “0”.
• MUR bit is cleared during the MU reset sequence.

0 N/A. Self clearing bit (default).

1 Asserts the Processor A MU reset.
4
BHR Processor B Hardware Reset. (Read-Write)
• BHR bit asserts and de-asserts the hardware reset of the Processor B.
• Set BHR bit to “1” to start a hardware reset of the Processor B.
• Clear the BHR bit to de-assert the Processor B hardware reset input.
• Assert the BHR bit for a minimum of 3 clock cycles of network clock (sampling clock in SRC) clock.
The BRS bit in MU_ASR register (b[7]) indicates the state of the Processor B. As soon as the
Processor B goes into Reset (BRS bit is set to “1”), the BHR bit can be de-asserted.
• Strobe-setting the BHR bit will not cause an internal MU reset but will be routed outside MU to
Processor B domain reset logic
• After clearing the BHR bit, monitor the value of the BRS bit at the ASR to know when the Processor
B reset sequence has ended.
• The BHR reset issued by the Processor A to the Processor B is maskable by the Processor B
(according to the settings of the BHRM bit in the BCR register). If the BHRM bit (in the BCR register)
is set to “1”, then the BHR reset is masked; if the BHRM bit (in the BCR register) is cleared (default),
then the BHR reset is enabled.
• The BHR bit does not return to the reset value during the software (MUR) reset.

0 De-assert Hardware reset to the Processor B. (default)

1 Assert Hardware reset to the Processor B.
3 This field is reserved.
- Reserved
ABFn
For n = {0, 1, 2} Processor A to Processor B Flag n. (Read-Write)
• ABFn bit is a read-write flag that is reflected in Fn bit in the BSR register on the Processor B-side.
• ABFn bit is cleared when the MU resets.

0 N/A. Self clearing bit (default).

1 Asserts the Processor A MU reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

144 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.5 MU Processor B-side Memory Map/Register Definition

This section contains the detailed register descriptions for the Processor B-side MU
registers.
MUB memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30AB_0000 Processor B Transmit Register 0 (MUB_BTR0) 32 R/W 0000_0000h 4.3.5.1/145
30AB_0004 Processor B Transmit Register 1 (MUB_BTR1) 32 R/W 0000_0000h 4.3.5.2/146
30AB_0008 Processor B Transmit Register 2 (MUB_BTR2) 32 R/W 0000_0000h 4.3.5.3/147
30AB_000C Processor B Transmit Register 3 (MUB_BTR3) 32 R/W 0000_0000h 4.3.5.4/147
30AB_0010 Processor B Receive Register 0 (MUB_BRR0) 32 R 0000_0000h 4.3.5.5/148
30AB_0014 Processor B Receive Register 1 (MUB_BRR1) 32 R 0000_0000h 4.3.5.6/149
30AB_0018 Processor B Receive Register 2 (MUB_BRR2) 32 R 0000_0000h 4.3.5.7/149
30AB_001C Processor B Receive Register 3 (MUB_BRR3) 32 R 0000_0000h 4.3.5.8/150
30AB_0020 Processor B Status Register (MUB_BSR) 32 R/W 00F0_0080h 4.3.5.9/151
4.3.5.10/
30AB_0024 Processor B Control Register (MUB_BCR) 32 R/W 0000_0000h
154

4.3.5.1 Processor B Transmit Register 0 (MUB_BTR0)

Use Processor B Transmit Register 0 (BTR0, 32-bit, write-only) to transmit a message or

data to the Processor A.
• You can only write to the BTR0 register when the TE0 bit in BSR register is set to
“1”.
• Reading the BTR0 register returns all zeros.
Address: 30AB_0000h base + 0h offset = 30AB_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BTR0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUB_BTR0 field descriptions

Field Description
BTR0
Processor B Transmit Register 0. (Write-only)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 145
Messaging Unit (MU)

MUB_BTR0 field descriptions (continued)

Field Description
• Data written to the BTR0 register is reflected on the Processor A-side in the Processor A Receive
Register 0 (ARR0). The BTR0 and ARR0 registers are not double-buffered—a write to the BTR0
register overrides the data readable at the ARR0 register.
• A write to the transmit register clears a “transmitter empty” bit (TE0) in the Processor B Status
Register (BSR) on the transmitter side, and sets a “receiver full” bit (RF0) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 0 on the Processor A-side).
• Any write to the BTR0 register will update all status information.

4.3.5.2 Processor B Transmit Register 1 (MUB_BTR1)

Use Processor B Transmit Register 1 (BTR1, 32-bit, write-only) to transmit a message or

data to the Processor A.
• You can only write to the BTR1 register when the TE1 bit in BSR register is set to
“1”.
• Reading the BTR1 register returns all zeros.
Address: 30AB_0000h base + 4h offset = 30AB_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BTR1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUB_BTR1 field descriptions

Field Description
BTR1
Processor B Transmit Register 1. (Write-only)
• Data written to the BTR1 register is reflected on the Processor A-side in the Processor A Receive
Register 1 (ARR1). The BTR1 and ARR1 registers are not double-buffered—a write to the BTR1
register overrides the data readable at the ARR1 register.
• A write to the transmit register clears a “transmitter empty” bit (TE1) in the Processor B Status
Register (BSR) on the transmitter side, and sets a “receiver full” bit (RF1) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 1 on the Processor A-side).
• Any write to the BTR1 register will update all status information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

146 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.5.3 Processor B Transmit Register 2 (MUB_BTR2)

Use Processor B Transmit Register 2 (BTR2, 32-bit, write-only) to transmit a message or

data to the Processor A.
• You can only write to the BTR2 register when the TE2 bit in BSR register is set to
“1”.
• Reading the BTR2 register returns all zeros.
Address: 30AB_0000h base + 8h offset = 30AB_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BTR2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUB_BTR2 field descriptions

Field Description
BTR2
Processor B Transmit Register 2. (Write-only)
• Data written to the BTR2 register is reflected on the Processor A-side in the Processor A Receive
Register 2 (ARR2). The BTR2 and ARR2 registers are not double-buffered—a write to the BTR2
register overrides the data readable at the ARR2 register.
• A write to the transmit register clears a “transmitter empty” bit (TE2) in the Processor B Status
Register (BSR) on the transmitter side, and sets a “receiver full” bit (RF2) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 2 on the Processor A-side).
• Any write to the BTR2 register will update all status information.

4.3.5.4 Processor B Transmit Register 3 (MUB_BTR3)

Use Processor B Transmit Register 3 (BTR3, 32-bit, write-only) to transmit a message or

data to the Processor A.
• You can only write to the BTR3 register when the TE3 bit in BSR register is set to
“1”.
• Reading the BTR3 register returns all zeros.
Address: 30AB_0000h base + Ch offset = 30AB_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BTR3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 147
Messaging Unit (MU)

MUB_BTR3 field descriptions

Field Description
BTR3
Processor B Transmit Register 3. (Write-only)
• Data written to the BTR3 register is reflected on the Processor A-side in the Processor A Receive
Register 3 (ARR3). The BTR3 and ARR3 registers are not double-buffered—a write to the BTR3
register overrides the data readable at the ARR3 register.
• A write to the transmit register clears a “transmitter empty” bit (TE3) in the Processor B Status
Register (BSR) on the transmitter side, and sets a “receiver full” bit (RF3) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 3 on the Processor A-side).
• Any write to the BTR3 register will update all status information.

4.3.5.5 Processor B Receive Register 0 (MUB_BRR0)

Use Processor B Receive Register 0 (BRR0, 32-bit, read-only) to receive a message or

data from the Processor A.
• Data written to the ATR0 register is immediately reflected in the BRR0 register.
• You can only read the BRR0 register when the RF0 bit in the BSR register is set to
“1”.
• Writing to the BRR0 register generates an error response to the Processor B.
Address: 30AB_0000h base + 10h offset = 30AB_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R BRR0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUB_BRR0 field descriptions

Field Description
BRR0
Processor B Receive Register 0. (Read-only)
• Reflects the data written to Processor A Transmit Register 0 (ATR0).
• Reading the BRR0 register clears the “receiver full” bit (RF0) in the Processor B Status Register
(BSR) on the receiver side, and sets the “transmitter empty” bit (TE0) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 0 on the Processor A-side).
• Any read of the BRR0 register will update all status information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

148 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.5.6 Processor B Receive Register 1 (MUB_BRR1)

Use Processor B Receive Register 1 (BRR1, 32-bit, read-only) to receive a message or

data from the Processor A.
• Data written to the ATR1 register is immediately reflected in the BRR1 register.
• You can only read the BRR1 register when the RF1 bit in the BSR register is set to
“1”.
• Writing to the BRR1 register generates an error response to the Processor B.
Address: 30AB_0000h base + 14h offset = 30AB_0014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R BRR1
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUB_BRR1 field descriptions

Field Description
BRR1
Processor B Receive Register 1. (Read-only)
• Reflects the data written to Processor A Transmit Register 1 (ATR1).
• Reading the BRR1 register clears the “receiver full” bit (RF1) in the Processor B Status Register
(BSR) on the receiver side, and sets the “transmitter empty” bit (TE1) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 1 on the Processor A-side).
• Any read of the BRR1 register will update all status information.

4.3.5.7 Processor B Receive Register 2 (MUB_BRR2)

Use Processor B Receive Register 2 (BRR2, 32-bit, read-only) to receive a message or

data from the Processor A.
• Data written to the ATR2 register is immediately reflected in the BRR2 register.
• You can only read the BRR2 register when the RF2 bit in the BSR register is set to
“1”.
• Writing to the BRR2 register generates an error response to the Processor B.
Address: 30AB_0000h base + 18h offset = 30AB_0018h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R BRR2
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 149
Messaging Unit (MU)

MUB_BRR2 field descriptions

Field Description
BRR2
Processor B Receive Register 2. (Read-only)
• Reflects the data written to Processor A Transmit Register 1 (ATR2).
• Reading the BRR2 register clears the “receiver full” bit (RF2) in the Processor B Status Register
(BSR) on the receiver side, and sets the “transmitter empty” bit (TE2) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 2 on the Processor A-side).
• Any read of the BRR2 register will update all status information.

4.3.5.8 Processor B Receive Register 3 (MUB_BRR3)

Use Processor B Receive Register 3 (BRR3, 32-bit, read-only) to receive a message or

data from the Processor A.
• Data written to the ATR3 register is immediately reflected in the BRR3 register.
• You can only read the BRR3 register when the RF3 bit in the BSR register is set to
“1”.
• Writing to the BRR3 register generates an error response to the Processor B.
Address: 30AB_0000h base + 1Ch offset = 30AB_001Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R BRR3
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUB_BRR3 field descriptions

Field Description
BRR3
Processor B Receive Register 3. (Read-only)
• Reflects the data written to Processor A Transmit Register 3 (ATR3).
• Reading the BRR3 register clears the “receiver full” bit (RF3) in the Processor B Status Register
(BSR) on the receiver side, and sets the “transmitter empty” bit (TE3) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 3 on the Processor A-side).
• Any read of the BRR3 register will update all status information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

150 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.3.5.9 Processor B Status Register (MUB_BSR)

Use the Processor B Status Register (BSR, 32-bit, read-write) to show interrupt status
from the Processor B, general purpose flags, the Processor A power mode, and to set dual
function control-status bits.
• Dual-purpose bits are set by the Processor B-side programmer, and cleared by the
MU logic.
Address: 30AB_0000h base + 20h offset = 30AB_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GIPn RFn TEn Reserved

Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved FUP ARS APM EP Fn

Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

MUB_BSR field descriptions

Field Description
31–28
GIPn For n = {0, 1, 2, 3} Processor B General Interrupt Request n Pending. (Read-Write)
• GIPn bit signals the Processor B that the GIRn bit in the ACR register on the Processor A-side was
set from “0” to “1”. If the GIEn bit in the BCR register is set to “1”, a General Interrupt n request is
issued.
• The GIPn bit is cleared by writing it back as “1”. Writing “0”, or writing “1” when the GIPn bit is
cleared is ignored. Use this feature in the interrupt routine, where the GIPn bit is cleared in order to
de-assert the interrupt request source at the interrupt controller.
• GIPn bit is cleared when the MU is reset.

0 Processor B general purpose interrupt n is not pending. (default)

1 Processor B general purpose interrupt n is pending.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 151
Messaging Unit (MU)

MUB_BSR field descriptions (continued)

Field Description
27–24
RFn For n = {0, 1, 2, 3} Processor B Receive Register n Full. (Read-only)
• RFn bit signals to the Processor B-side that new data was written by the Processor A to the ATRn
register, and is ready to be read by the Processor B in the BRRn register.
• The RFn bit is set to “1” when the ATRn register is written on the Processor A-side.
• After the RFn bit is set to “1”, the RFn bit signals the Processor B-side that new data is ready to be
read by the Processor B in the BRRn register, and a Receive n interrupt is issued on the Processor
A-side (if the RIEn bit in the BCR register has been set to “1”).
• RFn bit is cleared when the BRRn register is read, and when the MU is reset.

0 BRRn register is not full (default).

1 BRRn register has received data from ATRn register and is ready to be read by the Processor B.
23–20
TEn For n = {0, 1, 2, 3} Processor B Transmit Register n Empty. (Read-only)
• When TEn = “1”, it signals to the Processor B-side that the BTRn register is ready to be written on
the Processor B-side.
• The TEn bit is set to “1” after the ARRn register is read on the Processor A-side.
• Setting TEn bit will issue a transmit n interrupt on the Processor B-side (if the TIEn bit in the BCR
register is set to “1”.
• TEn bit is cleared after the BTRn register is written on the Processor B-side.
• TEn bit is set to “1” when the MU is reset.

0 BTRn register is not empty.

1 BTRn register is empty (default).
19–9 This field is reserved.
Reserved
8
FUP Processor B Flags Update Pending. (Read-only)
• FUP bit is set to “1” when the Processor B-side sends a Flags Update request to the Processor A-
side.
• A Flags Update request is generated when the BAF[2:0] bits of the BCR register change. No flag
update changes are allowed while the FUP bit is set to “1”. Any write to the BAF[2:0] bits, while the
FUP bit is set to “1”, will not generate a Flags Update event, and the BAF[2:0] bits will stay
unchanged.
• FUP bit is cleared when this Flags Update request is internally acknowledged (that the flag is
updated) from the MU Processor A-side, and during MU reset.

0 No flags updated, initiated by the Processor B, in progress (default)

1 Processor B initiated flags update, processing
7
ARS Processor A Reset State. (Read-only)
• ARS bit indicates if the Processor A-side of the MU is in a reset state or not.
• If the ARS bit is set to “1”, then the Processor A-side of the MU is still in the reset state.
• If the ARS bit is cleared, then both the Processor A and the Processor A-side of the MU are out of
reset.
• The ARS bit is set to “1” during: a Processor A system reset, or an MU reset (caused by setting the
MUR bit at the BCR register).
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

152 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

MUB_BSR field descriptions (continued)

Field Description
• The ARS bit is cleared when the reset sequence on the Processor A-side of the MU ends. After
issuing any of the three reset events mentioned previously, you should verify that the ARS bit is
cleared before starting any accesses.
• When Processor B side of MU comes out of reset ARS bit has value “1”(default).Then Processor B
sees the status of Processor A side and if Processor A has come out of reset then ARS bit goes
low.This takes 5-6 clock cycles.And if you read ARS bit now you will see it as low although its reset
value was "1" .

0 The Processor A or the Processor A-side of the MU is not in reset.

1 The Processor A or the Processor A-side of the MU is in reset.
6–5
APM Processor A Power Mode. (Read-only)
• APM[1:0] bits indicate the Processor A power mode.

00 The System is in Run Mode.

01 The System is in WAIT Mode.
10 Reserved.
11 The System is in STOP Mode.
4
EP Processor B-Side Event Pending. (Read-only)
• EP bit is set to “1” when the Processor B-side mechanism sends an event update request to the
Processor A-side.
• EP bit is cleared when the event update acknowledge is received. An “event” is any hardware
message that is reflected in the ASR register on the Processor A-side (for example, “transmit
register 0 written”). During normal operations, you do not have to deal with the state of the EP bit
because the event update mechanism works automatically.
• To ensure events have been posted to Processor A before entering STOP mode, you should verify
that the EP bit is cleared. If EP bit is set to “1”, you should wait and continue to poll it (EP bit) before
entering STOP mode.
• Reading the BSR register (to check the EP bit) should be the last access to the MU that should be
performed before entering STOP mode; otherwise, the EP bit may be set by subsequent additional
actions.
• Due to Processor B pipeline effects, three NOP operations (or their timing equivalent) should be
given after an instruction that sets an event before the EP bit can reflect this event.
• The EP bit is cleared when the MU resets.

0 The Processor B-side event is not pending (default).

1 The Processor B-side event is pending.
3 This field is reserved.
Reserved
Fn
For n = {0, 1, 2} Processor B-Side Flag n. (Read-only)
• Fn bit is the Processor B-side flag that reflects the values written to the ABFn bit in the Processor A
control register.
• Every time that the ABFn bit is written, the ABFn bit write event updates the Fn bit after the event
update latency, which is measured in terms of the number of clocks of the Processor A and the
Processor B.

0 ABFn bit in ACR register is written 0 (default).

1 ABFn bit in ACR register is written 1.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 153
Messaging Unit (MU)

4.3.5.10 Processor B Control Register (MUB_BCR)

Use the Processor B Control Register (BCR, 32-bit, read-write) to enable the MU
interrupts on the Processor B-side, and trigger events and interrupts on the Processor A-
side (wake from STOP, hardware reset, flag update).
For the fields GIEn, RIEn, TIEn and GIRn, n=0 corresponds to the high order bit and n=3
corresponds to the low order bit.
Address: 30AB_0000h base + 24h offset = 30AB_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GIEn RIEn TIEn GIRn

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved HRM BAFn

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MUB_BCR field descriptions

Field Description
31–28
GIEn For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Enable n. (Read-Write)
• GIEn bit enables Processor B General Interrupt n.
• If GIEn bit is set to “1” (enabled), then a General Interrupt n request is issued when the GIPn bit in
the BSR register is set to “1”.
• If GIEn is cleared (disabled), then the value of the GIPn bit is ignored and no General Interrupt n
request will be issued.
• GIEn bit is cleared when the MU resets.

0 Disables Processor B General Interrupt n. (default)

1 Enables Processor B General Interrupt n.
27–24
RIEn For n = {0, 1, 2, 3} Processor B Receive Interrupt Enable n. (Read-Write)
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

154 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

MUB_BCR field descriptions (continued)

Field Description
• RIEn bit enables Processor B Receive Interrupt n.
• If RIEn bit is set to “1” (enabled), then an Processor B Receive Interrupt n request is issued when
the RFn bit in the BSR register is set to “1”.
• If RIEn bit is cleared (disabled), then the value of the RFn bit is ignored and no Processor B Receive
Interrupt n request will be issued.
• RIEn bit is cleared when the MU resets.

0 Disables Processor B Receive Interrupt n. (default)

1 Enables Processor B Receive Interrupt n.
23–20
TIEn For n = {0, 1, 2, 3} Processor B Transmit Interrupt Enable n. (Read-Write)
• TIEn bit enables Processor B Transmit Interrupt n.
• If TIEn bit is set to “1” (enabled), then an Processor B Transmit Interrupt n request is issued when
the TEn bit in the BSR register is set to “1”.
• If TIEn bit is cleared (disabled), then the value of the TEn bit is ignored and no Processor B Transmit
Interrupt n request will be issued.
• TIEn bit is cleared when the MU resets.

0 Disables Processor B Transmit Interrupt n. (default)

1 Enables Processor B Transmit Interrupt n.
19–16
GIRn For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Request n. (Read-Write)
• Writing “1” to the GIRn bit sets the GIPn bit in the ASR register on the Processor A-side. If the GIEn
bit in the ACR register is set to “1” on the Processor A-side, a General Purpose Interrupt n request is
triggered.
• The GIRn bit is cleared if the GIPn bit (in the ASR register on the Processor A-side) is cleared by
writing it (GIPn bit) as “1”, thereby signalling the Processor B that the interrupt was accepted
(cleared by the software). The GIPn bit cannot be written as “0” on the Processor B-side.
• To ensure proper operations, you must verify that the GIRn bit is cleared (meaning that there is no
pending interrupt) before setting it (GIRn bit).
• GIRn bit is cleared when the MU resets.

0 Processor B General Interrupt n is not requested to the Processor A (default).

1 Processor B General Interrupt n is requested to the Processor A.
15–5 This field is reserved.
Reserved
4
HRM Processor B Hardware Reset Mask. (Read-Write)
• The Processor A can give a hardware reset to the Processor B by setting the BHR bit in the ACR
Register to “1”.
• When the HRM bit is set to “1” by the Processor B, the BHR reset issued by the Processor A is
masked (disabled by the Processor B).
• When the HRM bit is cleared, the BHR reset issued by the Processor A to the Processor B is not
masked (enabled by the Processor B).

0 BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware
reset).
1 BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
3 This field is reserved.
Reserved
BAFn
For n = {0, 1, 2} Processor B to Processor A Flag n. (Read-Write)
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 155
Semaphore (SEMA4)

MUB_BCR field descriptions (continued)

Field Description
• BAFn bit is a read-write flag that is reflected in Fn bit in the ASR register on the Processor A-side.
• BAFn bit is cleared when the MU resets.

0 Clears the Fn bit in the ASR register.

1 Sets the Fn bit in the ASR register.

4.4 Semaphore (SEMA4)

4.4.1 Overview
The Semaphores (SEMA4) module provides a platform IPS slave device which
implements 16 hardware-enforced gates.

4.4.1.1 Block Diagram

A simplified block diagram of the Semaphores module is shown in Figure 4-10. This is a
dual-processor configuration, where cp0 is core processor 0 and cp1 is core processor 1.
In the diagram, the register blocks named gate0, gate1,…, gate 15 include the finite state
machines (FSM) implementing the semaphore gates plus the interrupt notification logic.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

156 NXP Semiconductors
 Chapter 4 ARM Platform and Debug
ips_semaphores
0 aips_master
2
= =
master_eq_cp{0,1} 0 ips_wdata
31
= = =
wdata_eq_{unlock, cp[0-1]_lock}
ips_addr
decode

gate0 gate1 gate2 gate3

control

gate12 gate13 gate14 gate15

mux
0 ips_rdata
cp0_semaphore_int cp1_semaphore_int 31
IPS Bus

Figure 4-10. Semaphores Block Diagram

4.4.1.2 Features
The Semaphores module implements hardware-enforced semaphores as an IPS-mapped
slave peripheral device. The feature set includes:
• Support for 16 hardware-enforced gates in a dual-processor configuration
• Each hardware gate appears as a 3-state, 2-bit state machine, with all 16 gates
mapped as a byte-size array
• Processors lock gates by writing "processor_number+1" to the appropriate
gate and must read back the gate value to verify the lock operation was
successful.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 157
Semaphore (SEMA4)

3-state implementation:
if gate = 0b00, then state = unlocked
if gate = 0b01, then state = locked by processor 0
if gate = 0b10, then state = locked by processor 1
• Uses the bus master number/ID as a reference attribute plus the specified
data patterns to validate all write operations
• Once locked, the gate can (and must) be unlocked by a write of zeroes from
the locking processor
• Optional interrupt notification after a failed lock write provides a mechanism to
indicate when the gate is unlocked
• Secure reset mechanisms are supported to clear the contents of individual gates
or notification logic, as well as a clear_all capability
• Memory-mapped IPS slave peripheral platform module
• Interface to the IPS bus for programming-model accesses
• Two outputs (one per processor) for interrupt notification of failed lock writes

4.4.2 Functional Description

In this section, the functional operation of the Semaphores module, specifically the state
machines of the SEMA4_GATEn and SEMA4_CPnNTF registers are detailed.

4.4.2.1 Modes of Operation

The Semaphores module does not support any special modes of operation. As a slave
peripheral memory-mapped device located on the platform's IPS slave bus, it responds
based strictly on the memory addresses of the connected bus. The IPS bus is used to
access the Semaphores' programming model.

4.4.2.2 SEMA4_GATEn Operation

Recall each of the SEMA4_GATEn registers implements a 2-bit, 3-state machine. The
state transitions for each gate are shown in the following figure.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

158 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

reset
1

idle
00
~((master == cp0) & (wdata == cp0_lock))
&~((master == cp1) & (wdata == cp1_lock))
2
master == cp0 master == cp1
& (wdata == cp0_lock) & (wdata == cp1_lock)
3 4

cp0_lock cp1_lock
01 10

5 7
master != cp0 master != cp1
6 | (wdata != unlock) | (wdata != unlock) 8

master == cp0 master == cp1

& (wdata == unlock) & (wdata == unlock)
Figure 4-11. SEMA4_GATEn State Machine

The bus master number/ID is used to identify core processor 0 (cp0) or core processor 1
(cp1).
The state transitions for SEMA4_GATEn are defined in the following table.
Table 4-16. SEMA4_GATEn State Transitions
Transitio
Current State Next State Description
n
idle 1 Any reset, whether a system reset or an individual gate reset,
–
unconditionally forces the gate into the idle state.
idle 2 Unless a write of the appropriate lock value from the
idle corresponding processor occurs, the gate remains in the idle
state.
cp0_lock 3 When a write of the "cp0_lock" data value is initiated by
idle
processor 0, the gate transitions into the cp0_lock state.
cp1_lock 4 When a write of the "cp1_lock" value is initiated by processor
idle
1, the gate transitions into the cp1_lock state.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 159
Semaphore (SEMA4)

Table 4-16. SEMA4_GATEn State Transitions

(continued)
Transitio
Current State Next State Description
n
cp0_lock 5 Once in this state, the gate remains here if any attempted
cp0_lock
write is not from cp0 with the unlock data value.
idle 6 The gate returns to the idle (unlocked) state once a write from
cp0_lock
cp0 with the unlock data value occurs.
cp1_lock 7 Once in this state, the gate remains here if any attempted
cp1_lock
write is not from cp1 with the unlock data value.
idle 8 The gate returns to the idle (unlocked) state once a write from
cp1_lock
cp1 with the unlock data value occurs.

4.4.2.3 SEMA4_CPnNTF Operation

The failed lock write notification interrupt request is implemented in a 3-bit, 5-state
machine which records failed lock attempts and transitions based on gate locking and
unlocking. Two specific states are encoded and program-visible as
SEMA4_CP0NTF[GNn] and SEMA4_CP1NTF[GNn]. See the following figure.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

160 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

any_reset

idle
000 ~transition_condition_3
& ~transition_condition_4

2
master == cp0 master == cp1
& (wdata == cp0_lock) & (wdata == cp1_lock)
& (gate == cp1_lock) & (gate == cp0_lock)
3 4

wait4_cp1_unlock wait4_cp0_unlock
010 001
gate != unlock

gate != unlock
5 7

10 6 8 13

gate ==cp1_lock gate == unlock gate == unlock gate == cp0_lock

wait4_cp0_lock wait4_cp1_lock
110 101
gate = !cp0_lock
& !cp1_lock
9 12
gate = !cp0_lock
11 & !cp1_lock 14

gate == cp0_lock gate == cp1_lock

Figure 4-12. IRQ Notification State Machine

The state transitions of the IRQ notification function are defined in the following table.
Specific states of this machine are program-visible as the SEMA4_CPnNTF registers. In
particular, two states are program-visible:

if state = wait4_cp0_lock (0b110) // generate cp0_semaphore_int if properly enabled

then SEMA4_CP0NTF[GNn] = 1;
else SEMA4_CP0NTF[GNn] = 0

if state = wait4_cp1_lock (0b101) // generate cp1_semaphore_int if properly enabled

then SEMA4_CP1NTF[GNn] = 1;
else SEMA4_CP1NTF[GNn] = 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 161
Semaphore (SEMA4)

Table 4-17. IRQ Notification State Transitions

Transitio
Current State Next State Description
n
idle 1 Any reset, including a system reset or an individual
– notification or secure gate reset, unconditionally forces the
machine into the idle state.
idle 2 Unless a write of the appropriate lock value from the
idle corresponding processor to an already-locked gate occurs,
the machine remains in the idle state.
wait4_cp1_unlock 3 When a write of the "cp0_lock" data value is initiated by
processor 0 but the gate is already locked by cp1, the
idle
machine transitions into this state, where it waits for cp1 to
unlock the gate.
wait4_cp0_unlock 4 When a write of the "cp1_lock" data value is initiated by
processor 1but the gate is already locked by cp0, the machine
idle
transitions into this state, where it waits for cp0 to unlock the
gate
wait4_cp1_unlock wait4_cp1_unlock 5 Once in this state, the machine remains here until the gate is
unlocked.
wait4_cp1_unlock wait4_cp0_lock 6 From this state, the machine transitions into the next state,
waiting for cp0 to lock the gate, once it has been unlocked.
wait4_cp0_unlock wait4_cp0_unlock 7 Once in this state, the machine remains here until the gate is
unlocked.
wait4_cp0_unlock wait4_cp1_lock 8 From this state, the machine transitions into the next state,
waiting for cp1 to lock the gate, once it has been unlocked.
wait4_cp0_lock 9 In this state, the machine generates the notification interrupt
wait4_cp0_lock (if properly-enabled) and remains here until the gate is locked
by processor 0 or the gate is again locked by processor 1.
wait4_cp1_unlock 10 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is again locked
wait4_cp0_lock
by processor 1. With this transition, the notification interrupt
request is negated.
idle 11 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is finally locked
wait4_cp0_lock
by processor 0. With this transition, the notification interrupt
request is negated.
wait4_cp1_lock 12 In this state, the machine generates the notification interrupt
wait4_cp1_lock (if properly-enabled) and remains here until the gate is locked
by processor 1or the gate is again locked by processor 0.
wait4_cp0_unlock 13 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is again locked
wait4_cp1_lock
by processor 0. With this transition, the notification interrupt
request is negated.
idle 14 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is finally locked
wait4_cp1_lock
by processor 1. With this transition, the notification interrupt
request is negated.

The Semaphores module generates two interrupt request output signals, one per
processor, combining the SEMA4_CPnINE and SEMA4_CPnNTF registers, where the
boolean equations are:
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
162 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

cp0_semaphore_int
= SEMA4_CP0INE[INE0] & SEMA4_CP0NTF[GN0]
| SEMA4_CP0INE[INE1] & SEMA4_CP0NTF[GN1]
| SEMA4_CP0INE[INE2] & SEMA4_CP0NTF[GN2]
...
| SEMA4_CP0INE[INE15] & SEMA4_CP0NTF[GN15]
cp1_semaphore_int
= SEMA4_CP1INE[INE0] & SEMA4_CP1NTF[GN0]
| SEMA4_CP1INE[INE1] & SEMA4_CP1NTF[GN1]
| SEMA4_CP1INE[INE2] & SEMA4_CP1NTF[GN2]
...
| SEMA4_CP1INE[INE15] & SEMA4_CP1NTF[GN15]

4.4.3 External Signal Description

The Semaphores module does not include any external interfaces.

4.4.4 Initialization Information

The reset state of the Semaphores module allows it to begin operation without the need
for any further initialization. All the internal state machines are cleared by any reset
event, allowing the module to immediately begin operation.

4.4.5 Application Information

In an operational multi-core system, most interactions involving the Semaphores module
involves reads and writes to the SEMA4_GATEn registers for implementation of the
hardware-enforced software gate functions. Typical code segments for gate functions
perform the following operations:
• To lock (close) a gate
• The processor performs a byte write of "logical_processor_number + 1" to
gate[i]
• The processor reads back gate[i] and checks for a value of
"logical_processor_number + 1"

If the compare indicates the expected value, then the gate is locked; proceed with the
protected code segment. If the compare does not indicate the expected value, the lock
operation failed; repeat the process beginning with byte write to gate[i] in spin-wait loop,
or proceed with another execution path and wait for failed lock interrupt notification.
A simple C-language example of a gateLock function is shown in the following figure.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 163
Semaphore (SEMA4)
#define UNLOCK 0
#define CP0_LOCK 1
#define CP1_LOCK 2

void gateLock (n)

int n; /* gate number to lock */
{
int i;
int current_value;
int locked_value;

i = processor_number(); /* obtain logical CPU number */

if (i == 0)
locked_value = CP0_LOCK;
else
locked_value = CP1_LOCK;

/* read the current value of the gate and wait until the state == UNLOCK */
do {
current_value = gate[n];
} while (current_value != UNLOCK);

/* the current value of the gate == UNLOCK. attempt to lock the gate for this
processor. spin-wait in this loop until gate ownership is obtained */
do {
gate[n] = locked_value; /* write gate with processor_number + 1 */
current_value = gate[n]; /* read gate to verify ownership was obtained */
} while (current_value != locked_value);

Figure 4-13. Sample gateLock Function

• To unlock (open) a gate

• After completing the protected code segment, the locking processor performs a
byte write of zeroes to gate[i], opening (unlocking) the gate

A few comments on the logical CPU number are appropriate. In this example, a reference
to processor_number() is used to retrieve this hardware configuration value. Typically, the
logical processor numbers are defined by a hardwired input vector to the individual cores.
The exact method for accessing the logical processor number varies by architecture.
If the optional failed lock IRQ notification mechanisms are used, then accesses to the
related registers (SEMA4_CPnINE, SEMA4_ CPnNTF) are required. Note that there is
no required negation of the failed lock write notification interrupt, as the request is
automatically cleared by the Semaphores module once the gate has been successfully
locked by the "failing" processor.
Finally, in the event a system state requires a software-controlled reset of a gate or IRQ
notification register(s), accesses to the secure reset control registers (SEMA4_RSTGT,
SEMA4_RSTNTF) are required. For these situations, it is recommended that the

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

164 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

appropriate IRQ notification enable (SEMA4_CPnINE) bits should be disabled before

initiating the secure reset 2-write sequence (write RSTGT and write RSTNTF), to avoid
any race conditions involving spurious notification interrupt requests.

4.4.6 Memory map and register definition

The Semaphores module provides an IPS programming model mapped to an on-platform

16 KB space. The description here specifies a dual-core configuration with 16 semaphore
gates. All the register names are prefixed with "SEMA4" as an abbreviation for the full
module name.
The programming model is referenced using 8-, 16- and 32-bit accesses. Reads can use
any reference size, while writes are generally restricted to the size of the register.
Exceptions to the write size restrictions are detailed in the individual register
descriptions. Attempted references using inappropriate access sizes, to undefined
(reserved) addresses, or with a non-supported access type (for example, a write to a read-
only register) generate an IPS error termination.
The 16 KB Semaphores programming model map is shown in the following table.
SEMA4 memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30AC_0000 Semaphores Gate n Register (SEMA4_Gate0) 8 R/W 00h 4.4.6.1/166
30AC_0001 Semaphores Gate n Register (SEMA4_Gate1) 8 R/W 00h 4.4.6.1/166
30AC_0002 Semaphores Gate n Register (SEMA4_Gate2) 8 R/W 00h 4.4.6.1/166
30AC_0003 Semaphores Gate n Register (SEMA4_Gate3) 8 R/W 00h 4.4.6.1/166
30AC_0004 Semaphores Gate n Register (SEMA4_Gate4) 8 R/W 00h 4.4.6.1/166
30AC_0005 Semaphores Gate n Register (SEMA4_Gate5) 8 R/W 00h 4.4.6.1/166
30AC_0006 Semaphores Gate n Register (SEMA4_Gate6) 8 R/W 00h 4.4.6.1/166
30AC_0007 Semaphores Gate n Register (SEMA4_Gate7) 8 R/W 00h 4.4.6.1/166
30AC_0008 Semaphores Gate n Register (SEMA4_Gate8) 8 R/W 00h 4.4.6.1/166
30AC_0009 Semaphores Gate n Register (SEMA4_Gate9) 8 R/W 00h 4.4.6.1/166
30AC_000A Semaphores Gate n Register (SEMA4_Gate10) 8 R/W 00h 4.4.6.1/166
30AC_000B Semaphores Gate n Register (SEMA4_Gate11) 8 R/W 00h 4.4.6.1/166
30AC_000C Semaphores Gate n Register (SEMA4_Gate12) 8 R/W 00h 4.4.6.1/166
30AC_000D Semaphores Gate n Register (SEMA4_Gate13) 8 R/W 00h 4.4.6.1/166
30AC_000E Semaphores Gate n Register (SEMA4_Gate14) 8 R/W 00h 4.4.6.1/166
30AC_000F Semaphores Gate n Register (SEMA4_Gate15) 8 R/W 00h 4.4.6.1/166
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 165
Memory map and register definition

SEMA4 memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Semaphores Processor n IRQ Notification Enable
30AC_0040 16 R/W 0000h 4.4.6.2/167
(SEMA4_CP0INE)
Semaphores Processor n IRQ Notification Enable
30AC_0048 16 R/W 0000h 4.4.6.2/167
(SEMA4_CP1INE)
Semaphores Processor n IRQ Notification
30AC_0080 16 R 0000h 4.4.6.3/169
(SEMA4_CP0NTF)
Semaphores Processor n IRQ Notification
30AC_0088 16 R 0000h 4.4.6.3/169
(SEMA4_CP1NTF)
30AC_0100 Semaphores (Secure) Reset Gate n (SEMA4_RSTGT) 16 R/W 0000h 4.4.6.4/171
Semaphores (Secure) Reset IRQ Notification
30AC_0104 16 R/W 0000h 4.4.6.5/173
(SEMA4_RSTNTF)

4.4.6.1 Semaphores Gate n Register (SEMA4_Gaten)

Each semaphore gate is implemented in a 2-bit finite state machine (FSM), right-justified
in a byte data structure. The hardware uses the bus master number in conjunction with the
data patterns to validate all attempted write operations. Only processor bus masters can
modify the gate registers. Once locked, a gate can (and must) be opened (unlocked) by
the locking processor core.
Multiple gate values can be read in a single access, but only a single gate can be updated
via a write operation at a time. 16- and 32-bit writes to multiple gates are allowed, but the
write data operand must only update the state of a single gate. A byte write data value of
0x03 is defined as "no operation" and does not affect the state of the corresponding gate
register. Attempts to write multiple gates in a single aligned access with a size larger than
an 8-bit (byte) reference generate an error termination and do not allow any gate state
changes
Address: 30AC_0000h base + 0h offset + (1d × i), where i=0d to 15d

Bit 7 6 5 4 3 2 1 0

Read 0 GTFSM
Write
Reset 0 0 0 0 0 0 0 0

SEMA4_Gaten field descriptions

Field Description
7–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
GTFSM Gate Finite State Machine.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

166 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SEMA4_Gaten field descriptions (continued)

Field Description
Gate Finite State Machine. The hardware gate is maintained in a 3-state implementation-unlocked, locked
by processor 0 or locked by processor 1. For more details, see SEMA4_GATEn Operation .

NOTE: The state of the gate reflects the last processor that locked it, which can be useful during system
debug.

00 The gate is unlocked (free).

01 The gate has been locked by processor 0.
10 The gate has been locked by processor 1.
11 This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as
"no operation" and do not affect the gate state machine.

4.4.6.2 Semaphores Processor n IRQ Notification Enable

(SEMA4_CPnINE)
The application of a hardware semaphore module provides an opportunity for
implementation of helpful system-level features. An example is an optional mechanism to
generate a processor interrupt after a failed lock attempt. Recall traditional software gate
functions execute a spin-wait loop in an effort to obtain and lock the referenced gate.
With this module, the processor that fails in the lock attempt could continue with other
tasks and allow a properly-enabled notification interrupt to return its execution to the
original lock function.
The optional notification interrupt function consists of two registers for each processor:
an interrupt notification enable register (SEMA4_CPnINE) and the interrupt request
register (SEMA4_CPnNTF). To support implementations with more than 16 gates, these
registers can be referenced with aligned 16- or 32-bit accesses. For the SEMA4_CPnINE
registers, unimplemented bits read as zeroes, and writes are ignored.
Address: 30AC_0000h base + 40h offset + (8d × i), where i=0d to 1d
Bit 15 14 13 12 11 10 9 8
Read INE8 INE9 INE10 INE11 INE12 INE13 INE14 INE15
Write
Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0
Read INE0 INE1 INE2 INE3 INE4 INE5 INE6 INE7
Write
Reset 0 0 0 0 0 0 0 0

SEMA4_CPnINE field descriptions

Field Description
15 Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt
INE8 notification from a failed attempt to lock gate 8.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 167
Memory map and register definition

SEMA4_CPnINE field descriptions (continued)

Field Description
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
14 Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt
INE9 notification from a failed attempt to lock gate 9.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
13 Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt
INE10 notification from a failed attempt to lock gate 10.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
12 Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt
INE11 notification from a failed attempt to lock gate 11.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
11 Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt
INE12 notification from a failed attempt to lock gate 12.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
10 Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt
INE13 notification from a failed attempt to lock gate 13.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
9 Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt
INE14 notification from a failed attempt to lock gate 14.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
8 Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt
INE15 notification from a failed attempt to lock gate 15.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
7 Interrupt Request Notification Enable 0. This field is a bitmap to enable the generation of an interrupt
INE0 notification from a failed attempt to lock gate 0.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
6 Interrupt Request Notification Enable 1. This field is a bitmap to enable the generation of an interrupt
INE1 notification from a failed attempt to lock gate 1.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
5 Interrupt Request Notification Enable 2. This field is a bitmap to enable the generation of an interrupt
INE2 notification from a failed attempt to lock gate 2.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

168 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SEMA4_CPnINE field descriptions (continued)

Field Description
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
4 Interrupt Request Notification Enable 3. This field is a bitmap to enable the generation of an interrupt
INE3 notification from a failed attempt to lock gate 3.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
3 Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt
INE4 notification from a failed attempt to lock gate 4.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
2 Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt
INE5 notification from a failed attempt to lock gate 5.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
1 Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt
INE6 notification from a failed attempt to lock gate 6.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.
0 Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt
INE7 notification from a failed attempt to lock gate 7.

0 The generation of the notification interrupt is disabled.

1 The generation of the notification interrupt is enabled.

4.4.6.3 Semaphores Processor n IRQ Notification (SEMA4_CPnNTF)

The Semaphores module optionally allows the processor that fails in the lock attempt to
continue with other tasks and allow a properly-enabled notification interrupt to return its
execution to the original lock function rather than simply execute in a spin-wait loop.
The optional notification interrupt mechanism consists of two registers for each
processor: an interrupt notification enable register (SEMA4_CPnINE) and the read-only
notification interrupt request register (SEMA4_CPnNTF). To support implementations
with more than 16 gates, these registers can be referenced with aligned 16- or 32-bit
accesses. For the SEMA4_CPnNTF registers, unimplemented bits read as zeroes.
The notification interrupt is generated via a unique finite state machine (FSM), one per
hardware gate. This machine operates in the following manner:
1. When an attempted lock fails, the FSM enters a first state where it waits until the
gate is unlocked.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 169
Memory map and register definition

2. Once unlocked, the FSM enters a second state where it generates an interrupt request
to the “failed lock” processor.
3. When the “failed lock” processor succeeds in locking the gate, the IRQ is
automatically cleared and the FSM returns to the idle state. However, if the other
processor again locks the gate, the FSM returns to the first state, clears the interrupt
request, and then waits for the gate to be unlocked (again).
The notification interrupt request is implemented in a 3-bit, 5-state machine, where two
specific states are encoded and program-visible as SEMA4_CP0NTF[GNn] and
SEMA4_CP1NTF[GNn].
Address: 30AC_0000h base + 80h offset + (8d × i), where i=0d to 1d
Bit 15 14 13 12 11 10 9 8

Read GN8 GN9 GN10 GN11 GN12 GN13 GN14 GN15

Write
Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

Read GN0 GN1 GN2 GN3 GN4 GN5 GN6 GN7

Write
Reset 0 0 0 0 0 0 0 0

SEMA4_CPnNTF field descriptions

Field Description
15 Gate 8 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN8 attempt to lock gate 8. For more details, see SEMA4_CPnNTF Operation .
14 Gate 9 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN9 attempt to lock gate 9. For more details, see SEMA4_CPnNTF Operation .
13 Gate 10 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN10 attempt to lock gate 10. For more details, see SEMA4_CPnNTF Operation .
12 Gate 11 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN11 attempt to lock gate 11. For more details, see SEMA4_CPnNTF Operation .
11 Gate 12 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN12 attempt to lock gate 12. For more details, see SEMA4_CPnNTF Operation .
10 Gate 13 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN13 attempt to lock gate 13. For more details, see SEMA4_CPnNTF Operation .
9 Gate 14 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN14 attempt to lock gate 14. For more details, see SEMA4_CPnNTF Operation .
8 Gate 15 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN15 attempt to lock gate 15. For more details, see SEMA4_CPnNTF Operation .
7 Gate 0 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN0 attempt to lock gate 0. For more details, see SEMA4_CPnNTF Operation .
6 Gate 1 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN1 attempt to lock gate 1. For more details, see SEMA4_CPnNTF Operation .
5 Gate 2 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN2 attempt to lock gate 2. For more details, see SEMA4_CPnNTF Operation .

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

170 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SEMA4_CPnNTF field descriptions (continued)

Field Description
4 Gate 3 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN3 attempt to lock gate 3. For more details, see SEMA4_CPnNTF Operation .
3 Gate 4 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN4 attempt to lock gate 4. For more details, see SEMA4_CPnNTF Operation .
2 Gate 5 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN5 attempt to lock gate 5. For more details, see SEMA4_CPnNTF Operation .
1 Gate 6 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN6 attempt to lock gate 6. For more details, see SEMA4_CPnNTF Operation .
0 Gate 7 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN7 attempt to lock gate 7. For more details, see SEMA4_CPnNTF Operation .

4.4.6.4 Semaphores (Secure) Reset Gate n (SEMA4_RSTGT)

Although the intent of the hardware gate implementation specifies a protocol where the
locking processor must unlock the gate, it is recognized that system operation may
require a reset function to re-initialize the state of any gate(s) without requiring a system-
level reset.
To support this special gate reset requirement, the Semaphores module implements a
"secure" reset mechanism which allows a hardware gate (or all the gates) to be initialized
by following a specific dual-write access pattern. Using a technique similar to that
required for the servicing of a software watchdog timer, the secure gate reset requires two
consecutive writes with predefined data patterns from the same processor to force the
clearing of the specified gate(s). The required access pattern is:
1. A processor performs a 16-bit write to the SEMA4_RSTGT memory location. The
least significant byte (SEMA4_RSTGT[RSTGDP]) must be 0xe2; the most
significant byte is a "don't_care" for this reference.
2. The same processor then performs a second 16-bit write to the SEMA4_RSTGT
location. For this write, the lower byte (SEMA4_RSTGT[RSTGDP]) is the logical
complement of the first data pattern (0x1d) and the upper byte
(SEMA4_RSTGT[RSTGTN]) specifies the gate(s) to be reset. This gate field can
specify a single gate be cleared, or that all gates are cleared.
3. Reads of the SEMA4_RSTGT location return information on the 2-bit state machine
(SEMA4_RSTGT[RSTGSM]) which implements this function, the bus master
performing the reset (SEMA4_RSTGT[RSTGMS]) and the gate number(s) last
cleared (SEMA4_RSTGT[RSTGTN]). Reads of the SEMA4_RSTGT register do not
affect the secure reset finite state machine in any manner.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 171
Memory map and register definition

Address: 30AC_0000h base + 100h offset = 30AC_0100h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read RSTGTN RSTGSM_RSTGMS_RSTGDP
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SEMA4_RSTGT field descriptions

Field Description
15–8 Reset Gate Number. This 8-bit field specifies the specific hardware gate to be reset. This field is updated
RSTGTN by the second write.
This field contains the hexidecimal value of the gate number. If RSTGTN < 64, then reset the single gate
defined by RSTGTN, else reset all the gates. The corresponding secure IRQ notification state machine(s)
are also reset.
RSTGSM_
RSTGMS_ NOTE: This field contains sub-fields that vary depending on whether it is being read or written. Sub-fields
RSTGDP indicated as having read access are valid only for read operations. Sub-fields indicated as having
write access are valid only for write operations. Bit numbering in the descriptions begins with the
most significant bit numbered 0. See the following table for details.

Access Sub-Field Description

Read-Only 7-6 Reserved. Always reads 0.
Reserved
5-4 Reset Gate Finite State Machine. Reads of the SEMA4_RSTGT
register return the encoded state machine value. The reset state
RSTGSM
machine is maintained in a 2-bit, 3-state implementation, defined as:
00 Idle, waiting for the first data pattern write.
01 Waiting for the second data pattern write.
10 The 2-write sequence has completed. Generate the specified gate
reset(s). After the reset is performed, this machine returns to the
idle (waiting for first data pattern write) state. Note that the
RSTGSM = 0b10 state is valid for only a single machine cycle, so
it is impossible for a read to return this value
11 This state encoding is never used and therefore reserved.
3 Reserved. Always reads 0.
Reserved
2-0 Reset Gate Bus Master. This 3-bit read-only field records the logical
number of the bus master performing the gate reset function. The reset
RSTGMS
function requires that the two consecutive writes to this register be
initiated by the same bus master to succeed. This field is updated each
time a write to this register occurs. The association between system
bus master port numbers, the associated bus master device and the
logical processor number is SoC-specific. See the chip-specific
information section.
Write-Only 7-0 Reset Gate Data Pattern. This write-only field is accessed with the
specified data patterns on the two consecutive writes to enable the gate
RSTGDP
reset mechanism. For the first write, RSTGDP = 0xe2 while the second
write requires RSTGDP = 0x1d.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

172 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.4.6.5 Semaphores (Secure) Reset IRQ Notification

(SEMA4_RSTNTF)
As with the case of the secure reset function of the hardware gates, it is recognized that
system operation may require a reset function to re-initialize the state of the IRQ
notification logic without requiring a system-level reset.
To support this special notification reset requirement, the Semaphores module
implements a "secure" reset mechanism which allows an IRQ notification (or all the
notifications) to be initialized by following a specific dual-write access pattern. When
successful, the specified IRQ notification state machine(s) are reset. Using a technique
similar to that required for the servicing of a software watchdog timer, the secure reset
mechanism requires two consecutive writes with predefined data patterns from the same
processor to force the clearing of the IRQ notification(s). The required access pattern is:
1. A processor performs a 16-bit write to the SEMA4_RSTNTF memory location. The
least significant byte (SEMA4_RSTNTF[RSTNDP]) must be 0x47; the most
significant byte is a "don't_care" for this reference.
2. The same processor then performs a second 16-bit write to the SEMA4_RSTNTF
location. For this write, the lower byte (SEMA4_RSTNTF[RSTNDP]) is the logical
complement of the first data pattern (0xb8) and the upper byte
(SEMA4_RSTNTF[RSTNTN]) specifies the notification(s) to be reset. This field can
specify a single notification be cleared, or that all notifications are cleared.
3. Reads of the SEMA4_RSTNTF location return information on the 2-bit state
machine (SEMA4_RSTNTF[RSTNSM]) which implements this function, the bus
master performing the reset (SEMA4_RSTNTF[RSTNMS]) and the notification
number(s) last cleared (SEMA4_RSTNTF[RSTNTN]). Reads of the
SEMA4_RSTNTF register do not affect the secure reset finite state machine in any
manner.
Address: 30AC_0000h base + 104h offset = 30AC_0104h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read RSTNTN RSTNSM_RSTNMS_RSTNDP
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SEMA4_RSTNTF field descriptions

Field Description
15–8 Reset Notification Number. This 8-bit field specifies the specific IRQ notification state machine to be reset.
RSTNTN This field is updated by the second write.
This field contains the hexidecimal value of the gate number. If RSTNTN < 64, then reset the single IRQ
notification machine defined by RSTNTN, else reset all the notifications.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 173
On-Chip RAM Memory Controller (OCRAM)

SEMA4_RSTNTF field descriptions (continued)

Field Description
RSTNSM_
RSTNMS_ NOTE: This field contains sub-fields that vary depending on whether it is being read or written. Sub-fields
RSTNDP indicated as having read access are valid only for read operations. Sub-fields indicated as having
write access are valid only for write operations. Bit numbering in the descriptions begins with the
most significant bit numbered 0. See the following table for details.

Access Sub-Field Description

Read-Only 7-6 Reserved. Always reads 0.
Reserved
5-4 Reset Notification Finite State Machine. Reads of the SEMA4_RSTNTF
register return the encoded state machine value. The reset state
RSTNSM
machine is maintained in a 2-bit, 3-state implementation, defined as:
00 Idle, waiting for the first data pattern write.
01 Waiting for the second data pattern write.
10 The 2-write sequence has completed. Generate the specified
notification reset(s). After the reset is performed, this machine
returns to the idle (waiting for first data pattern write) state. Note
the RSTNSM = 10 state is valid for only a single machine cycle,
so it is impossible for a read to return this value.
11 This state encoding is never used and therefore reserved..
3 Reserved. Always reads 0.
Reserved
2-0 Reset Notification Bus Master. This 3-bit read-only field records the
logical number of the bus master performing the notification reset
RSTNMS
function. The reset function requires that the two consecutive writes to
this register be initiated by the same bus master to succeed. This field
is updated each time a write to this register occurs. The association
between system bus master port numbers, the associated bus master
device and the logical processor number is SoC-specific. See the chip-
specific information section.
Write-Only 7-0 Reset Notification Data Pattern. This write-only field is accessed with
the specified data patterns on the two consecutive writes to enable the
RSTNDP
notification reset mechanism. For the first write, RSTNDP = 0x47 while
the second write requires RSTNDP = 0xb8.

4.5 On-Chip RAM Memory Controller (OCRAM)

4.5.1 Overview
Various options are provided for adding a pipeline or wait-states in a read/write access, in
order to ensure flexible timing control at both high and low frequencies.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

174 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.5.1.1 Block diagram

The OCRAM block diagram is shown in the figure below.

OCRAM CONTROLLER
RDATA 0[63:0]
RDATA 1[63:0]
MUX RDATA 2[63:0]
RDATA 3[63:0]

AXI RADDR

Read Read Control

Control
Module
AXI RDATA MEM_SEL[3..0]

RAM
MUX
RAM MEM_WE[3..0]
RAM
MUX
RAM
MUX
Write Control MUX
AXI WADDR
MEM_ADDR[3..0]
WDATA [63:0]

AXI WDATA Write

Control
Module MEM_WDATA [3..0]
AXI WRESP

RD
REQ
DEC
Arbiter
Arbiter
Arbiter
Timing Arbiter
WR
Configuration
REQ
DEC

Figure 4-14. OCRAM Block Diagram

4.5.2 Functional Description

4.5.2.1 Read/Write Arbitration

The detailed rules used in arbitration are as follows:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 175
On-Chip RAM Memory Controller (OCRAM)

• If there is no granted read or write in the last cycle, and there is only a read request or
a write request, the request will be granted.
• If there is no granted read or write in the last cycle, and there are both read or write
requests coming in at the same time, the read request will be granted first.
• If a granted read/write transaction has just finished, the write/read request will have
the higher priority in the next cycle.
• If the first read/write access request in a transaction is granted, all the data transfer in
this burst will be finished before the next arbitration begins, that is, the round-robin
arbitration mechanism is based on AXI transaction, not data access.

4.5.2.2 Advanced Features

This section describes some advanced features designed to avoid timing issues when the
OCRAM is working at high frequency.

4.5.2.2.1 Read Data Wait State

When the wait state is enabled, it will take 2 cycles for each read access (each beat of a
read burst).
This can avoid the potential timing problem caused by the longer memory access time at
higher frequency.
When this feature is disabled, it only takes 1 clock cycle to finish a read transaction. That
is, read data is available in the next cycle of read request becomes valid on the bus.

4.5.2.2.2 Read Address Pipeline

When this feature is enabled, the read address from the AXI master is delayed 1 cycle
before it can be accepted by the OCRAM.
This can avoid setup time issues for the read access on the memory cell at high
frequency. Enabling this feature can cost, at most, 1 more clock cycle for each AXI read
transaction, that is, at most 1 more clock cycle for each read burst with multiple beats of
data.
When this feature is disabled, the read address from the AXI master can be accepted by
the OCRAM without delay, and data can become ready for master at next clock cycle (if
no other access and no read data wait).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

176 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.5.2.2.3 Write Data Pipeline

When this feature is enabled, the write data from the AXI master would be delayed 1
cycle before it can be accepted by the OCRAM.
This can avoid setup time issue for the write access on the memory cell at high
frequency. Enabling this feature would cost at most 1 more clock cycle for each AXI
write transaction, that is, at most 1 more clock cycle for each write burst with multiple
beats of data.
When this feature is disabled, the write data from the AXI master can be accepted by the
OCRAM without delay, and data can be written to memory at this cycle (if no other
access and write address is also ready at this cycle).

4.5.2.2.4 Write Address Pipeline

When this feature is enabled, the write address from the AXI master would be delayed 1
cycle before it can be accepted by the OCRAM.
This can avoid setup time issue for the write access on the memory cell at high
frequency. Enabling this feature would take at most 1 more clock cycle for each AXI
write transaction, that is, at most 1 more clock cycle for each write burst with multiple
beats of data.
When this feature is disabled, the write address from the AXI master can be accepted by
the OCRAM without delay, and data can be written to memory at this cycle (if no other
access and write data is also ready at this cycle).

4.5.3 Programmable Registers

There are no programmable registers in this block.

4.6 Network Interconnect Bus System (NIC)

4.6.1 Overview
This section provides an overview of the NIC-301 (Network Inter-Connect) AXI arbiter
IP.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 177
AHB to IP Bridge (AIPSTZ)

The NIC-301 (by Arm Ltd.) is a configurable AXI arbiter between several masters and
slaves. The NIC-301 IP is designed so that many configuration options are selected at the
hardware design stage, determined by SoC characteristics and needs, while several other
configuration options are software-controlled.
NOTE
The NIC-301 default settings are configured by NXP's board
support package (BSP), and in most cases should not be
modified by the customer. The default settings have gone
through exhaustive testing during the validation of the part, and
have proven to work well for the part's intended target
applications. Changes to the default settings may result in a
degradation in system performance.

4.6.2 External Signals

There are no external I/O interfaces for NIC-301.

4.7 AHB to IP Bridge (AIPSTZ)

4.7.1 Overview
This section provides an overview of the AHB to IP Bridge (AIPSTZ). This particular
peripheral is designed as the bridge between AHB bus and peripherals with the lower
bandwidth IP Slave (IPS) buses.

4.7.1.1 Features
The following list summarizes the key features of the bridge:
• The bridge supports the IPS slave bus signals.
• The bridge supports 8-, 16-, and 32-bit IPS peripherals. (Accesses larger than the size
of a peripheral are not supported, except to 32-bit memory.)
• The bridge supports a pair of IPS accesses for 64-bit and certain misaligned AHB
transfers to 32-bit memory in 64-bit platforms.
• The bridge directly supports up to 32 64-Kbyte external IPS peripherals, and 2 global
external IPS peripheral spaces. The bridge occupies 1 MBytes of total address space.
• The bridge provides configurable per-block and per-master access protections.
Access permissions are based on bus master (e.g. DMA or core) privilege levels and
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
178 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

resource domain. More details on the protection features and configuration can be
found in the Security Reference Manual
• Peripheral read transactions require a minimum of 2 hclk clocks, and unbuffered
write transactions require a minimum of 3 hclk clocks.
• The bridge uses one single asynchronous reset and one global clock.

4.7.2 Clocks
The following table describes the clock sources for AIPSTZ. Please see Clock Controller
Module (CCM) for clock setting, configuration and gating information.
Table 4-18. AIPSTZ Clocks
Clock name Clock Root Description
hclk ahb_clk_root Module clock

4.7.3 Functional Description

The AIPS bridge serves as a protocol translator between the AHB system bus and the IP
bus.
Support is provided for generating a pair of 32-bit IP bus accesses when targeted by a 64-
bit system bus access, or a misaligned access which crosses a 32-bit boundary. No other
bus-sizing access support is provided.
The AHB to IP bridge is the interface between the AHB and on-chip IPS peripherals,
which are sub-blocks containing readable/writable control and status registers.
The AHB master reads and writes these registers through the AIPSTZ. The bridge
generates block enables, the block address, transfer attributes, byte enables and write data
as inputs to the IPS peripherals. The bridge captures read data from the IPS interface and
drives it on the AHB.
Each bridge that connects to the IPS (or peripherals) are referred as AIPS. The chip has
several separate AIPS modules, and peripherals are grouped and assigned under each
AIPS block. The list of peripherals are indicated as n-1, ... and n-x for AIPS-1, ... and
AIPS-x respectively.

AIPS occupies a 1-Mbyte portion of the address space. The register maps of the IPS
peripherals are located on 64-Kbyte boundaries. Each IPS peripheral is allocated one 64-
Kbyte block of the memory map, and is activated by one of the block enables from the

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 179
AHB to IP Bridge (AIPSTZ)

bridge. Up to thirty-two 64-Kbyte external IPS peripherals may be implemented,

occupying contiguous blocks of 64-Kbytes. Two global external IPS block enables are
available for the remaining address space to allow for customization and expansion of
addressed peripheral devices. In addition, a single "non-global" block enable is also
asserted whenever any of the thirty-two non-global block enables is asserted.
The bridge is responsible for indicating to IPS peripherals if an access is in supervisor or
user mode. It may block user mode accesses to certain IPS peripherals or it may allow the
individual IPS peripherals to determine if user mode accesses are allowed. In addition,
peripherals may be designated as write-protected.
The bridge supports the notion of "trusted" masters for security purposes. Masters may be
individually designated as trusted for reads, trusted for writes, or trusted for both reads
and writes, as well as being forced to look as though all accesses from a master are in
user-mode privilege level. Refer to AIPSTZ Memory Map/Register Definition for more
information.
The AIPSTZ prevents access to a peripheral if the transaction originated from a source
from a resource domain that has been explicitly omitted. Resource domains are assigned
in the RDC submodule. Please refer to the RDC chapter for programming details.
All peripheral devices are expected to only require aligned accesses equal to or smaller in
size than the peripheral size. An exception to this rule is supported for 32-bit peripherals
to allow memory to be placed on the IPS.

4.7.4 Access Protections

The AIPSTZ bridge provides programmable access protections for both masters and
peripherals. It allows the privilege level of a master to be overridden, forcing it to user-
mode privilege, and allows masters to be designated as trusted or untrusted.
Peripherals may require supervisor privilege level for access, may restrict access to a
trusted master only, and may be write-protected. IP bus peripherals are subject to access
control policies set in both CSU registers and AIPSTZ registers. An access is blocked if it
is denied by either policy.
Masters and peripherals are assigned to one or more resource domains in the RDC
submodule (see the RDC chapter for details). Depending on RDC programming, masters
transactions through the AIPSTZ may or may not be allowed access to peripherals in
different resource domains.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

180 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.7.5 Access Support

Aligned 64-bit accesses, aligned and misaligned word and half word accesses, as well as
byte accesses are supported for 32-bit peripherals. Misaligned accesses are supported to
allow memory to be placed on the IPS.
Peripheral registers must not be misaligned, although no explicit checking is performed
by the AIPS bridge. The bridge will perform two IPS transfers for 64-bit accesses, word
accesses with byte offsets of 1, 2, or 3, and for half word accesses with a byte offset of 3.
All other accesses will be performed with a single IPS transfer.
Only aligned half word and byte accesses are supported for 16-bit peripherals. All other
accesses types are unsupported, and results of such accesses are undefined. They are not
terminated with an error response.
Only byte accesses are supported for 8-bit peripherals. All other accesses types are
unsupported, and results of such accesses are undefined. They are not terminated with an
error response.

4.7.6 Initialization Information

The AIPS bridge should be programmed before use.
The following registers should be initialized: The Master Privilege Registers
(AIPSTZ_MPRs), the Peripheral Access Control registers (AIPSTZ_PACRs), and the
Off-platform Peripheral Access Control registers (AIPSTZ_OPACRs) described in
AIPSTZ Memory Map/Register Definition.

4.7.6.1 Security Block

The AIPSTZ contains a security block that is connected to each off-platform peripheral.
This block filters accesses based on write/read, non-secure, and supervisor signals.
Each peripheral can be individually configured to allow or deny each of the following
transactions as described in the table below:
Table 4-19. Peripheral Access Configuration options
Config Bit Write Non-Secure Supervisor Meaning
0 0 0 0 Secure User Read
1 0 0 1 Secure Supervisor Read

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 181
AHB to IP Bridge (AIPSTZ)

Table 4-19. Peripheral Access Configuration options (continued)

Config Bit Write Non-Secure Supervisor Meaning
2 0 1 0 Non-Secure User Read
3 0 1 1 Non-Secure Supervisor Read
4 1 0 0 Secure User Write
5 1 0 1 Secure Supervisor Write
6 1 1 0 Non-Secure User Write
7 1 1 1 Non-Secure Supervisor Write

Each peripheral has a security configuration (sec_config_X) input for determining

whether to allow or deny a given access type. These are 8-bit vectors, with each bit
corresponding to one of the transactions above as listed in the Config Bit column of
Table 4-19. If the bit is asserted (1'b1), the transaction is allowed. If the bit is negated
(1'b0), the transaction is not allowed.
For example, if peripheral 0 is configured as follows:
sec_config_0 [7:0] = 8'b0011_0011
This peripheral can only be accessed by secure transactions. Bits 0, 1, 4, and 5 are
asserted and these bits refer to the four types of secure transactions. If an insecure
transaction is attempted to this peripheral, it will result in an error.
Eight bits per peripheral across an entire system can result in a large number of
configuration bits that must be assigned and controlled, most likely in a series of registers
in another block. To reduce the number of register bits required predefined sets of
security profiles can be defined and encapsulated in an external security translation block.
The table below describes one set of security profiles that has been proposed for use with
the AIPSTZ.
Table 4-20. Security Levels
CSU_SEC_LEVEL Non-Secure User Non-Secure Secure User Secure Supervisor
Supervisor
0 RD+WR RD+WR RD+WR RD+WR
1 NOT ALLOWED RD+WR RD+WR RD+WR
2 Read Only Read Only RD+WR RD+WR
3 NOT ALLOWED Read Only RD+WR RD+WR
4 NOT ALLOWED NOT ALLOWED RD+WR RD+WR
5 NOT ALLOWED NOT ALLOWED NOT ALLOWED RD+WR
6 NOT ALLOWED NOT ALLOWED Read Only Read Only
7 NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

182 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Information regarding CSU is provided in the Security Reference Manual. Contact your
NXP representative for information about obtaining this document.
A 3-bit input, 8-bit output translation block can be used such that only three register bits
are required to set the security profile and the translation block will drive the correct 8-bit
configuration vector. Each peripheral connected to the AIPSTZ would require this
translation block. The top level AIPSTZ has this three bit input line `csu_sec_level[2:0]'
corresponding to each peripheral X.

4.7.7 Off-Platform Peripherals Index

The off-platform peripherals index allocation is shown in the following table.
Table 4-21. External IPS Peripherals
OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4
OPAC31 Reserved QoSC Reserved Reserved
OPAC30 CSU Reserved ENET1 PLATFORM_CTRL
OPAC29 RDC PERFMON2 SDMA Reserved
OPAC28 SEMAPHORE2 PERFMON1 Reserved Reserved
OPAC27 SEMAPHORE1 Reserved QSPI Reserved
OPAC26 GPC Reserved Reserved Reserved
OPAC25 SRC Reserved Reserved Reserved
OPAC24 CCM Reserved Reserved TZASC
OPAC23 SNVS_HP Reserved Reserved Reserved
OPAC22 ANA_PLL Reserved uSDHC3 Reserved
OPAC21 OCOTP_CTRL Reserved uSDHC2 Reserved
OPAC20 IOMUXC_GPR Reserved uSDHC1 Reserved
OPAC19 IOMUXC Reserved Reserved Reserved
OPAC18 Reserved Reserved Reserved Reserved
OPAC17 ROMCP Reserved Reserved Reserved
OPAC16 Reserved GPT4 Reserved PCIE_PHY1
OPAC15 GPT3 GPT5 Reserved Reserved
OPAC14 GPT2 GPT6 Reserved Reserved
OPAC13 GPT1 Reserved Reserved Reserved
OPAC12 SDMA2 System Counter_CTRL SEMAPHORE-HS Reserved
OPAC11 SDMA3 System Counter_CMP MU-B Reserved
OPAC10 WDOG3 System Counter_RD MU-A Reserved
OPAC9 WDOG2 PWM4 Reserved Reserved
OPAC8 WDOG1 PWM3 Reserved Reserved
OPAC7 ANA_OSC PWM2 Reserved Reserved
OPAC6 ANA_TSENSOR PWM1 UART4 Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 183
AHB to IP Bridge (AIPSTZ)

Table 4-21. External IPS Peripherals (continued)

OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4
OPAC5 Reserved Reserved I2C4 USB2
OPAC4 GPIO5 Reserved I2C3 USB1
OPAC3 GPIO4 Reserved I2C2 MIPI_CSI
OPAC2 GPIO3 Reserved I2C1 CSI
OPAC1 GPIO2 Reserved Reserved MIPI_DSI
OPAC0 GPIO1 Reserved Reserved LCDIF
Global external IPS peripheral
OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4
OPAC33 Reserved Reserved CAAM Reserved
OPAC32 SPBA2: SPDIF2, Reserved SPBA1: UART2, Reserved
SPDIF1, MICFIL, SAI5, UART3, UART1,
SAI6, SAI3, SAI1 eCSPI3, eCSPI2,
eCSPI1.

4.7.8 AIPSTZ Memory Map/Register Definition

The memory map for the AIPS SW-visible registers is shown in the table below.
The MPROT and OPACR fields are 4 bits in width. Some bits may be reserved
depending on device.
AIPSTZ memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3000_0000 Master Priviledge Registers (AIPSTZ_MPR) 32 R/W 7700_0000h 4.7.8.1/185
Off-Platform Peripheral Access Control Registers
3000_0040 32 R/W 4444_4444h 4.7.8.2/187
(AIPSTZ_OPACR)
Off-Platform Peripheral Access Control Registers
3000_0044 32 R/W 4444_4444h 4.7.8.3/190
(AIPSTZ_OPACR1)
Off-Platform Peripheral Access Control Registers
3000_0048 32 R/W 4444_4444h 4.7.8.4/193
(AIPSTZ_OPACR2)
Off-Platform Peripheral Access Control Registers
3000_004C 32 R/W 4444_4444h 4.7.8.5/196
(AIPSTZ_OPACR3)
Off-Platform Peripheral Access Control Registers
3000_0050 32 R/W 4444_4444h 4.7.8.6/199
(AIPSTZ_OPACR4)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

184 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.7.8.1 Master Priviledge Registers (AIPSTZ_MPR)

Each AIPSTZ_MPR specifies 16 4-bit fields defining the access privilege level
associated with a bus master in the platform, as well as specifying whether write accesses
from this master are bufferable shown in Table 4-22
The registers provide one field per bus master, where field 15 corresponds to master 15,
field 14 to master 14,... field 0 to master 0 (typically the processor core). The master
index allocation is shown in the table below.
Table 4-22. MPROT Field
Bit Field Description
3 MBW Master Buffer Writes - This bit determines whether the AIPSTZ is enabled to buffer writes
from this master.
2 MTR Master Trusted for Reads - This bit determines whether the master is trusted for read
accesses.
1 MTW Master Trusted for Writes - This bit determines whether the master is trusted for write
accesses.
0 MPL Master Privilege Level - This bit determines how the privilege level of the master is
determined.

NOTE
The reset value is set to 0000_0000_7700_0000, which makes
master 0 and master 1 (Arm CORE) the trusted masters.
Trusted software can change the settings after reset.
Table 4-23. Master Index Allocation
Master Index Master Name Comments
Master 0 All masters excluding Arm core Share the same number allocation.
Master 1 Arm A53
Master 4 SDMA
Master 6 M4

Address: 3000_0000h base + 0h offset = 3000_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MPROT0 MPROT1 MPROT2 MPROT3 Reserved MPROT5 Reserved
Reset 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 185
AHB to IP Bridge (AIPSTZ)

AIPSTZ_MPR field descriptions

Field Description
31–28 Master 0 Priviledge, Buffer, Read, Write Control
MPROT0
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
27–24 Master 1 Priviledge, Buffer, Read, Write Control
MPROT1
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
23–20 Master 2 Priviledge, Buffer, Read, Write Control
MPROT2
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
19–16 Master 3 Priviledge, Buffer, Read, Write Control.
MPROT3
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

186 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AIPSTZ_MPR field descriptions (continued)

Field Description
15–12 This field is reserved.
- Reserved
11–8 Master 5 Priviledge, Buffer, Read, Write Control.
MPROT5
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
- This field is reserved.
Reserved

4.7.8.2 Off-Platform Peripheral Access Control Registers

(AIPSTZ_OPACR)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-24
Table 4-24. OPAC Field
Bit Field Description
3 BW Buffer Writes - This bit determines whether write accesses to this peripheral are allowed to
be buffered.1
2 SP Supervisor Protect - This bit determines whether the peripheral requires supervisor privilege
level for access.
1 WP Write Protect - This bit determines whether the peripheral allows write accesses.
0 TP Trusted Protect - This bit determines whether the peripheral allows accesses from an
untrusted master.

1. Buffered writes are not available for AIPSTZ. This bit should be set to '0'.

Address: 3000_0000h base + 40h offset = 3000_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC0 OPAC1 OPAC2 OPAC3 OPAC4 OPAC5 OPAC6 OPAC7
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 187
AHB to IP Bridge (AIPSTZ)

AIPSTZ_OPACR field descriptions

Field Description
31–28 Off-platform Peripheral Access Control 0
OPAC0
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 1
OPAC1
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 2
OPAC2
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 3
OPAC3
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

188 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AIPSTZ_OPACR field descriptions (continued)

Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 4
OPAC4
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 5
OPAC5
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 6
OPAC6
xxx0 TP0 — Accesses from an untrusted master are allowed.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 189
AHB to IP Bridge (AIPSTZ)

AIPSTZ_OPACR field descriptions (continued)

Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC7 Off-platform Peripheral Access Control 7

xxx0 TP0 — Accesses from an untrusted master are allowed.

xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

4.7.8.3 Off-Platform Peripheral Access Control Registers

(AIPSTZ_OPACR1)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-24
Address: 3000_0000h base + 44h offset = 3000_0044h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC8 OPAC9 OPAC10 OPAC11 OPAC12 OPAC13 OPAC14 OPAC15
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

190 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AIPSTZ_OPACR1 field descriptions

Field Description
31–28 Off-platform Peripheral Access Control 8
OPAC8
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 9
OPAC9
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 10
OPAC10
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 11
OPAC11
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 191
AHB to IP Bridge (AIPSTZ)

AIPSTZ_OPACR1 field descriptions (continued)

Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 12
OPAC12
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 13
OPAC13
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 14
OPAC14
xxx0 TP0 — Accesses from an untrusted master are allowed.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

192 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AIPSTZ_OPACR1 field descriptions (continued)

Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC15 Off-platform Peripheral Access Control 15

xxx0 TP0 — Accesses from an untrusted master are allowed.

xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

4.7.8.4 Off-Platform Peripheral Access Control Registers

(AIPSTZ_OPACR2)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-24
Address: 3000_0000h base + 48h offset = 3000_0048h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC16 OPAC17 OPAC18 OPAC19 OPAC20 OPAC21 OPAC22 OPAC23
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 193
AHB to IP Bridge (AIPSTZ)

AIPSTZ_OPACR2 field descriptions

Field Description
31–28 Off-platform Peripheral Access Control 16
OPAC16
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 17
OPAC17
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 18
OPAC18
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 19
OPAC19
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

194 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AIPSTZ_OPACR2 field descriptions (continued)

Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 20
OPAC20
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 21
OPAC21
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 22
OPAC22
xxx0 TP0 — Accesses from an untrusted master are allowed.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 195
AHB to IP Bridge (AIPSTZ)

AIPSTZ_OPACR2 field descriptions (continued)

Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC23 Off-platform Peripheral Access Control 23

xxx0 TP0 — Accesses from an untrusted master are allowed.

xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

4.7.8.5 Off-Platform Peripheral Access Control Registers

(AIPSTZ_OPACR3)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-24
Address: 3000_0000h base + 4Ch offset = 3000_004Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC24 OPAC25 OPAC26 OPAC27 OPAC28 OPAC29 OPAC30 OPAC31
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

196 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AIPSTZ_OPACR3 field descriptions

Field Description
31–28 Off-platform Peripheral Access Control 24
OPAC24
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 25
OPAC25
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 26
OPAC26
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 27
OPAC27
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 197
AHB to IP Bridge (AIPSTZ)

AIPSTZ_OPACR3 field descriptions (continued)

Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 28
OPAC28
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 29
OPAC29
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 30
OPAC30
xxx0 TP0 — Accesses from an untrusted master are allowed.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

198 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AIPSTZ_OPACR3 field descriptions (continued)

Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC31 Off-platform Peripheral Access Control 31

xxx0 TP0 — Accesses from an untrusted master are allowed.

xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

4.7.8.6 Off-Platform Peripheral Access Control Registers

(AIPSTZ_OPACR4)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-24
Address: 3000_0000h base + 50h offset = 3000_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC32 OPAC33 Reserved
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 199
Shared Peripheral Bus Arbiter (SPBA)

AIPSTZ_OPACR4 field descriptions

Field Description
31–28 Off-platform Peripheral Access Control 32
OPAC32
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 33
OPAC33
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
- This field is reserved.
Reserved

4.8 Shared Peripheral Bus Arbiter (SPBA)

4.8.1 Overview
The Shared Peripheral Bus Arbiter (SPBA) is a three-to-one IP Bus interface arbiter.
Three masters arbitrate for shared peripheral access through the SPBA.
The SPBA has three primary functions:
• The IP Bus Line switches a master to one peripheral

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

200 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• The Masters arbiter arbitrates between the three masters to solve concurrent access or
restricted access to peripherals
• The Control Registers and Ownership Control includes a set of registers which are
reachable through software and permit the access scheme to be defined for each
peripheral (Resource Ownership and Access Control). It generates signals for the
external steering logic of interrupts and DMA signals.
The figure below shows the SPBA block diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 201
Shared Peripheral Bus Arbiter (SPBA)

MASTER A MASTER B MASTER C

mb_dead_owner
ma_dead_owner
mc_dead_owner

Control
Registers
obsc0 Masters
+
IOSRTR Arbitration
obsc31 Ownership
module
Control
SPBA

IP-bus interface

IPMUX

Per0 Per30

Out-of-band signals

Figure 4-15. SPBA Block Diagram

4.8.1.1 Features
The SPBA includes the following features:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

202 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• Three IP Bus masters arbitration: Master A, B and C

• Support for DMA masters
• 32-bit data
• Supports up to 31 shared peripherals, each consuming 64 kilobytes of address space
• SPBA can be considered the 32nd peripheral, used for resource ownership and access
control of the 31 peripherals
• Provides 31 sets of out of band steering control (OBSC) signals to the off-block
steering logic
• Operating frequency up to 67 MHz
• Clocks: ipg_clk, ipg_clk_s

4.8.1.2 Modes of operation

SPBA behavior is transparent when accessing a peripheral, though it has these distinct
modes of operation.
Reset/Abort
The SPBA has a hardware reset which initializes all registers, arbitration and
peripherals rights registers (PRRs).
An abort signal input is provided allowing each master to abort its current access and
release ownership (in case of master reset sequence).
Functional
Once a master request is granted, its IP Bus signals are steered to the requested
peripheral.
Standby
No clock needed. The SPBA needs clocks only during access to the PRRs, arbitration,
and abort phases. It generates two clock enable signals indicating when the clocks
must be provided.
Configuration
During this phase, a master accesses the SPBA PRRs. The SPBA memory-mapped
registers are seen as a shared peripheral.

4.8.2 Clocks
The table found here describes the clock sources for SPBA.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 203
Shared Peripheral Bus Arbiter (SPBA)

Please see Clock Controller Module (CCM) for clock setting, configuration and gating
information.
Table 4-25. SPBA Clocks
Clock name Clock Root Description
ipg_clk ipg_clk_root Peripheral clock
ipg_clk_s ipg_clk_root Peripheral access clock

4.8.3 Functional description

4.8.3.1 Masters arbitration

The arbitration mechanism determines which port will control the master port, based on a
simple round-robin arbitration scheme.
There are several use cases to consider.
• Only one master request per access. The master is switched to the shared peripheral
bus, without arbitration. Figure 4-16 shows the MB request on the global module
enable signal, served without wait state.
• If two masters simultaneously access SPBA, the last granted master is held off using
the <master>_ips_xfr_wait output signal (default value is high). When the master is
granted sips_xfr_wait, shared IP Bus peripheral is connected to
<master>_ips_xfr_wait outputs.
• If three masters simultaneously access SPBA, then the last two granted masters are
held off using <master>_ips_xfr_wait. Figure 4-17 shows a case in which the last
two accesses granted are MA and MB. The requests are used even if they are in the
same cycle.
• If after reset, at the first multiple access, no master has been granted, the priority is
static: Master A (MA), Master B (MB) and last Master C (MC) port.
• No master request. No master switch to shared peripherals.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

204 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

ipg_clk

mb_ips_module_en

mb_ips_addr[24:0] 0x0000000

mb_ips_xfr_wait

mb_ips_rdata[31:0] valid data

sips_module_en[0]

sips_ips_xfr_wait

sips_rdata[31:0] valid data

Figure 4-16. Example of one master request, no SPBA arbitration

The following figure assumes MA and MB have been the last two masters granted in the
previous transfers (MA then MB).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 205
Shared Peripheral Bus Arbiter (SPBA)

clk

mb_ips_module_en

mb_ips_addr[24:0] 0x0000000

mb_ips_xfer_wait

mb_ips_rdata[31:0] valid data

ma_ips_module_en

ma_ips_addr[24:0] 0x004000

ma_ips_xfer_wait

ma_ips_rdata[31:0] valid data

mc_ips_module_en

mc_ips_addr[24:0] 0x0008000

mc_ips_xfer_wait

mc_ips_rdata[31:0] valid data

sips_module_en[0]

sips_module_en[1]

sips_module_en[2]

MASTER_GRANTED MC MA MB

Figure 4-17. Example of three master requests: Masters already granted are "waited";

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

206 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.8.4 Resource ownership control

The resource ownership control regulates access to the shared peripherals and determines
the steering of out-of-band signals.

4.8.4.1 Access control

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 207
Shared Peripheral Bus Arbiter (SPBA)

4.8.4.1.1 Peripheral access

The peripheral access (resource access) of the requesting master is given by the
corresponding RAR bit of the Peripheral Right Register. It determines if the master has
access privilege to the resource.
Any attempt at access made by a requesting master whose access privilege bit is not set
(in the PRR) is terminated with a bus error (<master>_ips_xfr_err is asserted by SPBA
logic). The master that owns the resource can lock the peripheral for itself and/or grant
other masters access to the peripheral by setting the appropriate bit(s) in the RAR field.

ipg_clk_s

mb_ips_module_en

mb_ips_addr[24:0] 0x3C008

mb_ips_wdata[31:0] 31'd2

mb_ips_rwb

mb_ips_xfr_wait

obsc2[4:0] 5'b10010

Master B is taking ownership of peripheral 2 by writing 3'b010 in the SPBA peripheral 2 right register (rarfield)
This ownership can be checked on obsc2 output as roi2[1:0] = 2'b10 and rar2[2:0] = 3'b010
(obsc[4:0] = {roi2[1], roi2[0], rar2[2], rar2[1], rar2[0]})

Figure 4-18. Example of one master B gaining ownership of peripheral 2

4.8.4.1.2 Peripheral Right Register access

The ROI bits of the Peripheral Right Register (PRR) determine which master is allowed
to make write access to PRR. The identification of the requesting master is compared to
the ROI bits of the PRR to determine if the master has ownership of the corresponding
register.
Any attempted write access to a PRR already owned by another master will be ignored.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

208 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.8.4.2 Owner election

When the peripheral is not owned by any master (ROI="00", after coming out of reset for
instance), the first master to perform successfully a write to the RAR bits of the PRR is
granted ownership of the peripheral and its associated PRR.
After writing to the PRR (RAR bit(s)), the master must read it back to make sure that it
was granted ownership. If the RMO field is 2'b11, then the ownership claim is successful.
If RMO is 2'b10, another master claimed ownership before this master was able to
complete its write. This resolves the case in which two or more masters attempt to write
the PRR at the same time; only the first master will be granted ownership. However all
masters must read the PRR to determine if this case occurred, and if so, whether they
were the first master which was granted ownership.
NOTE
A master that has been granted ownership of the PRR does not
automatically have the right access to the peripheral; it must
still set its own RAR bits in the PRR to access the peripheral.

4.8.4.3 Ending ownership

Ownership may be voluntarily ended by the owning master, or automatically upon
assertion of a master-specific dead_owner signal.
The former is appropriate for software-controlled yielding of ownership. The latter is
appropriate for automatic yielding of ownership when the owner has gone into reset.
When a master is reset, it clears the ROI bits of the PRRs owned by the corresponding
master. When the owner is dead (in reset), all peripherals previously owned by that
master must be changed to the un-owned state.
NOTE
It is the programmer's responsibility to make sure the
peripherals are placed in an appropriate state before ending
ownership.

4.8.4.3.1 Software Controlled Ownership Ending

The ROI bits will be automatically cleared when the master that owns the PRR access
right clears (write) the RAR bits (Table 2).
It will then end the ownership of the PRR.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 209
Shared Peripheral Bus Arbiter (SPBA)

4.8.4.4 The Un-owned State

During the time when the peripheral is un-owned (i.e the ROI field contains all 0's), all
masters have full access to it (RAR bits can then be modified by a master if ROI[1:0] =
2'b0).
In such cases it is necessary for software to ensure any necessary coherency in the
resource, there is no hardware protection.

4.8.5 SPBA Memory Map/Register Definition

The SPBA control registers (Peripheral Right Registers) are mapped as a virtual shared
peripheral.
SPBA can support up to 31 shared peripherals. Each of them has its own Peripheral Right
Register (PRR) accessible within the SPBA memory-mapped registers, and consists of
the Requesting Master Owner, the Resource Owner ID and the Resource Access Right
fields.
SPBA memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
300F_0000 Peripheral Rights Register (SPBA2_PRR0) 32 R/W 0000_0007h 4.8.5.1/212
300F_0004 Peripheral Rights Register (SPBA2_PRR1) 32 R/W 0000_0007h 4.8.5.1/212
300F_0008 Peripheral Rights Register (SPBA2_PRR2) 32 R/W 0000_0007h 4.8.5.1/212
300F_000C Peripheral Rights Register (SPBA2_PRR3) 32 R/W 0000_0007h 4.8.5.1/212
300F_0010 Peripheral Rights Register (SPBA2_PRR4) 32 R/W 0000_0007h 4.8.5.1/212
300F_0014 Peripheral Rights Register (SPBA2_PRR5) 32 R/W 0000_0007h 4.8.5.1/212
300F_0018 Peripheral Rights Register (SPBA2_PRR6) 32 R/W 0000_0007h 4.8.5.1/212
300F_001C Peripheral Rights Register (SPBA2_PRR7) 32 R/W 0000_0007h 4.8.5.1/212
300F_0020 Peripheral Rights Register (SPBA2_PRR8) 32 R/W 0000_0007h 4.8.5.1/212
300F_0024 Peripheral Rights Register (SPBA2_PRR9) 32 R/W 0000_0007h 4.8.5.1/212
300F_0028 Peripheral Rights Register (SPBA2_PRR10) 32 R/W 0000_0007h 4.8.5.1/212
300F_002C Peripheral Rights Register (SPBA2_PRR11) 32 R/W 0000_0007h 4.8.5.1/212
300F_0030 Peripheral Rights Register (SPBA2_PRR12) 32 R/W 0000_0007h 4.8.5.1/212
300F_0034 Peripheral Rights Register (SPBA2_PRR13) 32 R/W 0000_0007h 4.8.5.1/212
300F_0038 Peripheral Rights Register (SPBA2_PRR14) 32 R/W 0000_0007h 4.8.5.1/212
300F_003C Peripheral Rights Register (SPBA2_PRR15) 32 R/W 0000_0007h 4.8.5.1/212
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

210 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SPBA memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
300F_0040 Peripheral Rights Register (SPBA2_PRR16) 32 R/W 0000_0007h 4.8.5.1/212
300F_0044 Peripheral Rights Register (SPBA2_PRR17) 32 R/W 0000_0007h 4.8.5.1/212
300F_0048 Peripheral Rights Register (SPBA2_PRR18) 32 R/W 0000_0007h 4.8.5.1/212
300F_004C Peripheral Rights Register (SPBA2_PRR19) 32 R/W 0000_0007h 4.8.5.1/212
300F_0050 Peripheral Rights Register (SPBA2_PRR20) 32 R/W 0000_0007h 4.8.5.1/212
300F_0054 Peripheral Rights Register (SPBA2_PRR21) 32 R/W 0000_0007h 4.8.5.1/212
300F_0058 Peripheral Rights Register (SPBA2_PRR22) 32 R/W 0000_0007h 4.8.5.1/212
300F_005C Peripheral Rights Register (SPBA2_PRR23) 32 R/W 0000_0007h 4.8.5.1/212
300F_0060 Peripheral Rights Register (SPBA2_PRR24) 32 R/W 0000_0007h 4.8.5.1/212
300F_0064 Peripheral Rights Register (SPBA2_PRR25) 32 R/W 0000_0007h 4.8.5.1/212
300F_0068 Peripheral Rights Register (SPBA2_PRR26) 32 R/W 0000_0007h 4.8.5.1/212
300F_006C Peripheral Rights Register (SPBA2_PRR27) 32 R/W 0000_0007h 4.8.5.1/212
300F_0070 Peripheral Rights Register (SPBA2_PRR28) 32 R/W 0000_0007h 4.8.5.1/212
300F_0074 Peripheral Rights Register (SPBA2_PRR29) 32 R/W 0000_0007h 4.8.5.1/212
300F_0078 Peripheral Rights Register (SPBA2_PRR30) 32 R/W 0000_0007h 4.8.5.1/212
300F_007C Peripheral Rights Register (SPBA2_PRR31) 32 R/W 0000_0007h 4.8.5.1/212
308F_0000 Peripheral Rights Register (SPBA1_PRR0) 32 R/W 0000_0007h 4.8.5.1/212
308F_0004 Peripheral Rights Register (SPBA1_PRR1) 32 R/W 0000_0007h 4.8.5.1/212
308F_0008 Peripheral Rights Register (SPBA1_PRR2) 32 R/W 0000_0007h 4.8.5.1/212
308F_000C Peripheral Rights Register (SPBA1_PRR3) 32 R/W 0000_0007h 4.8.5.1/212
308F_0010 Peripheral Rights Register (SPBA1_PRR4) 32 R/W 0000_0007h 4.8.5.1/212
308F_0014 Peripheral Rights Register (SPBA1_PRR5) 32 R/W 0000_0007h 4.8.5.1/212
308F_0018 Peripheral Rights Register (SPBA1_PRR6) 32 R/W 0000_0007h 4.8.5.1/212
308F_001C Peripheral Rights Register (SPBA1_PRR7) 32 R/W 0000_0007h 4.8.5.1/212
308F_0020 Peripheral Rights Register (SPBA1_PRR8) 32 R/W 0000_0007h 4.8.5.1/212
308F_0024 Peripheral Rights Register (SPBA1_PRR9) 32 R/W 0000_0007h 4.8.5.1/212
308F_0028 Peripheral Rights Register (SPBA1_PRR10) 32 R/W 0000_0007h 4.8.5.1/212
308F_002C Peripheral Rights Register (SPBA1_PRR11) 32 R/W 0000_0007h 4.8.5.1/212
308F_0030 Peripheral Rights Register (SPBA1_PRR12) 32 R/W 0000_0007h 4.8.5.1/212
308F_0034 Peripheral Rights Register (SPBA1_PRR13) 32 R/W 0000_0007h 4.8.5.1/212
308F_0038 Peripheral Rights Register (SPBA1_PRR14) 32 R/W 0000_0007h 4.8.5.1/212
308F_003C Peripheral Rights Register (SPBA1_PRR15) 32 R/W 0000_0007h 4.8.5.1/212
308F_0040 Peripheral Rights Register (SPBA1_PRR16) 32 R/W 0000_0007h 4.8.5.1/212
308F_0044 Peripheral Rights Register (SPBA1_PRR17) 32 R/W 0000_0007h 4.8.5.1/212
308F_0048 Peripheral Rights Register (SPBA1_PRR18) 32 R/W 0000_0007h 4.8.5.1/212
308F_004C Peripheral Rights Register (SPBA1_PRR19) 32 R/W 0000_0007h 4.8.5.1/212
308F_0050 Peripheral Rights Register (SPBA1_PRR20) 32 R/W 0000_0007h 4.8.5.1/212
308F_0054 Peripheral Rights Register (SPBA1_PRR21) 32 R/W 0000_0007h 4.8.5.1/212
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 211
Shared Peripheral Bus Arbiter (SPBA)

SPBA memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
308F_0058 Peripheral Rights Register (SPBA1_PRR22) 32 R/W 0000_0007h 4.8.5.1/212
308F_005C Peripheral Rights Register (SPBA1_PRR23) 32 R/W 0000_0007h 4.8.5.1/212
308F_0060 Peripheral Rights Register (SPBA1_PRR24) 32 R/W 0000_0007h 4.8.5.1/212
308F_0064 Peripheral Rights Register (SPBA1_PRR25) 32 R/W 0000_0007h 4.8.5.1/212
308F_0068 Peripheral Rights Register (SPBA1_PRR26) 32 R/W 0000_0007h 4.8.5.1/212
308F_006C Peripheral Rights Register (SPBA1_PRR27) 32 R/W 0000_0007h 4.8.5.1/212
308F_0070 Peripheral Rights Register (SPBA1_PRR28) 32 R/W 0000_0007h 4.8.5.1/212
308F_0074 Peripheral Rights Register (SPBA1_PRR29) 32 R/W 0000_0007h 4.8.5.1/212
308F_0078 Peripheral Rights Register (SPBA1_PRR30) 32 R/W 0000_0007h 4.8.5.1/212
308F_007C Peripheral Rights Register (SPBA1_PRR31) 32 R/W 0000_0007h 4.8.5.1/212

4.8.5.1 Peripheral Rights Register (SPBAx_PRRn)

This register controls master ownership and access for a peripheral.

Address: Base address + 0h offset + (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R RMO ROI

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
RARC

RARA

Reserved RARB

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

212 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SPBAx_PRRn field descriptions

Field Description
31–30 Requesting Master Owner. This 2-bit register field indicates if the corresponding resource is owned by the
RMO requesting master or not. This register is reset to 2'b0 if ROI = 2'b0.

00 UNOWNED — The resource is unowned.

01 Reserved.
10 ANOTHER_MASTER — The resource is owned by another master.
11 REQUESTING_MASTER — The resource is owned by the requesting master.
29–18 This field is reserved.
- Reserved
17–16 Resource Owner ID. This field indicates which master (one at a time) can access to the PRR for rights
ROI modification. This is a read-only register.
After reset, ROI bits are cleared ("00" -> un-owned resource).
A master performing a write access to the an un-owned PRR will get its ID automatically written into ROI,
while modifying RARx bits. It can then read back the RMO, RAR, ROI bits to make sure RMO returns the
right value, ROI bits contain its ID and RARx bits are correctly asserted. Then no other master (whom ID is
different from the one stored in ROI) will be able to modify RAR fields.
Owner master of a peripheral can assert its dead_owner signal, or write 1'b0 in the RARx to release the
ownership (ROI[1:0] reset to 2'b0).

00 UNOWNED — Unowned resource.

01 MASTER_A — The resource is owned by master A port.
10 MASTER_B — The resource is owned by master B port.
11 MASTER_C — The resource is owned by master C port.
15–3 This field is reserved.
- Reserved
2 Resource Access Right. Control and Status bit for master C.
RARC
This field indicates whether master C can access the peripheral. From 0 up to 3 masters can have
permission to access a resource (all the master can be granted on a peripheral, but only one access at a
time will be granted by SPBA).

0 PROHIBITED — Access to peripheral is not allowed.

1 ALLOWED — Access to peripheral is granted.
1 Resource Access Right. Control and Status bit for master B.
RARB
This field indicates whether master B can access the peripheral. From 0 up to 3 masters can have
permission to access a resource (all the master can be granted on a peripheral, but only one access at a
time will be granted by SPBA).

0 PROHIBITED — Access to peripheral is not allowed.

1 ALLOWED — Access to peripheral is granted.
0 Resource Access Right. Control and Status bit for master A.
RARA
This field indicates whether master A can access the peripheral. From 0 up to 3 masters can have
permission to access a resource (all the master can be granted on a peripheral, but only one access at a
time will be granted by SPBA).

0 PROHIBITED — Access to peripheral is not allowed.

1 ALLOWED — Access to peripheral is granted.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 213
System Counter (SYS_CTR)

4.9 System Counter (SYS_CTR)

4.9.1 Overview
The System Counter (SYS_CTR) is a programmable system counter, which provides a
shared time base to multiple processors. It is intended for applications where the counter
is always powered on, and supports multiple unrelated clocks.

4.9.1.1 Block Diagram

The block diagram of the System Counter is shown below.

Processor
System Platform 0
Bus
Counter 56-bit, Gray

24 MHz base_clk
32 kHz slow_clk
Processor
Platform 1

Figure 4-19. System Counter Block Diagram

4.9.1.2 Features
• Two counter clock frequencies
• Base clock for normal operation
• Alternate clock for low power operation
• 56-bit counter width
• Gray coded counter output for distribution to the processor timers
• 2 Compare Frames
• Each compare frame contains a 64-bit compare value
• Each compare frame contains programmable interrupt generation

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

214 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.2 Functional Description

The System Counter inputs two counter clock sources and outputs a gray coded counter
value and interrupt signals (one per compare frame) to the platform’s interrupt controller.

4.9.2.1 Operation
After reset, the System Counter is disabled with count value reset to zero and base
frequency selected. Once the counter is enabled, it will increment the appropriate value
on each rising edge of the selected clock. Because the System Counter is handling a 56-
bit count value across multiple clock domains, synchronization is necessary. The System
Counter provides synchronization mechanisms between the various clock domains.
When the system switches the counter’s clock source, there is a short pause while the
clock multiplexer is handling the clock transition. In order to maintain an accurate count
value, the clock control logic employs two offset counters; one for the base-to-slow
transtion and one for the slow-to-base transition. These offset counters only operate
during the clock transition time to compensate for the idled source clock. Both counters
run off of the base clock. The transition offset values are added to the system count value
at the appropriate time when the counter’s clock is restored.
NOTE
Both base clock and alternate clock must be running when
changing frequencies.

4.9.2.2 Clocks
The System Counter clocks are shown in the table below.
Table 4-26. Clocks
Clock Description
ipg_clk Peripheral Clock
ipg_clk_s Gated peripheral clock for register transactions
base_clk Base Clock. This clock is used during normal operation. It is internally divided by 3
before use.
slow_clk Slow Clock. This clock is used during low power mode. It is internally divided by 64
before use.
ctr_clk Counter Clock. The ctr_clk is generated by selecting either the base_clk or slow_clk.
Because the compare frame must generate an interrupt when either clock is selected,
most of the compare frame logic resides in this clock domain.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 215
Memory Map and Register Description

4.9.3 Programming Model

The System Counter module contians three programmer’s model sections. Each sections
has an indepentent module enable to allow individual secure access control.
Table 4-27. Programming Model
Programming Model Description
CNTControlBase This model controls the counter frequency, enable, debug, and count value. This model
also contains the frequency modes table which supplies control and status for the
frequency of the System Counter.
CNTReadBase This model allows the user to read the count value.
CNTCompareBase This model controls the compare value frequency, enable, interrupt mask, and interrupt
status for each compare frame.

4.9.4 Memory Map and Register Description

SYS_CTR_CONTROL Hardware Register Format Summary

SYS_CTR_CONTROL memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
306C_0000 Counter Control Register (SYS_CTR_CONTROL_CNTCR) 32 R/W 0000_0000h 4.9.4.1/217
306C_0004 Counter Status Register (SYS_CTR_CONTROL_CNTSR) 32 R 0000_0100h 4.9.4.2/219
Counter Count Value Low Register
306C_0008 32 R/W 0000_0000h 4.9.4.3/220
(SYS_CTR_CONTROL_CNTCV0)
Counter Count Value High Register
306C_000C 32 R/W 0000_0000h 4.9.4.4/221
(SYS_CTR_CONTROL_CNTCV1)
Frequency Modes Table 0 Register
306C_0020 32 R 007A_1200h 4.9.4.5/221
(SYS_CTR_CONTROL_CNTFID0)
Frequency Modes Table 1 Register
306C_0024 32 R 0000_0200h 4.9.4.6/222
(SYS_CTR_CONTROL_CNTFID1)
Frequency Modes Table 2 Register
306C_0028 32 R 0000_0000h 4.9.4.7/222
(SYS_CTR_CONTROL_CNTFID2)
306C_0FD0 Counter ID Register (SYS_CTR_CONTROL_CNTID0) 32 R 0000_0000h 4.9.4.8/223
Counter Count Value Low Register
306A_0000 32 R 0000_0000h 4.9.4.1/224
(SYS_CTR_READ_CNTCV0)
Counter Count Value High Register
306A_0004 32 R 0000_0000h 4.9.4.2/224
(SYS_CTR_READ_CNTCV1)
306A_0FD0 Counter ID Register (SYS_CTR_READ_CNTID0) 32 R 0000_0000h 4.9.4.3/225

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

216 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SYS_CTR_CONTROL memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Compare Count Value Low Register
306B_0020 32 R 0000_0000h 4.9.4.1/225
(SYS_CTR_COMPARE_CMPCVL0)
Compare Count Value High Register
306B_0024 32 R 0000_0000h 4.9.4.2/226
(SYS_CTR_COMPARE_CMPCVH0)
Compare Control Register
306B_002C 32 R/W 0000_0000h 4.9.4.3/226
(SYS_CTR_COMPARE_CMPCR0)
Compare Count Value Low Register
306B_0120 32 R 0000_0000h 4.9.4.1/225
(SYS_CTR_COMPARE_CMPCVL1)
Compare Count Value High Register
306B_0124 32 R 0000_0000h 4.9.4.2/226
(SYS_CTR_COMPARE_CMPCVH1)
Compare Control Register
306B_012C 32 R/W 0000_0000h 4.9.4.3/226
(SYS_CTR_COMPARE_CMPCR1)
306B_0FD0 Counter ID Register (SYS_CTR_COMPARE_CNTID0) 32 R 0000_0000h 4.9.4.4/228

4.9.4.1 Counter Control Register (SYS_CTR_CONTROL_CNTCR)

The 32-bit Counter Control Register defines the basic operating configuration of the
System Counter.
The System Counter operates using a fixed base frequency. However, the counter can
increment at a lower, alternate frequency than the base frequency, using a
correspondingly larger increment. For example, it can increment by 15625 and run at a
frequency of 1/15625 of the base frequency. The two frequencies available are
indentified in the frequency modes table. These two frequencies are the base frequency
(table entry 0) and the lower, alternate frequency (table entry 1). Setting the FCR1 bit
selects the alternate frequency. Setting the FCR0 bit selects the base frequency. Setting or
clearing both FCR0 and FCR1 will have no effect; the freqeuncy will not change.
Address: 306C_0000h base + 0h offset = 306C_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
HDBG

Reserved FCR1 FCR0 Reserved EN

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 217
Memory Map and Register Description

SYS_CTR_CONTROL_CNTCR field descriptions

Field Description
31–10 This field is reserved.
- Reserved
9 Frequency Change Request, ID 1
FCR1
0 No change.
1 Select frequency modes table entry 1, the base frequency.
8 Frequency Change Request, ID 0
FCR0
0 No change.
1 Select frequency modes table entry 0, the base frequency.
7–2 This field is reserved.
- Reserved
1 Enable Debug
HDBG
0 The assertion of the debug input is ignored.
1 The assertion of the debug input causes the System Counter to halt.
0 Enable Counting
EN
0 Counter disabled
1 Counter enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

218 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.2 Counter Status Register (SYS_CTR_CONTROL_CNTSR)

The system counter status register provides information concerning the clock frequency
and debug state.
Address: 306C_0000h base + 4h offset = 306C_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DBGH
FCA1

FCA0

Reserved Reserved

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTSR field descriptions

Field Description
31–10 This field is reserved.
- Reserved
9 Frequency Change Acknowledge, ID 1
FCA1
0 Base frequency is not selected.
1 Base frequency is selected.
8 Frequency Change Acknowledge, ID 0
FCA0
0 Base frequency is not selected.
1 Base frequency is selected.
7–1 This field is reserved.
- Reserved
0 Debug Halt
DBGH
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 219
Memory Map and Register Description

SYS_CTR_CONTROL_CNTSR field descriptions (continued)

Field Description
0 Counter is not halted by debug.
1 Counter is halted by debug.

4.9.4.3 Counter Count Value Low Register

(SYS_CTR_CONTROL_CNTCV0)

The Counter Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306C_0000h base + 8h offset = 306C_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
CNTCV0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTCV0 field descriptions

Field Description
CNTCV0 Counter Count Value bits [31:0]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

220 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.4 Counter Count Value High Register

(SYS_CTR_CONTROL_CNTCV1)

The Counter Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306C_0000h base + Ch offset = 306C_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved CNTCV1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTCV1 field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CNTCV1 Counter Count Value bits [55:32]

4.9.4.5 Frequency Modes Table 0 Register

(SYS_CTR_CONTROL_CNTFID0)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 221
Memory Map and Register Description

Address: 306C_0000h base + 20h offset = 306C_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID0
W

Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID0 field descriptions

Field Description
CNTFID0 Base Frequency (24 MHz /3 = 8 MHz)

4.9.4.6 Frequency Modes Table 1 Register

(SYS_CTR_CONTROL_CNTFID1)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
Address: 306C_0000h base + 24h offset = 306C_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID1
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID1 field descriptions

Field Description
CNTFID1 Alternate Frequency (32 kHz /64 = 512 Hz)

4.9.4.7 Frequency Modes Table 2 Register

(SYS_CTR_CONTROL_CNTFID2)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

222 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
Address: 306C_0000h base + 28h offset = 306C_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID2
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID2 field descriptions

Field Description
CNTFID2 End Marker

4.9.4.8 Counter ID Register (SYS_CTR_CONTROL_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306C_0000h base + FD0h offset = 306C_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 223
Memory Map and Register Description

4.9.4.1 Counter Count Value Low Register

(SYS_CTR_READ_CNTCV0)

The Counter Count Value Low register indicates the current count value bits 31-0.
Address: 306A_0000h base + 0h offset = 306A_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTCV0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTCV0 field descriptions

Field Description
CNTCV0 Counter Count Value bits [31:0]

4.9.4.2 Counter Count Value High Register

(SYS_CTR_READ_CNTCV1)

The Counter Count Value High register indicates the current count value bits 63-32.
Address: 306A_0000h base + 4h offset = 306A_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTCV1
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTCV1 field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CNTCV1 Counter Count Value bits [55:32]. Bits[63:56] are always zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

224 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.3 Counter ID Register (SYS_CTR_READ_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306A_0000h base + FD0h offset = 306A_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

4.9.4.1 Compare Count Value Low Register

(SYS_CTR_COMPARE_CMPCVLn)

The Compare Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306B_0000h base + 20h offset + (256d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CMPCV0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCVLn field descriptions

Field Description
CMPCV0 Compare Count Value bits [31:0]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 225
Memory Map and Register Description

4.9.4.2 Compare Count Value High Register

(SYS_CTR_COMPARE_CMPCVHn)

The Compare Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306B_0000h base + 24h offset + (256d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CMPCV1
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCVHn field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CMPCV1 Compare Count Value bits [55:32]. Bits[63:56] are always zero.

4.9.4.3 Compare Control Register (SYS_CTR_COMPARE_CMPCRn)

The compare control register provides control and status of the compare function. When
enabled, the ISTAT bit indicates whether the counter value is greater than or equal to the
value in the compare value register (CMPCV). The ISTAT equation is:
ISTAT = (CNTCV >= CMPCV)
ISTAT takes no account of the value of the IMASK bit. If ISTAT is set to 1 and IMASK
is 0, then the interrupt request is asserted. Clearing the enable bit (EN=0) will clear the
status bit (ISTAT=0) and will negate the interrupt output signal.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

226 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Address: 306B_0000h base + 2Ch offset + (256d × i), where i=0d to 1d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ISTAT
R

IMASK
Reserved EN

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCRn field descriptions

Field Description
31–3 This field is reserved.
- Reserved
2 Compare (interrupt) status
ISTAT
0 Counter value is less than the compare value or compare is disabled.
1 Counter value is greater than or equal to the compare value and compare is enabled.
1 Interrupt request mask
IMASK
0 Interrupt output signal is not masked.
1 Interrupt output signal is masked.
0 Enable the compare function
EN
0 Compare disabled
1 Compare enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 227
Memory Map and Register Description

4.9.4.4 Counter ID Register (SYS_CTR_COMPARE_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306B_0000h base + FD0h offset = 306B_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

The read frame registers are all read-only. These registers read the same values as the
control frame registers for the count value and counter ID. They are processed via a
separate mechanism from the control frame to allow nonsecure, user mode access.
SYS_CTR_READ memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
306C_0000 Counter Control Register (SYS_CTR_CONTROL_CNTCR) 32 R/W 0000_0000h 4.9.4.1/217
306C_0004 Counter Status Register (SYS_CTR_CONTROL_CNTSR) 32 R 0000_0100h 4.9.4.2/219
Counter Count Value Low Register
306C_0008 32 R/W 0000_0000h 4.9.4.3/220
(SYS_CTR_CONTROL_CNTCV0)
Counter Count Value High Register
306C_000C 32 R/W 0000_0000h 4.9.4.4/221
(SYS_CTR_CONTROL_CNTCV1)
Frequency Modes Table 0 Register
306C_0020 32 R 007A_1200h 4.9.4.5/221
(SYS_CTR_CONTROL_CNTFID0)
Frequency Modes Table 1 Register
306C_0024 32 R 0000_0200h 4.9.4.6/222
(SYS_CTR_CONTROL_CNTFID1)
Frequency Modes Table 2 Register
306C_0028 32 R 0000_0000h 4.9.4.7/222
(SYS_CTR_CONTROL_CNTFID2)
306C_0FD0 Counter ID Register (SYS_CTR_CONTROL_CNTID0) 32 R 0000_0000h 4.9.4.8/223
Counter Count Value Low Register
306A_0000 32 R 0000_0000h 4.9.4.1/224
(SYS_CTR_READ_CNTCV0)
Counter Count Value High Register
306A_0004 32 R 0000_0000h 4.9.4.2/224
(SYS_CTR_READ_CNTCV1)
306A_0FD0 Counter ID Register (SYS_CTR_READ_CNTID0) 32 R 0000_0000h 4.9.4.3/225

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

228 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SYS_CTR_READ memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Compare Count Value Low Register
306B_0020 32 R 0000_0000h 4.9.4.1/225
(SYS_CTR_COMPARE_CMPCVL0)
Compare Count Value High Register
306B_0024 32 R 0000_0000h 4.9.4.2/226
(SYS_CTR_COMPARE_CMPCVH0)
Compare Control Register
306B_002C 32 R/W 0000_0000h 4.9.4.3/226
(SYS_CTR_COMPARE_CMPCR0)
Compare Count Value Low Register
306B_0120 32 R 0000_0000h 4.9.4.1/225
(SYS_CTR_COMPARE_CMPCVL1)
Compare Count Value High Register
306B_0124 32 R 0000_0000h 4.9.4.2/226
(SYS_CTR_COMPARE_CMPCVH1)
Compare Control Register
306B_012C 32 R/W 0000_0000h 4.9.4.3/226
(SYS_CTR_COMPARE_CMPCR1)
306B_0FD0 Counter ID Register (SYS_CTR_COMPARE_CNTID0) 32 R 0000_0000h 4.9.4.4/228

4.9.4.1 Counter Control Register (SYS_CTR_CONTROL_CNTCR)

The 32-bit Counter Control Register defines the basic operating configuration of the
System Counter.
The System Counter operates using a fixed base frequency. However, the counter can
increment at a lower, alternate frequency than the base frequency, using a
correspondingly larger increment. For example, it can increment by 15625 and run at a
frequency of 1/15625 of the base frequency. The two frequencies available are
indentified in the frequency modes table. These two frequencies are the base frequency
(table entry 0) and the lower, alternate frequency (table entry 1). Setting the FCR1 bit
selects the alternate frequency. Setting the FCR0 bit selects the base frequency. Setting or
clearing both FCR0 and FCR1 will have no effect; the freqeuncy will not change.
Address: 306C_0000h base + 0h offset = 306C_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
HDBG

Reserved FCR1 FCR0 Reserved EN

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 229
Memory Map and Register Description

SYS_CTR_CONTROL_CNTCR field descriptions

Field Description
31–10 This field is reserved.
- Reserved
9 Frequency Change Request, ID 1
FCR1
0 No change.
1 Select frequency modes table entry 1, the base frequency.
8 Frequency Change Request, ID 0
FCR0
0 No change.
1 Select frequency modes table entry 0, the base frequency.
7–2 This field is reserved.
- Reserved
1 Enable Debug
HDBG
0 The assertion of the debug input is ignored.
1 The assertion of the debug input causes the System Counter to halt.
0 Enable Counting
EN
0 Counter disabled
1 Counter enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

230 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.2 Counter Status Register (SYS_CTR_CONTROL_CNTSR)

The system counter status register provides information concerning the clock frequency
and debug state.
Address: 306C_0000h base + 4h offset = 306C_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DBGH
FCA1

FCA0

Reserved Reserved

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTSR field descriptions

Field Description
31–10 This field is reserved.
- Reserved
9 Frequency Change Acknowledge, ID 1
FCA1
0 Base frequency is not selected.
1 Base frequency is selected.
8 Frequency Change Acknowledge, ID 0
FCA0
0 Base frequency is not selected.
1 Base frequency is selected.
7–1 This field is reserved.
- Reserved
0 Debug Halt
DBGH
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 231
Memory Map and Register Description

SYS_CTR_CONTROL_CNTSR field descriptions (continued)

Field Description
0 Counter is not halted by debug.
1 Counter is halted by debug.

4.9.4.3 Counter Count Value Low Register

(SYS_CTR_CONTROL_CNTCV0)

The Counter Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306C_0000h base + 8h offset = 306C_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
CNTCV0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTCV0 field descriptions

Field Description
CNTCV0 Counter Count Value bits [31:0]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

232 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.4 Counter Count Value High Register

(SYS_CTR_CONTROL_CNTCV1)

The Counter Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306C_0000h base + Ch offset = 306C_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved CNTCV1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTCV1 field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CNTCV1 Counter Count Value bits [55:32]

4.9.4.5 Frequency Modes Table 0 Register

(SYS_CTR_CONTROL_CNTFID0)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 233
Memory Map and Register Description

Address: 306C_0000h base + 20h offset = 306C_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID0
W

Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID0 field descriptions

Field Description
CNTFID0 Base Frequency (24 MHz /3 = 8 MHz)

4.9.4.6 Frequency Modes Table 1 Register

(SYS_CTR_CONTROL_CNTFID1)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
Address: 306C_0000h base + 24h offset = 306C_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID1
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID1 field descriptions

Field Description
CNTFID1 Alternate Frequency (32 kHz /64 = 512 Hz)

4.9.4.7 Frequency Modes Table 2 Register

(SYS_CTR_CONTROL_CNTFID2)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

234 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
Address: 306C_0000h base + 28h offset = 306C_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID2
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID2 field descriptions

Field Description
CNTFID2 End Marker

4.9.4.8 Counter ID Register (SYS_CTR_CONTROL_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306C_0000h base + FD0h offset = 306C_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 235
Memory Map and Register Description

4.9.4.1 Counter Count Value Low Register

(SYS_CTR_READ_CNTCV0)

The Counter Count Value Low register indicates the current count value bits 31-0.
Address: 306A_0000h base + 0h offset = 306A_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTCV0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTCV0 field descriptions

Field Description
CNTCV0 Counter Count Value bits [31:0]

4.9.4.2 Counter Count Value High Register

(SYS_CTR_READ_CNTCV1)

The Counter Count Value High register indicates the current count value bits 63-32.
Address: 306A_0000h base + 4h offset = 306A_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTCV1
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTCV1 field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CNTCV1 Counter Count Value bits [55:32]. Bits[63:56] are always zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

236 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.3 Counter ID Register (SYS_CTR_READ_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306A_0000h base + FD0h offset = 306A_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

4.9.4.1 Compare Count Value Low Register

(SYS_CTR_COMPARE_CMPCVLn)

The Compare Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306B_0000h base + 20h offset + (256d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CMPCV0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCVLn field descriptions

Field Description
CMPCV0 Compare Count Value bits [31:0]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 237
Memory Map and Register Description

4.9.4.2 Compare Count Value High Register

(SYS_CTR_COMPARE_CMPCVHn)

The Compare Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306B_0000h base + 24h offset + (256d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CMPCV1
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCVHn field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CMPCV1 Compare Count Value bits [55:32]. Bits[63:56] are always zero.

4.9.4.3 Compare Control Register (SYS_CTR_COMPARE_CMPCRn)

The compare control register provides control and status of the compare function. When
enabled, the ISTAT bit indicates whether the counter value is greater than or equal to the
value in the compare value register (CMPCV). The ISTAT equation is:
ISTAT = (CNTCV >= CMPCV)
ISTAT takes no account of the value of the IMASK bit. If ISTAT is set to 1 and IMASK
is 0, then the interrupt request is asserted. Clearing the enable bit (EN=0) will clear the
status bit (ISTAT=0) and will negate the interrupt output signal.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

238 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Address: 306B_0000h base + 2Ch offset + (256d × i), where i=0d to 1d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ISTAT
R

IMASK
Reserved EN

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCRn field descriptions

Field Description
31–3 This field is reserved.
- Reserved
2 Compare (interrupt) status
ISTAT
0 Counter value is less than the compare value or compare is disabled.
1 Counter value is greater than or equal to the compare value and compare is enabled.
1 Interrupt request mask
IMASK
0 Interrupt output signal is not masked.
1 Interrupt output signal is masked.
0 Enable the compare function
EN
0 Compare disabled
1 Compare enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 239
Memory Map and Register Description

4.9.4.4 Counter ID Register (SYS_CTR_COMPARE_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306B_0000h base + FD0h offset = 306B_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

Each compare frame consists of a 256 byte region. Each compare frame has its own
compare value and control register. Each compare frame is capable of generating one
maskable interrupt.
SYS_CTR_COMPARE memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
306C_0000 Counter Control Register (SYS_CTR_CONTROL_CNTCR) 32 R/W 0000_0000h 4.9.4.1/217
306C_0004 Counter Status Register (SYS_CTR_CONTROL_CNTSR) 32 R 0000_0100h 4.9.4.2/219
Counter Count Value Low Register
306C_0008 32 R/W 0000_0000h 4.9.4.3/220
(SYS_CTR_CONTROL_CNTCV0)
Counter Count Value High Register
306C_000C 32 R/W 0000_0000h 4.9.4.4/221
(SYS_CTR_CONTROL_CNTCV1)
Frequency Modes Table 0 Register
306C_0020 32 R 007A_1200h 4.9.4.5/221
(SYS_CTR_CONTROL_CNTFID0)
Frequency Modes Table 1 Register
306C_0024 32 R 0000_0200h 4.9.4.6/222
(SYS_CTR_CONTROL_CNTFID1)
Frequency Modes Table 2 Register
306C_0028 32 R 0000_0000h 4.9.4.7/222
(SYS_CTR_CONTROL_CNTFID2)
306C_0FD0 Counter ID Register (SYS_CTR_CONTROL_CNTID0) 32 R 0000_0000h 4.9.4.8/223
Counter Count Value Low Register
306A_0000 32 R 0000_0000h 4.9.4.1/224
(SYS_CTR_READ_CNTCV0)
Counter Count Value High Register
306A_0004 32 R 0000_0000h 4.9.4.2/224
(SYS_CTR_READ_CNTCV1)
306A_0FD0 Counter ID Register (SYS_CTR_READ_CNTID0) 32 R 0000_0000h 4.9.4.3/225

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

240 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SYS_CTR_COMPARE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Compare Count Value Low Register
306B_0020 32 R 0000_0000h 4.9.4.1/225
(SYS_CTR_COMPARE_CMPCVL0)
Compare Count Value High Register
306B_0024 32 R 0000_0000h 4.9.4.2/226
(SYS_CTR_COMPARE_CMPCVH0)
Compare Control Register
306B_002C 32 R/W 0000_0000h 4.9.4.3/226
(SYS_CTR_COMPARE_CMPCR0)
Compare Count Value Low Register
306B_0120 32 R 0000_0000h 4.9.4.1/225
(SYS_CTR_COMPARE_CMPCVL1)
Compare Count Value High Register
306B_0124 32 R 0000_0000h 4.9.4.2/226
(SYS_CTR_COMPARE_CMPCVH1)
Compare Control Register
306B_012C 32 R/W 0000_0000h 4.9.4.3/226
(SYS_CTR_COMPARE_CMPCR1)
306B_0FD0 Counter ID Register (SYS_CTR_COMPARE_CNTID0) 32 R 0000_0000h 4.9.4.4/228

4.9.4.1 Counter Control Register (SYS_CTR_CONTROL_CNTCR)

The 32-bit Counter Control Register defines the basic operating configuration of the
System Counter.
The System Counter operates using a fixed base frequency. However, the counter can
increment at a lower, alternate frequency than the base frequency, using a
correspondingly larger increment. For example, it can increment by 15625 and run at a
frequency of 1/15625 of the base frequency. The two frequencies available are
indentified in the frequency modes table. These two frequencies are the base frequency
(table entry 0) and the lower, alternate frequency (table entry 1). Setting the FCR1 bit
selects the alternate frequency. Setting the FCR0 bit selects the base frequency. Setting or
clearing both FCR0 and FCR1 will have no effect; the freqeuncy will not change.
Address: 306C_0000h base + 0h offset = 306C_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
HDBG

Reserved FCR1 FCR0 Reserved EN

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 241
Memory Map and Register Description

SYS_CTR_CONTROL_CNTCR field descriptions

Field Description
31–10 This field is reserved.
- Reserved
9 Frequency Change Request, ID 1
FCR1
0 No change.
1 Select frequency modes table entry 1, the base frequency.
8 Frequency Change Request, ID 0
FCR0
0 No change.
1 Select frequency modes table entry 0, the base frequency.
7–2 This field is reserved.
- Reserved
1 Enable Debug
HDBG
0 The assertion of the debug input is ignored.
1 The assertion of the debug input causes the System Counter to halt.
0 Enable Counting
EN
0 Counter disabled
1 Counter enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

242 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.2 Counter Status Register (SYS_CTR_CONTROL_CNTSR)

The system counter status register provides information concerning the clock frequency
and debug state.
Address: 306C_0000h base + 4h offset = 306C_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DBGH
FCA1

FCA0

Reserved Reserved

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTSR field descriptions

Field Description
31–10 This field is reserved.
- Reserved
9 Frequency Change Acknowledge, ID 1
FCA1
0 Base frequency is not selected.
1 Base frequency is selected.
8 Frequency Change Acknowledge, ID 0
FCA0
0 Base frequency is not selected.
1 Base frequency is selected.
7–1 This field is reserved.
- Reserved
0 Debug Halt
DBGH
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 243
Memory Map and Register Description

SYS_CTR_CONTROL_CNTSR field descriptions (continued)

Field Description
0 Counter is not halted by debug.
1 Counter is halted by debug.

4.9.4.3 Counter Count Value Low Register

(SYS_CTR_CONTROL_CNTCV0)

The Counter Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306C_0000h base + 8h offset = 306C_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
CNTCV0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTCV0 field descriptions

Field Description
CNTCV0 Counter Count Value bits [31:0]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

244 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.4 Counter Count Value High Register

(SYS_CTR_CONTROL_CNTCV1)

The Counter Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306C_0000h base + Ch offset = 306C_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved CNTCV1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTCV1 field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CNTCV1 Counter Count Value bits [55:32]

4.9.4.5 Frequency Modes Table 0 Register

(SYS_CTR_CONTROL_CNTFID0)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 245
Memory Map and Register Description

Address: 306C_0000h base + 20h offset = 306C_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID0
W

Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID0 field descriptions

Field Description
CNTFID0 Base Frequency (24 MHz /3 = 8 MHz)

4.9.4.6 Frequency Modes Table 1 Register

(SYS_CTR_CONTROL_CNTFID1)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
Address: 306C_0000h base + 24h offset = 306C_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID1
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID1 field descriptions

Field Description
CNTFID1 Alternate Frequency (32 kHz /64 = 512 Hz)

4.9.4.7 Frequency Modes Table 2 Register

(SYS_CTR_CONTROL_CNTFID2)
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

246 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
Address: 306C_0000h base + 28h offset = 306C_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTFID2
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTFID2 field descriptions

Field Description
CNTFID2 End Marker

4.9.4.8 Counter ID Register (SYS_CTR_CONTROL_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306C_0000h base + FD0h offset = 306C_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_CONTROL_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 247
Memory Map and Register Description

4.9.4.1 Counter Count Value Low Register

(SYS_CTR_READ_CNTCV0)

The Counter Count Value Low register indicates the current count value bits 31-0.
Address: 306A_0000h base + 0h offset = 306A_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTCV0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTCV0 field descriptions

Field Description
CNTCV0 Counter Count Value bits [31:0]

4.9.4.2 Counter Count Value High Register

(SYS_CTR_READ_CNTCV1)

The Counter Count Value High register indicates the current count value bits 63-32.
Address: 306A_0000h base + 4h offset = 306A_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTCV1
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTCV1 field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CNTCV1 Counter Count Value bits [55:32]. Bits[63:56] are always zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

248 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.9.4.3 Counter ID Register (SYS_CTR_READ_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306A_0000h base + FD0h offset = 306A_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_READ_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

4.9.4.1 Compare Count Value Low Register

(SYS_CTR_COMPARE_CMPCVLn)

The Compare Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306B_0000h base + 20h offset + (256d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CMPCV0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCVLn field descriptions

Field Description
CMPCV0 Compare Count Value bits [31:0]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 249
Memory Map and Register Description

4.9.4.2 Compare Count Value High Register

(SYS_CTR_COMPARE_CMPCVHn)

The Compare Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
Address: 306B_0000h base + 24h offset + (256d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CMPCV1
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCVHn field descriptions

Field Description
31–25 This field is reserved.
- Reserved
CMPCV1 Compare Count Value bits [55:32]. Bits[63:56] are always zero.

4.9.4.3 Compare Control Register (SYS_CTR_COMPARE_CMPCRn)

The compare control register provides control and status of the compare function. When
enabled, the ISTAT bit indicates whether the counter value is greater than or equal to the
value in the compare value register (CMPCV). The ISTAT equation is:
ISTAT = (CNTCV >= CMPCV)
ISTAT takes no account of the value of the IMASK bit. If ISTAT is set to 1 and IMASK
is 0, then the interrupt request is asserted. Clearing the enable bit (EN=0) will clear the
status bit (ISTAT=0) and will negate the interrupt output signal.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

250 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Address: 306B_0000h base + 2Ch offset + (256d × i), where i=0d to 1d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ISTAT
R

IMASK
Reserved EN

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CMPCRn field descriptions

Field Description
31–3 This field is reserved.
- Reserved
2 Compare (interrupt) status
ISTAT
0 Counter value is less than the compare value or compare is disabled.
1 Counter value is greater than or equal to the compare value and compare is enabled.
1 Interrupt request mask
IMASK
0 Interrupt output signal is not masked.
1 Interrupt output signal is masked.
0 Enable the compare function
EN
0 Compare disabled
1 Compare enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 251
TrustZone Address Space Controller (TZASC)

4.9.4.4 Counter ID Register (SYS_CTR_COMPARE_CNTID0)

The Counter ID register indicates the architecture version 0.

Address: 306B_0000h base + FD0h offset = 306B_0FD0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CNTID
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_CTR_COMPARE_CNTID0 field descriptions

Field Description
CNTID Counter Identification. Counter ID 0.

4.10 TrustZone Address Space Controller (TZASC)

4.10.1 Overview
The TrustZone Address Space Controller (TZASC) protects security-sensitive SW and
data in a trusted execution environment against potentially compromised SW running on
the platform.
The TZASC block diagram is shown in figure below.

APB Slave TZASC Interrupt signal

Interface
AXI Bus
AXI bus Slave Address Master (to DDR Controller)
Interface Region Control Interface
Security lock signal

Clock and reset

Figure 4-20. TZASC Block Diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

252 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

The TZASC is an IP by Arm ("CoreLink™ TrustZone Address Space Controller

TZC-380"), designed to provide configurable protection over program (SW) memory
space.
The main features of TZASC are:
• Supports 16 independent address regions
• Access controls are independently programmable for each address region
• Sensitive registers may be locked
• Host interrupt may be programmed to signal attempted access control violations
• AXI master/slave interfaces for transactions
• APB slave interface for configuration and status reporting
NOTE
In this device it is necessary to set
TZASC_ID_SWAP_BYPASS in IOMUXC_GPR10[1] to
avoid an AXI bus error when using GPU.

4.10.2 Clocks
The table found here describes the clock sources for TZASC.
Table 4-28. TZASC Clocks
Clock name Clock Root Description
aclk ccm_clk_root Module clock

4.10.3 Address Mapping in various memory mapping modes

The TZASC region base address starts at the beginning of DDR memory space
(0x40000000) instead of the beginning of memory map (0x00000000). In this case the
addresses configured in TZASC controller will be 1GB (0x40000000) offset and does not
match the local addresses.
For example, setting region_setup_low_x=0xBE000000 maps
DDR_ADDR=0xFE000000, the same behavior is observed with fail_address_x registers.
Memory "aliasing" implications on TZASC settings - in systems which does not utilize
the maximal supported DDR space the controller is designed for, the whole DDR
memory map becomes "aliased" (replicated) by the size of the physical memory used. In

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 253
System Debug

such cases, the TZASC must be configured to protect all aliased regions as well (i.e.
effectively reducing the number of available TZASC regions, since all aliased regions
must be handled, for each "real" space needing protection).
For complete details on TZASC functionality and the programming model, see the Arm
document, “CoreLink™ TrustZone Address Space Controller TZC-380 Technical
Reference Manual, (Rev r0p1 or newer)”, available at http://infocenter.arm.com.

4.11 System Debug

4.11.1 Debug

4.11.1.1 Debug Architecture

The chapter describes the debug architecture of the chip.

4.11.1.2 Debug System Features

The chip debug is based on Arm’s CoreSight platform, with support for Quad-core A53
platform and Cortex-M4 core. The key features of the debug system include:
• Support 5-pins(JTAG) interface.
• Support both non-intrusive and halt-mode trace/debug options.
• MDM-AP registers for debugger to control mutli-core halt/resume cores.
• Trace Memory Controller (TMC) is used to enable capturing trace.
• 4KB in SOC trace block.
• ETR is used to allow routing trace data to system memory.
• Support ARM real time trace interface (TPIU) 16-bit @133MHz.
• Support cross trigger between Quad Cortex-A53 and Cortex-M4.
• 4 JTAG security levels, via SJC security functions together with e-Fuse (challenge
response, field return, intrusive detection)

4.11.1.3 System level debug architecture

The debug architecture is shown in the following figure:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

254 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

AHB Bus
To SOC
M4 Quad A53 Core
DAP Core Sight

MDM
AHB-AP
AP

SWJ
DAP bus
DP

APB bus
APBIC
APB-AP
w/ ROM APB bus

APH Bus
APSEL From SOC
JTAG AP
Decoder

cJTAG

SJC

Main JTAG JTAG _MOD

Port Figure 4-21. Debug Architecture Diagram

4.11.1.4 Functional description

This section gives a brief overview of the modules that are implemented within the
Cortex-M/Cortex-A Core Platform. The debug blocks are part of the overall CoreSight
platform debug system, which include the ETR, CTM, CTI, ATB replicator, APB address
decode, TPIU and DAP. The CoreSight™ compatible Embedded Trace Macrocell (ETM)
enables traces of program flow to be collected, compressed, and fed into the trace
infrastructure. The Cross Trigger Interface (CTI) is included to provide a common
programming model for use by the debug tools, control the trigger sources, and interface
to the Cross Trigger Matrix (CTM). The debug is controlled via an ARM Debug Access
Port (DAP).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 255
Debug

4.11.1.4.1 Embedded Trace Router (ETR)

The Embedded Trace Router (ETR) is a CoreSight trace component which buffers trace
data before dumping that data into DRAM through the AXI bus (via AXI master port).
The output of the funnel is the ETR, and has the ability to buffer a certain amount before
writing the data to DRAM.

4.11.1.4.2 Embedded Trace Macrocell (ETM)

The Embedded Trace Macrocell (ETM) is a CoreSight component. The ETM trace unit is
a module that performs real-time instruction flow tracing based on the Embedded Trace
Macrocell (ETM) architecture ETMv4.

4.11.1.4.3 Cross Trigger Matrix (CTM)

The CoreSight CTI channel signals from all the cores are combined using a Cross Trigger
Matrix (CTM) block so that a single cross trigger channel interface is presented in the
Cortex processor. This module can combine four internal channel interfaces
corresponding to each core along with one external channel interface.
In the Cortex processor CTM, the external channel output is driven by the OR output of
all internal channel outputs. Each internal channel input is driven by the OR output of
internal channel outputs of all other CTIs in addition to the external channel input.

4.11.1.4.4 Cross Trigger Interface (CTI)

The Cortex processor has a single external cross trigger channel interface. This external
interface is connected to the CoreSight Cross Trigger Interface (CTI) interface
corresponding to each core through a Cross Trigger Matrix (CTM). A number of
Embedded Cross Trigger (ECT) trigger inputs and trigger outputs are connected between
debug components in the Cortex-A processor and CoreSight CTI blocks.
The CTI enables the debug logic, ETM trace unit, and performance monitoring, to
interact with each other and with other CoreSight components. This is called cross
triggering. For example, you configure the CTI to generate an interrupt when the ETM
trace unit trigger event occurs.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

256 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.11.1.4.5 AMBA Trace Bus Interface (ATB)

The AMBA Trace Bus (ATB) CoreSight debug components are part of the Trace stream
block. The ATB components consist of the ATB Funnel and ATB Replicator. The ATB
Funnel is used to merge several streams together to produce a single output to the ATB
Replicator. The ATB Replicator enables two trace sinks to be wired together and receive
ATB trace data from the same trace source.

4.11.1.4.6 Advanced Peripheral Bus Interface (APB)

The APB asynchronous interface / bridge connects several debug components. Each
component has a single separate APB interface from the APB-IC (w/ ROM), which
hooks up to a separate APB asynchronous component. The APB interface connects the
core debug functions to the DAP.

4.11.1.4.7 Instrumentation Trace Macrocell (ITM)

The Instrumentation Trace Macrocell (ITM) is a application-driven trace source that
supports printf style debugging to trace operating system and application events. The
ITM generates diagnostic system information as packets. Multiple sources can generate
packets. If multiple sources generate packets at the same time, the ITM arbitrates the
order in which packets are output. These sources in decreasing order of priority are:
• Software trace. Software can write directly to ITM stimulus registers to generate
packets.
• Hardware trace. The DWT generates these packets, and the ITM outputs them.
• Time stamping. Timestamps are generated relative to packets. The ITM contains a
21-bit counter to generate the timestamp. The Cortex-M processor clock or the
bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter.

4.11.1.4.8 Data Watchpoint and Trace (DWT)

The Data Watchpoint and Trace (DWT) debug unit provides watchpoints, data tracing,
and system profiling for the processor.

4.11.1.4.9 Debug Access Port (DAP)

The Debug Access Port (DAP) is a physical port that connects to external debug tools.
The DAP is part of the standardized ARM Debug Interface, and provides a bridge
between a JTAG pin interface and on-chip memory mapped peripherals via the DAP bus.
Transactions generated by the DAP are referred to as External Debugger Accesses.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 257
System JTAG Controller (SJC)

4.11.1.5 JTAG topology

There is only one JTAG on the chip, and two JTAG modes are supported. Select via the
JTAG_MOD pin.
• Debug mode: JTAG_MOD == 0, DAP is the only TAP controller in the daisy chain.
SJC will be attached to JTAG-AP of DAP.
• Test mode: JTAG_MOD == 1, SJC is the only TAP controller in the daisy chain.
1149.1-compliant, and support 1149.6 AC coupled test.
When the JTAG interface is in Debug Mode, it can be operating in standard 5-pin JTAG
interface. cJTAG/SWD interface is not supported by this chip.

4.12 System JTAG Controller (SJC)

4.12.1 Overview
The System JTAG Controller (SJC) provides debug and test control with the maximum
security.
The test access port (TAP) is designed to support features compatible with the IEEE
Standard 1149.1 v2001 (JTAG).
The figure below shows an overview of the JTAG architecture.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

258 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

Cortex
A53

ETM’s, CTI’s

APB
SDMA

JTAG-AP
DA P
OnCE
TDI TDO TDI TDO

TDI
DA P
TDO

DAP
SDMA
SJC Bypass TAP
Bus

Cortex-M4

1 0
SJC TAP Ctlr
ExtraDebug Registers

JTAG_TMS
JTAG_TCK
JTAG_TRSTB JTAG_TDO
I/O PINS JTAG_TDI JTAG_MOD

Figure 4-22. System JTAG Controller (SJC) Block Diagram

4.12.1.1 Features
The JTAG interface of chip, shared by SJC and DFT_TAP (for IEEE1149.1), provides
the following capabilities:
• JTAG IEEE1149.1 mandatory instructions, see EXTEST Instruction, SAMPLE/
PRELOAD Instruction , and BYPASS Instruction .
• JTAG IEEE1149.1 optional instructions, see ID_CODE Instruction (SJC IDCODE /
DFT_TAP IDCODE), HIGHZ Instruction, and CLAMP Instruction.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 259
System JTAG Controller (SJC)

• JTAG IEEE P1149.1 (standard JTAG) interface to off-chip test and development
equipment for true IEEE 1149.1 compliance, used primarily for board-level
implementation of boundary scan.
• Debug-related control and status, such as putting selected cores into reset and/or
debug mode and the ability to monitor individual core status signals via JTAG.
• Provides means for accessing each OnCE/ICE TAP controller independently to
control a target system (see Modes of Operation).
• ExtraDebug logic (see ENABLE_ExtraDebug Instruction ).
• The maximum clock speed of the SJC is one-eight of the lowest frequency of the
accessed OnCE/ICE. For example in normal operation (no core in low-power mode),
this frequency is one-eight of the SDMA frequency if this core is present in the TDI-
TDO chain (serially connected with other cores or standalone). The user must also
consider the 25 MHz frequency limitation on the CE bus.
• Core compliant modes to support standalone core debuggers (see Modes of
Operation).
• Multi-cores daisy chained mode (default one) to support multi-core debuggers (see
Modes of Operation).
Detailed information about the SJC is provided in the Security Reference Manual.
Contact your NXP representative for information about obtaining this document.

4.12.1.2 Modes of Operation

The SJC modes are controlled through both the TAP select register (SJC_TSR) and the
MOD input port.
The MOD port (typically connected to pad of the same name) selects between two
possible topologies of TAP connections while using SJC functions, as seen at SoC level:
• Negating it (this should be the default state) selects all the TAPs ( SJC, SDMA, DAP
and Arm/ETM) to be connected in the TDI-TDO chain, which is referred to as "daisy
chain" mode, throughout this chapter.
• Asserting it only selects the SJC TAP to be connected in the TDI-TDO chain.
SJC features are enabled by configuring the SJC input pin: MOD. Refer to the following
table for MOD settings details:
Table 4-29. SJC Modes
MOD Name Description
0 Daisy chain ALL For common SW debug (High speed and production)
1 SJC only SJC compliant mode

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

260 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

NOTE
IEEE1149.1 standard features are enabled by below IO
configurations: (TEST_MODE, BOOT_MODE1,
BOOT_MODE0, JTAG_MOD) = (1110)
The following figure shows the SJC mode selection flow. The numbers shown in
parenthesis below each block name indicates the TAP's IR length.

M OD = 0

SJC SDMA DAP_A9 DAP_M4

TDI (5) (4) (4) (4) TDO

M OD = 1
SoC JTAG (SJC)
TDI (5)
TDO

(number in brackets lists IR length of given TAP)

Figure 4-23. SJC Mode Selection Using MOD Pin Sampling

The Connect SDMA bit inside TAP select register controls the SDMA TAP bypass.
• When negated (should be the default state), the SDMA TAP is bypassed with a
single D-FF (Flip-flop) during Shift-Dr path
• When asserted SDMA TAP is connected inside the chain
• When taking the SDMA into bypass or out of bypass (by writing to tapsel reg),
additional cycle with TMS '0' should be given
The TAP selection block (TSB) provides a simple method of integrating various pieces of
IP that have embedded TAPs.
• Provides a way to connect up multiple TAPs within a single SoC
• Follow the state of SJC TAP, and when the Test-Logic-Reset (TLR) state is reached,
reset all TAPs
The figure below shows the TAP Selection Block and SOC TAP Chain Scheme.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 261
System JTAG Controller (SJC)

SJC
MOD

TDI sdma_bypass
tdi SJC
TCK tdo
tck TAP

Alter. TAP
tdo
Bypass
tdi SDMA 1
tdo
tck TAP 0

1 SOC TDO
0

DAP
TAP

Note: The default daisy chain connectivity is highlighted in yellow

Figure 4-24. TAP Selection Block and SoC TAP Chain Scheme

NOTE
It is the responsibility of the user to ensure that in any
configuration of the TAP controllers chosen, all of the TAPs in
the chain comply with the demands of TCK clock frequency as
well as the required ratio between TCK clock frequency and
that of the core's to which the TAP refers.

4.12.2 TAP Selection Block (TSB)

As described in Modes of Operation, the SJC can access cores in different modes selected
through a TSB.

4.12.2.1 Select Mode Using Software

Conceptually, the SJC_TSR is a data register which is accessed through Access TSR IR
instruction of SJC TAP.
The following figure shows the process of using reserved IR to access the SJC_TSR.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
262 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SJC JTAG
IR space

Reserved

ACCESS_TSR IR

Shift-DR
TDI TDO
TAP select shift register

TAP select register

Update-DR

Figure 4-25. Using Reserved IR to Access the TAP Select Register (SJC_TSR)

The SJC_TSR can only be changed during the update-DR state of the TSB JTAG state
machine. This is necessary to prevent a TAP that is being selected from losing
synchronization with the TSB state machine when the TSB state machine returns to run-
test-idle. Therefore, an associated shift register for the SJC_TSR is loaded into the
SJC_TSR during the update-DR state (see the figure above). The shift register must also
capture the state of the SJC_TSR when in the Capture-DR state for visibility of the
contents of the SJC_TSR. See TAP Select Instruction , for more information.

4.12.3 Boundary Scan Register (BSR)

The Boundary Scan Register (BSR) in the JTAG implementation contains bits for all
device signal and clock pins and associated control signals.
All SoC bidirectional pins have a single register bit in the boundary scan register for pin
data, and are controlled by an associated control bit in the boundary scan register.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 263
System JTAG Controller (SJC)

4.12.4 SJC Instruction Register (SJIR)

The SJC Instruction register is provided in the following table. The SJC Instruction
register is 5 bits wide.
Table 4-30. SJC Instruction Register
(SJIR)
Code SJC IR
B4 B3 B2 B1 B0
0 0 0 0 0 SJC IDCODE
0 0 0 0 1 Reserved
0 0 0 1 0
0 0 0 1 1 Reserved
0 0 1 0 0 ENABLE_ExtraDebug
0 0 1 0 1 ENTER_DEBUG (secured)
0 0 1 1 0 Reserved
0 0 1 1 1 TAP select
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0 Reserved
0 1 0 1 1 Reserved
0 1 1 0 0 Security Output challenge
0 1 1 0 1 Security Enter response
- Reserved
1 1 1 1 1 Reserved

The instruction register is reset to 0b00000 in the test-logic-reset controller state which is
equivalent to the SJC IDCODE instruction.
During the capture-IR controller state, the parallel inputs to the instruction register are
loaded with the code 01 in the least significant bits as required by the standard; the most
significant bits are loaded with the values 00, leading to a capture value of 0b00001.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

264 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.4.1 DFT_TAP JTAG Instruction Register (DJIR)

The DFT_TAP JTAG Instruction register is provided in the following table. The
DFT_TAP JTAG Instruction register is 5 bits wide.
Table 4-31. DFT_TAP JTAG Instruction Register (DJIR)
Code DFT_TAP IR
B4 B3 B2 B1 B0
0/1 1 1 1 1 BYPASS
0 0 0 1 0 EXTEST
0 0 0 1 1 SAMPLE/PRELOAD
0 0 1 1 0 CLAMP
0 0 1 0 0 DFT_TAP IDCODE

The DFT_TAP JTAG instruction register is reset to 0b00000, which is reserved.

4.12.4.2 ID_CODE Instruction (SJC IDCODE / DFT_TAP IDCODE)

Selects the ID register, and the system logic controls the I/O pins. This instruction is
provided as a public instruction to allow the manufacturer, part number and version of a
component to be determined through the TAP.
The table below shows the ID register configuration.
Table 4-32. ID Configuration Register (SJC IDCODE / DFT_TAP IDCODE)
IDCODE ID Configuration Register
BIT 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT
31 16
Version Information[3:0] Part Number (Bits 27-16)
TYPE r r r r r r r r r r r r r r r r
RESET 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0
Note:
BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0
15
Part Number (Bits 15-12) Manufacturer Identity 1
TYPE r r r r r r r r r r r r r r r r
RESET 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1
Note:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 265
System JTAG Controller (SJC)

Table 4-33. SJC ID Configuration Register Description (SJC

IDCODE)
Field Description
31-28 IC/SoC Version information number.
Version Information Initial value: '0000'
This number is subject to changes, for new IC/SoC (System On A Chip) revision releases.
27-12 Customer Part Number
Part Number The 16-bit Part Number value is unique for every NXP SoC / IC.
See System Debug chapter for exact register value for a specific SoC.
11-1 Manufacturer Identity
Manufacturer Identity NXP Manufacturer Identity code.
Bits [11:1] - 00000001110
0 Tied to logic 1.

Table 4-34. DFT_TAP ID Configuration Register Description (DFT_TAP IDCODE)

Field Description
31-28 IC/SoC Version information number.
Version Information Initial value: '0001'
This number is subject to changes, for new IC/SoC (System On A Chip) revision releases.
27-12 Customer Part Number
Part Number The 16-bit Part Number value is unique for every NXP SoC / IC.
Value: 1100111110000000
See System Debug chapter for exact register value for a specific SoC.
11-1 Manufacturer Identity
Manufacturer Identity NXP Manufacturer Identity code.
Value: 01010101001
0 Tied to logic 1.

One application of the ID register is to distinguish the manufacturer(s) of components on

a board when multiple sourcing is used. As more components emerge which conform to
the IEEE 1149.1 standard, it is desirable to allow for a system diagnostic controller unit
to blindly interrogate a board design to determine the type of each component in each
location. This information is also available for factory process monitoring and for failure
mode analysis of assembled boards.
Once the IDCODE instruction is decoded, it selects the ID register which is a 32 Bit data
register. Because the bypass register loads a logic 0 at the start of a scan cycle, whereas
the ID register loads a logic 1 into its least significant bit, examination of the first bit of
data shifted out of a component during a test data scan sequence immediate following
exit from Test-Logic-Reset controller state shows whether such a register is included in

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

266 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

the design. When the IDCODE instruction is selected, the operation of the test logic has
no effect on the operation of the on-chip system logic as required by the IEEE 1149.1
standard.

4.12.4.3 SAMPLE/PRELOAD Instruction

Selects the boundary scan register and the system logic controls the I/O pins.
The SAMPLE/PRELOAD instruction provides two separate functions:
• First, it provides a means to obtain a snapshot of system data and control signals. The
snapshot occurs on the rising edge of TCK in the capture-DR controller state. The
data can be observed by shifting it transparently through the boundary scan register.
• The second function of SAMPLE/PRELOAD is to initialize the boundary scan
register output cells prior to selection of EXTEST. This initialization ensures that
known data appears on the outputs when entering the EXTEST instruction.
NOTE
Because there is no internal synchronization between the JTAG
clock (TCK) and the system clock (CLK), the user must
provide some form of external synchronization to achieve
meaningful results.
For more details on the function and use of SAMPLE/PRELOAD, refer to the appropriate
IEEE 1149.1 document.

4.12.4.4 EXTEST Instruction

Selects the boundary scan register, and the 1149.1 test logic has control of the I/O pins.
By using the TAP controller, the register is capable of:
• Scanning user-defined values into the output buffers,
• Capturing values presented to input pins
• Controlling the direction of bidirectional pins,
• Controlling the output drive of tri-statable output pins.
For more details on the function and use of EXTEST, refer to the appropriate IEEE
1149.1 document.
The EXTEST instruction also asserts internal reset for the cores (through CCM, refer to
Figure 4-28) to force a predictable internal state while performing external boundary scan
operations.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 267
System JTAG Controller (SJC)

4.12.4.5 HIGHZ Instruction

All output drivers, including the two-state drivers, are turned off (that is, high
impedance). The instruction selects the bypass register.
In this mode, all internal pullup resistors on all the pins (except for the TMS, TDI, TCK,
TRSTB pins) are disabled. This disabling functionality is not built into SJC, but should
be implemented by some logic in the SOC/IO Pads.
For more details on the function and use of HIGHZ, refer to the IEEE 1149.1 document.
The HIGHZ instruction also asserts internal reset for the cores (through CCM, refer to
Figure 4-28) to force a predictable internal state while performing external boundary scan
operations.

4.12.4.6 BYPASS Instruction

Selects the single Bit bypass register and the system logic controls the I/O pins.
This creates a shift-register path from TDI to the bypass register and, finally, to TDO,
circumventing the boundary scan register. This instruction is used to enhance test
efficiency when a component other than the SoC Core based device becomes the device
under test.
When the bypass register is selected by the current instruction, the shift-register stage is
set to a logic zero on the rising edge of TCK in the capture-DR controller state.
Therefore, the first bit to be shifted out after selecting the bypass register is always a
logic zero.
For more details on the function and use of BYPASS, refer to the appropriate IEEE
1149.1 document.

4.12.4.7 CLAMP Instruction

The CLAMP instruction is established initially with the SAMPLE and PRELOAD
instructions.
It drives preset values onto the outputs of devices and then, unlike the SAMPLE and
PRELOAD instructions, it selects the bypass register between TDI and TDO. CLAMP
can be used to set values on the outputs of certain devices to avoid bus contention
problems.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

268 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.4.8 ENABLE_ExtraDebug Instruction

The TDI and TDO pins are connected directly to the ExtraDebug registers, the SJC TAP
controller remaining connected to TDI and TMS.
The ExtraDebug shift register consists of 38 bits (maximum) comprising a 32-bits data
field (maximum length, see Accessing ExtraDebug Registers,), a 5 bits address field and
read/write bit. On a register read, the data field does not need to be filled in. The
particular ExtraDebug register connected between TDI and TDO at a given time is
selected by the ExtraDebug controller depending on the ExtraDebug Address being
currently decoded. All communication with the ExtraDebug controller is done through
the Select-DR-Scan path of the JTAG TAP Controller.

4.12.4.9 ENTER_DEBUG instruction

The ENTER_DEBUG instruction is used to generate a debug request event to SDMA and
the Arm Core Platform simultaneously (practically, inherited minimal skew is expected,
due to difference in event signal propagation in the different modules).
The TDI and TDO are connected to the Instruction Register (IR). After the
acknowledgment of the Debug Mode is received (can be checked by reading the Core
Status Register part of the ExtraDebug logic), the user can perform system debug
functions on the cores.
NOTE
The ENTER_DEBUG event issue to the cores, can be masked,
by bits in DCR register.
NOTE
It is user's responsibility to shift-in another IR value (like
IDCODE) before trying to bring the cores out of debug mode,
as the debug request signals to the cores remains asserted as
long as ENTER_DEBUG IR is in place.
NOTE
The user need to check that cores are in debug mode (watching
debug acknowledge signal) before leaving ENTER_DEBUG
instruction, otherwise debug request might not take affect.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 269
System JTAG Controller (SJC)

4.12.4.10 TAP Select Instruction

By means of TAP select instruction a user can access TAP select register and by
controlling its only bit SDMA Bypass, control whether SDMA TAP is bypassed or not.
Table 4-35. TAP Select Register (TSR)
TAP Select Register
BIT 0
Connect SDMA
TYPE rw
RESET 0
Note:

Table 4-36. TAP Select Register Description

Field Description
0 Connect SDMA
SDMA Bypass Control whether SDMA TAP is bypassed or not:
• 0 - SDMA TAP is bypassed by the alternate TAP inside SJC (emulating 4-bit IR
and 1-bit bypass path).
• 1 - SDMA TAP is connected to the TDI-TDO chain.

NOTE: Additional cycle with TMS '0' should be inserted, after writing to this register, to
allow the SDMA tap be sync before SDMA get into / out of bypass.

4.12.5 Security
JTAG manipulation is one of the known hackers' ways of executing unauthorized
program code, getting control over the OS and run code in privileged modes.
The SJC provides a debug access to several H/W blocks including the Arm processor and
the system bus. This allows for program control and manipulation as well as visibility
into system peripherals and memory. The ETM and NEXUS interfaces allow bus
transactions to be traced. Together these tools provide the hacker all the access needed to
completely comprise the system. Means must be provided to block any malicious JTAG
access.
The SJC provides a way of regulating the JTAG access.
The following are the different JTAG security modes:
• Mode #1: No Debug-Maximum Security. All security sensitive JTAG features are
permanently blocked.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

270 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• Mode #2: Secure JTAG-High security. JTAG use is regulated by secret key based
authentication mechanism.
• Mode #3: JTAG Enabled-Low security. JTAG always enabled.
The JTAG security modes are configured using eFUSEs which can burned after
packaging by applying electrical signals. The fuse burning is irreversible process, once a
fuse is burned (e-fuse or laser fuse) it is impossible to change the fuse back to the un-
burned state.

4.12.5.1 JTAG Security Modes

JTAG can be in one of JTAG security modes which is selected by setting the SJC eFuse
configuration. The physical location of the fuses is not in the SJC.

4.12.5.1.1 Mode 1: No Debug - Maximum Security

No Debug JTAG security mode provides the highest security level.
In this mode, all JTAG features are disabled except for:
• ScanBoundary Scan
• PLL bypass- Bypass Arm or/and USB PLL.
• Visibility of the following status bits: power mode - normal, standby, stop, shutdown,
and so on
These features do not reduce the security level of the product, and they allows to perform
important tests and board connectivity checks.

4.12.5.1.2 Mode 2: Secure JTAG - High Security

The Secure JTAG mode limits the JTAG access by using challenge/response based
authentication mechanism. Any access to JTAG port is being checked. Only authorized
debug devices (that is, devices having the right response) can access the JTAG,
unauthorized JTAG access attempts are denied.
The intent of this mode is to allow return field testing. When a secured JTAG device is
being returned for debugging, this mode allows authorized re-activation of the JTAG.

4.12.5.1.2.1 Challenge/Response Mechanism in System JTAG Mode

When SJC is in Sysytem JTAG mode the authentication process is as follows:
1. Shift Output Challenge instruction to IR.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 271
System JTAG Controller (SJC)

2. Passing through Capture-DR state of the SJC and by performing Shift-DR operations
Challenge code can be accessed from TDO.
3. Shift Enter Response instruction to IR. By performing Shift-DR, operations enter
Response code value through TDI. As Update-DR state is entered, Response code is
compared with the correct one.
In Fixed challenge-response pair mode, each part has its individual challenge - response
pair which is determined at manufacturing time, and does not change later on. The SJC
compares the user's response to the expected response.

SJC

Access Policy

External
System JTAG User Debug
Response JTAG Port Machine
compare
Challenge
Response
Expected

Fixed Challenge-Response

Figure 4-26. Mode #2 - Secure JTAG with Fixed Challenge-response Pair

4.12.5.1.3 Mode 3: JTAG Enabled - Low Security

In the JTAG Enabled JTAG security mode, all JTAG features are enabled.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

272 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.5.2 Software Enabled JTAG

To increase the flexibility of the SJC, an option to enable the JTAG via software is added
and is available only in Secure JTAG mode. By writing '1' to HAB_JDE (HAB JTAG
DEBUG ENABLE) bit in the eFuse controller module, the JTAG is opened, regardless of
its security mode. It is the responsibility of software to assert or negate this bit.
Additionally, a corresponding lock bit is available (in the eFuse control module) to ensure
that only trusted software is able to set the JDE bit. When the LOCK bit is set, no future
change of JDE is possible, until the next POR (power-on-reset) cycle.
The platform initialization software should set the LOCK bit for JDE bit before
transferring control to the application code.
The S/W JTAG enable allows JTAG enabling without activating the challenge-Response
mechanism (which requires JTAG access tool enhancement or special H/W). The JTAG
S/W enable does not allow debug in case of boot or memory fault as it requires reset
before entering debug.
This feature can be permanently blocked by burning the dedicated eFuse.
NOTE
The S/W enabled JTAG feature reduces the overall security
level of the system as it relies on S/W protections. If this feature
is not required, it is strongly recommended to burn the
JTAG_HEO eFuse which disables this feature.

4.12.5.3 Kill Trace

The kill trace signal disables any output of the ETM block. The ETM can be accessed
either via JTAG port and/or by direct software code. Blocking the JTAG port also yields
assertion of the kill trace signal. This resulted in blocking of trace port. The intention of
this action is to block any attempt to break into the system via software manipulation of
the debug modules. The kill trace, when active, prevents trace output even in case where
it can be activated via chip pin.
The kill trace feature needs to be activated by burning a dedicated eFuse. If the fuse is left
intact, kill trace is never activated as seen in Figure 4-27.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 273
System JTAG Controller (SJC)

JTAG access policy (JTAG Block)

Kill Trace SJC
ETM

Kill Trace Enable

(KTE) fuse

Figure 4-27. Kill Trace eFuse

The kill trace is asserted when "kill trace enable" fuse is burned and "ipt_secur_block"
signal in SJC is asserted, which happens when at least one of the following is true:
• Mode #2 (Secure JTAG) and no code has been entered
• Mode #2 (Secure JTAG) with burned Bypass and Re-enable fuses
• Mode #2 (Secure JTAG) with incorrect response entered
• Mode #1 (No debug)
• TRST_B signal is active
• POR has not ever been asserted

4.12.5.4 SJC Disable Fuse

In addition to the different JTAG security modes that are implemented internally in the
System JTAG Controller (SJC), there is an option to disable the SJC functionality by
eFuse configuration. This creates additional JTAG mode that is, JTAG Disabled with
highest level of JTAG protection. In this mode all JTAG features are disabled.
Specifically, the following debug features are disabled in addition to the features that
were already disabled in No Debug JTAG mode:
• Boundary scan register (SJC_BSR)
• Non-Secure JTAG control registers (PLL configuration, Deterministic Reset, PLL
bypass)
• Non-Secure JTAG status registers (Core status)
• Chip Identification Code (IDCODE)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

274 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.6 Functional Description

This section provides a complete functional description of the block.

4.12.6.1 Static Core Debug

The SJC JTAG TAP controller is fully compatible with the IEEE 1149.1a-2001 Standard
Test Access Port and Boundary Scan Architecture specifications.
The Arm platform has an integrated JTAG interface and a TAP controller to manage its
own ICE. Also it can access an embedded trace ETM interface, see Arm core and ETM
Technical reference guide for more information.
The SDMA has a TAP controller to manage its own OnCE, see SDMA OnCE
specifications for more details.
The OnCE and ICE provide a mean of interacting with the cores and their peripherals
non-intrusively so that a user may examine registers, memories to facilitate hardware and
software development. Refer to TAP Selection Block (TSB), for more information.

4.12.6.2 Reset Mechanism

The following figure shows the SJC reset logic

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 275
System JTAG Controller (SJC)

RESET_IN reset
Reset control
POR
CCM

IR!= sjc_ieee_reset_b

EXTEST or HighZ

TRST
AND SDMA CORE
POR AND OnCE TAP Controller
OnCE reset
TSB TAP state!= TestLogicReset

sjc_trst_b
SJC DAP

Figure 4-28. SJC Reset Logic

NOTE
• Asserting TRSTB in any scan mode resets the TCR loosing
the testmode configuration and selects default TAP.
• SJC generates an IEEE reset signal to the CCM when in
one of the IEEE modes HIGHZ or EXTEST. This signal
generates a system reset to the cores until exit from one of
these modes.
• The TSB generates Once/ICE reset (either TRSTB if
implemented or other) when its TAP state reaches Test-
Logic-Reset (meaning that TAP accessed is also reaching
Test-Logic-Reset).

4.12.7 Initialization/Application Information

The control afforded by the output enable signals using the boundary scan register and
the EXTEST instruction requires a compatible circuit-board test environment to avoid
device-destructive configurations. The user must avoid situations in which the SJC output
drivers are enabled into actively driven networks.
There are two constraints related to the JTAG interface:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

276 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

• Ensure that the JTAG test logic is kept transparent to the system logic by forcing
TAP into the Test-Logic-Reset controller state. During power-up, SJC's internal
TRSTB is asserted as IC's POR_B is asserted which forces the TAP controller into
this state. After that, if TMS either remains unconnected or is connected to VCC,
then the TAP controller cannot leave the Test-Logic-Reset state, regardless of the
state of TCK.
• DE_B is an IO pin with pullup and care must be taken of the direction when driving
this signal.

4.12.8 SJC Memory Map/Register Definition

In addition to the standard accessible JTAG registers (per IEEE1149.1 standard) listed in
SJC Instruction Register (SJIR) , the chip contains the following registers accessed using
the ExtraDebug mechanism, controlled via "ENABLE_ExtraDebug" IR instruction.
NOTE
SJC registers are only accessible by JTAG interface. They are
not memory mapped to processor address space, so the absolute
addresses provided by default in the SJC memory map are not
valid.
This section assumes the JTAG controller is accessed in standalone mode or daisy
chained (defined by TAP Selection Block) using the appropriate TSB configuration.
See "System Debug" chapter for more details about the general purpose register
descriptions that are unique to this chip.
SJC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
General Purpose Unsecured Status Register 1 4.12.8.1/
0 32 R 0000_0000h
(SJC_GPUSR1) 279
General Purpose Unsecured Status Register 2 4.12.8.2/
1 32 R 0000_0000h
(SJC_GPUSR2) 281
General Purpose Unsecured Status Register 3 4.12.8.3/
2 32 R 0000_0000h
(SJC_GPUSR3) 281
4.12.8.4/
3 General Purpose Secured Status Register (SJC_GPSSR) 32 R 0000_0000h
282
4.12.8.5/
4 Debug Control Register (SJC_DCR) 32 R/W 0000_0000h
283
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 277
System JTAG Controller (SJC)

SJC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
4.12.8.6/
5 Security Status Register (SJC_SSR) 32 R See section
285
4.12.8.7/
7 General Purpose Clocks Control Register (SJC_GPCCR) 32 R/W 0000_0000h
288

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

278 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.8.1 General Purpose Unsecured Status Register 1

(SJC_GPUSR1)

The General Purpose Unsecured Status Register 1 is a read only register used to check
the status of the different Cores and of the PLL. The rest of its bits are for general
purpose use.
Address: 0h base + 0h offset = 0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 279
System JTAG Controller (SJC)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_LOCK

A_DBG
A_WFI
R S_STAT

Reserved
Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SJC_GPUSR1 field descriptions

Field Description
31–9 This field is reserved.
- Reserved.
8 PLL_LOCK
PLL_LOCK
A Combined PLL-Lock flag indicator, for all the PLL's.
7 This field is reserved.
- Reserved
6–5 This field is reserved.
- Reserved.
4–2 3 LSBits of SDMA core statusH.
S_STAT
1 Arm core wait-for interrupt bit
A_WFI
Bit 1 is the Arm core standbywfi (stand by wait-for interrupt). When this bit is HIGH, Arm core is in wait for
interrupt mode.
0 Arm core debug status bit
A_DBG
Bit 0 is the Arm core DBGACK (debug acknowledge)
DBGACK can be overwritten in the Arm core DCR to force a particular DBGACK value. Consequently
interpretation of the DBGACK value is highly dependent on the debug sequence. When this bit is HIGH,
Arm core is in debug.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

280 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.8.2 General Purpose Unsecured Status Register 2

(SJC_GPUSR2)
Address: 0h base + 1h offset = 1h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R STBYWFE S_STAT STBYWFI

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SJC_GPUSR2 field descriptions

Field Description
31–12 This field is reserved.
- Reserved
11–8 STBYWFE[3:0]
STBYWFE
Reflecting the "Standby Wait For Event" signals of all cores.
7–4 S_STAT[3:0]
S_STAT
SDMA debug status bits: debug_core_state[3:0]
STBYWFI STBYWFI[3:0]
These bits provide status of "Standby Wait-For-Interrupt" state of all Arm cores.

4.12.8.3 General Purpose Unsecured Status Register 3

(SJC_GPUSR3)
Address: 0h base + 2h offset = 2h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SYS_ IPG_ IPG_

R
Reserved WAIT STOP WAIT
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SJC_GPUSR3 field descriptions

Field Description
31–3 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 281
System JTAG Controller (SJC)

SJC_GPUSR3 field descriptions (continued)

Field Description
2 System In wait
SYS_WAIT
Indication on System in wait mode (from CCM).
1 IPG_STOP
IPG_STOP
CCM's "ipg_stop" signal indication
0 IPG_WAIT
IPG_WAIT
CCM's "ipg_wait" signal indication

4.12.8.4 General Purpose Secured Status Register (SJC_GPSSR)

The General Purpose Secured Status Register is a read-only register used to check the
status of the different critical information in the SoC. This register cannot be accessed in
secure modes.
Address: 0h base + 3h offset = 3h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R GPSSR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SJC_GPSSR field descriptions

Field Description
GPSSR General Purpose Secured Status Register
Register is used for testing and debug.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

282 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.8.5 Debug Control Register (SJC_DCR)

This register is used to control propagation of debug request from DE_B pad to the cores
and debug signals from internal logic to the DE_B pad.
Address: 0h base + 4h offset = 4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIRECT_SDMA_REQ_EN
DIRECT_ARM_REQ_EN
R

DE_TO_SDMA
DEBUG_OBS

DE_TO_ARM
Reserved

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SJC_DCR field descriptions

Field Description
31–7 This field is reserved.
- Reserved
6 Pass Debug Enable event from DE_B pin to Arm platform debug request signal(s).
DIRECT_ARM_
This bit controls the propagation of debug request DE_B to the Arm platform.
REQ_EN
0 Disable propagation of system debug to (DE_B pin) to Arm platform.
1 Enable propagation of system debug to (DE_B pin) to Arm platform.
5 Debug enable of the sdma debug request
DIRECT_SDMA_
This bit controls the propagation of debug request DE_B to the sdma.
REQ_EN
0 Disable propagation of system debug to (DE_B pin) to sdma.
1 Enable propagation of system debug to (DE_B pin) to sdma.
4 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 283
System JTAG Controller (SJC)

SJC_DCR field descriptions (continued)

Field Description
3 Debug observability
DEBUG_OBS
This bit controls the propagation of the "system debug" input to SJC (driven by the ECT logic), to the
DE_B pad.
(This logic can be used to pass debug acknowledge event from ECT out to the PAD, for example).
The SJC's "system_debug" input is tied to logic HIGH value, therefore, set of "debug_obs" bit, will result in
unconditional assertion of DE_B pad.

0 Disable propagation of system debug to DE_B pin

1 Unconditional assertion of pad DE_B
2 This field is reserved.
- Reserved
1 SDMA debug request input propagation
DE_TO_SDMA
This bit controls the propagation of debug request to SDMA, when the JTAG state machine is put in
"ENTER_DEBUG" IR instruction..

0 Disable propagation of debug request to SDMA

1 Enable propagation of debug request to SDMA
0 Arm platform debug request input propagation
DE_TO_ARM
This bit controls the propagation of debug request to Arm platform ("dbgreq"), when the JTAG state
machine is put in "ENTER_DEBUG" IR instruction.

0 Disable propagation of debug request to Arm platform

1 Enable propagation of debug request to Arm platform

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

284 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

4.12.8.6 Security Status Register (SJC_SSR)

Address: 0h base + 5h offset = 5h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R -

Reserv
ed

Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 285
System JTAG Controller (SJC)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BOOTIND

SWE

SWF

KTA
R RSSTAT SJM FT EBG EBF KTF
Reserved

Reserved

Reserved
Reserv
ed

Reset 0* 0* 0* 0* 0* 0* 0* 1* 0* 0* 0* 0* 0* 0* 0* 0*

* Notes:
• The SJM reset value, reflects the JTAG security state, as defined by status of JTAG_SMODE[1:0] fuses. See the SJM
bitfield description for details on valid values.

SJC_SSR field descriptions

Field Description
31–17 Reserved.
-
16–15 This field is reserved.
- Reserved
14 Boot Indication
BOOTIND
Inverted Internal Boot indication, i.e inverse of SRC: "src_int_boot" signal
13 This field is reserved.
- Reserved
12–11 Response status
RSSTAT
Response status bits

00 Response wasn't entered

01 Response was entered but not verified
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

286 NXP Semiconductors
 Chapter 4 ARM Platform and Debug

SJC_SSR field descriptions (continued)

Field Description
10 Response was entered and is incorrect
11 Response is correct
10–9 SJC Secure mode
SJM
Secure JTAG mode, as set by external fuses.

00 No debug (#1)
01 Secure JTAG (#2)
10 Reserved
11 JTAG enabled (#3)
8 Fuse type
FT
Fuse type bit - e-fuse or laser fuse

0 E-fuse technology
1 Laser fuse technology
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5 External boot granted
EBG
External boot enabled, requested and granted

1 granted
0 not granted
4 External Boot fuse
EBF
Status of the external boot disable fuse

0 (intact) - external boot is allowed

1 (burned) - external boot is disabled
3 SW enable
SWE
SW JTAG enable status

1 enabled
0 disabled
2 Software JTAG enable fuse
SWF
Status of the no SW disable JTAG fuse

0 (intact) - SW enable possible

1 (intact) - no SW enable possible
1 Kill Trace is active
KTA
1 active
0 not active
0 Kill Trace Enable fuse value
KTF
0 (intact) - kill trace is never active
1 (burned) - kill trace functionality enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 287
System JTAG Controller (SJC)

4.12.8.7 General Purpose Clocks Control Register (SJC_GPCCR)

This register is used to configure clock related modes in SOC, see System Configuration
chapter for more information. Those bits are directly connected to JTAG outputs. Bit 0 of
GPCCR controls SDMA clocks invocation. When out of reset, the SDMA is in sleep
mode with no SDMA clock running. Unlike events, debug requests does not wake
SDMA if it is in sleep mode. The debug request is recognized by the SDMA only when it
exits sleep mode upon reception of an event. To be able to enter debug mode even if no
event is triggered, the SDMA clock on bit needs to be set prior to sending the debug
request (clear at reset).
Address: 0h base + 7h offset = 7h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

-
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACLKOFFDIS
R

SCLKR
-
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SJC_GPCCR field descriptions

Field Description
31–2 Reserved
-
1 Disable/prevent Arm platform clock/power shutdown
ACLKOFFDIS
0 SDMA Clock ON Register - This bit forces the clock on of the SDMA
SCLKR

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

288 NXP Semiconductors
Chapter 5
Clocks and Power Management

5.1 Clock Control Module (CCM)

5.1.1 Overview
Clock Control Module (CCM) manages the on-chip module clocks. CCM receives clocks
from PLLs and oscillators and creates clocks for on-chip peripherals through a set of
multiplexers, dividers and gates. When entering or exiting a low power mode, CCM
automatically turns on and off PLLs and peripheral clocks.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 289
Clock Control Module (CCM)

CCM Low Power Clock Gating

(LPCG)

Clock Root Generation

CCM_EXT_CLK[4:1] LPCG
Blocks

clock slices Module Clocks

Clock Roots
cg

mux
: cg div
cg
PLL cg
Clock Source from cg

PLL/Divider cg
24 MHz PLLs cg
cg

mux
: cg div
cg
32 kHz
to on-chip
peripherals
Pre-Dividers PLL Enable
PLL
Control
PLL Lock

Clock Gating Control

DSM WAIT / STOP Clock Enable
(CCGR)

Clock Gate

GPC SRC

CCM_CLKO[2:1]

Figure 5-1. CCM Block Diagram

5.1.2 Clock Root Selects

The table below details the clock root slices and clock source selection inputs for each
clock slice.
NOTE
The value of all clock root slice registers
(CCM_TARGET_ROOTn) are zero after Power On Reset
(POR) with the exception of DRAM clock. Please see the
System Boot chapter for ROM reset values and default
frequency settings for the clock root slices.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

290 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
0 ARM_A53_CLK_ROOT 0x8000 1000 000 - 24M_REF_CLK
001 - ARM_PLL_CLK
100 - SYSTEM_PLL1_CLK
101 - SYSTEM_PLL1_DIV2
011 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV2
111 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
1 ARM_M4_CLK_ROOT 0x8080 400 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV3
010 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
111 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
2 VPU_A53_CLK_ROOT 0x8100 800 000 - 24M_REF_CLK
001 - ARM_PLL_CLK
111 - VPU_PLL_CLK
100 - SYSTEM_PLL1_CLK
101 - SYSTEM_PLL1_DIV2
011 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV2
110 - AUDIO_PLL1_CLK
3 GPU3D_CLK_ROOT 0x8180 1000 000 - 24M_REF_CLK
001 - GPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
4 GPU2D_CLK_ROOT 0x8200 1000 000 - 24M_REF_CLK
001 - GPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 291
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
16 MAIN_AXI_CLK_ROOT 0x8800 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
111 -
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV3
011 - SYSTEM_PLL2_DIV4
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
17 ENET_AXI_CLK_ROOT 0x8880 266 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
011 - SYSTEM_PLL2_DIV4
100 - SYSTEM_PLL2_DIV5
111 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
18 NAND_USDHC_BUS_CLK_R 0x8900 266 000 - 24M_REF_CLK
OOT
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL1_DIV6
110 - SYSTEM_PLL2_DIV4
011 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
19 VPU_BUS_CLK_ROOT 0x8980 800 000 - 24M_REF_CLK
010 - VPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
111 -
101 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL3_CLK
011 - AUDIO_PLL2_CLK
20 DISPLAY_AXI_CLK_ROOT 0x8A00 500 000 - 24M_REF_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

292 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL2_CLK
110 - EXT_CLK_1
111 - EXT_CLK_4
21 DISPLAY_APB_CLK_ROOT 0x8A80 200 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL2_CLK
110 - EXT_CLK_1
111 - EXT_CLK_3
22 DISPLAY_RTRM_CLK_ROO 0x8B00 500 000 - 24M_REF_CLK
T
001 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV5
100 - AUDIO_PLL1_CLK
101 - VIDEO_PLL_CLK
110 - EXT_CLK_2
111 - EXT_CLK_3
23 USB_BUS_CLK_ROOT 0x8B80 500 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_4
24 GPU_AXI_CLK_ROOT 0x8C00 800 000 - 24M_REF_CLK
010 - GPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 293
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
25 GPU_AHB_CLK_ROOT 0x8C80 400 000 - 24M_REF_CLK
010 - GPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
26 NOC_CLK_ROOT 0x8D00 800 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK
100 - SYSTEM_PLL2_DIV2
010 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
27 NOC_APB_CLK_ROOT 0x8D80 800 000 - 24M_REF_CLK
101 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV2
011 - SYSTEM_PLL2_DIV3
100 - SYSTEM_PLL2_DIV5
010 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
32 AHB_CLK_ROOT 0x9000 133 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV2
001 - SYSTEM_PLL1_DIV6
100 - SYSTEM_PLL2_DIV8
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
34 AUDIO_AHB_CLK_ROOT 0x9100 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

294 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
001 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL2_DIV6
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
36 MIPI_DSI_ESC_RX_CLK_RO 0x9200 133 000 - 24M_REF_CLK
OT
011 - SYSTEM_PLL1_CLK
010 - SYSTEM_PLL1_DIV10
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV10
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
110 - EXT_CLK_3
48 DRAM_SEL_CFG 0x9800 800 000 - DRAM_PLL1_CLK
49 CORE_SEL_CFG 0x9880 800 000 - DRAM_PLL1_CLK
64 DRAM_ALT_CLK_ROOT 0xA000 800 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_CLK
111 - SYSTEM_PLL1_DIV3
010 - SYSTEM_PLL1_DIV8
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL2_DIV2
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
65 DRAM_APB_CLK_ROOT 0xA080 200 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
66 VPU_G1_CLK_ROOT 0xA100 800 000 - 24M_REF_CLK
001 - VPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_CLK
101 - SYSTEM_PLL2_DIV8
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 295
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
67 VPU_G2_CLK_ROOT 0xA180 800 000 - 24M_REF_CLK
001 - VPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_CLK
101 - SYSTEM_PLL2_DIV8
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
68 DISPLAY_DTRC_CLK_ROO 0xA200 600 000 - 24M_REF_CLK
T
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV5
011 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
69 DISPLAY_DC8000_CLK_RO 0xA280 600 000 - 24M_REF_CLK
OT
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV5
011 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
70 PCIE_CTRL_CLK_ROOT 0xA300 333 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV3
101 - SYSTEM_PLL2_DIV2
110 - SYSTEM_PLL2_DIV3
001 - SYSTEM_PLL2_DIV4
010 - SYSTEM_PLL2_DIV5
111 - SYSTEM_PLL3_CLK
71 PCIE_PHY_CLK_ROOT 0xA380 100 000 - 24M_REF_CLK
111 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL2_DIV2
001 - SYSTEM_PLL2_DIV10
011 - EXT_CLK_1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

296 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
100 - EXT_CLK_2
101 - EXT_CLK_3
110 - EXT_CLK_4
72 PCIE_AUX_CLK_ROOT 0xA400 10 000 - 24M_REF_CLK
111 - SYSTEM_PLL1_DIV4
110 - SYSTEM_PLL1_DIV5
101 - SYSTEM_PLL1_DIV10
001 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL2_DIV10
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
73 DC_PIXEL_CLK_ROOT 0xA480 594 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
101 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL3_CLK
011 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
001 - VIDEO_PLL_CLK
111 - EXT_CLK_4
74 LCDIF_PIXEL_CLK_ROOT 0xA500 250 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
101 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL3_CLK
011 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
001 - VIDEO_PLL_CLK
111 - EXT_CLK_4
75 SAI1_CLK_ROOT 0xA580 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_1
111 - EXT_CLK_2
76 SAI2_CLK_ROOT 0xA600 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 297
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_2
111 - EXT_CLK_3
77 SAI3_CLK_ROOT 0xA680 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_3
111 - EXT_CLK_4
79 SAI5_CLK_ROOT 0xA780 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_2
111 - EXT_CLK_3
80 SAI6_CLK_ROOT 0xA800 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_3
111 - EXT_CLK_4
81 SPDIF1_CLK_ROOT 0xA880 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_2
111 - EXT_CLK_3
82 SPDIF2_CLK_ROOT 0xA900 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

298 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
110 - EXT_CLK_3
111 - EXT_CLK_4
83 ENET_REF_CLK_ROOT 0xA980 125 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV5
001 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL2_DIV10
010 - SYSTEM_PLL2_DIV20
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - EXT_CLK_4
84 ENET_TIMER_CLK_ROOT 0xAA00 125 000 - 24M_REF_CLK
001 - SYSTEM_PLL2_DIV10
010 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
011 - EXT_CLK_1
100 - EXT_CLK_2
101 - EXT_CLK_3
110 - EXT_CLK_4
85 ENET_PHY_REF_CLK_ROO 0xAA80 125 000 - 24M_REF_CLK
T
100 - SYSTEM_PLL2_DIV2
011 - SYSTEM_PLL2_DIV5
010 - SYSTEM_PLL2_DIV8
001 - SYSTEM_PLL2_DIV20
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
86 NAND_CLK_ROOT 0xAB00 500 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_DIV2
001 - SYSTEM_PLL2_DIV2
110 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
010 - AUDIO_PLL1_CLK
100 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
87 QSPI_CLK_ROOT 0xAB80 400 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 299
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
010 - SYSTEM_PLL2_DIV3
110 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL2_CLK
88 USDHC1_CLK_ROOT 0xAC00 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
89 USDHC2_CLK_ROOT 0xAC80 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
90 I2C1_CLK_ROOT 0xAD00 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
91 I2C2_CLK_ROOT 0xAD80 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

300 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
92 I2C3_CLK_ROOT 0xAE00 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
93 I2C4_CLK_ROOT 0xAE80 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
94 UART1_CLK_ROOT 0xAF00 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_4
95 UART2_CLK_ROOT 0xAF80 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_3
96 UART3_CLK_ROOT 0xB000 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 301
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_4
97 UART4_CLK_ROOT 0xB080 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_3
98 USB_CORE_REF_CLK_ROO 0xB100 125 000 - 24M_REF_CLK
T
001 - SYSTEM_PLL1_DIV8
010 - SYSTEM_PLL1_DIV20
100 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_3
99 USB_PHY_REF_CLK_ROOT 0xB180 100 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV8
010 - SYSTEM_PLL1_DIV20
100 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_3
100 GIC_CLK_ROOT 0xB200 400 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
010 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_4
101 ECSPI1_CLK_ROOT 0xB280 80 000 - 24M_REF_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

302 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
102 ECSPI2_CLK_ROOT 0xB300 80 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
103 PWM1_CLK_ROOT 0xB380 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_1
104 PWM2_CLK_ROOT 0xB400 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_1
105 PWM3_CLK_ROOT 0xB480 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 303
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
106 PWM4_CLK_ROOT 0xB500 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
107 GPT1_CLK_ROOT 0xB580 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_1
108 GPT2_CLK_ROOT 0xB600 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_2
109 GPT3_CLK_ROOT 0xB680 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_3
110 GPT4_CLK_ROOT 0xB700 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

304 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_1
111 GPT5_CLK_ROOT 0xB780 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_2
112 GPT6_CLK_ROOT 0xB800 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_3
113 TRACE_CLK_ROOT 0xB880 133 000 - 24M_REF_CLK
011 - VPU_PLL_CLK
010 - SYSTEM_PLL1_DIV5
001 - SYSTEM_PLL1_DIV6
100 - SYSTEM_PLL2_DIV8
101 - SYSTEM_PLL3_CLK
110 - EXT_CLK_1
111 - EXT_CLK_3
114 WDOG_CLK_ROOT 0xB900 66 000 - 24M_REF_CLK
011 - VPU_PLL_CLK
010 - SYSTEM_PLL1_DIV5
001 - SYSTEM_PLL1_DIV6
110 - SYSTEM_PLL1_DIV10
111 - SYSTEM_PLL2_DIV6
100 - SYSTEM_PLL2_DIV8
101 - SYSTEM_PLL3_CLK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 305
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
115 WRCLK_CLK_ROOT 0xB980 40 000 - 24M_REF_CLK
010 - VPU_PLL_CLK
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
001 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL3_CLK
116 IPP_DO_CLKO1 0xBA00 266 000 - 24M_REF_CLK
110 - VPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV4
111 - SYSTEM_PLL1_DIV10
101 - SYSTEM_PLL2_DIV2
100 - AUDIO_PLL2_CLK
117 IPP_DO_CLKO2 0xBA80 266 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
001 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV6
100 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - 32K_REF_CLK
118 MIPI_DSI_CORE_CLK_ROO 0xBB00 266 000 - 24M_REF_CLK
T
011 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
119 MIPI_DSI_PHY_REF_CLK_R 0xBB80 125 000 - 24M_REF_CLK
OOT
011 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV8
010 - SYSTEM_PLL2_DIV10
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

306 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
120 MIPI_DSI_DBI_CLK_ROOT 0xBC00 266 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV10
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
121 USDHC3_CLK_ROOT 0xBC80 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
122 MIPI_CSI1_CORE_CLK_RO 0xBD00 333 000 - 24M_REF_CLK
OT
011 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
123 MIPI_CSI1_PHY_REF_CLK_ 0xBD80 125 000 - 24M_REF_CLK
ROOT
011 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV3
010 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
124 MIPI_CSI1_ESC_CLK_ROOT 0xBE00 133 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_CLK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 307
Clock Control Module (CCM)

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
010 - SYSTEM_PLL1_DIV10
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV10
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
110 - EXT_CLK_3
125 MIPI_CSI2_CORE_CLK_RO 0xBE80 266 000 - 24M_REF_CLK
OT
011 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
126 MIPI_CSI2_PHY_REF_CLK_ 0xBF00 125 000 - 24M_REF_CLK
ROOT
011 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV3
010 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
127 MIPI_CSI2_ESC_CLK_ROOT 0xBF80 133 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_CLK
010 - SYSTEM_PLL1_DIV10
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV10
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
110 - EXT_CLK_3
128 PCIE2_CTRL_CLK_ROOT 0xC000 500 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV3
101 - SYSTEM_PLL2_DIV2
110 - SYSTEM_PLL2_DIV3
001 - SYSTEM_PLL2_DIV4
010 - SYSTEM_PLL2_DIV5
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

308 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-1. Clock Root Table (continued)

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
111 - SYSTEM_PLL3_CLK
129 PCIE2_PHY_CLK_ROOT 0xC080 100 000 - 24M_REF_CLK
111 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL2_DIV2
001 - SYSTEM_PLL2_DIV10
011 - EXT_CLK_1
100 - EXT_CLK_2
101 - EXT_CLK_3
110 - EXT_CLK_4
130 PCIE2_AUX_CLK_ROOT 0xC100 10 000 - 24M_REF_CLK
111 - SYSTEM_PLL1_DIV4
110 - SYSTEM_PLL1_DIV5
101 - SYSTEM_PLL1_DIV10
001 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL2_DIV10
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
131 ECSPI3_CLK_ROOT 0xC180 80 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
132 PDM_CLK_ROOT 0xC200 200 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV10
101 - SYSTEM_PLL3_CLK
010 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - EXT_CLK_3
133 VPU_H1_CLK_ROOT 0xC280 800 000 - 24M_REF_CLK
001 - VPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 309
Clock Control Module (CCM)

Table 5-1. Clock Root Table

Slice Clock Root Offset Max Freq Source Select
Index n (MHz)
(CCM_TARGET_ROOTn[MUX])
101 - SYSTEM_PLL2_DIV8
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
100 - AUDIO_PLL2_CLK

5.1.3 Clock Tree

The figure below illustrates the clock sources from the PLLs.
NOTE
Some clock gates illustrated below are symbolic of distributed
clock gates (multiple) and not a sole clock gate. These clock
slices typically source multiple IP (e.g. bus clocks).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

310 NXP Semiconductors
 PLL
PLL3

PLL2
PLL1
PLL2
Audio
PLL1

Audio

PLL1

DRAM

OSC_24M
OSC_32K

System

System
VIDEO

System

VPU PLL
EXT_CLK_1
EXT_CLK_2
EXT_CLK_3
EXT_CLK_4

ARM PLL
GPU PLL

NXP Semiconductors
/3
/4
/5
/6
/8

/2

/8

/2
/3
/4
/5
/6
/10
/20

/10
DIV
DIV
DIV

/20

DIV
DIV
DIV
DIV
24M_REF_CLK
ARM_PLL_CLK
DRAM_PLL_CLK
VPU_PLL_CLK
GPU_PLL_CLK
SYSTEM_PLL1_CLK
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8
SYSTEM_PLL1_DIV10
SYSTEM_PLL1_DIV20
SYSTEM_PLL2_CLK
SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5

Figure 5-2. CCM input clock sources

SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8
SYSTEM_PLL2_DIV10
SYSTEM_PLL2_DIV20
SYSTEM_PLL3_CLK
AUDIO_PLL1_CLK
AUDIO_PLL2_CLK
VIDEO_PLL1_CLK

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

32K_REF_CLK
EXT_CLK_1
EXT_CLK_2

The figure below illustrates the clock slices of CCM and clock root generation.
EXT_CLK_3
EXT_CLK_4

311
Chapter 5 Clocks and Power Management
Clock Control Module (CCM)

LPCG
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg
ARM_A53_CLK_ROOT
POST[MUX_B]
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg
ARM_M4_CLK_ROOT
POST[MUX_B]
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg CCGR79
GPU3D_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg CCGR102
GPU2D_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg
MAIN_AXI_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
PRE[PRE_PODF_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg
ENET_AXI_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
PRE[PRE_PODF_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg NAND_USDHC_BUS_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B] PRE[PRE_PODF_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR99
VPU_BUS_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
PRE[PRE_PODF_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR93
DISPLAY_AXI_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
PRE[PRE_PODF_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR93
DISPLAY_APB_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR93
DISPLAY_RTRM_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg
USB_BUS_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_B]
SYSTEM_PLL1_DIV20

SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10

SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8

SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8

EXT_CLK_2
GPU_PLL_CLK

EXT_CLK_1

EXT_CLK_4
EXT_CLK_3
VPU_PLL_CLK
ARM_PLL_CLK
DRAM_PLL_CLK

SYSTEM_PLL1_CLK

SYSTEM_PLL2_CLK

SYSTEM_PLL3_CLK

32K_REF_CLK
VIDEO_PLL1_CLK
24M_REF_CLK

AUDIO_PLL1_CLK
AUDIO_PLL2_CLK

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

312 NXP Semiconductors
 Chapter 5 Clocks and Power Management

LPCG
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg CCGR87
GPU_AXI_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg CCGR87
GPU_AHB_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg
NOC_CLK_ROOT
POST[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
POST[MUX_A]
POST[SELECT]
cg
NOC_APB_CLK_ROOT
POST[MUX_B]
cg POST[POST_PODF]
POST[MUX_B] AHB_CLK_ROOT
POST[MUX_A]
POST[MUX_A] cg
POST[SELECT]
cg IPG[POST_PODF]
IPG_CLK_ROOT
POST[MUX_B] cg
cg AHB[POST_PODF]
POST[MUX_B] AUDIO_AHB_CLK_ROOT
POST[MUX_A]
POST[MUX_A]
cg
POST[SELECT]
cg IPG[POST_PODF]
AUDIO_IPG_CLK_ROOT
POST[MUX_B] cg
cg AHB[POST_PODF]

POST[MUX_B]
POST[MUX_A]
POST[MUX_A] CCGR5
PRE[PRE_PODF_A] POST[POST_PODF]
DRAM_ALT_CLK_ROOT
cg cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR5
DRAM_APB_CLK_ROOT
cg cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR86
VPU_G1_CLK_ROOT
cg cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR90
VPU_G2_CLK_ROOT
cg cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR93
DISPLAY_DC8000_CLK_ROOT
cg cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
PCIE_PHY_CLK_ROOT
cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR37
PCIE_AUX_CLK_ROOT
cg cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
DC_PIXEL_CLK_ROOT
cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
LCDIF_PIXEL_CLK_ROOT
cg
POST[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR51
SAI1_CLK_ROOT
cg cg
SYSTEM_PLL1_DIV20

SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10

SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8

SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8

EXT_CLK_2
GPU_PLL_CLK

EXT_CLK_1

EXT_CLK_4
EXT_CLK_3
VPU_PLL_CLK
ARM_PLL_CLK
DRAM_PLL_CLK

SYSTEM_PLL1_CLK

SYSTEM_PLL2_CLK

SYSTEM_PLL3_CLK

32K_REF_CLK
VIDEO_PLL1_CLK
24M_REF_CLK

AUDIO_PLL1_CLK
AUDIO_PLL2_CLK

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 313
Clock Control Module (CCM)
LPCG
POST[MUX_A] CCGR52
PRE[PRE_PODF_A] POST[POST_PODF]
SAI2_CLK_ROOT
cg cg
POST[MUX_A] CCGR53
PRE[PRE_PODF_A] POST[POST_PODF]
SAI3_CLK_ROOT
cg cg
POST[MUX_A] CCGR55
PRE[PRE_PODF_A] POST[POST_PODF]
SAI5_CLK_ROOT
cg cg
POST[MUX_A] CCGR56
PRE[PRE_PODF_A] POST[POST_PODF]
SAI6_CLK_ROOT
cg cg
POST[MUX_A]
PRE[PRE_PODF_A] POST[POST_PODF]
SPDIF1_CLK_ROOT
cg
POST[MUX_A]
PRE[PRE_PODF_A] POST[POST_PODF]
SPDIF2_CLK_ROOT
cg
POST[MUX_A] CCGR10
PRE[PRE_PODF_A] POST[POST_PODF]
ENET_REF_CLK_ROOT
cg cg
POST[MUX_A] CCGR10
PRE[PRE_PODF_A] POST[POST_PODF]
ENET_TIMER_CLK_ROOT
cg cg
POST[MUX_A]
PRE[PRE_PODF_A] POST[POST_PODF]
ENET_PHY_REF_CLK_ROOT
cg
POST[MUX_A] CCGR48
PRE[PRE_PODF_A] POST[POST_PODF]
NAND_CLK_ROOT
cg cg
POST[MUX_A] CCGR47
PRE[PRE_PODF_A] POST[POST_PODF]
QSPI_CLK_ROOT
cg cg
POST[MUX_A] CCGR81
PRE[PRE_PODF_A] POST[POST_PODF]
USDHC1_CLK_ROOT
cg cg
POST[MUX_A] CCGR82
PRE[PRE_PODF_A] POST[POST_PODF] USDHC2_CLK_ROOT
cg cg
POST[MUX_A] CCGR23
PRE[PRE_PODF_A] POST[POST_PODF] I2C1_CLK_ROOT
cg cg
POST[MUX_A] CCGR24
PRE[PRE_PODF_A] POST[POST_PODF] I2C2_CLK_ROOT
cg cg
POST[MUX_A] CCGR25
PRE[PRE_PODF_A] POST[POST_PODF] I2C3_CLK_ROOT
cg cg
POST[MUX_A] CCGR26
PRE[PRE_PODF_A] POST[POST_PODF] I2C4_CLK_ROOT
cg cg
POST[MUX_A] CCGR73
PRE[PRE_PODF_A] POST[POST_PODF] UART1_CLK_ROOT
cg cg
POST[MUX_A] CCGR74
PRE[PRE_PODF_A] POST[POST_PODF] UART2_CLK_ROOT
cg cg
POST[MUX_A] CCGR75
PRE[PRE_PODF_A] POST[POST_PODF] UART3_CLK_ROOT
cg cg
POST[MUX_A] CCGR76
PRE[PRE_PODF_A] POST[POST_PODF] UART4_CLK_ROOT
cg cg
POST[MUX_A]
PRE[PRE_PODF_A] POST[POST_PODF] USB_PHY_REF_CLK_ROOT
cg cg
POST[MUX_A] CCGR92
PRE[PRE_PODF_A] POST[POST_PODF] GIC_CLK_ROOT
cg cg
POST[MUX_A] CCGR7
PRE[PRE_PODF_A] POST[POST_PODF] ECSPI1_CLK_ROOT
cg cg
POST[MUX_A] CCGR8
PRE[PRE_PODF_A] POST[POST_PODF] ECSPI2_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR8
ECSPI3_CLK_ROOT
cg cg
SYSTEM_PLL1_DIV20

SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10

SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8

SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8

EXT_CLK_2
GPU_PLL_CLK

EXT_CLK_1

EXT_CLK_4
EXT_CLK_3
VPU_PLL_CLK
ARM_PLL_CLK
DRAM_PLL_CLK

SYSTEM_PLL1_CLK

SYSTEM_PLL2_CLK

SYSTEM_PLL3_CLK

32K_REF_CLK
VIDEO_PLL1_CLK
24M_REF_CLK

AUDIO_PLL1_CLK
AUDIO_PLL2_CLK

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

314 NXP Semiconductors
 Chapter 5 Clocks and Power Management
LPCG
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR40
PWM1_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR41
PWM2_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR42
PWM3_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR43
PWM4_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR16
GPT1_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR17
GPT2_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR18
GPT3_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR19
GPT4_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR20
GPT5_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR21
GPT6_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR72
TRACE_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
WDOG_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
WRCLK_CLK_ROOT
cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
MIPI_DSI_CORE_CLK_ROOT
cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
MIPI_DSI_PHY_REF_CLK_ROOT
cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
MIPI_DSI_DBI_CLK_ROOT
cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
MIPI_CSI1_CORE_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
MIPI_CSI1_PHY_REF_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
MIPI_CSI1_ESC_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR102
MIPI_CSI2_CORE_CLK_ROOT
cg cg

POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR102

MIPI_CSI2_PHY_REF_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR102
MIPI_CSI2_ESC_CLK_ROOT
cg cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
PCIE2_PHY_CLK_ROOT
cg
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR100
PCIE2_AUX_CLK_ROOT
cg cg

POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR91

PDM_CLK_ROOT
cg cg
SYSTEM_PLL1_DIV20

SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10

SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8

SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8

EXT_CLK_2
GPU_PLL_CLK

EXT_CLK_1

EXT_CLK_4
EXT_CLK_3
VPU_PLL_CLK
ARM_PLL_CLK
DRAM_PLL_CLK

SYSTEM_PLL1_CLK

SYSTEM_PLL2_CLK

SYSTEM_PLL3_CLK

32K_REF_CLK
VIDEO_PLL1_CLK
25M_REF_CLK

AUDIO_PLL1_CLK
AUDIO_PLL2_CLK

Figure 5-3. CCM Clock Tree Root Slices

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 315
Clock Control Module (CCM)

5.1.4 System Clocks

The table below shows the CCM output module clock connectivity and gating.

Table 5-2. System Clocks and Gating

Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable (CCGR)
AIPS_TZ_V2 aips_tz1.hclk AHB_CLK_ROOT clk_enable_ipmux1
(CCGR28)
ipmux1. master_clk AHB_CLK_ROOT clk_enable_ipmux1
(CCGR28)
ipmux1. slave_clk IPG_CLK_ROOT clk_enable_ipmux1
(CCGR28)
aips_tz2.hclk AHB_CLK_ROOT clk_enable_ipmux2
(CCGR29)
Ipmux2. master_clk AHB_CLK_ROOT clk_enable_ipmux2
(CCGR29)
Ipmux2. slave_clk IPG_CLK_ROOT clk_enable_ipmux2
(CCGR29)
aips_tz3.hclk AHB_CLK_ROOT clk_enable_ipmux3
(CCGR30)
Ipmux3. master_clk AHB_CLK_ROOT clk_enable_ipmux3
(CCGR30)
Ipmux3. slave_clk IPG_CLK_ROOT clk_enable_ipmux3
(CCGR30)
APBHDMA apbhdma.hclk NAND_USDHC_BUS_CLK_R clk_enable_rawnand
OOT (CCGR48)
apbhdma_sec.mst_hclk NAND_USDHC_BUS_CLK_R clk_enable_rawnand
OOT (CCGR48)
CAAM caam.aclk AHB_CLK_ROOT -
caam.ckil CKIL_SYNC_CLK_ROOT -
caam.ipg_clk IPG_CLK_ROOT -
caam.ipg_clk_s IPG_CLK_ROOT -
BCH rawnand.u_bch_input_apb_clk NAND_USDHC_BUS_CLK_R clk_enable_rawnand
OOT (CCGR48)
rawnand.u_gpmi_bch_input_bch_clk NAND_USDHC_BUS_CLK_R clk_enable_rawnand
OOT (CCGR48)
DAP dap.dapclk_2_2 AHB_CLK_ROOT clk_enable_debug (CCGR4)
CORESIGHT coresight.DBGCLK MAIN_AXI_CLK_ROOT clk_enable_trace (CCGR72)
coresight.traceclkin TRACE_CLK_ROOT clk_enable_trace (CCGR72)
coresight_mem.cs_etf_clk MAIN_AXI_CLK_ROOT clk_enable_trace (CCGR72)
eCSPI ecspi1. ipg_clk IPG_CLK_ROOT clk_enable_ecspi1 (CCGR7)
ecspi1. ipg_clk_per ECSPI1_CLK_ROOT clk_enable_ecspi1 (CCGR7)
ecspi1. ipg_clk_s IPG_CLK_ROOT clk_enable_ecspi1 (CCGR7)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

316 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-2. System Clocks and Gating (continued)

Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable (CCGR)
ecspi2. ipg_clk IPG_CLK_ROOT clk_enable_ecspi2 (CCGR8)
ecspi2. ipg_clk_per ECSPI2_CLK_ROOT clk_enable_ecspi2 (CCGR8)
ecspi2. ipg_clk_s IPG_CLK_ROOT clk_enable_ecspi2 (CCGR8)
ecspi3. ipg_clk IPG_CLK_ROOT clk_enable_ecspi3 (CCGR9)
ecspi3. ipg_clk_per ECSPI3_CLK_ROOT clk_enable_ecspi3 (CCGR9)
ecspi3. ipg_clk_s IPG_CLK_ROOT clk_enable_ecspi3 (CCGR9)
ENET enet1. ipp_ind_mac0_txclk ENET_REF_CLK_ROOT clk_enable_enet1 (CCGR10)
enet1. ipg_clk ENET_AXI_CLK_ROOT clk_enable_enet1 (CCGR10)
enet1. ipg_clk_mac0 ENET_AXI_CLK_ROOT clk_enable_enet1 (CCGR10)
enet1. ipg_clk_mac0_s ENET_AXI_CLK_ROOT clk_enable_enet1 (CCGR10)
enet1. ipg_clk_s ENET_AXI_CLK_ROOT clk_enable_enet1 (CCGR10)
enet1. ipg_clk_time ENET_TIMER_CLK_ROOT clk_enable_enet1 (CCGR10)
enet1_mem. mac0_rxmem_clk ENET_AXI_CLK_ROOT clk_enable_enet1 (CCGR10)
enet1_mem. mac0_txmem_clk ENET_AXI_CLK_ROOT clk_enable_enet1 (CCGR10)
GPIO gpio1.ipg_clk_s IPG_CLK_ROOT clk_enable_gpio1 (CCGR11)
gpio2.ipg_clk_s IPG_CLK_ROOT clk_enable_gpio2 (CCGR12)
gpio3.ipg_clk_s IPG_CLK_ROOT clk_enable_gpio3 (CCGR13)
gpio4.ipg_clk_s IPG_CLK_ROOT clk_enable_gpio4 (CCGR14)
gpio5.ipg_clk_s IPG_CLK_ROOT clk_enable_gpio5 (CCGR15)
GPMI rawnand.u_gpmi_bch_input_gpmi_io_clk NAND_CLK_ROOT clk_enable_rawnand
(CCGR48)
rawnand.u_gpmi_input_apb_clk NAND_USDHC_BUS_CLK_R clk_enable_rawnand
OOT (CCGR48)
GPT gpt1.ipg_clk GPT1_CLK_ROOT clk_enable_gpt1 (CCGR16)
gpt1.ipg_clk_24m ANAMIX_OSC_24M_CLK clk_enable_gpt1 (CCGR16)
gpt1.ipg_clk_highfreq GPT1_CLK_ROOT clk_enable_gpt1 (CCGR16)
gpt1.ipg_clk_s GPT1_CLK_ROOT clk_enable_gpt1 (CCGR16)
gpt2.ipg_clk GPT2_CLK_ROOT clk_enable_gpt2 (CCGR17)
gpt2.ipg_clk_24m ANAMIX_OSC_24M_CLK clk_enable_gpt2 (CCGR17)
gpt2.ipg_clk_highfreq GPT2_CLK_ROOT clk_enable_gpt2 (CCGR17)
gpt2.ipg_clk_s GPT2_CLK_ROOT clk_enable_gpt2 (CCGR17)
gpt3.ipg_clk GPT3_CLK_ROOT clk_enable_gpt3 (CCGR18)
gpt3.ipg_clk_24m ANAMIX_OSC_24M_CLK clk_enable_gpt3 (CCGR18)
gpt3.ipg_clk_highfreq GPT3_CLK_ROOT clk_enable_gpt3 (CCGR18)
gpt3.ipg_clk_s GPT3_CLK_ROOT clk_enable_gpt3 (CCGR18)
gpt4.ipg_clk GPT4_CLK_ROOT clk_enable_gpt4 (CCGR19)
gpt4.ipg_clk_24m ANAMIX_OSC_24M_CLK clk_enable_gpt4 (CCGR19)
gpt4.ipg_clk_highfreq GPT4_CLK_ROOT clk_enable_gpt4 (CCGR19)
gpt4.ipg_clk_s GPT4_CLK_ROOT clk_enable_gpt4 (CCGR19)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 317
Clock Control Module (CCM)

Table 5-2. System Clocks and Gating (continued)

Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable (CCGR)
gpt5.ipg_clk GPT5_CLK_ROOT clk_enable_gpt5 (CCGR20)
gpt5.ipg_clk_24m ANAMIX_OSC_24M_CLK clk_enable_gpt5 (CCGR20)
gpt5.ipg_clk_highfreq GPT5_CLK_ROOT clk_enable_gpt5 (CCGR20)
gpt5.ipg_clk_s GPT5_CLK_ROOT clk_enable_gpt5 (CCGR20)
gpt6.ipg_clk GPT6_CLK_ROOT clk_enable_gpt6 (CCGR21)
gpt6.ipg_clk_24m ANAMIX_OSC_24M_CLK clk_enable_gpt6 (CCGR21)
gpt6.ipg_clk_highfreq GPT6_CLK_ROOT clk_enable_gpt6 (CCGR21)
gpt6.ipg_clk_s GPT6_CLK_ROOT clk_enable_gpt6 (CCGR21)
I2C i2c1. ipg_clk_patref I2C1_CLK_ROOT clk_enable_i2c1 (CCGR23)
i2c1. ipg_clk_s I2C1_CLK_ROOT clk_enable_i2c1 (CCGR23)
i2c2. ipg_clk_patref I2C2_CLK_ROOT clk_enable_i2c2 (CCGR24)
i2c2. ipg_clk_s I2C2_CLK_ROOT clk_enable_i2c2 (CCGR24)
i2c3. ipg_clk_patref I2C3_CLK_ROOT clk_enable_i2c3 (CCGR25)
i2c3. ipg_clk_s I2C3_CLK_ROOT clk_enable_i2c3 (CCGR25)
i2c4. ipg_clk_patref I2C4_CLK_ROOT clk_enable_i2c4 (CCGR26)
i2c4. ipg_clk_s I2C4_CLK_ROOT clk_enable_i2c4 (CCGR26)
IOMUXC iomuxc.ipg_clk_s IPG_CLK_ROOT clk_enable_iomux (CCGR27)
iomuxc_gpr.ipg_clk_s IPG_CLK_ROOT clk_enable_iomux (CCGR27)
MU mu.ipg_clk_dsp IPG_CLK_ROOT clk_enable_mu (CCGR33)
mu.ipg_clk_mcu IPG_CLK_ROOT clk_enable_mu (CCGR33)
mu.ipg_clk_s_dsp IPG_CLK_ROOT clk_enable_mu (CCGR33)
mu.ipg_clk_s_mcu IPG_CLK_ROOT clk_enable_mu (CCGR33)
OCOTP ocotp.ipg_clk IPG_CLK_ROOT clk_enable_ocotp (CCGR34)
ocotp.ipg_clk_s IPG_CLK_ROOT clk_enable_ocotp (CCGR34)
OCRAM ocram_ctrl.clk MAIN_AXI_CLK_ROOT clk_enable_ocram (CCGR35)
ocram_ctrl_s.clk AHB_CLK_ROOT clk_enable_ocram_s
(CCGR36)
ocram_exsc.aclk_exsc MAIN_AXI_CLK_ROOT clk_enable_ocram (CCGR35)
ocram_exsc.ipg_clk IPG_CLK_ROOT clk_enable_ocram (CCGR35)
ocram_mem.clk MAIN_AXI_CLK_ROOT clk_enable_ocram (CCGR35)
ocram_s_exsc.aclk_exsc AHB_CLK_ROOT clk_enable_ocram_s
(CCGR36)
ocram_s_exsc.ipg_clk IPG_CLK_ROOT clk_enable_ocram_s
(CCGR36)
ocram_s_mem.clk AHB_CLK_ROOT clk_enable_ocram_s
(CCGR36)
PCIe pcie_ctrl.auxclk PCIE_AUX_CLK_ROOT clk_enable_pcie (CCGR37)
pcie_ctrl.mstr_aclk PCIE_CTRL_CLK_ROOT clk_enable_pcie (CCGR37)
pcie_ctrl.slv_aclk PCIE_CTRL_CLK_ROOT clk_enable_pcie (CCGR37)
pcie_exsc.aclk_exsc PCIE_CTRL_CLK_ROOT clk_enable_pcie (CCGR37)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

318 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-2. System Clocks and Gating (continued)

Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable (CCGR)
pcie_exsc.ipg_clk IPG_CLK_ROOT clk_enable_pcie (CCGR37)
pcie_mem.mstr_axi_clk PCIE_CTRL_CLK_ROOT clk_enable_pcie (CCGR37)
pcie_mem.slv_axi_clk PCIE_CTRL_CLK_ROOT clk_enable_pcie (CCGR37)
PWM pwm1.ipg_clk PWM1_CLK_ROOT clk_enable_pwm1 (CCGR40)
pwm1.ipg_clk_highfreq PWM1_CLK_ROOT clk_enable_pwm1 (CCGR40)
pwm1.ipg_clk_s PWM1_CLK_ROOT clk_enable_pwm1 (CCGR40)
pwm2.ipg_clk PWM2_CLK_ROOT clk_enable_pwm2 (CCGR41)
pwm2.ipg_clk_highfreq PWM2_CLK_ROOT clk_enable_pwm2 (CCGR41)
pwm2.ipg_clk_s PWM2_CLK_ROOT clk_enable_pwm2 (CCGR41)
pwm3.ipg_clk PWM3_CLK_ROOT clk_enable_pwm3 (CCGR42)
pwm3.ipg_clk_highfreq PWM3_CLK_ROOT clk_enable_pwm3 (CCGR42)
pwm3.ipg_clk_s PWM3_CLK_ROOT clk_enable_pwm3 (CCGR42)
pwm4.ipg_clk PWM4_CLK_ROOT clk_enable_pwm4 (CCGR43)
pwm4.ipg_clk_highfreq PWM4_CLK_ROOT clk_enable_pwm4 (CCGR43)
pwm4.ipg_clk_s PWM4_CLK_ROOT clk_enable_pwm4 (CCGR43)
FLEXSPI flexspi_wrapper.hclk AHB_CLK_ROOT clk_enable_qspi (CCGR47)
flexspi_wrapper.ipg_clk IPG_CLK_ROOT clk_enable_qspi (CCGR47)
flexspi_wrapper.ipg_clk_s IPG_CLK_ROOT clk_enable_qspi (CCGR47)
flexspi_wrapper.ipg_clk_4xsfif QSPI_CLK_ROOT clk_enable_qspi (CCGR47)
flexspi_wrapper.ipg_clk_s IPG_CLK_ROOT clk_enable_qspi (CCGR47)
qspi_sec.ipg_clk IPG_CLK_ROOT clk_enable_qspi (CCGR47)
qspi_sec.ipg_clk_s IPG_CLK_ROOT clk_enable_qspi (CCGR47)
qspi_sec.mst_hclk AHB_CLK_ROOT clk_enable_qspi (CCGR47)
RDC rdc. ipg_clk_s IPG_CLK_ROOT clk_enable_rdc (CCGR49)
rdc. ipg_clk IPG_CLK_ROOT clk_enable_rdc (CCGR49)
rdc_mem. ipg_clk IPG_CLK_ROOT clk_enable_rdc (CCGR49)
SAI sai1.ipg_clk AUDIO_AHB_CLK_ROOT clk_enable_sai1 (CCGR51)
sai1.ipg_clk_s AUDIO_AHB_CLK_ROOT clk_enable_sai1 (CCGR51)
sai1.ipg_clk_sai_mclk SAI1_CLK_ROOT clk_enable_sai1 (CCGR51)
sai1.ipt_clk_sai_bclk SAI1_CLK_ROOT clk_enable_sai1 (CCGR51)
sai1.ipt_clk_sai_bclk_b SAI1_CLK_ROOT clk_enable_sai1 (CCGR51)
sai2.ipg_clk AUDIO_AHB_CLK_ROOT clk_enable_sai2 (CCGR52)
sai2.ipg_clk_s AUDIO_AHB_CLK_ROOT clk_enable_sai2 (CCGR52)
sai2.ipg_clk_sai_mclk SAI2_CLK_ROOT clk_enable_sai2 (CCGR52)
sai2.ipt_clk_sai_bclk SAI2_CLK_ROOT clk_enable_sai2 (CCGR52)
sai2.ipt_clk_sai_bclk_b SAI2_CLK_ROOT clk_enable_sai2 (CCGR52)
sai3.ipg_clk AUDIO_AHB_CLK_ROOT clk_enable_sai3 (CCGR53)
sai3.ipg_clk_s AUDIO_AHB_CLK_ROOT clk_enable_sai3 (CCGR53)
sai3.ipg_clk_sai_mclk SAI3_CLK_ROOT clk_enable_sai3 (CCGR53)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 319
Clock Control Module (CCM)

Table 5-2. System Clocks and Gating (continued)

Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable (CCGR)
sai3.ipt_clk_sai_bclk SA3_CLK_ROOT clk_enable_sai3 (CCGR53)
sai3.ipt_clk_sai_bclk_b SA3_CLK_ROOT clk_enable_sai3 (CCGR53)
sai5.ipg_clk AUDIO_AHB_CLK_ROOT clk_enable_sai5 (CCGR55)
sai5.ipg_clk_s AUDIO_AHB_CLK_ROOT clk_enable_sai5 (CCGR55)
sai5.ipg_clk_sai_mclk SAI5_CLK_ROOT clk_enable_sai5 (CCGR55)
sai5.ipt_clk_sai_bclk SAI5_CLK_ROOT clk_enable_sai5 (CCGR55)
sai5.ipt_clk_sai_bclk_b SAI5_CLK_ROOT clk_enable_sai5 (CCGR55)
sai6.ipg_clk AUDIO_AHB_CLK_ROOT clk_enable_sai6 (CCGR56)
sai6.ipg_clk_s AUDIO_AHB_CLK_ROOT clk_enable_sai6 (CCGR56)
sai6.ipg_clk_sai_mclk SAI6_CLK_ROOT clk_enable_sai6 (CCGR56)
sai6.ipt_clk_sai_bclk SAI6_CLK_ROOT clk_enable_sai6 (CCGR56)
sai6.ipt_clk_sai_bclk_b SAI6_CLK_ROOT clk_enable_sai6 (CCGR56)
SDMA sdma1. ips_hostctrl_clk IPG_CLK_ROOT clk_enable_sdma1 (CCGR58)
sdma1. sdma_ap_ahb_clk AHB_CLK_ROOT clk_enable_sdma1 (CCGR58)
sdma1. sdma_core_clk IPG_CLK_ROOT clk_enable_sdma1 (CCGR58)
sdma2. ips_hostctrl_clk AUDIO_IPG_CLK_ROOT clk_enable_sdma2 (CCGR59)
sdma2. sdma_ap_ahb_clk AUDIO_AHB_CLK_ROOT clk_enable_sdma2 (CCGR59)
sdma2. sdma_core_clk AUDIO_IPG_CLK_ROOT clk_enable_sdma2 (CCGR59)
SEMA4 sema1.clk IPG_CLK_ROOT clk_enable_sema1 (CCGR61)
sema2.clk IPG_CLK_ROOT clk_enable_sema2 (CCGR62)
SIM sim_display.cm4clk ARM_M4_CLK_ROOT GPC controlled
sim_display.mainclk MAIN_AXI_CLK_ROOT clk_enable_sim_display
(CCGR63)
sim_display.mainclk_r MAIN_AXI_CLK_ROOT clk_enable_sim_display
(CCGR63)
sim_enet.mainclk ENET_AXI_CLK_ROOT clk_enable_sim_enet
(CCGR64)
sim_enet.mainclk_r ENET_AXI_CLK_ROOT clk_enable_sim_enet
(CCGR64)
sim_m.mainclk AHB_CLK_ROOT clk_enable_sim_m (CCGR65)
sim_m.mainclk_r AHB_CLK_ROOT clk_enable_sim_m (CCGR65)
sim_m.usdhcclk NAND_USDHC_BUS_CLK_R clk_enable_sim_m (CCGR65)
OOT
sim_m.usdhcclk_r NAND_USDHC_BUS_CLK_R clk_enable_sim_m (CCGR65)
OOT
sim_main.cm4clk ARM_M4_CLK_ROOT GPC controlled
sim_main.enetclk ENET_AXI_CLK_ROOT clk_enable_sim_enet
(CCGR64)
sim_main.mainclk MAIN_AXI_CLK_ROOT clk_enable_sim_main
(CCGR66)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

320 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-2. System Clocks and Gating (continued)

Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable (CCGR)
sim_main.mainclk_r MAIN_AXI_CLK_ROOT clk_enable_sim_main
(CCGR66)
sim_main.per_mclk AHB_CLK_ROOT clk_enable_sim_m (CCGR65)
sim_main.per_sclk AHB_CLK_ROOT clk_enable_sim_s (CCGR67)
sim_main.usdhcclk NAND_USDHC_BUS_CLK_R clk_enable_sim_m (CCGR65)
OOT
sim_main.wakeupclk AHB_CLK_ROOT clk_enable_sim_wakeup
(CCGR68)
sim_s.apbhdmaclk NAND_USDHC_BUS_CLK_R clk_enable_rawnand
OOT (CCGR48)
sim_s.gpv4clk ENET_AXI_CLK_ROOT clk_enable_sim_enet
(CCGR64)
sim_s.mainclk AHB_CLK_ROOT clk_enable_sim_s (CCGR67)
sim_s.mainclk_r AHB_CLK_ROOT clk_enable_sim_s (CCGR67)
sim_s.weimclk AHB_CLK_ROOT clk_enable_sim_s_weimclk
(CCGR4)
sim_wakeup.mainclk AHB_CLK_ROOT clk_enable_sim_wakeup
(CCGR68)
sim_wakeup.mainclk_r AHB_CLK_ROOT clk_enable_sim_wakeup
(CCGR68)
SNVS snvs_hs_wrapper.ipg_clk IPG_CLK_ROOT clk_enable_snvs (CCGR71)
snvs_hs_wrapper.ipg_clk_s IPG_CLK_ROOT clk_enable_snvs (CCGR71)
SPBA spba1.ipg_clk IPG_CLK_ROOT clk_enable_ipmux3
(CCGR30)
spba1.ipg_clk_s IPG_CLK_ROOT clk_enable_ipmux3
(CCGR30)
UART uart1.ipg_clk IPG_CLK_ROOT clk_enable_uart1 (CCGR73)
uart1.ipg_clk_s IPG_CLK_ROOT clk_enable_uart1 (CCGR73)
uart1.ipg_perclk UART1_CLK_ROOT clk_enable_uart1 (CCGR73)
uart2.ipg_clk IPG_CLK_ROOT clk_enable_uart2 (CCGR74)
uart2.ipg_clk_s IPG_CLK_ROOT clk_enable_uart2 (CCGR74)
uart2.ipg_perclk UART2_CLK_ROOT clk_enable_uart2 (CCGR74)
uart3.ipg_clk IPG_CLK_ROOT clk_enable_uart3 (CCGR75)
uart3.ipg_clk_s IPG_CLK_ROOT clk_enable_uart3 (CCGR75)
uart3.ipg_perclk UART3_CLK_ROOT clk_enable_uart3 (CCGR75)
uart4.ipg_clk IPG_CLK_ROOT clk_enable_uart4 (CCGR76)
uart4.ipg_clk_s IPG_CLK_ROOT clk_enable_uart4 (CCGR76)
uart4.ipg_perclk UART4_CLK_ROOT clk_enable_uart4 (CCGR76)
uSDHC usdhc1.hclk NAND_USDHC_BUS_CLK_R clk_enable_usdhc1
OOT (CCGR81)
usdhc1.ipg_clk IPG_CLK_ROOT clk_enable_usdhc1
(CCGR81)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 321
Clock Control Module (CCM)

Table 5-2. System Clocks and Gating (continued)

Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable (CCGR)
usdhc1.ipg_clk_perclk USDHC1_CLK_ROOT clk_enable_usdhc1
(CCGR81)
usdhc1.ipg_clk_s IPG_CLK_ROOT clk_enable_usdhc1
(CCGR81)
usdhc2.hclk NAND_USDHC_BUS_CLK_R clk_enable_usdhc2
OOT (CCGR82)
usdhc2.ipg_clk IPG_CLK_ROOT clk_enable_usdhc2
(CCGR82)
usdhc2.ipg_clk_perclk USDHC2_CLK_ROOT clk_enable_usdhc2
(CCGR82)
usdhc2.ipg_clk_s IPG_CLK_ROOT clk_enable_usdhc2
(CCGR82)
usdhc3.hclk NAND_USDHC_BUS_CLK_R clk_enable_usdhc3
OOT (CCGR94)
usdhc3.ipg_clk IPG_CLK_ROOT clk_enable_usdhc3
(CCGR94)
usdhc3.ipg_clk_perclk USDHC3_CLK_ROOT clk_enable_usdhc3
(CCGR94)
usdhc3.ipg_clk_s IPG_CLK_ROOT clk_enable_usdhc3
(CCGR94)
WDOG wdog1.ipg_clk WDOG_CLK_ROOT clk_enable_wdog1 (CCGR83)
wdog1.ipg_clk_s WDOG_CLK_ROOT clk_enable_wdog1 (CCGR83)
wdog2.ipg_clk WDOG_CLK_ROOT clk_enable_wdog2 (CCGR84)
wdog2.ipg_clk_s WDOG_CLK_ROOT clk_enable_wdog2 (CCGR84)
wdog3.ipg_clk WDOG_CLK_ROOT clk_enable_wdog3 (CCGR85)
wdog3.ipg_clk_s WDOG_CLK_ROOT clk_enable_wdog3 (CCGR85)

5.1.5 Functional Description

CCM receives clocks from PLLs and oscillators. Then the clock root generation logic
inside CCM will generate various clock roots required for core, bus, and peripheral
blocks. These clock roots will be delivered to each module through LPCG, which
contains the clock gating logic for each clock.
The following sections further describe the functional details of CCM.

5.1.5.1 Input Clocks

The table below describes the input clock sources that supply the 8: 1 selector muxes to
the clock slices in the clock root generator.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

322 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Control Register Input Clock Frequency (MHz) Description

(CCM_PLL_CTRLn)
12 ARM_PLL_CLK 1600 Arm PLL
13 GPU_PLL_CLK 1600 GPU PLL clock output
14 VPU_PLL_CLK 800 VPU PLL clock output
15 DRAM_PLL1_CLK 800 DDR PLL
16 SYSTEM_PLL1_CLK 800 System PLL1 output clock
17 SYSTEM_PLL1_DIV2 400 System PLL1 divided 2 clock output
18 SYSTEM_PLL1_DIV3 266 System PLL1 divided 3 clock output
19 SYSTEM_PLL1_DIV4 200 System PLL1 divided 4 clock output
20 SYSTEM_PLL1_DIV5 160 System PLL1 divided 5 clock output
21 SYSTEM_PLL1_DIV6 133 System PLL1 divided 6 clock output
22 SYSTEM_PLL1_DIV8 100 System PLL1 divided 8 clock output
23 SYSTEM_PLL1_DIV10 80 System PLL1 divided 10 clock output
24 SYSTEM_PLL1_DIV20 40 System PLL divided 20 clock output
25 SYSTEM_PLL2_CLK 1000 System PLL2 output clock
26 SYSTEM_PLL2_DIV2 500 System PLL2 divided 2 clock output
27 SYSTEM_PLL2_DIV3 333 System PLL2 divided 3 clock output
28 SYSTEM_PLL2_DIV4 250 System PLL2 divided 4 clock output
29 SYSTEM_PLL2_DIV5 200 System PLL2 divided 5 clock output
30 SYSTEM_PLL2_DIV6 166 System PLL2 divided 6 clock output
31 SYSTEM_PLL2_DIV8 125 System PLL2 divided 8 clock output
32 SYSTEM_PLL2_DIV10 100 System PLL2 divided 10 clock output
33 SYSTEM_PLL2_DIV20 50 System PLL2 divided 20 clock output
34 SYSTEM_PLL3_CLK 1000 System PLL3 output clock
35 AUDIO_PLL1_CLK 650 Audio PLL1 clock output
36 AUDIO_PLL2_CLK 650 Audio PLL2 clock output
37 VIDEO_PLL1_CLK 650 Video PLL1 clock output
external source 32K_REF_CLK 0.032 32K oscillator clock output
external source 24M_REF_CLK 24 24M oscillator clock output
external source EXT_CLK_1 133 Clock input from external IO
external source EXT_CLK_2 133 Clock input from external IO
external source EXT_CLK_3 133 Clock input from external IO
external source EXT_CLK_4 133 Clock input from external IO

5.1.5.2 CKIL Synchronizer

CCM provides a synchronized version of the 32K clock called CKIL Synchronizer
(CKIL_SYNC). The CKIL_SYNC clock is generated and synchronized by the
IPG_CLK_ROOT when IPG_CLK_ROOT is active.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 323
Clock Control Module (CCM)

When the system enters low-power mode that requires the shutdown of
IPG_CLK_ROOT, the CKIL Synchonrizer will be bypassed and fed directly from the
XTALOSC 32K source.
NOTE
CKIL_SYNC needs to be configured the same as the PLL for
ipg_clk

5.1.5.3 Clock Components

The details of the CCM clock components are detailed below.

5.1.5.3.1 Clock Divider

The synchronized clock dividers (PRE_PODF and POST_PODF) can be used to perform
integer division on the source clock frequency. The divider guarantees a clean clock
signal on its output during the change of the divide factor. Dividers perform a 1/(N+1)
divide. A glitch can cause a sync-divider to go into an unrecoverable state, therefore a
clean clock signal must be provided to a sync-divider.

5.1.5.3.2 Clock Switching Multiplexer

The 2-to-1 clock switching multiplexers can guarantee a clean clock signal when
switching between 2 clock sources. Both clock inputs must be active when switching. If
there is any glitch in the selected clock source, then it may be transferred to the output
clock while the de-selected source is blocked. Glitches may cause an unpredictable state,
and will recover in 2~3 cycles.
The clock switching multiplexers shutdown the current active clock source before
switching. After receiving an acknowledgement that the current clock source has
shutdown, the multiplexer turns on the selected clock source. As the acknowledgement of
turning on the new clock source is received, the clock source switch finishes.

5.1.5.3.3 Clock Gate

A clock gate cell is used to gate clocks. When gated, the clock will stop at 0. A clock gate
cell can accept glitches on its clock inputs. If the gate cell is off, it will block or absorb
glitches. If the gate cell is on, it may pass glitches to its output. A gate cell needs 2~3
clock cycles to change states. The state during this period is either on or off and will
recover in 2~3 cycles, but cannot be predicted which state it is in during this period.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

324 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.5.3.4 8 to 1 Multiplexer
The 8-to-1 multiplexer is a combinational multiplexer that can switch anytime. The
multiplexer output does not guarantee a clean clock signal. The output clock path from
the multiplexer must be clock gated before changing the multiplexer selection. This will
insure a clean clock source change.

5.1.5.4 Clock Slices

There are several types of clock generation slices in CCM. The slices are categorized as
Core, Bus, Peripheral (IP), and DRAM.

Clock Source from Clock Root 0

PLL/PFD/Divider Clock Slice 0

Clock Root 1
Clock Slice 1

...

Clock Root N
Clock Slice N

Figure 5-4. Clock Slices

The following figure illustrates the CCM clock components that a clock slice can
comprise of, and the associated register controls. Not all clock slice types will comprise
of all the components provided in the figure below. Please refer to the following sections
to identify the components included in particular clock slice type. The slice shown below
is comprised of a post divider and a clock switching multiplexer with 2 input sources.
Each input source has a pre-divider, a clock gate and a clock multiplexer inside.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 325
Clock Control Module (CCM)

CCM_PREn[MUX_A]
clk 0
clk 1

MUX_A
CCM_PREn[EN_A]
clk 2
clk 3 CG
clk 4
clk 5 CCM_PREn[PRE_PODF_A]
CCM_POSTn[SELECT]
clk 6
clk 7 PRE_PODF_A

MUX
POST_PODF
PRE_PODF_B
CCM_POSTn[POST_PODF]

MUX_B
CCM_PREn[PRE_PODF_B]
CG
CCM_PREn[EN_B]

CCM_PREn[MUX_B]

Figure 5-5. Clock Slice Components

5.1.5.4.1 Core clock slice

Core clock slices are designed for high speed, non-stop clock generation, typically for an
Arm core. A core clock slice is comprised of a post divider and a 2-to-1 clock switching
multiplexer with 2 input sources. Each input source has a clock gate and a 8-to-1 clock
multiplexer. To run at high frequency, the post divider is only 3 bits, which is half the bit
width of other slices. The two 8-to-1 multiplexers are not glitch-less, so switching them
should only be done when they are clock gated to prevent propagation glitches.

clk 0
clk 1
MUX_A

clk 2
clk 3
CG
clk 4
clk 5
clk 6
clk 7
MUX

POST_PODF
MUX_B

CG

Figure 5-6. Core clock slice

5.1.5.4.2 Bus clock slice

Bus clock slices are comprised of a post divider and a clock switching multiplexer with 2
input sources. Each input source has a pre-divider, a clock gate and a clock multiplexer
inside. The pre-divider is three bits and provides a maximum division factor of 8. The

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

326 NXP Semiconductors
 Chapter 5 Clocks and Power Management

post-divider is six bits. The two 8-to-1 multiplexers are not glitch-less, so switching
should only be done when they are clock gated to prevent propagation glitches. The eight
clock selections are the same for MUX_A and MUX_B.

clk 0
clk 1

MUX_A
clk 2
clk 3 CG
clk 4
clk 5
clk 6
clk 7 PRE_PODF_A

MUX
POST_PODF
PRE_PODF_B
MUX_B

CG

Figure 5-7. Bus clock slice

5.1.5.4.3 Peripheral clock slice

The peripheral (IP) clock slices are comprised of a clock multiplexer, clock gate, pre-
divider and post-divider. The pre-divider is three bit and can divide down by a factor of 8.
The post-divider is six bit . The 8-to-1 multiplexer is not glitch-less, so switching should
only be done when they are clock gated to prevent propagation glitches.
Peripheral clock slices must be stopped to change the clock source.

clk 0
clk 1
clk 2
MUX_A

clk 3
clk 4 CG PRE_PODF_A POST_PODF
clk 5
clk 6
clk 7

Figure 5-8. Peripheral clock slice

5.1.5.4.4 SSCG and Fractional PLLs

The Spread Spectrum Clock Generator (SSCG) and Fractional-N PLLs are detailed
below.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 327
Clock Control Module (CCM)

The fractional PLL consists of a phase-frequency detector (PFD), charge pump, voltage
controller oscillator (VCO), a 6-bit pre divider, 10-bit main divider, a 3-bit scaler, a delta-
sigma modulator (DSM) and an automatic frequency control (AFC).
The figure below shows the Fractional PLL block diagram.

AFC_ENB

EXTAFC[4:0]

MUX
ICP[2:0] AFC_CODE[4:0]
5

FREF
Phase UP Voltage
Charge VCOOUT FOUT
Pre-Divider Frequency Controlled Scaler
FIN FEED Pump
Detector DN Oscillator

P[5:0] S[2:0] BYPASS

Main /2Divider
K[15:0] Divider

SEL_PF[1:0]
20 10
Modulation
SSCG_EN DSM
Control
FSEL

MFR[7:0] MRR[5:0] M[9:0]

FREF
FEED _OUT

MUX
FEED
FREF
AFC_ENB
FEED AFC
AFC_CODE[4:0]
FEED_EN

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

328 NXP Semiconductors
 Chapter 5 Clocks and Power Management

FIN/p Phase Voltage FVCO Post-Scaler

Pre- Divider
FIN Frequency Controlled (s) FOUT
(p)
Detector Ocsillator

Programmable CCM_ANALOG_xx_FDIV_CTL0[PLL_PRE_DIV]
Pre-Divider Main Divider
FVCO/m
(m)

Programmable CCM_ANALOG_xx_FDIV_CTL0[PLL_MAIN_DIV]
Main Divider

Programmable CCM_ANALOG_xx_FDIV_CTL0[PLL_POST_DIV]

Post-Divider

Figure 5-9. Fractional PLL Block Diagram

Formula for Fraction PLLOUT:

• FOUT=((m+k/65536) x FIN) /(p x 2s)
• Where, 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6, -32768 ≤ k ≤ 32767
• p, m, and s are unsigned integers. k is a two's complement integer.
• Where, FOUT is the output frequency, FIN is the input frequency, and p,m,s and k
are division values for pre-divider, main divider, scaler and DSM respectively
When SSCG_EN = 1, the spread spectrum mode is enabled. The associated formulas and
values are provided below:
• Modulation frequency (MF) = FFIN / p / mfr / (2^5) [Hz]
• Modulation rate (MR) = mfr x mrr / m / (2^6) x 100 [%]
• Where, 0 ≤ mfr ≤ 255, 1 ≤ mrr ≤ 63, 0 ≤ mrr x mfr ≤ 512
The ARM PLL, GPU PLL, VPU PLL, Audio PLL1/2, and Video PLL1 are fractional
PLLs. The frequency on these can be tuned to be very accurate to meet audio and video
interface requirements.

5.1.5.5 Clock gate control

CCM can perform automatic clock shutdown of on-chip peripherals according to system
low power mode. Each logic domain can respectively declare its dependency level on
each clock. If a clock is detected that is not dependant on any domain, it will be shutdown
to save power.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 329
Clock Control Module (CCM)

Clock generation inside the CCM creates a clock root for on-chip peripherals. Before the
clock root goes into peripherals via low power clock gating cells. By controlling these
LPCGs, CCM can manage on-chip peripheral clocks.
Clock gate controls use active clock gating, which means the low power clock gating
(LPCG) requires an active clock root. The clock generation module only performs
multiplexing, gating and dividing on clock sources. Therefore, the clock root from the
generation module will stop when the corresponding clock source stops.
The ENABLE bit must be set for the clock root that LPCG is actively gating.

5.1.5.6 Clock source control

The CCM can perform automatic PLL shutdown of CCM_ANALOG according to
system low power mode. Each logic domain can respectively declare its dependency
level on each clock. If a PLL is not dependent on any domain, it will be shutdown to save
power.
PLLs in CCM_ANALOG can also be controlled by the CCM via setting the override bits
in the respective PLL's control register.
For PLLs, there are controls on every PLL, PFD and divider. PLLs are the source for the
PFDs and dividers. For any clock that is enabled, its source must be left on, otherwise,
the behavior is undefined. For a shutdown clock source, if it is set as dependent by
writing to the clock source control registers (CCM_PLL_CTRLn[SETTING0/1/2/3]), the
controlling logic will turn on the source immediately, while the setting goes into a
shadow register. After the clock source is ready, the setting will be accepted by the
source control logic, and copied from the shadow register to the setting register.
Handshake with the PLL happens if the change of the setting causes a PLL to start up or
shutdown. The time cost is determined by the PLL that is under control. Software can
poll the setting field for a new setting value.

5.1.5.7 Access control

CCM can implement its own access control based on domain to provide more precise
control on shared resources. Access controls are implemented on clock root generation,
clock gate control, and clock source control. Access control logic does not impact read
access, but blocks unauthentic write access.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

330 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Access controls on clock root generation are independent between every clock root. A
sticky authentic fail flag is set when a domain writes to a register and authentication fails.
The access control logic contains a whitelist and a semaphore. By default, each clock
root's access control logic is disabled after power-on reset. Software can enable access
control anytime after reset.
NOTE
Once access logic is enabled, it cannot be disabled until the
next power-on reset.
Table 5-3. Whitelist
Enabled Write access will be authenticated before being performed.
Disabled every access on protected item will be performed.

NOTE
Only domains that are on the whitelist can perform write access
to this clock root when access control is enabled.
Table 5-4. Semaphore
Enabled A domain must obtain the semaphore’s ownership before its write access can be
authenticated. Only a domain on the whitelist can obtain the ownership and the
ownership will last until the domain explicitly releases the ownership. Semaphore
obtain will fail if it is already fetched by some other domain.
Disabled Authentic check will check only on whitelist.

NOTE
Semaphore is intended to help software keep the clock root
from unexpectedly changing.
Access control of clock gate and clock source control is performed in a simple operation.
Every domain can only write on the bits for it's own setting. Any write to irrespective
domain will be ignored.

5.1.5.8 System level considerations

Clock shutdown strategy
Any clock shutdown should first shutdown the LPCG, then the PLL. If the LPCG is
configured not to shutdown, the clock root for the LPCG should not stop either. Violating
this rule leads the system into an unpredictable state.
Core clock root frequency

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 331
Clock Control Module (CCM)

If the core clock is set lower that one third of the IPG clock, SRC needs to generate a
longer reset signal to match the requirement from the Arm core. This typically happens
when the Arm core runs at some divided value of the XTAL 24M while IPG clock is
supplied by the PLL.
DRAM clock
The DRAM PHYM clock needs a clock frequency faster that 400MHz.
USB OTG CLOCK
The USB clock may not be a reliable clock source in some applications. This clock may
stop when USB cable is disconnected.

5.1.6 Programming Guide

5.1.6.1 Set, Clear, and Toggle register features

Every register of the CCM has set, clear, and toggle features.
The set feature for a given register is located at:
Base Address of the register + 0x04
The clear feature for a given register is located at:
Base Address of the regsister + 0x08
The toggle feature is located at:
Base Address of the register + 0x0c
Read from all 4 locations to get the current register value. Writing to the base register bits
sets the register to the write value. Writing 1 to the set register bits sets them to 1, while
writing 0 has no effect. Writing 1 to the clear register bits clears them to 0, while writing
0 has no effect. Writing 1 to the toggle register bits sets them to invert the value, while
writing 0 has no effect.

5.1.6.2 PLL Interface

CCM can control PLLs inside CCM_ANALOG when entering or leaving low-power
mode. Software must set the PLL override inside CCM_ANALOG before entering low-
power mode after power-on reset (POR).
There are four levels of low-power modes in a logic domain:
• Not needed
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
332 NXP Semiconductors
 Chapter 5 Clocks and Power Management

• Needed in RUN
• Needed in RUN and WAIT
• Needed in RUN, WAIT, and STOP
CCM only takes action while domain status are switching between STOP (DEEP SLEEP
mode is considered the same as STOP). There are 4 domains that can be assigned. Any
CPU platform can be assigned to any domain by RDC. If a domain is empty, the domain
is considered as STOP.
Each domain can declare its dependency to CCM. The use of any clock, without
declaring it in its own domain, is not permitted. A domain declares its dependency on a
clock by writing the dependency level. Settings against behavior in low-power mode are
as follows:
Table 5-5. Domain Dependency
Domain Level Run Wait Stop / Deep sleep
0
1 Required
2 Required Required
3 Required Required Required

Table 5-6. CCGR Program Interface

CC Domain3 Domain2 Domain1 Domain0
GR
31-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Level1 Level0 Level1 Level0 Level1 Level0 Level1 Level0

Each domain can change only bits assigned to control access. Any irrelevant write to it
will be ignored. For example, Domain 0 can only write to bits [1:0]. Any bits written to,
other than bits [1:0], will be ignored. Other domains can read all of the other domain
settings. The default value for domain 0 is 2, and will enter STOP mode after shutting
down. When the default value of the other domain setting is 0, it will not be required.
When setting clock source, the settings will not take effect immediately. The setting will
enter the shadow register first. If a PLL shutdown or new setting enters the shadow
register to declare dependency on the PLL, the PLL will turn on immediately. When the
PLL is ready, the setting in shadow register will be updated to the new setting. During
this period, the pending bit will be set and cleared. Then CCM will send the PLL control
signal as a shadow register and inform GPC the PLL status according to the setting
register. In other cases, the setting will be updated from the shadow register immediately.
Clock sources have dependency on each other.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 333
Clock Control Module (CCM)

NOTE
Do not shutdown the parent clock when the required child clock
is active. Attempting to do so will lead to unpredicable and
unrecoverable behavior. It is recommended to shutdown the
parent clock and child clock together.

5.1.6.3 CCGR Interface

Before a clock root goes to on–chip peripherals, the clock root is distributed through low
power clock gates (LPCG). These LPCG are implemented to automatically perform clock
shutdown when a domain enters and leaves a low-power state.
There are four levels of low-power modes in a logic domain:
• Not needed
• Needed in RUN
• Needed in RUN and WAIT
• Needed in RUN, WAIT, and STOP
CCM only takes action while domain status are switching between STOP (DEEP SLEEP
mode is considered the same as STOP). There are 4 domains that can be assigned. Any
CPU platform can be assigned to any domain by RDC. If a domain is empty, the domain
is considered as STOP.
Each domain can declare its dependency to CCM. The use of any clock, without
declaring it in its own domain, is not permitted. A domain declares its dependency on a
clock by writing the dependency level. Settings against behavior in low-power mode are
as follows:
Table 5-7. Domain Dependency
Domain Level RUN WAIT STOP/ DEEP SLEEP
0
1 Required
2 Required Required
3 Required Required Required

Table 5-8. CCGR Program Interface

CC Domain3 Domain2 Domain1 Domain0
GR
31-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Level1 Level0 Level1 Level0 Level1 Level0 Level1 Level0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

334 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Each domain can change only bits assigned to control access. Any irrelevant write to it
will be ignored. For example, Domain 0 can only write to bits [1:0]. Any bits written to,
other than bits [1:0], will be ignored. Other domains can read all of the other domain
settings. The default value for domain 0 is 2, and will enter STOP mode after shutting
down. When the default value of the other domain setting is 0, it will not be required.

The table below lists the CCM Clock Gating Register (CCGR) and associated offset for
each LPCG enable.
NOTE
Not all CCGRs are mapped.
NOTE
Sec_debug clock gating (CCGR60) must be active in low
power mode. DO NOT gate this clock in low power mode to
guarantee the low power mode functions such as stop WDOG
counting.
Table 5-9. CCGR Mapping Table
Gating Register LPCG Enable Offset
CCM_CCGR0 DVFS (GPC) 0x4000
CCM_CCGR1 Anamix 0x4010
CCM_CCGR2 CPU 0x4020
CCM_CCGR3 CSU 0x4030
CCM_CCGR4 Debug 0x4040
CCM_CCGR5 DDR1 0x4050
CCM_CCGR6 Reserved 0x4060
CCM_CCGR7 ECSPI1 0x4070
CCM_CCGR8 ECSPI2 0x4080
CCM_CCGR9 ECSPI3 0x4090
CCM_CCGR10 ENET1 0x40A0
CCM_CCGR11 GPIO1 0x40B0
CCM_CCGR12 GPIO2 0x40C0
CCM_CCGR13 GPIO3 0x40D0
CCM_CCGR14 GPIO4 0x40E0
CCM_CCGR15 GPIO5 0x40F0
CCM_CCGR16 GPT1 0x4100
CCM_CCGR17 GPT2 0x4110
CCM_CCGR18 GPT3 0x4120
CCM_CCGR19 GPT4 0x4130
CCM_CCGR20 GPT5 0x4140
CCM_CCGR21 GPT6 0x4150

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 335
Clock Control Module (CCM)

Table 5-9. CCGR Mapping Table (continued)

Gating Register LPCG Enable Offset
CCM_CCGR22 HS 0x4160
CCM_CCGR23 I2C1 0x4170
CCM_CCGR24 I2C2 0x4180
CCM_CCGR25 I2C3 0x4190
CCM_CCGR26 I2C4 0x41A0
CCM_CCGR27 IOMUX 0x41B0
CCM_CCGR28 IPMUX1 0x41C0
CCM_CCGR29 IPMUX2 0x41D0
CCM_CCGR30 IPMUX3 0x41E0
CCM_CCGR31 IPMUX4 0x41F0
CCM_CCGR32 SNVSMIX 0x4200
CCM_CCGR33 MU 0x4210
CCM_CCGR34 OCOTP 0x4220
CCM_CCGR35 OCRAM 0x4230
CCM_CCGR36 OCRAM_s 0x4240
CCM_CCGR37 PCIE 0x4250
CCM_CCGR38 PERFMON1 0x4260
CCM_CCGR39 PERFMON2 0x4270
CCM_CCGR40 PWM1 0x4280
CCM_CCGR41 PWM2 0x4290
CCM_CCGR42 PWM3 0x42A0
CCM_CCGR43 PWM4 0x42B0
CCM_CCGR44 QoS 0x42C0
CCM_CCGR45 QoS_Dispmix 0x42D0
CCM_CCGR46 QoS_ENET 0x42E0
CCM_CCGR47 QSPI 0x42F0
CCM_CCGR48 NAND (APBHDMA, GPMI, BCH) 0x4300
CCM_CCGR49 RDC 0x4310
CCM_CCGR50 ROM 0x4320
CCM_CCGR51 SAI1 0x4330
CCM_CCGR52 SAI2 0x4340
CCM_CCGR53 SAI3 0x4350
CCM_CCGR54 SAI4 0x4360
CCM_CCGR55 SAI5 0x4370
CCM_CCGR56 SAI6 0x4380
CCM_CCGR57 SCTR 0x4390
CCM_CCGR58 SDMA1 0x43A0
CCM_CCGR59 SDMA2 0x43B0
CCM_CCGR60 SEC_DEBUG 0x43C0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

336 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Table 5-9. CCGR Mapping Table (continued)

Gating Register LPCG Enable Offset
CCM_CCGR61 SEMA1 0x43D0
CCM_CCGR62 SEMA2 0x43E0
CCM_CCGR63 SIM_display 0x43F0
CCM_CCGR64 SIM_ENET 0x4400
CCM_CCGR65 SIM_m 0x4410
CCM_CCGR66 SIM_main 0x4420
CCM_CCGR67 SIM_s 0x4430
CCM_CCGR68 SIM_wakeup 0x4440
CCM_CCGR69 SIM_HSIO 0x4450
CCM_CCGR70 Reserved 0x4460
CCM_CCGR71 SNVS 0x4470
CCM_CCGR72 Trace 0x4480
CCM_CCGR73 UART1 0x4490
CCM_CCGR74 UART2 0x44A0
CCM_CCGR75 UART3 0x44B0
CCM_CCGR76 UART4 0x44C0
CCM_CCGR77 USB 0x44D0
CCM_CCGR78 Reserved 0x44E0
CCM_CCGR79 GPU3D 0x44F0
CCM_CCGR80 Reserved 0x4500
CCM_CCGR81 USDHC1 0x4510
CCM_CCGR82 USDHC2 0x4520
CCM_CCGR83 WDOG1 0x4530
CCM_CCGR84 WDOG2 0x4540
CCM_CCGR85 WDOG3 0x4550
CCM_CCGR86 VPUG1 0x4560
CCM_CCGR87 GPU 0x4570
CCM_CCGR88 Reserved 0x4580
CCM_CCGR89 VPUH1 0x4590
CCM_CCGR90 VPUG2 0x45A0
CCM_CCGR91 PDM 0x45B0
CCM_CCGR92 GIC 0x45C0
CCM_CCGR93 Display 0x45D0
CCM_CCGR94 USDHC3 0x45E0
CCM_CCGR95 SDMA3 0x45F0
CCM_CCGR96 XTALOSC 0x4600
CCM_CCGR97 PLL 0x4610
CCM_CCGR98 TEMPSENSOR 0x4620
CCM_CCGR99 VPUMIX 0x4630

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 337
Clock Control Module (CCM)

Table 5-9. CCGR Mapping Table (continued)

Gating Register LPCG Enable Offset
CCM_CCGR100 Reserved 0x4640
CCM_CCGR101 Reserved 0x4650
CCM_CCGR102 GPU2D 0x4660

5.1.6.4 Target Interface

The Target Interface is optimized to simplify software operation. Using this interface, all
clock roots are in the same program model with the same register bit field mapping. The
software does not handle the details of the clock slice and clock slice types. Software
writes the desired settings to the register, and the internal hardware logic generates a
required sequence to achieve the desired settings.
The Target Interface requires the software to provide whether a clock is active, the clock
source number to be selected, pre-divide value, and post-divide value. If a clock slice
does not support a setting, that setting is simply ignored, and will not effect the supported
fields.
Freq = (clock source freq)/(pre_div+1)/(post_div+1)
The internal logic sequence of the Target Interface guarantees a clean clock on output
without frequency overshoot. A requirement of the Target Interface's software is that the
target clock source is active.
The Target Interface sequence begins by opening all clocks, applying highest divider
value, switching to the new clock source, then decreasing divider value to the target
frequency. If Shutdown is requested, it will be performed last.
The clock output is always active when using the Target Interface. For intermediate
frequency requests, the Target Interface choses the lowest frequency source to avoid
frequency overshoot on the Peripheral clock slices. For Core and Bus clock slices, the
clock switching multiplexer is used to guarantee smooth clock switching.
A write operation on a target interface completes once the output clock is running at the
desired setting. Software polling is not necessary to determine clock stability.
STEP STATE OPERATION
0 SMART_IDLE Idle state, no write operation is pending
1 SMART_WAIT_READY State occurs when a write access is received, wait for every
field to be ready
2 SMART_APPLY_GATE1 Open all branches, all gates inside clock slices

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

338 NXP Semiconductors
 Chapter 5 Clocks and Power Management

3 SMART_WAIT_GATE1 Wait for gate applied

4 SMART_APPLY_PODF1 apply post divider and post divider for if new value generate
slower clock
5 SMART_WAIT_PODF1 Wait for divider accept new value
6 SMART_APPLY_GATE2 shutdown spare branch if exist, else shutdown working
branch
7 SMART_WAIT_GATE2 Wait for shutdown operation complete
8 SMART_APPLY_MUX Change multiplexer to new source on spare branch if exist,
else switch working one
9 SMART_APPLY_GATE3 open gates on all branches
10 SMART_WAIT_GATE3 Wait for gates opened
11 SMART_APPLY_SWITCH Switch clock switching multiplexer if there is one
12 SMART_WAIT_SWITCH Wait for clock switching multiplexer switch
13 SMART_APPLY_PODF2 apply post divider and post divider for if new value generate
faster clock
14 SMART_WAIT_PODF2 Wait for divider accept new value
15 SMART_APPLY_GATE4 apply clock gate setting, shutdown spare one if there is
16 SMART_WAIT_GATE4 Wait for gate applied
17 SMART_APPLY_AUTO apply auto and auto divider
18 SMART_DONE Finish, wait for bus operation complete

5.1.6.5 Normal Interface

Normal interface provide more controllable thing that target interface. And also provide
protections against dangerous operation.
Normal interface provides safe sequences to handle each clock component, divider, gate,
multiplexer. But it is software that needs to care the order and relationship between
updating components.
Writing to this interface will complete immediately, and internal logic will continue try to
apply written values to clock components. A busy flag will be assert during applying.
Field access rule:
1. Only one field can be modified a time
2. No field can be modified when any field pending
3. Not violate change condition in following table
FIELD CHANGE CONDITION FINISH CONDITION
Auto immediate
Auto-divider immediate

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 339
Clock Control Module (CCM)

Bypass Gatea active and gateb active Bypass switch complete

Post-divider New divider value applied
Gate B Bypass disable New gate value active
Pre-divider B Bypass disable and gateb not gated New divider value applied
MUX B Bypass disable and gateb gating immediate
Gate A Bypass New gate value active
Pre-divider A Bypass and gatea not gated New divider value applied
MUX A Bypass and gatea gating immediate

• Error will be reported if access rules violated.

• Unsafe or ambiguous access will be ignored.
If a write access as blocked by normal interface, the write operation will be ignored. And
a sticky bit “violate” will be set. The bit will last until software clears it explicitly. The
violate bit is 4 bits inside CCM, each for a logic domain. Each domain can read and clear
the bit for itself, the bits for other domain is neither visible nor clearable.

5.1.7 CCM Memory Map/Register Definition

The Memory Map below represents the full array for CCM.
NOTE
Not all mapped Clock Slices and CCGRs are tied to functional
components.
Please see the following for the functional mapping tables and information:
• CCM_PLL_CTRL - Input Clocks
• CCM_TARGET_ROOT - Clock Root Selects
• CCM_CCGR - CCGR Interface
CCM memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_0000 General Purpose Register (CCM_GPR0) 32 R/W 0000_0000h 5.1.7.1/494
3038_0004 General Purpose Register (CCM_GPR0_SET) 32 R/W 0000_0000h 5.1.7.1/494
3038_0008 General Purpose Register (CCM_GPR0_CLR) 32 R/W 0000_0000h 5.1.7.1/494
3038_000C General Purpose Register (CCM_GPR0_TOG) 32 R/W 0000_0000h 5.1.7.1/494
3038_0800 CCM PLL Control Register (CCM_PLL_CTRL0) 32 R/W 0000_0002h 5.1.7.2/495
3038_0804 CCM PLL Control Register (CCM_PLL_CTRL0_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0808 CCM PLL Control Register (CCM_PLL_CTRL0_CLR) 32 R/W 0000_0002h 5.1.7.4/499
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

340 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_080C CCM PLL Control Register (CCM_PLL_CTRL0_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0810 CCM PLL Control Register (CCM_PLL_CTRL1) 32 R/W 0000_0002h 5.1.7.2/495
3038_0814 CCM PLL Control Register (CCM_PLL_CTRL1_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0818 CCM PLL Control Register (CCM_PLL_CTRL1_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_081C CCM PLL Control Register (CCM_PLL_CTRL1_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0820 CCM PLL Control Register (CCM_PLL_CTRL2) 32 R/W 0000_0002h 5.1.7.2/495
3038_0824 CCM PLL Control Register (CCM_PLL_CTRL2_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0828 CCM PLL Control Register (CCM_PLL_CTRL2_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_082C CCM PLL Control Register (CCM_PLL_CTRL2_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0830 CCM PLL Control Register (CCM_PLL_CTRL3) 32 R/W 0000_0002h 5.1.7.2/495
3038_0834 CCM PLL Control Register (CCM_PLL_CTRL3_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0838 CCM PLL Control Register (CCM_PLL_CTRL3_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_083C CCM PLL Control Register (CCM_PLL_CTRL3_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0840 CCM PLL Control Register (CCM_PLL_CTRL4) 32 R/W 0000_0002h 5.1.7.2/495
3038_0844 CCM PLL Control Register (CCM_PLL_CTRL4_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0848 CCM PLL Control Register (CCM_PLL_CTRL4_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_084C CCM PLL Control Register (CCM_PLL_CTRL4_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0850 CCM PLL Control Register (CCM_PLL_CTRL5) 32 R/W 0000_0002h 5.1.7.2/495
3038_0854 CCM PLL Control Register (CCM_PLL_CTRL5_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0858 CCM PLL Control Register (CCM_PLL_CTRL5_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_085C CCM PLL Control Register (CCM_PLL_CTRL5_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0860 CCM PLL Control Register (CCM_PLL_CTRL6) 32 R/W 0000_0002h 5.1.7.2/495
3038_0864 CCM PLL Control Register (CCM_PLL_CTRL6_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0868 CCM PLL Control Register (CCM_PLL_CTRL6_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_086C CCM PLL Control Register (CCM_PLL_CTRL6_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0870 CCM PLL Control Register (CCM_PLL_CTRL7) 32 R/W 0000_0002h 5.1.7.2/495
3038_0874 CCM PLL Control Register (CCM_PLL_CTRL7_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0878 CCM PLL Control Register (CCM_PLL_CTRL7_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_087C CCM PLL Control Register (CCM_PLL_CTRL7_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0880 CCM PLL Control Register (CCM_PLL_CTRL8) 32 R/W 0000_0002h 5.1.7.2/495
3038_0884 CCM PLL Control Register (CCM_PLL_CTRL8_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0888 CCM PLL Control Register (CCM_PLL_CTRL8_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_088C CCM PLL Control Register (CCM_PLL_CTRL8_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0890 CCM PLL Control Register (CCM_PLL_CTRL9) 32 R/W 0000_0002h 5.1.7.2/495
3038_0894 CCM PLL Control Register (CCM_PLL_CTRL9_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0898 CCM PLL Control Register (CCM_PLL_CTRL9_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_089C CCM PLL Control Register (CCM_PLL_CTRL9_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_08A0 CCM PLL Control Register (CCM_PLL_CTRL10) 32 R/W 0000_0002h 5.1.7.2/495
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 341
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_08A4 CCM PLL Control Register (CCM_PLL_CTRL10_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_08A8 CCM PLL Control Register (CCM_PLL_CTRL10_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_08AC CCM PLL Control Register (CCM_PLL_CTRL10_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_08B0 CCM PLL Control Register (CCM_PLL_CTRL11) 32 R/W 0000_0002h 5.1.7.2/495
3038_08B4 CCM PLL Control Register (CCM_PLL_CTRL11_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_08B8 CCM PLL Control Register (CCM_PLL_CTRL11_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_08BC CCM PLL Control Register (CCM_PLL_CTRL11_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_08C0 CCM PLL Control Register (CCM_PLL_CTRL12) 32 R/W 0000_0002h 5.1.7.2/495
3038_08C4 CCM PLL Control Register (CCM_PLL_CTRL12_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_08C8 CCM PLL Control Register (CCM_PLL_CTRL12_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_08CC CCM PLL Control Register (CCM_PLL_CTRL12_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_08D0 CCM PLL Control Register (CCM_PLL_CTRL13) 32 R/W 0000_0002h 5.1.7.2/495
3038_08D4 CCM PLL Control Register (CCM_PLL_CTRL13_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_08D8 CCM PLL Control Register (CCM_PLL_CTRL13_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_08DC CCM PLL Control Register (CCM_PLL_CTRL13_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_08E0 CCM PLL Control Register (CCM_PLL_CTRL14) 32 R/W 0000_0002h 5.1.7.2/495
3038_08E4 CCM PLL Control Register (CCM_PLL_CTRL14_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_08E8 CCM PLL Control Register (CCM_PLL_CTRL14_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_08EC CCM PLL Control Register (CCM_PLL_CTRL14_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_08F0 CCM PLL Control Register (CCM_PLL_CTRL15) 32 R/W 0000_0002h 5.1.7.2/495
3038_08F4 CCM PLL Control Register (CCM_PLL_CTRL15_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_08F8 CCM PLL Control Register (CCM_PLL_CTRL15_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_08FC CCM PLL Control Register (CCM_PLL_CTRL15_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0900 CCM PLL Control Register (CCM_PLL_CTRL16) 32 R/W 0000_0002h 5.1.7.2/495
3038_0904 CCM PLL Control Register (CCM_PLL_CTRL16_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0908 CCM PLL Control Register (CCM_PLL_CTRL16_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_090C CCM PLL Control Register (CCM_PLL_CTRL16_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0910 CCM PLL Control Register (CCM_PLL_CTRL17) 32 R/W 0000_0002h 5.1.7.2/495
3038_0914 CCM PLL Control Register (CCM_PLL_CTRL17_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0918 CCM PLL Control Register (CCM_PLL_CTRL17_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_091C CCM PLL Control Register (CCM_PLL_CTRL17_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0920 CCM PLL Control Register (CCM_PLL_CTRL18) 32 R/W 0000_0002h 5.1.7.2/495
3038_0924 CCM PLL Control Register (CCM_PLL_CTRL18_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0928 CCM PLL Control Register (CCM_PLL_CTRL18_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_092C CCM PLL Control Register (CCM_PLL_CTRL18_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0930 CCM PLL Control Register (CCM_PLL_CTRL19) 32 R/W 0000_0002h 5.1.7.2/495
3038_0934 CCM PLL Control Register (CCM_PLL_CTRL19_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0938 CCM PLL Control Register (CCM_PLL_CTRL19_CLR) 32 R/W 0000_0002h 5.1.7.4/499
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

342 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_093C CCM PLL Control Register (CCM_PLL_CTRL19_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0940 CCM PLL Control Register (CCM_PLL_CTRL20) 32 R/W 0000_0002h 5.1.7.2/495
3038_0944 CCM PLL Control Register (CCM_PLL_CTRL20_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0948 CCM PLL Control Register (CCM_PLL_CTRL20_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_094C CCM PLL Control Register (CCM_PLL_CTRL20_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0950 CCM PLL Control Register (CCM_PLL_CTRL21) 32 R/W 0000_0002h 5.1.7.2/495
3038_0954 CCM PLL Control Register (CCM_PLL_CTRL21_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0958 CCM PLL Control Register (CCM_PLL_CTRL21_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_095C CCM PLL Control Register (CCM_PLL_CTRL21_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0960 CCM PLL Control Register (CCM_PLL_CTRL22) 32 R/W 0000_0002h 5.1.7.2/495
3038_0964 CCM PLL Control Register (CCM_PLL_CTRL22_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0968 CCM PLL Control Register (CCM_PLL_CTRL22_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_096C CCM PLL Control Register (CCM_PLL_CTRL22_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0970 CCM PLL Control Register (CCM_PLL_CTRL23) 32 R/W 0000_0002h 5.1.7.2/495
3038_0974 CCM PLL Control Register (CCM_PLL_CTRL23_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0978 CCM PLL Control Register (CCM_PLL_CTRL23_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_097C CCM PLL Control Register (CCM_PLL_CTRL23_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0980 CCM PLL Control Register (CCM_PLL_CTRL24) 32 R/W 0000_0002h 5.1.7.2/495
3038_0984 CCM PLL Control Register (CCM_PLL_CTRL24_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0988 CCM PLL Control Register (CCM_PLL_CTRL24_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_098C CCM PLL Control Register (CCM_PLL_CTRL24_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0990 CCM PLL Control Register (CCM_PLL_CTRL25) 32 R/W 0000_0002h 5.1.7.2/495
3038_0994 CCM PLL Control Register (CCM_PLL_CTRL25_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0998 CCM PLL Control Register (CCM_PLL_CTRL25_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_099C CCM PLL Control Register (CCM_PLL_CTRL25_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_09A0 CCM PLL Control Register (CCM_PLL_CTRL26) 32 R/W 0000_0002h 5.1.7.2/495
3038_09A4 CCM PLL Control Register (CCM_PLL_CTRL26_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_09A8 CCM PLL Control Register (CCM_PLL_CTRL26_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_09AC CCM PLL Control Register (CCM_PLL_CTRL26_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_09B0 CCM PLL Control Register (CCM_PLL_CTRL27) 32 R/W 0000_0002h 5.1.7.2/495
3038_09B4 CCM PLL Control Register (CCM_PLL_CTRL27_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_09B8 CCM PLL Control Register (CCM_PLL_CTRL27_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_09BC CCM PLL Control Register (CCM_PLL_CTRL27_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_09C0 CCM PLL Control Register (CCM_PLL_CTRL28) 32 R/W 0000_0002h 5.1.7.2/495
3038_09C4 CCM PLL Control Register (CCM_PLL_CTRL28_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_09C8 CCM PLL Control Register (CCM_PLL_CTRL28_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_09CC CCM PLL Control Register (CCM_PLL_CTRL28_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_09D0 CCM PLL Control Register (CCM_PLL_CTRL29) 32 R/W 0000_0002h 5.1.7.2/495
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 343
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_09D4 CCM PLL Control Register (CCM_PLL_CTRL29_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_09D8 CCM PLL Control Register (CCM_PLL_CTRL29_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_09DC CCM PLL Control Register (CCM_PLL_CTRL29_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_09E0 CCM PLL Control Register (CCM_PLL_CTRL30) 32 R/W 0000_0002h 5.1.7.2/495
3038_09E4 CCM PLL Control Register (CCM_PLL_CTRL30_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_09E8 CCM PLL Control Register (CCM_PLL_CTRL30_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_09EC CCM PLL Control Register (CCM_PLL_CTRL30_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_09F0 CCM PLL Control Register (CCM_PLL_CTRL31) 32 R/W 0000_0002h 5.1.7.2/495
3038_09F4 CCM PLL Control Register (CCM_PLL_CTRL31_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_09F8 CCM PLL Control Register (CCM_PLL_CTRL31_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_09FC CCM PLL Control Register (CCM_PLL_CTRL31_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0A00 CCM PLL Control Register (CCM_PLL_CTRL32) 32 R/W 0000_0002h 5.1.7.2/495
3038_0A04 CCM PLL Control Register (CCM_PLL_CTRL32_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0A08 CCM PLL Control Register (CCM_PLL_CTRL32_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_0A0C CCM PLL Control Register (CCM_PLL_CTRL32_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0A10 CCM PLL Control Register (CCM_PLL_CTRL33) 32 R/W 0000_0002h 5.1.7.2/495
3038_0A14 CCM PLL Control Register (CCM_PLL_CTRL33_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0A18 CCM PLL Control Register (CCM_PLL_CTRL33_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_0A1C CCM PLL Control Register (CCM_PLL_CTRL33_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0A20 CCM PLL Control Register (CCM_PLL_CTRL34) 32 R/W 0000_0002h 5.1.7.2/495
3038_0A24 CCM PLL Control Register (CCM_PLL_CTRL34_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0A28 CCM PLL Control Register (CCM_PLL_CTRL34_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_0A2C CCM PLL Control Register (CCM_PLL_CTRL34_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0A30 CCM PLL Control Register (CCM_PLL_CTRL35) 32 R/W 0000_0002h 5.1.7.2/495
3038_0A34 CCM PLL Control Register (CCM_PLL_CTRL35_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0A38 CCM PLL Control Register (CCM_PLL_CTRL35_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_0A3C CCM PLL Control Register (CCM_PLL_CTRL35_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0A40 CCM PLL Control Register (CCM_PLL_CTRL36) 32 R/W 0000_0002h 5.1.7.2/495
3038_0A44 CCM PLL Control Register (CCM_PLL_CTRL36_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0A48 CCM PLL Control Register (CCM_PLL_CTRL36_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_0A4C CCM PLL Control Register (CCM_PLL_CTRL36_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0A50 CCM PLL Control Register (CCM_PLL_CTRL37) 32 R/W 0000_0002h 5.1.7.2/495
3038_0A54 CCM PLL Control Register (CCM_PLL_CTRL37_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0A58 CCM PLL Control Register (CCM_PLL_CTRL37_CLR) 32 R/W 0000_0002h 5.1.7.4/499
3038_0A5C CCM PLL Control Register (CCM_PLL_CTRL37_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_0A60 CCM PLL Control Register (CCM_PLL_CTRL38) 32 R/W 0000_0002h 5.1.7.2/495
3038_0A64 CCM PLL Control Register (CCM_PLL_CTRL38_SET) 32 R/W 0000_0002h 5.1.7.3/497
3038_0A68 CCM PLL Control Register (CCM_PLL_CTRL38_CLR) 32 R/W 0000_0002h 5.1.7.4/499
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

344 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_0A6C CCM PLL Control Register (CCM_PLL_CTRL38_TOG) 32 R/W 0000_0002h 5.1.7.5/501
3038_4000 CCM Clock Gating Register (CCM_CCGR0) 32 R/W 0000_0002h 5.1.7.6/502
3038_4004 CCM Clock Gating Register (CCM_CCGR0_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4008 CCM Clock Gating Register (CCM_CCGR0_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_400C CCM Clock Gating Register (CCM_CCGR0_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4010 CCM Clock Gating Register (CCM_CCGR1) 32 R/W 0000_0002h 5.1.7.6/502
3038_4014 CCM Clock Gating Register (CCM_CCGR1_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4018 CCM Clock Gating Register (CCM_CCGR1_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_401C CCM Clock Gating Register (CCM_CCGR1_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4020 CCM Clock Gating Register (CCM_CCGR2) 32 R/W 0000_0002h 5.1.7.6/502
3038_4024 CCM Clock Gating Register (CCM_CCGR2_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4028 CCM Clock Gating Register (CCM_CCGR2_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_402C CCM Clock Gating Register (CCM_CCGR2_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4030 CCM Clock Gating Register (CCM_CCGR3) 32 R/W 0000_0002h 5.1.7.6/502
3038_4034 CCM Clock Gating Register (CCM_CCGR3_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4038 CCM Clock Gating Register (CCM_CCGR3_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_403C CCM Clock Gating Register (CCM_CCGR3_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4040 CCM Clock Gating Register (CCM_CCGR4) 32 R/W 0000_0002h 5.1.7.6/502
3038_4044 CCM Clock Gating Register (CCM_CCGR4_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4048 CCM Clock Gating Register (CCM_CCGR4_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_404C CCM Clock Gating Register (CCM_CCGR4_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4050 CCM Clock Gating Register (CCM_CCGR5) 32 R/W 0000_0002h 5.1.7.6/502
3038_4054 CCM Clock Gating Register (CCM_CCGR5_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4058 CCM Clock Gating Register (CCM_CCGR5_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_405C CCM Clock Gating Register (CCM_CCGR5_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4060 CCM Clock Gating Register (CCM_CCGR6) 32 R/W 0000_0002h 5.1.7.6/502
3038_4064 CCM Clock Gating Register (CCM_CCGR6_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4068 CCM Clock Gating Register (CCM_CCGR6_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_406C CCM Clock Gating Register (CCM_CCGR6_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4070 CCM Clock Gating Register (CCM_CCGR7) 32 R/W 0000_0002h 5.1.7.6/502
3038_4074 CCM Clock Gating Register (CCM_CCGR7_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4078 CCM Clock Gating Register (CCM_CCGR7_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_407C CCM Clock Gating Register (CCM_CCGR7_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4080 CCM Clock Gating Register (CCM_CCGR8) 32 R/W 0000_0002h 5.1.7.6/502
3038_4084 CCM Clock Gating Register (CCM_CCGR8_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4088 CCM Clock Gating Register (CCM_CCGR8_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_408C CCM Clock Gating Register (CCM_CCGR8_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4090 CCM Clock Gating Register (CCM_CCGR9) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 345
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4094 CCM Clock Gating Register (CCM_CCGR9_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4098 CCM Clock Gating Register (CCM_CCGR9_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_409C CCM Clock Gating Register (CCM_CCGR9_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_40A0 CCM Clock Gating Register (CCM_CCGR10) 32 R/W 0000_0002h 5.1.7.6/502
3038_40A4 CCM Clock Gating Register (CCM_CCGR10_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_40A8 CCM Clock Gating Register (CCM_CCGR10_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_40AC CCM Clock Gating Register (CCM_CCGR10_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_40B0 CCM Clock Gating Register (CCM_CCGR11) 32 R/W 0000_0002h 5.1.7.6/502
3038_40B4 CCM Clock Gating Register (CCM_CCGR11_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_40B8 CCM Clock Gating Register (CCM_CCGR11_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_40BC CCM Clock Gating Register (CCM_CCGR11_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_40C0 CCM Clock Gating Register (CCM_CCGR12) 32 R/W 0000_0002h 5.1.7.6/502
3038_40C4 CCM Clock Gating Register (CCM_CCGR12_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_40C8 CCM Clock Gating Register (CCM_CCGR12_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_40CC CCM Clock Gating Register (CCM_CCGR12_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_40D0 CCM Clock Gating Register (CCM_CCGR13) 32 R/W 0000_0002h 5.1.7.6/502
3038_40D4 CCM Clock Gating Register (CCM_CCGR13_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_40D8 CCM Clock Gating Register (CCM_CCGR13_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_40DC CCM Clock Gating Register (CCM_CCGR13_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_40E0 CCM Clock Gating Register (CCM_CCGR14) 32 R/W 0000_0002h 5.1.7.6/502
3038_40E4 CCM Clock Gating Register (CCM_CCGR14_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_40E8 CCM Clock Gating Register (CCM_CCGR14_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_40EC CCM Clock Gating Register (CCM_CCGR14_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_40F0 CCM Clock Gating Register (CCM_CCGR15) 32 R/W 0000_0002h 5.1.7.6/502
3038_40F4 CCM Clock Gating Register (CCM_CCGR15_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_40F8 CCM Clock Gating Register (CCM_CCGR15_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_40FC CCM Clock Gating Register (CCM_CCGR15_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4100 CCM Clock Gating Register (CCM_CCGR16) 32 R/W 0000_0002h 5.1.7.6/502
3038_4104 CCM Clock Gating Register (CCM_CCGR16_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4108 CCM Clock Gating Register (CCM_CCGR16_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_410C CCM Clock Gating Register (CCM_CCGR16_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4110 CCM Clock Gating Register (CCM_CCGR17) 32 R/W 0000_0002h 5.1.7.6/502
3038_4114 CCM Clock Gating Register (CCM_CCGR17_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4118 CCM Clock Gating Register (CCM_CCGR17_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_411C CCM Clock Gating Register (CCM_CCGR17_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4120 CCM Clock Gating Register (CCM_CCGR18) 32 R/W 0000_0002h 5.1.7.6/502
3038_4124 CCM Clock Gating Register (CCM_CCGR18_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4128 CCM Clock Gating Register (CCM_CCGR18_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

346 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_412C CCM Clock Gating Register (CCM_CCGR18_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4130 CCM Clock Gating Register (CCM_CCGR19) 32 R/W 0000_0002h 5.1.7.6/502
3038_4134 CCM Clock Gating Register (CCM_CCGR19_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4138 CCM Clock Gating Register (CCM_CCGR19_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_413C CCM Clock Gating Register (CCM_CCGR19_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4140 CCM Clock Gating Register (CCM_CCGR20) 32 R/W 0000_0002h 5.1.7.6/502
3038_4144 CCM Clock Gating Register (CCM_CCGR20_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4148 CCM Clock Gating Register (CCM_CCGR20_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_414C CCM Clock Gating Register (CCM_CCGR20_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4150 CCM Clock Gating Register (CCM_CCGR21) 32 R/W 0000_0002h 5.1.7.6/502
3038_4154 CCM Clock Gating Register (CCM_CCGR21_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4158 CCM Clock Gating Register (CCM_CCGR21_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_415C CCM Clock Gating Register (CCM_CCGR21_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4160 CCM Clock Gating Register (CCM_CCGR22) 32 R/W 0000_0002h 5.1.7.6/502
3038_4164 CCM Clock Gating Register (CCM_CCGR22_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4168 CCM Clock Gating Register (CCM_CCGR22_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_416C CCM Clock Gating Register (CCM_CCGR22_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4170 CCM Clock Gating Register (CCM_CCGR23) 32 R/W 0000_0002h 5.1.7.6/502
3038_4174 CCM Clock Gating Register (CCM_CCGR23_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4178 CCM Clock Gating Register (CCM_CCGR23_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_417C CCM Clock Gating Register (CCM_CCGR23_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4180 CCM Clock Gating Register (CCM_CCGR24) 32 R/W 0000_0002h 5.1.7.6/502
3038_4184 CCM Clock Gating Register (CCM_CCGR24_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4188 CCM Clock Gating Register (CCM_CCGR24_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_418C CCM Clock Gating Register (CCM_CCGR24_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4190 CCM Clock Gating Register (CCM_CCGR25) 32 R/W 0000_0002h 5.1.7.6/502
3038_4194 CCM Clock Gating Register (CCM_CCGR25_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4198 CCM Clock Gating Register (CCM_CCGR25_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_419C CCM Clock Gating Register (CCM_CCGR25_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_41A0 CCM Clock Gating Register (CCM_CCGR26) 32 R/W 0000_0002h 5.1.7.6/502
3038_41A4 CCM Clock Gating Register (CCM_CCGR26_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_41A8 CCM Clock Gating Register (CCM_CCGR26_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_41AC CCM Clock Gating Register (CCM_CCGR26_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_41B0 CCM Clock Gating Register (CCM_CCGR27) 32 R/W 0000_0002h 5.1.7.6/502
3038_41B4 CCM Clock Gating Register (CCM_CCGR27_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_41B8 CCM Clock Gating Register (CCM_CCGR27_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_41BC CCM Clock Gating Register (CCM_CCGR27_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_41C0 CCM Clock Gating Register (CCM_CCGR28) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 347
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_41C4 CCM Clock Gating Register (CCM_CCGR28_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_41C8 CCM Clock Gating Register (CCM_CCGR28_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_41CC CCM Clock Gating Register (CCM_CCGR28_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_41D0 CCM Clock Gating Register (CCM_CCGR29) 32 R/W 0000_0002h 5.1.7.6/502
3038_41D4 CCM Clock Gating Register (CCM_CCGR29_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_41D8 CCM Clock Gating Register (CCM_CCGR29_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_41DC CCM Clock Gating Register (CCM_CCGR29_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_41E0 CCM Clock Gating Register (CCM_CCGR30) 32 R/W 0000_0002h 5.1.7.6/502
3038_41E4 CCM Clock Gating Register (CCM_CCGR30_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_41E8 CCM Clock Gating Register (CCM_CCGR30_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_41EC CCM Clock Gating Register (CCM_CCGR30_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_41F0 CCM Clock Gating Register (CCM_CCGR31) 32 R/W 0000_0002h 5.1.7.6/502
3038_41F4 CCM Clock Gating Register (CCM_CCGR31_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_41F8 CCM Clock Gating Register (CCM_CCGR31_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_41FC CCM Clock Gating Register (CCM_CCGR31_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4200 CCM Clock Gating Register (CCM_CCGR32) 32 R/W 0000_0002h 5.1.7.6/502
3038_4204 CCM Clock Gating Register (CCM_CCGR32_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4208 CCM Clock Gating Register (CCM_CCGR32_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_420C CCM Clock Gating Register (CCM_CCGR32_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4210 CCM Clock Gating Register (CCM_CCGR33) 32 R/W 0000_0002h 5.1.7.6/502
3038_4214 CCM Clock Gating Register (CCM_CCGR33_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4218 CCM Clock Gating Register (CCM_CCGR33_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_421C CCM Clock Gating Register (CCM_CCGR33_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4220 CCM Clock Gating Register (CCM_CCGR34) 32 R/W 0000_0002h 5.1.7.6/502
3038_4224 CCM Clock Gating Register (CCM_CCGR34_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4228 CCM Clock Gating Register (CCM_CCGR34_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_422C CCM Clock Gating Register (CCM_CCGR34_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4230 CCM Clock Gating Register (CCM_CCGR35) 32 R/W 0000_0002h 5.1.7.6/502
3038_4234 CCM Clock Gating Register (CCM_CCGR35_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4238 CCM Clock Gating Register (CCM_CCGR35_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_423C CCM Clock Gating Register (CCM_CCGR35_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4240 CCM Clock Gating Register (CCM_CCGR36) 32 R/W 0000_0002h 5.1.7.6/502
3038_4244 CCM Clock Gating Register (CCM_CCGR36_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4248 CCM Clock Gating Register (CCM_CCGR36_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_424C CCM Clock Gating Register (CCM_CCGR36_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4250 CCM Clock Gating Register (CCM_CCGR37) 32 R/W 0000_0002h 5.1.7.6/502
3038_4254 CCM Clock Gating Register (CCM_CCGR37_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4258 CCM Clock Gating Register (CCM_CCGR37_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

348 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_425C CCM Clock Gating Register (CCM_CCGR37_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4260 CCM Clock Gating Register (CCM_CCGR38) 32 R/W 0000_0002h 5.1.7.6/502
3038_4264 CCM Clock Gating Register (CCM_CCGR38_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4268 CCM Clock Gating Register (CCM_CCGR38_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_426C CCM Clock Gating Register (CCM_CCGR38_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4270 CCM Clock Gating Register (CCM_CCGR39) 32 R/W 0000_0002h 5.1.7.6/502
3038_4274 CCM Clock Gating Register (CCM_CCGR39_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4278 CCM Clock Gating Register (CCM_CCGR39_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_427C CCM Clock Gating Register (CCM_CCGR39_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4280 CCM Clock Gating Register (CCM_CCGR40) 32 R/W 0000_0002h 5.1.7.6/502
3038_4284 CCM Clock Gating Register (CCM_CCGR40_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4288 CCM Clock Gating Register (CCM_CCGR40_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_428C CCM Clock Gating Register (CCM_CCGR40_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4290 CCM Clock Gating Register (CCM_CCGR41) 32 R/W 0000_0002h 5.1.7.6/502
3038_4294 CCM Clock Gating Register (CCM_CCGR41_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4298 CCM Clock Gating Register (CCM_CCGR41_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_429C CCM Clock Gating Register (CCM_CCGR41_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_42A0 CCM Clock Gating Register (CCM_CCGR42) 32 R/W 0000_0002h 5.1.7.6/502
3038_42A4 CCM Clock Gating Register (CCM_CCGR42_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_42A8 CCM Clock Gating Register (CCM_CCGR42_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_42AC CCM Clock Gating Register (CCM_CCGR42_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_42B0 CCM Clock Gating Register (CCM_CCGR43) 32 R/W 0000_0002h 5.1.7.6/502
3038_42B4 CCM Clock Gating Register (CCM_CCGR43_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_42B8 CCM Clock Gating Register (CCM_CCGR43_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_42BC CCM Clock Gating Register (CCM_CCGR43_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_42C0 CCM Clock Gating Register (CCM_CCGR44) 32 R/W 0000_0002h 5.1.7.6/502
3038_42C4 CCM Clock Gating Register (CCM_CCGR44_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_42C8 CCM Clock Gating Register (CCM_CCGR44_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_42CC CCM Clock Gating Register (CCM_CCGR44_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_42D0 CCM Clock Gating Register (CCM_CCGR45) 32 R/W 0000_0002h 5.1.7.6/502
3038_42D4 CCM Clock Gating Register (CCM_CCGR45_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_42D8 CCM Clock Gating Register (CCM_CCGR45_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_42DC CCM Clock Gating Register (CCM_CCGR45_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_42E0 CCM Clock Gating Register (CCM_CCGR46) 32 R/W 0000_0002h 5.1.7.6/502
3038_42E4 CCM Clock Gating Register (CCM_CCGR46_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_42E8 CCM Clock Gating Register (CCM_CCGR46_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_42EC CCM Clock Gating Register (CCM_CCGR46_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_42F0 CCM Clock Gating Register (CCM_CCGR47) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 349
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_42F4 CCM Clock Gating Register (CCM_CCGR47_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_42F8 CCM Clock Gating Register (CCM_CCGR47_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_42FC CCM Clock Gating Register (CCM_CCGR47_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4300 CCM Clock Gating Register (CCM_CCGR48) 32 R/W 0000_0002h 5.1.7.6/502
3038_4304 CCM Clock Gating Register (CCM_CCGR48_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4308 CCM Clock Gating Register (CCM_CCGR48_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_430C CCM Clock Gating Register (CCM_CCGR48_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4310 CCM Clock Gating Register (CCM_CCGR49) 32 R/W 0000_0002h 5.1.7.6/502
3038_4314 CCM Clock Gating Register (CCM_CCGR49_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4318 CCM Clock Gating Register (CCM_CCGR49_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_431C CCM Clock Gating Register (CCM_CCGR49_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4320 CCM Clock Gating Register (CCM_CCGR50) 32 R/W 0000_0002h 5.1.7.6/502
3038_4324 CCM Clock Gating Register (CCM_CCGR50_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4328 CCM Clock Gating Register (CCM_CCGR50_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_432C CCM Clock Gating Register (CCM_CCGR50_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4330 CCM Clock Gating Register (CCM_CCGR51) 32 R/W 0000_0002h 5.1.7.6/502
3038_4334 CCM Clock Gating Register (CCM_CCGR51_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4338 CCM Clock Gating Register (CCM_CCGR51_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_433C CCM Clock Gating Register (CCM_CCGR51_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4340 CCM Clock Gating Register (CCM_CCGR52) 32 R/W 0000_0002h 5.1.7.6/502
3038_4344 CCM Clock Gating Register (CCM_CCGR52_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4348 CCM Clock Gating Register (CCM_CCGR52_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_434C CCM Clock Gating Register (CCM_CCGR52_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4350 CCM Clock Gating Register (CCM_CCGR53) 32 R/W 0000_0002h 5.1.7.6/502
3038_4354 CCM Clock Gating Register (CCM_CCGR53_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4358 CCM Clock Gating Register (CCM_CCGR53_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_435C CCM Clock Gating Register (CCM_CCGR53_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4360 CCM Clock Gating Register (CCM_CCGR54) 32 R/W 0000_0002h 5.1.7.6/502
3038_4364 CCM Clock Gating Register (CCM_CCGR54_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4368 CCM Clock Gating Register (CCM_CCGR54_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_436C CCM Clock Gating Register (CCM_CCGR54_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4370 CCM Clock Gating Register (CCM_CCGR55) 32 R/W 0000_0002h 5.1.7.6/502
3038_4374 CCM Clock Gating Register (CCM_CCGR55_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4378 CCM Clock Gating Register (CCM_CCGR55_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_437C CCM Clock Gating Register (CCM_CCGR55_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4380 CCM Clock Gating Register (CCM_CCGR56) 32 R/W 0000_0002h 5.1.7.6/502
3038_4384 CCM Clock Gating Register (CCM_CCGR56_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4388 CCM Clock Gating Register (CCM_CCGR56_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

350 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_438C CCM Clock Gating Register (CCM_CCGR56_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4390 CCM Clock Gating Register (CCM_CCGR57) 32 R/W 0000_0002h 5.1.7.6/502
3038_4394 CCM Clock Gating Register (CCM_CCGR57_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4398 CCM Clock Gating Register (CCM_CCGR57_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_439C CCM Clock Gating Register (CCM_CCGR57_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_43A0 CCM Clock Gating Register (CCM_CCGR58) 32 R/W 0000_0002h 5.1.7.6/502
3038_43A4 CCM Clock Gating Register (CCM_CCGR58_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_43A8 CCM Clock Gating Register (CCM_CCGR58_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_43AC CCM Clock Gating Register (CCM_CCGR58_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_43B0 CCM Clock Gating Register (CCM_CCGR59) 32 R/W 0000_0002h 5.1.7.6/502
3038_43B4 CCM Clock Gating Register (CCM_CCGR59_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_43B8 CCM Clock Gating Register (CCM_CCGR59_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_43BC CCM Clock Gating Register (CCM_CCGR59_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_43C0 CCM Clock Gating Register (CCM_CCGR60) 32 R/W 0000_0002h 5.1.7.6/502
3038_43C4 CCM Clock Gating Register (CCM_CCGR60_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_43C8 CCM Clock Gating Register (CCM_CCGR60_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_43CC CCM Clock Gating Register (CCM_CCGR60_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_43D0 CCM Clock Gating Register (CCM_CCGR61) 32 R/W 0000_0002h 5.1.7.6/502
3038_43D4 CCM Clock Gating Register (CCM_CCGR61_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_43D8 CCM Clock Gating Register (CCM_CCGR61_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_43DC CCM Clock Gating Register (CCM_CCGR61_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_43E0 CCM Clock Gating Register (CCM_CCGR62) 32 R/W 0000_0002h 5.1.7.6/502
3038_43E4 CCM Clock Gating Register (CCM_CCGR62_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_43E8 CCM Clock Gating Register (CCM_CCGR62_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_43EC CCM Clock Gating Register (CCM_CCGR62_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_43F0 CCM Clock Gating Register (CCM_CCGR63) 32 R/W 0000_0002h 5.1.7.6/502
3038_43F4 CCM Clock Gating Register (CCM_CCGR63_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_43F8 CCM Clock Gating Register (CCM_CCGR63_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_43FC CCM Clock Gating Register (CCM_CCGR63_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4400 CCM Clock Gating Register (CCM_CCGR64) 32 R/W 0000_0002h 5.1.7.6/502
3038_4404 CCM Clock Gating Register (CCM_CCGR64_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4408 CCM Clock Gating Register (CCM_CCGR64_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_440C CCM Clock Gating Register (CCM_CCGR64_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4410 CCM Clock Gating Register (CCM_CCGR65) 32 R/W 0000_0002h 5.1.7.6/502
3038_4414 CCM Clock Gating Register (CCM_CCGR65_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4418 CCM Clock Gating Register (CCM_CCGR65_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_441C CCM Clock Gating Register (CCM_CCGR65_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4420 CCM Clock Gating Register (CCM_CCGR66) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 351
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4424 CCM Clock Gating Register (CCM_CCGR66_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4428 CCM Clock Gating Register (CCM_CCGR66_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_442C CCM Clock Gating Register (CCM_CCGR66_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4430 CCM Clock Gating Register (CCM_CCGR67) 32 R/W 0000_0002h 5.1.7.6/502
3038_4434 CCM Clock Gating Register (CCM_CCGR67_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4438 CCM Clock Gating Register (CCM_CCGR67_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_443C CCM Clock Gating Register (CCM_CCGR67_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4440 CCM Clock Gating Register (CCM_CCGR68) 32 R/W 0000_0002h 5.1.7.6/502
3038_4444 CCM Clock Gating Register (CCM_CCGR68_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4448 CCM Clock Gating Register (CCM_CCGR68_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_444C CCM Clock Gating Register (CCM_CCGR68_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4450 CCM Clock Gating Register (CCM_CCGR69) 32 R/W 0000_0002h 5.1.7.6/502
3038_4454 CCM Clock Gating Register (CCM_CCGR69_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4458 CCM Clock Gating Register (CCM_CCGR69_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_445C CCM Clock Gating Register (CCM_CCGR69_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4460 CCM Clock Gating Register (CCM_CCGR70) 32 R/W 0000_0002h 5.1.7.6/502
3038_4464 CCM Clock Gating Register (CCM_CCGR70_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4468 CCM Clock Gating Register (CCM_CCGR70_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_446C CCM Clock Gating Register (CCM_CCGR70_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4470 CCM Clock Gating Register (CCM_CCGR71) 32 R/W 0000_0002h 5.1.7.6/502
3038_4474 CCM Clock Gating Register (CCM_CCGR71_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4478 CCM Clock Gating Register (CCM_CCGR71_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_447C CCM Clock Gating Register (CCM_CCGR71_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4480 CCM Clock Gating Register (CCM_CCGR72) 32 R/W 0000_0002h 5.1.7.6/502
3038_4484 CCM Clock Gating Register (CCM_CCGR72_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4488 CCM Clock Gating Register (CCM_CCGR72_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_448C CCM Clock Gating Register (CCM_CCGR72_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4490 CCM Clock Gating Register (CCM_CCGR73) 32 R/W 0000_0002h 5.1.7.6/502
3038_4494 CCM Clock Gating Register (CCM_CCGR73_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4498 CCM Clock Gating Register (CCM_CCGR73_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_449C CCM Clock Gating Register (CCM_CCGR73_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_44A0 CCM Clock Gating Register (CCM_CCGR74) 32 R/W 0000_0002h 5.1.7.6/502
3038_44A4 CCM Clock Gating Register (CCM_CCGR74_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_44A8 CCM Clock Gating Register (CCM_CCGR74_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_44AC CCM Clock Gating Register (CCM_CCGR74_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_44B0 CCM Clock Gating Register (CCM_CCGR75) 32 R/W 0000_0002h 5.1.7.6/502
3038_44B4 CCM Clock Gating Register (CCM_CCGR75_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_44B8 CCM Clock Gating Register (CCM_CCGR75_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

352 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_44BC CCM Clock Gating Register (CCM_CCGR75_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_44C0 CCM Clock Gating Register (CCM_CCGR76) 32 R/W 0000_0002h 5.1.7.6/502
3038_44C4 CCM Clock Gating Register (CCM_CCGR76_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_44C8 CCM Clock Gating Register (CCM_CCGR76_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_44CC CCM Clock Gating Register (CCM_CCGR76_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_44D0 CCM Clock Gating Register (CCM_CCGR77) 32 R/W 0000_0002h 5.1.7.6/502
3038_44D4 CCM Clock Gating Register (CCM_CCGR77_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_44D8 CCM Clock Gating Register (CCM_CCGR77_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_44DC CCM Clock Gating Register (CCM_CCGR77_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_44E0 CCM Clock Gating Register (CCM_CCGR78) 32 R/W 0000_0002h 5.1.7.6/502
3038_44E4 CCM Clock Gating Register (CCM_CCGR78_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_44E8 CCM Clock Gating Register (CCM_CCGR78_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_44EC CCM Clock Gating Register (CCM_CCGR78_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_44F0 CCM Clock Gating Register (CCM_CCGR79) 32 R/W 0000_0002h 5.1.7.6/502
3038_44F4 CCM Clock Gating Register (CCM_CCGR79_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_44F8 CCM Clock Gating Register (CCM_CCGR79_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_44FC CCM Clock Gating Register (CCM_CCGR79_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4500 CCM Clock Gating Register (CCM_CCGR80) 32 R/W 0000_0002h 5.1.7.6/502
3038_4504 CCM Clock Gating Register (CCM_CCGR80_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4508 CCM Clock Gating Register (CCM_CCGR80_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_450C CCM Clock Gating Register (CCM_CCGR80_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4510 CCM Clock Gating Register (CCM_CCGR81) 32 R/W 0000_0002h 5.1.7.6/502
3038_4514 CCM Clock Gating Register (CCM_CCGR81_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4518 CCM Clock Gating Register (CCM_CCGR81_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_451C CCM Clock Gating Register (CCM_CCGR81_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4520 CCM Clock Gating Register (CCM_CCGR82) 32 R/W 0000_0002h 5.1.7.6/502
3038_4524 CCM Clock Gating Register (CCM_CCGR82_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4528 CCM Clock Gating Register (CCM_CCGR82_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_452C CCM Clock Gating Register (CCM_CCGR82_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4530 CCM Clock Gating Register (CCM_CCGR83) 32 R/W 0000_0002h 5.1.7.6/502
3038_4534 CCM Clock Gating Register (CCM_CCGR83_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4538 CCM Clock Gating Register (CCM_CCGR83_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_453C CCM Clock Gating Register (CCM_CCGR83_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4540 CCM Clock Gating Register (CCM_CCGR84) 32 R/W 0000_0002h 5.1.7.6/502
3038_4544 CCM Clock Gating Register (CCM_CCGR84_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4548 CCM Clock Gating Register (CCM_CCGR84_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_454C CCM Clock Gating Register (CCM_CCGR84_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4550 CCM Clock Gating Register (CCM_CCGR85) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 353
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4554 CCM Clock Gating Register (CCM_CCGR85_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4558 CCM Clock Gating Register (CCM_CCGR85_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_455C CCM Clock Gating Register (CCM_CCGR85_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4560 CCM Clock Gating Register (CCM_CCGR86) 32 R/W 0000_0002h 5.1.7.6/502
3038_4564 CCM Clock Gating Register (CCM_CCGR86_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4568 CCM Clock Gating Register (CCM_CCGR86_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_456C CCM Clock Gating Register (CCM_CCGR86_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4570 CCM Clock Gating Register (CCM_CCGR87) 32 R/W 0000_0002h 5.1.7.6/502
3038_4574 CCM Clock Gating Register (CCM_CCGR87_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4578 CCM Clock Gating Register (CCM_CCGR87_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_457C CCM Clock Gating Register (CCM_CCGR87_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4580 CCM Clock Gating Register (CCM_CCGR88) 32 R/W 0000_0002h 5.1.7.6/502
3038_4584 CCM Clock Gating Register (CCM_CCGR88_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4588 CCM Clock Gating Register (CCM_CCGR88_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_458C CCM Clock Gating Register (CCM_CCGR88_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4590 CCM Clock Gating Register (CCM_CCGR89) 32 R/W 0000_0002h 5.1.7.6/502
3038_4594 CCM Clock Gating Register (CCM_CCGR89_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4598 CCM Clock Gating Register (CCM_CCGR89_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_459C CCM Clock Gating Register (CCM_CCGR89_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_45A0 CCM Clock Gating Register (CCM_CCGR90) 32 R/W 0000_0002h 5.1.7.6/502
3038_45A4 CCM Clock Gating Register (CCM_CCGR90_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_45A8 CCM Clock Gating Register (CCM_CCGR90_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_45AC CCM Clock Gating Register (CCM_CCGR90_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_45B0 CCM Clock Gating Register (CCM_CCGR91) 32 R/W 0000_0002h 5.1.7.6/502
3038_45B4 CCM Clock Gating Register (CCM_CCGR91_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_45B8 CCM Clock Gating Register (CCM_CCGR91_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_45BC CCM Clock Gating Register (CCM_CCGR91_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_45C0 CCM Clock Gating Register (CCM_CCGR92) 32 R/W 0000_0002h 5.1.7.6/502
3038_45C4 CCM Clock Gating Register (CCM_CCGR92_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_45C8 CCM Clock Gating Register (CCM_CCGR92_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_45CC CCM Clock Gating Register (CCM_CCGR92_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_45D0 CCM Clock Gating Register (CCM_CCGR93) 32 R/W 0000_0002h 5.1.7.6/502
3038_45D4 CCM Clock Gating Register (CCM_CCGR93_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_45D8 CCM Clock Gating Register (CCM_CCGR93_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_45DC CCM Clock Gating Register (CCM_CCGR93_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_45E0 CCM Clock Gating Register (CCM_CCGR94) 32 R/W 0000_0002h 5.1.7.6/502
3038_45E4 CCM Clock Gating Register (CCM_CCGR94_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_45E8 CCM Clock Gating Register (CCM_CCGR94_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

354 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_45EC CCM Clock Gating Register (CCM_CCGR94_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_45F0 CCM Clock Gating Register (CCM_CCGR95) 32 R/W 0000_0002h 5.1.7.6/502
3038_45F4 CCM Clock Gating Register (CCM_CCGR95_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_45F8 CCM Clock Gating Register (CCM_CCGR95_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_45FC CCM Clock Gating Register (CCM_CCGR95_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4600 CCM Clock Gating Register (CCM_CCGR96) 32 R/W 0000_0002h 5.1.7.6/502
3038_4604 CCM Clock Gating Register (CCM_CCGR96_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4608 CCM Clock Gating Register (CCM_CCGR96_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_460C CCM Clock Gating Register (CCM_CCGR96_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4610 CCM Clock Gating Register (CCM_CCGR97) 32 R/W 0000_0002h 5.1.7.6/502
3038_4614 CCM Clock Gating Register (CCM_CCGR97_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4618 CCM Clock Gating Register (CCM_CCGR97_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_461C CCM Clock Gating Register (CCM_CCGR97_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4620 CCM Clock Gating Register (CCM_CCGR98) 32 R/W 0000_0002h 5.1.7.6/502
3038_4624 CCM Clock Gating Register (CCM_CCGR98_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4628 CCM Clock Gating Register (CCM_CCGR98_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_462C CCM Clock Gating Register (CCM_CCGR98_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4630 CCM Clock Gating Register (CCM_CCGR99) 32 R/W 0000_0002h 5.1.7.6/502
3038_4634 CCM Clock Gating Register (CCM_CCGR99_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4638 CCM Clock Gating Register (CCM_CCGR99_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_463C CCM Clock Gating Register (CCM_CCGR99_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4640 CCM Clock Gating Register (CCM_CCGR100) 32 R/W 0000_0002h 5.1.7.6/502
3038_4644 CCM Clock Gating Register (CCM_CCGR100_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4648 CCM Clock Gating Register (CCM_CCGR100_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_464C CCM Clock Gating Register (CCM_CCGR100_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4650 CCM Clock Gating Register (CCM_CCGR101) 32 R/W 0000_0002h 5.1.7.6/502
3038_4654 CCM Clock Gating Register (CCM_CCGR101_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4658 CCM Clock Gating Register (CCM_CCGR101_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_465C CCM Clock Gating Register (CCM_CCGR101_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4660 CCM Clock Gating Register (CCM_CCGR102) 32 R/W 0000_0002h 5.1.7.6/502
3038_4664 CCM Clock Gating Register (CCM_CCGR102_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4668 CCM Clock Gating Register (CCM_CCGR102_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_466C CCM Clock Gating Register (CCM_CCGR102_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4670 CCM Clock Gating Register (CCM_CCGR103) 32 R/W 0000_0002h 5.1.7.6/502
3038_4674 CCM Clock Gating Register (CCM_CCGR103_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4678 CCM Clock Gating Register (CCM_CCGR103_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_467C CCM Clock Gating Register (CCM_CCGR103_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4680 CCM Clock Gating Register (CCM_CCGR104) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 355
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4684 CCM Clock Gating Register (CCM_CCGR104_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4688 CCM Clock Gating Register (CCM_CCGR104_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_468C CCM Clock Gating Register (CCM_CCGR104_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4690 CCM Clock Gating Register (CCM_CCGR105) 32 R/W 0000_0002h 5.1.7.6/502
3038_4694 CCM Clock Gating Register (CCM_CCGR105_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4698 CCM Clock Gating Register (CCM_CCGR105_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_469C CCM Clock Gating Register (CCM_CCGR105_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_46A0 CCM Clock Gating Register (CCM_CCGR106) 32 R/W 0000_0002h 5.1.7.6/502
3038_46A4 CCM Clock Gating Register (CCM_CCGR106_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_46A8 CCM Clock Gating Register (CCM_CCGR106_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_46AC CCM Clock Gating Register (CCM_CCGR106_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_46B0 CCM Clock Gating Register (CCM_CCGR107) 32 R/W 0000_0002h 5.1.7.6/502
3038_46B4 CCM Clock Gating Register (CCM_CCGR107_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_46B8 CCM Clock Gating Register (CCM_CCGR107_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_46BC CCM Clock Gating Register (CCM_CCGR107_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_46C0 CCM Clock Gating Register (CCM_CCGR108) 32 R/W 0000_0002h 5.1.7.6/502
3038_46C4 CCM Clock Gating Register (CCM_CCGR108_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_46C8 CCM Clock Gating Register (CCM_CCGR108_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_46CC CCM Clock Gating Register (CCM_CCGR108_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_46D0 CCM Clock Gating Register (CCM_CCGR109) 32 R/W 0000_0002h 5.1.7.6/502
3038_46D4 CCM Clock Gating Register (CCM_CCGR109_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_46D8 CCM Clock Gating Register (CCM_CCGR109_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_46DC CCM Clock Gating Register (CCM_CCGR109_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_46E0 CCM Clock Gating Register (CCM_CCGR110) 32 R/W 0000_0002h 5.1.7.6/502
3038_46E4 CCM Clock Gating Register (CCM_CCGR110_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_46E8 CCM Clock Gating Register (CCM_CCGR110_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_46EC CCM Clock Gating Register (CCM_CCGR110_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_46F0 CCM Clock Gating Register (CCM_CCGR111) 32 R/W 0000_0002h 5.1.7.6/502
3038_46F4 CCM Clock Gating Register (CCM_CCGR111_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_46F8 CCM Clock Gating Register (CCM_CCGR111_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_46FC CCM Clock Gating Register (CCM_CCGR111_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4700 CCM Clock Gating Register (CCM_CCGR112) 32 R/W 0000_0002h 5.1.7.6/502
3038_4704 CCM Clock Gating Register (CCM_CCGR112_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4708 CCM Clock Gating Register (CCM_CCGR112_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_470C CCM Clock Gating Register (CCM_CCGR112_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4710 CCM Clock Gating Register (CCM_CCGR113) 32 R/W 0000_0002h 5.1.7.6/502
3038_4714 CCM Clock Gating Register (CCM_CCGR113_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4718 CCM Clock Gating Register (CCM_CCGR113_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

356 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_471C CCM Clock Gating Register (CCM_CCGR113_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4720 CCM Clock Gating Register (CCM_CCGR114) 32 R/W 0000_0002h 5.1.7.6/502
3038_4724 CCM Clock Gating Register (CCM_CCGR114_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4728 CCM Clock Gating Register (CCM_CCGR114_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_472C CCM Clock Gating Register (CCM_CCGR114_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4730 CCM Clock Gating Register (CCM_CCGR115) 32 R/W 0000_0002h 5.1.7.6/502
3038_4734 CCM Clock Gating Register (CCM_CCGR115_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4738 CCM Clock Gating Register (CCM_CCGR115_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_473C CCM Clock Gating Register (CCM_CCGR115_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4740 CCM Clock Gating Register (CCM_CCGR116) 32 R/W 0000_0002h 5.1.7.6/502
3038_4744 CCM Clock Gating Register (CCM_CCGR116_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4748 CCM Clock Gating Register (CCM_CCGR116_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_474C CCM Clock Gating Register (CCM_CCGR116_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4750 CCM Clock Gating Register (CCM_CCGR117) 32 R/W 0000_0002h 5.1.7.6/502
3038_4754 CCM Clock Gating Register (CCM_CCGR117_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4758 CCM Clock Gating Register (CCM_CCGR117_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_475C CCM Clock Gating Register (CCM_CCGR117_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4760 CCM Clock Gating Register (CCM_CCGR118) 32 R/W 0000_0002h 5.1.7.6/502
3038_4764 CCM Clock Gating Register (CCM_CCGR118_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4768 CCM Clock Gating Register (CCM_CCGR118_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_476C CCM Clock Gating Register (CCM_CCGR118_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4770 CCM Clock Gating Register (CCM_CCGR119) 32 R/W 0000_0002h 5.1.7.6/502
3038_4774 CCM Clock Gating Register (CCM_CCGR119_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4778 CCM Clock Gating Register (CCM_CCGR119_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_477C CCM Clock Gating Register (CCM_CCGR119_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4780 CCM Clock Gating Register (CCM_CCGR120) 32 R/W 0000_0002h 5.1.7.6/502
3038_4784 CCM Clock Gating Register (CCM_CCGR120_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4788 CCM Clock Gating Register (CCM_CCGR120_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_478C CCM Clock Gating Register (CCM_CCGR120_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4790 CCM Clock Gating Register (CCM_CCGR121) 32 R/W 0000_0002h 5.1.7.6/502
3038_4794 CCM Clock Gating Register (CCM_CCGR121_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4798 CCM Clock Gating Register (CCM_CCGR121_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_479C CCM Clock Gating Register (CCM_CCGR121_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_47A0 CCM Clock Gating Register (CCM_CCGR122) 32 R/W 0000_0002h 5.1.7.6/502
3038_47A4 CCM Clock Gating Register (CCM_CCGR122_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_47A8 CCM Clock Gating Register (CCM_CCGR122_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_47AC CCM Clock Gating Register (CCM_CCGR122_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_47B0 CCM Clock Gating Register (CCM_CCGR123) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 357
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_47B4 CCM Clock Gating Register (CCM_CCGR123_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_47B8 CCM Clock Gating Register (CCM_CCGR123_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_47BC CCM Clock Gating Register (CCM_CCGR123_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_47C0 CCM Clock Gating Register (CCM_CCGR124) 32 R/W 0000_0002h 5.1.7.6/502
3038_47C4 CCM Clock Gating Register (CCM_CCGR124_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_47C8 CCM Clock Gating Register (CCM_CCGR124_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_47CC CCM Clock Gating Register (CCM_CCGR124_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_47D0 CCM Clock Gating Register (CCM_CCGR125) 32 R/W 0000_0002h 5.1.7.6/502
3038_47D4 CCM Clock Gating Register (CCM_CCGR125_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_47D8 CCM Clock Gating Register (CCM_CCGR125_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_47DC CCM Clock Gating Register (CCM_CCGR125_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_47E0 CCM Clock Gating Register (CCM_CCGR126) 32 R/W 0000_0002h 5.1.7.6/502
3038_47E4 CCM Clock Gating Register (CCM_CCGR126_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_47E8 CCM Clock Gating Register (CCM_CCGR126_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_47EC CCM Clock Gating Register (CCM_CCGR126_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_47F0 CCM Clock Gating Register (CCM_CCGR127) 32 R/W 0000_0002h 5.1.7.6/502
3038_47F4 CCM Clock Gating Register (CCM_CCGR127_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_47F8 CCM Clock Gating Register (CCM_CCGR127_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_47FC CCM Clock Gating Register (CCM_CCGR127_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4800 CCM Clock Gating Register (CCM_CCGR128) 32 R/W 0000_0002h 5.1.7.6/502
3038_4804 CCM Clock Gating Register (CCM_CCGR128_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4808 CCM Clock Gating Register (CCM_CCGR128_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_480C CCM Clock Gating Register (CCM_CCGR128_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4810 CCM Clock Gating Register (CCM_CCGR129) 32 R/W 0000_0002h 5.1.7.6/502
3038_4814 CCM Clock Gating Register (CCM_CCGR129_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4818 CCM Clock Gating Register (CCM_CCGR129_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_481C CCM Clock Gating Register (CCM_CCGR129_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4820 CCM Clock Gating Register (CCM_CCGR130) 32 R/W 0000_0002h 5.1.7.6/502
3038_4824 CCM Clock Gating Register (CCM_CCGR130_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4828 CCM Clock Gating Register (CCM_CCGR130_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_482C CCM Clock Gating Register (CCM_CCGR130_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4830 CCM Clock Gating Register (CCM_CCGR131) 32 R/W 0000_0002h 5.1.7.6/502
3038_4834 CCM Clock Gating Register (CCM_CCGR131_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4838 CCM Clock Gating Register (CCM_CCGR131_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_483C CCM Clock Gating Register (CCM_CCGR131_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4840 CCM Clock Gating Register (CCM_CCGR132) 32 R/W 0000_0002h 5.1.7.6/502
3038_4844 CCM Clock Gating Register (CCM_CCGR132_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4848 CCM Clock Gating Register (CCM_CCGR132_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

358 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_484C CCM Clock Gating Register (CCM_CCGR132_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4850 CCM Clock Gating Register (CCM_CCGR133) 32 R/W 0000_0002h 5.1.7.6/502
3038_4854 CCM Clock Gating Register (CCM_CCGR133_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4858 CCM Clock Gating Register (CCM_CCGR133_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_485C CCM Clock Gating Register (CCM_CCGR133_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4860 CCM Clock Gating Register (CCM_CCGR134) 32 R/W 0000_0002h 5.1.7.6/502
3038_4864 CCM Clock Gating Register (CCM_CCGR134_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4868 CCM Clock Gating Register (CCM_CCGR134_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_486C CCM Clock Gating Register (CCM_CCGR134_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4870 CCM Clock Gating Register (CCM_CCGR135) 32 R/W 0000_0002h 5.1.7.6/502
3038_4874 CCM Clock Gating Register (CCM_CCGR135_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4878 CCM Clock Gating Register (CCM_CCGR135_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_487C CCM Clock Gating Register (CCM_CCGR135_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4880 CCM Clock Gating Register (CCM_CCGR136) 32 R/W 0000_0002h 5.1.7.6/502
3038_4884 CCM Clock Gating Register (CCM_CCGR136_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4888 CCM Clock Gating Register (CCM_CCGR136_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_488C CCM Clock Gating Register (CCM_CCGR136_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4890 CCM Clock Gating Register (CCM_CCGR137) 32 R/W 0000_0002h 5.1.7.6/502
3038_4894 CCM Clock Gating Register (CCM_CCGR137_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4898 CCM Clock Gating Register (CCM_CCGR137_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_489C CCM Clock Gating Register (CCM_CCGR137_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_48A0 CCM Clock Gating Register (CCM_CCGR138) 32 R/W 0000_0002h 5.1.7.6/502
3038_48A4 CCM Clock Gating Register (CCM_CCGR138_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_48A8 CCM Clock Gating Register (CCM_CCGR138_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_48AC CCM Clock Gating Register (CCM_CCGR138_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_48B0 CCM Clock Gating Register (CCM_CCGR139) 32 R/W 0000_0002h 5.1.7.6/502
3038_48B4 CCM Clock Gating Register (CCM_CCGR139_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_48B8 CCM Clock Gating Register (CCM_CCGR139_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_48BC CCM Clock Gating Register (CCM_CCGR139_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_48C0 CCM Clock Gating Register (CCM_CCGR140) 32 R/W 0000_0002h 5.1.7.6/502
3038_48C4 CCM Clock Gating Register (CCM_CCGR140_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_48C8 CCM Clock Gating Register (CCM_CCGR140_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_48CC CCM Clock Gating Register (CCM_CCGR140_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_48D0 CCM Clock Gating Register (CCM_CCGR141) 32 R/W 0000_0002h 5.1.7.6/502
3038_48D4 CCM Clock Gating Register (CCM_CCGR141_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_48D8 CCM Clock Gating Register (CCM_CCGR141_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_48DC CCM Clock Gating Register (CCM_CCGR141_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_48E0 CCM Clock Gating Register (CCM_CCGR142) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 359
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_48E4 CCM Clock Gating Register (CCM_CCGR142_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_48E8 CCM Clock Gating Register (CCM_CCGR142_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_48EC CCM Clock Gating Register (CCM_CCGR142_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_48F0 CCM Clock Gating Register (CCM_CCGR143) 32 R/W 0000_0002h 5.1.7.6/502
3038_48F4 CCM Clock Gating Register (CCM_CCGR143_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_48F8 CCM Clock Gating Register (CCM_CCGR143_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_48FC CCM Clock Gating Register (CCM_CCGR143_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4900 CCM Clock Gating Register (CCM_CCGR144) 32 R/W 0000_0002h 5.1.7.6/502
3038_4904 CCM Clock Gating Register (CCM_CCGR144_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4908 CCM Clock Gating Register (CCM_CCGR144_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_490C CCM Clock Gating Register (CCM_CCGR144_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4910 CCM Clock Gating Register (CCM_CCGR145) 32 R/W 0000_0002h 5.1.7.6/502
3038_4914 CCM Clock Gating Register (CCM_CCGR145_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4918 CCM Clock Gating Register (CCM_CCGR145_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_491C CCM Clock Gating Register (CCM_CCGR145_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4920 CCM Clock Gating Register (CCM_CCGR146) 32 R/W 0000_0002h 5.1.7.6/502
3038_4924 CCM Clock Gating Register (CCM_CCGR146_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4928 CCM Clock Gating Register (CCM_CCGR146_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_492C CCM Clock Gating Register (CCM_CCGR146_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4930 CCM Clock Gating Register (CCM_CCGR147) 32 R/W 0000_0002h 5.1.7.6/502
3038_4934 CCM Clock Gating Register (CCM_CCGR147_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4938 CCM Clock Gating Register (CCM_CCGR147_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_493C CCM Clock Gating Register (CCM_CCGR147_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4940 CCM Clock Gating Register (CCM_CCGR148) 32 R/W 0000_0002h 5.1.7.6/502
3038_4944 CCM Clock Gating Register (CCM_CCGR148_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4948 CCM Clock Gating Register (CCM_CCGR148_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_494C CCM Clock Gating Register (CCM_CCGR148_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4950 CCM Clock Gating Register (CCM_CCGR149) 32 R/W 0000_0002h 5.1.7.6/502
3038_4954 CCM Clock Gating Register (CCM_CCGR149_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4958 CCM Clock Gating Register (CCM_CCGR149_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_495C CCM Clock Gating Register (CCM_CCGR149_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4960 CCM Clock Gating Register (CCM_CCGR150) 32 R/W 0000_0002h 5.1.7.6/502
3038_4964 CCM Clock Gating Register (CCM_CCGR150_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4968 CCM Clock Gating Register (CCM_CCGR150_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_496C CCM Clock Gating Register (CCM_CCGR150_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4970 CCM Clock Gating Register (CCM_CCGR151) 32 R/W 0000_0002h 5.1.7.6/502
3038_4974 CCM Clock Gating Register (CCM_CCGR151_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4978 CCM Clock Gating Register (CCM_CCGR151_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

360 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_497C CCM Clock Gating Register (CCM_CCGR151_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4980 CCM Clock Gating Register (CCM_CCGR152) 32 R/W 0000_0002h 5.1.7.6/502
3038_4984 CCM Clock Gating Register (CCM_CCGR152_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4988 CCM Clock Gating Register (CCM_CCGR152_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_498C CCM Clock Gating Register (CCM_CCGR152_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4990 CCM Clock Gating Register (CCM_CCGR153) 32 R/W 0000_0002h 5.1.7.6/502
3038_4994 CCM Clock Gating Register (CCM_CCGR153_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4998 CCM Clock Gating Register (CCM_CCGR153_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_499C CCM Clock Gating Register (CCM_CCGR153_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_49A0 CCM Clock Gating Register (CCM_CCGR154) 32 R/W 0000_0002h 5.1.7.6/502
3038_49A4 CCM Clock Gating Register (CCM_CCGR154_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_49A8 CCM Clock Gating Register (CCM_CCGR154_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_49AC CCM Clock Gating Register (CCM_CCGR154_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_49B0 CCM Clock Gating Register (CCM_CCGR155) 32 R/W 0000_0002h 5.1.7.6/502
3038_49B4 CCM Clock Gating Register (CCM_CCGR155_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_49B8 CCM Clock Gating Register (CCM_CCGR155_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_49BC CCM Clock Gating Register (CCM_CCGR155_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_49C0 CCM Clock Gating Register (CCM_CCGR156) 32 R/W 0000_0002h 5.1.7.6/502
3038_49C4 CCM Clock Gating Register (CCM_CCGR156_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_49C8 CCM Clock Gating Register (CCM_CCGR156_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_49CC CCM Clock Gating Register (CCM_CCGR156_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_49D0 CCM Clock Gating Register (CCM_CCGR157) 32 R/W 0000_0002h 5.1.7.6/502
3038_49D4 CCM Clock Gating Register (CCM_CCGR157_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_49D8 CCM Clock Gating Register (CCM_CCGR157_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_49DC CCM Clock Gating Register (CCM_CCGR157_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_49E0 CCM Clock Gating Register (CCM_CCGR158) 32 R/W 0000_0002h 5.1.7.6/502
3038_49E4 CCM Clock Gating Register (CCM_CCGR158_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_49E8 CCM Clock Gating Register (CCM_CCGR158_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_49EC CCM Clock Gating Register (CCM_CCGR158_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_49F0 CCM Clock Gating Register (CCM_CCGR159) 32 R/W 0000_0002h 5.1.7.6/502
3038_49F4 CCM Clock Gating Register (CCM_CCGR159_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_49F8 CCM Clock Gating Register (CCM_CCGR159_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_49FC CCM Clock Gating Register (CCM_CCGR159_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A00 CCM Clock Gating Register (CCM_CCGR160) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A04 CCM Clock Gating Register (CCM_CCGR160_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A08 CCM Clock Gating Register (CCM_CCGR160_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A0C CCM Clock Gating Register (CCM_CCGR160_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A10 CCM Clock Gating Register (CCM_CCGR161) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 361
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4A14 CCM Clock Gating Register (CCM_CCGR161_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A18 CCM Clock Gating Register (CCM_CCGR161_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A1C CCM Clock Gating Register (CCM_CCGR161_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A20 CCM Clock Gating Register (CCM_CCGR162) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A24 CCM Clock Gating Register (CCM_CCGR162_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A28 CCM Clock Gating Register (CCM_CCGR162_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A2C CCM Clock Gating Register (CCM_CCGR162_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A30 CCM Clock Gating Register (CCM_CCGR163) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A34 CCM Clock Gating Register (CCM_CCGR163_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A38 CCM Clock Gating Register (CCM_CCGR163_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A3C CCM Clock Gating Register (CCM_CCGR163_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A40 CCM Clock Gating Register (CCM_CCGR164) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A44 CCM Clock Gating Register (CCM_CCGR164_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A48 CCM Clock Gating Register (CCM_CCGR164_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A4C CCM Clock Gating Register (CCM_CCGR164_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A50 CCM Clock Gating Register (CCM_CCGR165) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A54 CCM Clock Gating Register (CCM_CCGR165_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A58 CCM Clock Gating Register (CCM_CCGR165_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A5C CCM Clock Gating Register (CCM_CCGR165_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A60 CCM Clock Gating Register (CCM_CCGR166) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A64 CCM Clock Gating Register (CCM_CCGR166_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A68 CCM Clock Gating Register (CCM_CCGR166_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A6C CCM Clock Gating Register (CCM_CCGR166_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A70 CCM Clock Gating Register (CCM_CCGR167) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A74 CCM Clock Gating Register (CCM_CCGR167_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A78 CCM Clock Gating Register (CCM_CCGR167_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A7C CCM Clock Gating Register (CCM_CCGR167_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A80 CCM Clock Gating Register (CCM_CCGR168) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A84 CCM Clock Gating Register (CCM_CCGR168_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A88 CCM Clock Gating Register (CCM_CCGR168_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A8C CCM Clock Gating Register (CCM_CCGR168_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4A90 CCM Clock Gating Register (CCM_CCGR169) 32 R/W 0000_0002h 5.1.7.6/502
3038_4A94 CCM Clock Gating Register (CCM_CCGR169_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4A98 CCM Clock Gating Register (CCM_CCGR169_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4A9C CCM Clock Gating Register (CCM_CCGR169_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4AA0 CCM Clock Gating Register (CCM_CCGR170) 32 R/W 0000_0002h 5.1.7.6/502
3038_4AA4 CCM Clock Gating Register (CCM_CCGR170_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4AA8 CCM Clock Gating Register (CCM_CCGR170_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

362 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4AAC CCM Clock Gating Register (CCM_CCGR170_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4AB0 CCM Clock Gating Register (CCM_CCGR171) 32 R/W 0000_0002h 5.1.7.6/502
3038_4AB4 CCM Clock Gating Register (CCM_CCGR171_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4AB8 CCM Clock Gating Register (CCM_CCGR171_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4ABC CCM Clock Gating Register (CCM_CCGR171_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4AC0 CCM Clock Gating Register (CCM_CCGR172) 32 R/W 0000_0002h 5.1.7.6/502
3038_4AC4 CCM Clock Gating Register (CCM_CCGR172_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4AC8 CCM Clock Gating Register (CCM_CCGR172_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4ACC CCM Clock Gating Register (CCM_CCGR172_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4AD0 CCM Clock Gating Register (CCM_CCGR173) 32 R/W 0000_0002h 5.1.7.6/502
3038_4AD4 CCM Clock Gating Register (CCM_CCGR173_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4AD8 CCM Clock Gating Register (CCM_CCGR173_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4ADC CCM Clock Gating Register (CCM_CCGR173_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4AE0 CCM Clock Gating Register (CCM_CCGR174) 32 R/W 0000_0002h 5.1.7.6/502
3038_4AE4 CCM Clock Gating Register (CCM_CCGR174_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4AE8 CCM Clock Gating Register (CCM_CCGR174_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4AEC CCM Clock Gating Register (CCM_CCGR174_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4AF0 CCM Clock Gating Register (CCM_CCGR175) 32 R/W 0000_0002h 5.1.7.6/502
3038_4AF4 CCM Clock Gating Register (CCM_CCGR175_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4AF8 CCM Clock Gating Register (CCM_CCGR175_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4AFC CCM Clock Gating Register (CCM_CCGR175_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B00 CCM Clock Gating Register (CCM_CCGR176) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B04 CCM Clock Gating Register (CCM_CCGR176_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B08 CCM Clock Gating Register (CCM_CCGR176_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B0C CCM Clock Gating Register (CCM_CCGR176_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B10 CCM Clock Gating Register (CCM_CCGR177) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B14 CCM Clock Gating Register (CCM_CCGR177_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B18 CCM Clock Gating Register (CCM_CCGR177_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B1C CCM Clock Gating Register (CCM_CCGR177_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B20 CCM Clock Gating Register (CCM_CCGR178) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B24 CCM Clock Gating Register (CCM_CCGR178_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B28 CCM Clock Gating Register (CCM_CCGR178_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B2C CCM Clock Gating Register (CCM_CCGR178_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B30 CCM Clock Gating Register (CCM_CCGR179) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B34 CCM Clock Gating Register (CCM_CCGR179_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B38 CCM Clock Gating Register (CCM_CCGR179_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B3C CCM Clock Gating Register (CCM_CCGR179_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B40 CCM Clock Gating Register (CCM_CCGR180) 32 R/W 0000_0002h 5.1.7.6/502
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 363
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4B44 CCM Clock Gating Register (CCM_CCGR180_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B48 CCM Clock Gating Register (CCM_CCGR180_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B4C CCM Clock Gating Register (CCM_CCGR180_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B50 CCM Clock Gating Register (CCM_CCGR181) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B54 CCM Clock Gating Register (CCM_CCGR181_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B58 CCM Clock Gating Register (CCM_CCGR181_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B5C CCM Clock Gating Register (CCM_CCGR181_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B60 CCM Clock Gating Register (CCM_CCGR182) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B64 CCM Clock Gating Register (CCM_CCGR182_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B68 CCM Clock Gating Register (CCM_CCGR182_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B6C CCM Clock Gating Register (CCM_CCGR182_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B70 CCM Clock Gating Register (CCM_CCGR183) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B74 CCM Clock Gating Register (CCM_CCGR183_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B78 CCM Clock Gating Register (CCM_CCGR183_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B7C CCM Clock Gating Register (CCM_CCGR183_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B80 CCM Clock Gating Register (CCM_CCGR184) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B84 CCM Clock Gating Register (CCM_CCGR184_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B88 CCM Clock Gating Register (CCM_CCGR184_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B8C CCM Clock Gating Register (CCM_CCGR184_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4B90 CCM Clock Gating Register (CCM_CCGR185) 32 R/W 0000_0002h 5.1.7.6/502
3038_4B94 CCM Clock Gating Register (CCM_CCGR185_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4B98 CCM Clock Gating Register (CCM_CCGR185_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4B9C CCM Clock Gating Register (CCM_CCGR185_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4BA0 CCM Clock Gating Register (CCM_CCGR186) 32 R/W 0000_0002h 5.1.7.6/502
3038_4BA4 CCM Clock Gating Register (CCM_CCGR186_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4BA8 CCM Clock Gating Register (CCM_CCGR186_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4BAC CCM Clock Gating Register (CCM_CCGR186_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4BB0 CCM Clock Gating Register (CCM_CCGR187) 32 R/W 0000_0002h 5.1.7.6/502
3038_4BB4 CCM Clock Gating Register (CCM_CCGR187_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4BB8 CCM Clock Gating Register (CCM_CCGR187_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4BBC CCM Clock Gating Register (CCM_CCGR187_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4BC0 CCM Clock Gating Register (CCM_CCGR188) 32 R/W 0000_0002h 5.1.7.6/502
3038_4BC4 CCM Clock Gating Register (CCM_CCGR188_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4BC8 CCM Clock Gating Register (CCM_CCGR188_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4BCC CCM Clock Gating Register (CCM_CCGR188_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4BD0 CCM Clock Gating Register (CCM_CCGR189) 32 R/W 0000_0002h 5.1.7.6/502
3038_4BD4 CCM Clock Gating Register (CCM_CCGR189_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4BD8 CCM Clock Gating Register (CCM_CCGR189_CLR) 32 R/W 0000_0002h 5.1.7.8/507
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

364 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4BDC CCM Clock Gating Register (CCM_CCGR189_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4BE0 CCM Clock Gating Register (CCM_CCGR190) 32 R/W 0000_0002h 5.1.7.6/502
3038_4BE4 CCM Clock Gating Register (CCM_CCGR190_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4BE8 CCM Clock Gating Register (CCM_CCGR190_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4BEC CCM Clock Gating Register (CCM_CCGR190_TOG) 32 R/W 0000_0002h 5.1.7.9/509
3038_4BF0 CCM Clock Gating Register (CCM_CCGR191) 32 R/W 0000_0002h 5.1.7.6/502
3038_4BF4 CCM Clock Gating Register (CCM_CCGR191_SET) 32 R/W 0000_0002h 5.1.7.7/505
3038_4BF8 CCM Clock Gating Register (CCM_CCGR191_CLR) 32 R/W 0000_0002h 5.1.7.8/507
3038_4BFC CCM Clock Gating Register (CCM_CCGR191_TOG) 32 R/W 0000_0002h 5.1.7.9/509
5.1.7.10/
3038_8000 Target Register (CCM_TARGET_ROOT0) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8004 Target Register (CCM_TARGET_ROOT0_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8008 Target Register (CCM_TARGET_ROOT0_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_800C Target Register (CCM_TARGET_ROOT0_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8010 Miscellaneous Register (CCM_MISC0) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8014 Miscellaneous Register (CCM_MISC_ROOT0_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8018 Miscellaneous Register (CCM_MISC_ROOT0_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_801C Miscellaneous Register (CCM_MISC_ROOT0_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8020 Post Divider Register (CCM_POST0) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8024 Post Divider Register (CCM_POST_ROOT0_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8028 Post Divider Register (CCM_POST_ROOT0_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_802C Post Divider Register (CCM_POST_ROOT0_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8030 Pre Divider Register (CCM_PRE0) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8034 Pre Divider Register (CCM_PRE_ROOT0_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8038 Pre Divider Register (CCM_PRE_ROOT0_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_803C Pre Divider Register (CCM_PRE_ROOT0_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8070 Access Control Register (CCM_ACCESS_CTRL0) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 365
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_8074 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT0_SET) 549
Access Control Register 5.1.7.28/
3038_8078 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT0_CLR) 552
Access Control Register 5.1.7.29/
3038_807C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT0_TOG) 554
5.1.7.10/
3038_8080 Target Register (CCM_TARGET_ROOT1) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8084 Target Register (CCM_TARGET_ROOT1_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8088 Target Register (CCM_TARGET_ROOT1_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_808C Target Register (CCM_TARGET_ROOT1_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8090 Miscellaneous Register (CCM_MISC1) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8094 Miscellaneous Register (CCM_MISC_ROOT1_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8098 Miscellaneous Register (CCM_MISC_ROOT1_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_809C Miscellaneous Register (CCM_MISC_ROOT1_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_80A0 Post Divider Register (CCM_POST1) 32 R/W 0000_0000h
523
5.1.7.19/
3038_80A4 Post Divider Register (CCM_POST_ROOT1_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_80A8 Post Divider Register (CCM_POST_ROOT1_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_80AC Post Divider Register (CCM_POST_ROOT1_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_80B0 Pre Divider Register (CCM_PRE1) 32 R/W 1000_0000h
535
5.1.7.23/
3038_80B4 Pre Divider Register (CCM_PRE_ROOT1_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_80B8 Pre Divider Register (CCM_PRE_ROOT1_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_80BC Pre Divider Register (CCM_PRE_ROOT1_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_80F0 Access Control Register (CCM_ACCESS_CTRL1) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_80F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT1_SET) 549
Access Control Register 5.1.7.28/
3038_80F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT1_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

366 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_80FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT1_TOG) 554
5.1.7.10/
3038_8100 Target Register (CCM_TARGET_ROOT2) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8104 Target Register (CCM_TARGET_ROOT2_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8108 Target Register (CCM_TARGET_ROOT2_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_810C Target Register (CCM_TARGET_ROOT2_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8110 Miscellaneous Register (CCM_MISC2) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8114 Miscellaneous Register (CCM_MISC_ROOT2_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8118 Miscellaneous Register (CCM_MISC_ROOT2_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_811C Miscellaneous Register (CCM_MISC_ROOT2_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8120 Post Divider Register (CCM_POST2) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8124 Post Divider Register (CCM_POST_ROOT2_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8128 Post Divider Register (CCM_POST_ROOT2_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_812C Post Divider Register (CCM_POST_ROOT2_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8130 Pre Divider Register (CCM_PRE2) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8134 Pre Divider Register (CCM_PRE_ROOT2_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8138 Pre Divider Register (CCM_PRE_ROOT2_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_813C Pre Divider Register (CCM_PRE_ROOT2_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8170 Access Control Register (CCM_ACCESS_CTRL2) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8174 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT2_SET) 549
Access Control Register 5.1.7.28/
3038_8178 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT2_CLR) 552
Access Control Register 5.1.7.29/
3038_817C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT2_TOG) 554
5.1.7.10/
3038_8180 Target Register (CCM_TARGET_ROOT3) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 367
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_8184 Target Register (CCM_TARGET_ROOT3_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8188 Target Register (CCM_TARGET_ROOT3_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_818C Target Register (CCM_TARGET_ROOT3_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8190 Miscellaneous Register (CCM_MISC3) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8194 Miscellaneous Register (CCM_MISC_ROOT3_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8198 Miscellaneous Register (CCM_MISC_ROOT3_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_819C Miscellaneous Register (CCM_MISC_ROOT3_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_81A0 Post Divider Register (CCM_POST3) 32 R/W 0000_0000h
523
5.1.7.19/
3038_81A4 Post Divider Register (CCM_POST_ROOT3_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_81A8 Post Divider Register (CCM_POST_ROOT3_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_81AC Post Divider Register (CCM_POST_ROOT3_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_81B0 Pre Divider Register (CCM_PRE3) 32 R/W 1000_0000h
535
5.1.7.23/
3038_81B4 Pre Divider Register (CCM_PRE_ROOT3_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_81B8 Pre Divider Register (CCM_PRE_ROOT3_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_81BC Pre Divider Register (CCM_PRE_ROOT3_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_81F0 Access Control Register (CCM_ACCESS_CTRL3) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_81F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT3_SET) 549
Access Control Register 5.1.7.28/
3038_81F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT3_CLR) 552
Access Control Register 5.1.7.29/
3038_81FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT3_TOG) 554
5.1.7.10/
3038_8200 Target Register (CCM_TARGET_ROOT4) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8204 Target Register (CCM_TARGET_ROOT4_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8208 Target Register (CCM_TARGET_ROOT4_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

368 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_820C Target Register (CCM_TARGET_ROOT4_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8210 Miscellaneous Register (CCM_MISC4) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8214 Miscellaneous Register (CCM_MISC_ROOT4_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8218 Miscellaneous Register (CCM_MISC_ROOT4_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_821C Miscellaneous Register (CCM_MISC_ROOT4_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8220 Post Divider Register (CCM_POST4) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8224 Post Divider Register (CCM_POST_ROOT4_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8228 Post Divider Register (CCM_POST_ROOT4_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_822C Post Divider Register (CCM_POST_ROOT4_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8230 Pre Divider Register (CCM_PRE4) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8234 Pre Divider Register (CCM_PRE_ROOT4_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8238 Pre Divider Register (CCM_PRE_ROOT4_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_823C Pre Divider Register (CCM_PRE_ROOT4_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8270 Access Control Register (CCM_ACCESS_CTRL4) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8274 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT4_SET) 549
Access Control Register 5.1.7.28/
3038_8278 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT4_CLR) 552
Access Control Register 5.1.7.29/
3038_827C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT4_TOG) 554
5.1.7.10/
3038_8280 Target Register (CCM_TARGET_ROOT5) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8284 Target Register (CCM_TARGET_ROOT5_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8288 Target Register (CCM_TARGET_ROOT5_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_828C Target Register (CCM_TARGET_ROOT5_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8290 Miscellaneous Register (CCM_MISC5) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 369
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_8294 Miscellaneous Register (CCM_MISC_ROOT5_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8298 Miscellaneous Register (CCM_MISC_ROOT5_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_829C Miscellaneous Register (CCM_MISC_ROOT5_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_82A0 Post Divider Register (CCM_POST5) 32 R/W 0000_0000h
523
5.1.7.19/
3038_82A4 Post Divider Register (CCM_POST_ROOT5_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_82A8 Post Divider Register (CCM_POST_ROOT5_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_82AC Post Divider Register (CCM_POST_ROOT5_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_82B0 Pre Divider Register (CCM_PRE5) 32 R/W 1000_0000h
535
5.1.7.23/
3038_82B4 Pre Divider Register (CCM_PRE_ROOT5_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_82B8 Pre Divider Register (CCM_PRE_ROOT5_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_82BC Pre Divider Register (CCM_PRE_ROOT5_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_82F0 Access Control Register (CCM_ACCESS_CTRL5) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_82F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT5_SET) 549
Access Control Register 5.1.7.28/
3038_82F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT5_CLR) 552
Access Control Register 5.1.7.29/
3038_82FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT5_TOG) 554
5.1.7.10/
3038_8300 Target Register (CCM_TARGET_ROOT6) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8304 Target Register (CCM_TARGET_ROOT6_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8308 Target Register (CCM_TARGET_ROOT6_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_830C Target Register (CCM_TARGET_ROOT6_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8310 Miscellaneous Register (CCM_MISC6) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8314 Miscellaneous Register (CCM_MISC_ROOT6_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8318 Miscellaneous Register (CCM_MISC_ROOT6_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

370 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_831C Miscellaneous Register (CCM_MISC_ROOT6_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8320 Post Divider Register (CCM_POST6) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8324 Post Divider Register (CCM_POST_ROOT6_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8328 Post Divider Register (CCM_POST_ROOT6_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_832C Post Divider Register (CCM_POST_ROOT6_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8330 Pre Divider Register (CCM_PRE6) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8334 Pre Divider Register (CCM_PRE_ROOT6_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8338 Pre Divider Register (CCM_PRE_ROOT6_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_833C Pre Divider Register (CCM_PRE_ROOT6_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8370 Access Control Register (CCM_ACCESS_CTRL6) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8374 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT6_SET) 549
Access Control Register 5.1.7.28/
3038_8378 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT6_CLR) 552
Access Control Register 5.1.7.29/
3038_837C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT6_TOG) 554
5.1.7.10/
3038_8380 Target Register (CCM_TARGET_ROOT7) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8384 Target Register (CCM_TARGET_ROOT7_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8388 Target Register (CCM_TARGET_ROOT7_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_838C Target Register (CCM_TARGET_ROOT7_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8390 Miscellaneous Register (CCM_MISC7) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8394 Miscellaneous Register (CCM_MISC_ROOT7_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8398 Miscellaneous Register (CCM_MISC_ROOT7_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_839C Miscellaneous Register (CCM_MISC_ROOT7_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_83A0 Post Divider Register (CCM_POST7) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 371
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_83A4 Post Divider Register (CCM_POST_ROOT7_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_83A8 Post Divider Register (CCM_POST_ROOT7_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_83AC Post Divider Register (CCM_POST_ROOT7_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_83B0 Pre Divider Register (CCM_PRE7) 32 R/W 1000_0000h
535
5.1.7.23/
3038_83B4 Pre Divider Register (CCM_PRE_ROOT7_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_83B8 Pre Divider Register (CCM_PRE_ROOT7_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_83BC Pre Divider Register (CCM_PRE_ROOT7_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_83F0 Access Control Register (CCM_ACCESS_CTRL7) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_83F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT7_SET) 549
Access Control Register 5.1.7.28/
3038_83F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT7_CLR) 552
Access Control Register 5.1.7.29/
3038_83FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT7_TOG) 554
5.1.7.10/
3038_8400 Target Register (CCM_TARGET_ROOT8) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8404 Target Register (CCM_TARGET_ROOT8_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8408 Target Register (CCM_TARGET_ROOT8_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_840C Target Register (CCM_TARGET_ROOT8_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8410 Miscellaneous Register (CCM_MISC8) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8414 Miscellaneous Register (CCM_MISC_ROOT8_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8418 Miscellaneous Register (CCM_MISC_ROOT8_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_841C Miscellaneous Register (CCM_MISC_ROOT8_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8420 Post Divider Register (CCM_POST8) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8424 Post Divider Register (CCM_POST_ROOT8_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8428 Post Divider Register (CCM_POST_ROOT8_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

372 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_842C Post Divider Register (CCM_POST_ROOT8_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8430 Pre Divider Register (CCM_PRE8) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8434 Pre Divider Register (CCM_PRE_ROOT8_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8438 Pre Divider Register (CCM_PRE_ROOT8_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_843C Pre Divider Register (CCM_PRE_ROOT8_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8470 Access Control Register (CCM_ACCESS_CTRL8) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8474 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT8_SET) 549
Access Control Register 5.1.7.28/
3038_8478 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT8_CLR) 552
Access Control Register 5.1.7.29/
3038_847C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT8_TOG) 554
5.1.7.10/
3038_8480 Target Register (CCM_TARGET_ROOT9) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8484 Target Register (CCM_TARGET_ROOT9_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8488 Target Register (CCM_TARGET_ROOT9_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_848C Target Register (CCM_TARGET_ROOT9_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8490 Miscellaneous Register (CCM_MISC9) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8494 Miscellaneous Register (CCM_MISC_ROOT9_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8498 Miscellaneous Register (CCM_MISC_ROOT9_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_849C Miscellaneous Register (CCM_MISC_ROOT9_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_84A0 Post Divider Register (CCM_POST9) 32 R/W 0000_0000h
523
5.1.7.19/
3038_84A4 Post Divider Register (CCM_POST_ROOT9_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_84A8 Post Divider Register (CCM_POST_ROOT9_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_84AC Post Divider Register (CCM_POST_ROOT9_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_84B0 Pre Divider Register (CCM_PRE9) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 373
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_84B4 Pre Divider Register (CCM_PRE_ROOT9_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_84B8 Pre Divider Register (CCM_PRE_ROOT9_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_84BC Pre Divider Register (CCM_PRE_ROOT9_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_84F0 Access Control Register (CCM_ACCESS_CTRL9) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_84F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT9_SET) 549
Access Control Register 5.1.7.28/
3038_84F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT9_CLR) 552
Access Control Register 5.1.7.29/
3038_84FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT9_TOG) 554
5.1.7.10/
3038_8500 Target Register (CCM_TARGET_ROOT10) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8504 Target Register (CCM_TARGET_ROOT10_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8508 Target Register (CCM_TARGET_ROOT10_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_850C Target Register (CCM_TARGET_ROOT10_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8510 Miscellaneous Register (CCM_MISC10) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8514 Miscellaneous Register (CCM_MISC_ROOT10_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8518 Miscellaneous Register (CCM_MISC_ROOT10_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_851C Miscellaneous Register (CCM_MISC_ROOT10_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8520 Post Divider Register (CCM_POST10) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8524 Post Divider Register (CCM_POST_ROOT10_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8528 Post Divider Register (CCM_POST_ROOT10_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_852C Post Divider Register (CCM_POST_ROOT10_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8530 Pre Divider Register (CCM_PRE10) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8534 Pre Divider Register (CCM_PRE_ROOT10_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8538 Pre Divider Register (CCM_PRE_ROOT10_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

374 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_853C Pre Divider Register (CCM_PRE_ROOT10_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8570 Access Control Register (CCM_ACCESS_CTRL10) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8574 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT10_SET) 549
Access Control Register 5.1.7.28/
3038_8578 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT10_CLR) 552
Access Control Register 5.1.7.29/
3038_857C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT10_TOG) 554
5.1.7.10/
3038_8580 Target Register (CCM_TARGET_ROOT11) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8584 Target Register (CCM_TARGET_ROOT11_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8588 Target Register (CCM_TARGET_ROOT11_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_858C Target Register (CCM_TARGET_ROOT11_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8590 Miscellaneous Register (CCM_MISC11) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8594 Miscellaneous Register (CCM_MISC_ROOT11_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8598 Miscellaneous Register (CCM_MISC_ROOT11_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_859C Miscellaneous Register (CCM_MISC_ROOT11_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_85A0 Post Divider Register (CCM_POST11) 32 R/W 0000_0000h
523
5.1.7.19/
3038_85A4 Post Divider Register (CCM_POST_ROOT11_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_85A8 Post Divider Register (CCM_POST_ROOT11_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_85AC Post Divider Register (CCM_POST_ROOT11_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_85B0 Pre Divider Register (CCM_PRE11) 32 R/W 1000_0000h
535
5.1.7.23/
3038_85B4 Pre Divider Register (CCM_PRE_ROOT11_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_85B8 Pre Divider Register (CCM_PRE_ROOT11_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_85BC Pre Divider Register (CCM_PRE_ROOT11_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_85F0 Access Control Register (CCM_ACCESS_CTRL11) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 375
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_85F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT11_SET) 549
Access Control Register 5.1.7.28/
3038_85F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT11_CLR) 552
Access Control Register 5.1.7.29/
3038_85FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT11_TOG) 554
5.1.7.10/
3038_8600 Target Register (CCM_TARGET_ROOT12) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8604 Target Register (CCM_TARGET_ROOT12_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8608 Target Register (CCM_TARGET_ROOT12_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_860C Target Register (CCM_TARGET_ROOT12_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8610 Miscellaneous Register (CCM_MISC12) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8614 Miscellaneous Register (CCM_MISC_ROOT12_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8618 Miscellaneous Register (CCM_MISC_ROOT12_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_861C Miscellaneous Register (CCM_MISC_ROOT12_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8620 Post Divider Register (CCM_POST12) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8624 Post Divider Register (CCM_POST_ROOT12_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8628 Post Divider Register (CCM_POST_ROOT12_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_862C Post Divider Register (CCM_POST_ROOT12_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8630 Pre Divider Register (CCM_PRE12) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8634 Pre Divider Register (CCM_PRE_ROOT12_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8638 Pre Divider Register (CCM_PRE_ROOT12_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_863C Pre Divider Register (CCM_PRE_ROOT12_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8670 Access Control Register (CCM_ACCESS_CTRL12) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8674 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT12_SET) 549
Access Control Register 5.1.7.28/
3038_8678 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT12_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

376 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_867C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT12_TOG) 554
5.1.7.10/
3038_8680 Target Register (CCM_TARGET_ROOT13) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8684 Target Register (CCM_TARGET_ROOT13_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8688 Target Register (CCM_TARGET_ROOT13_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_868C Target Register (CCM_TARGET_ROOT13_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8690 Miscellaneous Register (CCM_MISC13) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8694 Miscellaneous Register (CCM_MISC_ROOT13_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8698 Miscellaneous Register (CCM_MISC_ROOT13_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_869C Miscellaneous Register (CCM_MISC_ROOT13_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_86A0 Post Divider Register (CCM_POST13) 32 R/W 0000_0000h
523
5.1.7.19/
3038_86A4 Post Divider Register (CCM_POST_ROOT13_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_86A8 Post Divider Register (CCM_POST_ROOT13_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_86AC Post Divider Register (CCM_POST_ROOT13_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_86B0 Pre Divider Register (CCM_PRE13) 32 R/W 1000_0000h
535
5.1.7.23/
3038_86B4 Pre Divider Register (CCM_PRE_ROOT13_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_86B8 Pre Divider Register (CCM_PRE_ROOT13_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_86BC Pre Divider Register (CCM_PRE_ROOT13_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_86F0 Access Control Register (CCM_ACCESS_CTRL13) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_86F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT13_SET) 549
Access Control Register 5.1.7.28/
3038_86F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT13_CLR) 552
Access Control Register 5.1.7.29/
3038_86FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT13_TOG) 554
5.1.7.10/
3038_8700 Target Register (CCM_TARGET_ROOT14) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 377
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_8704 Target Register (CCM_TARGET_ROOT14_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8708 Target Register (CCM_TARGET_ROOT14_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_870C Target Register (CCM_TARGET_ROOT14_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8710 Miscellaneous Register (CCM_MISC14) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8714 Miscellaneous Register (CCM_MISC_ROOT14_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8718 Miscellaneous Register (CCM_MISC_ROOT14_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_871C Miscellaneous Register (CCM_MISC_ROOT14_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8720 Post Divider Register (CCM_POST14) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8724 Post Divider Register (CCM_POST_ROOT14_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8728 Post Divider Register (CCM_POST_ROOT14_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_872C Post Divider Register (CCM_POST_ROOT14_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8730 Pre Divider Register (CCM_PRE14) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8734 Pre Divider Register (CCM_PRE_ROOT14_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8738 Pre Divider Register (CCM_PRE_ROOT14_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_873C Pre Divider Register (CCM_PRE_ROOT14_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8770 Access Control Register (CCM_ACCESS_CTRL14) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8774 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT14_SET) 549
Access Control Register 5.1.7.28/
3038_8778 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT14_CLR) 552
Access Control Register 5.1.7.29/
3038_877C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT14_TOG) 554
5.1.7.10/
3038_8780 Target Register (CCM_TARGET_ROOT15) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8784 Target Register (CCM_TARGET_ROOT15_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8788 Target Register (CCM_TARGET_ROOT15_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

378 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_878C Target Register (CCM_TARGET_ROOT15_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8790 Miscellaneous Register (CCM_MISC15) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8794 Miscellaneous Register (CCM_MISC_ROOT15_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8798 Miscellaneous Register (CCM_MISC_ROOT15_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_879C Miscellaneous Register (CCM_MISC_ROOT15_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_87A0 Post Divider Register (CCM_POST15) 32 R/W 0000_0000h
523
5.1.7.19/
3038_87A4 Post Divider Register (CCM_POST_ROOT15_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_87A8 Post Divider Register (CCM_POST_ROOT15_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_87AC Post Divider Register (CCM_POST_ROOT15_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_87B0 Pre Divider Register (CCM_PRE15) 32 R/W 1000_0000h
535
5.1.7.23/
3038_87B4 Pre Divider Register (CCM_PRE_ROOT15_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_87B8 Pre Divider Register (CCM_PRE_ROOT15_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_87BC Pre Divider Register (CCM_PRE_ROOT15_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_87F0 Access Control Register (CCM_ACCESS_CTRL15) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_87F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT15_SET) 549
Access Control Register 5.1.7.28/
3038_87F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT15_CLR) 552
Access Control Register 5.1.7.29/
3038_87FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT15_TOG) 554
5.1.7.10/
3038_8800 Target Register (CCM_TARGET_ROOT16) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8804 Target Register (CCM_TARGET_ROOT16_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8808 Target Register (CCM_TARGET_ROOT16_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_880C Target Register (CCM_TARGET_ROOT16_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8810 Miscellaneous Register (CCM_MISC16) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 379
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_8814 Miscellaneous Register (CCM_MISC_ROOT16_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8818 Miscellaneous Register (CCM_MISC_ROOT16_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_881C Miscellaneous Register (CCM_MISC_ROOT16_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8820 Post Divider Register (CCM_POST16) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8824 Post Divider Register (CCM_POST_ROOT16_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8828 Post Divider Register (CCM_POST_ROOT16_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_882C Post Divider Register (CCM_POST_ROOT16_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8830 Pre Divider Register (CCM_PRE16) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8834 Pre Divider Register (CCM_PRE_ROOT16_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8838 Pre Divider Register (CCM_PRE_ROOT16_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_883C Pre Divider Register (CCM_PRE_ROOT16_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8870 Access Control Register (CCM_ACCESS_CTRL16) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8874 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT16_SET) 549
Access Control Register 5.1.7.28/
3038_8878 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT16_CLR) 552
Access Control Register 5.1.7.29/
3038_887C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT16_TOG) 554
5.1.7.10/
3038_8880 Target Register (CCM_TARGET_ROOT17) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8884 Target Register (CCM_TARGET_ROOT17_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8888 Target Register (CCM_TARGET_ROOT17_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_888C Target Register (CCM_TARGET_ROOT17_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8890 Miscellaneous Register (CCM_MISC17) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8894 Miscellaneous Register (CCM_MISC_ROOT17_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8898 Miscellaneous Register (CCM_MISC_ROOT17_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

380 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_889C Miscellaneous Register (CCM_MISC_ROOT17_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_88A0 Post Divider Register (CCM_POST17) 32 R/W 0000_0000h
523
5.1.7.19/
3038_88A4 Post Divider Register (CCM_POST_ROOT17_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_88A8 Post Divider Register (CCM_POST_ROOT17_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_88AC Post Divider Register (CCM_POST_ROOT17_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_88B0 Pre Divider Register (CCM_PRE17) 32 R/W 1000_0000h
535
5.1.7.23/
3038_88B4 Pre Divider Register (CCM_PRE_ROOT17_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_88B8 Pre Divider Register (CCM_PRE_ROOT17_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_88BC Pre Divider Register (CCM_PRE_ROOT17_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_88F0 Access Control Register (CCM_ACCESS_CTRL17) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_88F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT17_SET) 549
Access Control Register 5.1.7.28/
3038_88F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT17_CLR) 552
Access Control Register 5.1.7.29/
3038_88FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT17_TOG) 554
5.1.7.10/
3038_8900 Target Register (CCM_TARGET_ROOT18) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8904 Target Register (CCM_TARGET_ROOT18_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8908 Target Register (CCM_TARGET_ROOT18_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_890C Target Register (CCM_TARGET_ROOT18_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8910 Miscellaneous Register (CCM_MISC18) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8914 Miscellaneous Register (CCM_MISC_ROOT18_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8918 Miscellaneous Register (CCM_MISC_ROOT18_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_891C Miscellaneous Register (CCM_MISC_ROOT18_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8920 Post Divider Register (CCM_POST18) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 381
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_8924 Post Divider Register (CCM_POST_ROOT18_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8928 Post Divider Register (CCM_POST_ROOT18_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_892C Post Divider Register (CCM_POST_ROOT18_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8930 Pre Divider Register (CCM_PRE18) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8934 Pre Divider Register (CCM_PRE_ROOT18_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8938 Pre Divider Register (CCM_PRE_ROOT18_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_893C Pre Divider Register (CCM_PRE_ROOT18_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8970 Access Control Register (CCM_ACCESS_CTRL18) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8974 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT18_SET) 549
Access Control Register 5.1.7.28/
3038_8978 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT18_CLR) 552
Access Control Register 5.1.7.29/
3038_897C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT18_TOG) 554
5.1.7.10/
3038_8980 Target Register (CCM_TARGET_ROOT19) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8984 Target Register (CCM_TARGET_ROOT19_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8988 Target Register (CCM_TARGET_ROOT19_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_898C Target Register (CCM_TARGET_ROOT19_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8990 Miscellaneous Register (CCM_MISC19) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8994 Miscellaneous Register (CCM_MISC_ROOT19_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8998 Miscellaneous Register (CCM_MISC_ROOT19_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_899C Miscellaneous Register (CCM_MISC_ROOT19_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_89A0 Post Divider Register (CCM_POST19) 32 R/W 0000_0000h
523
5.1.7.19/
3038_89A4 Post Divider Register (CCM_POST_ROOT19_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_89A8 Post Divider Register (CCM_POST_ROOT19_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

382 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_89AC Post Divider Register (CCM_POST_ROOT19_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_89B0 Pre Divider Register (CCM_PRE19) 32 R/W 1000_0000h
535
5.1.7.23/
3038_89B4 Pre Divider Register (CCM_PRE_ROOT19_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_89B8 Pre Divider Register (CCM_PRE_ROOT19_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_89BC Pre Divider Register (CCM_PRE_ROOT19_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_89F0 Access Control Register (CCM_ACCESS_CTRL19) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_89F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT19_SET) 549
Access Control Register 5.1.7.28/
3038_89F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT19_CLR) 552
Access Control Register 5.1.7.29/
3038_89FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT19_TOG) 554
5.1.7.10/
3038_8A00 Target Register (CCM_TARGET_ROOT20) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8A04 Target Register (CCM_TARGET_ROOT20_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8A08 Target Register (CCM_TARGET_ROOT20_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8A0C Target Register (CCM_TARGET_ROOT20_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8A10 Miscellaneous Register (CCM_MISC20) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8A14 Miscellaneous Register (CCM_MISC_ROOT20_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8A18 Miscellaneous Register (CCM_MISC_ROOT20_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8A1C Miscellaneous Register (CCM_MISC_ROOT20_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8A20 Post Divider Register (CCM_POST20) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8A24 Post Divider Register (CCM_POST_ROOT20_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8A28 Post Divider Register (CCM_POST_ROOT20_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8A2C Post Divider Register (CCM_POST_ROOT20_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8A30 Pre Divider Register (CCM_PRE20) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 383
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_8A34 Pre Divider Register (CCM_PRE_ROOT20_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8A38 Pre Divider Register (CCM_PRE_ROOT20_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8A3C Pre Divider Register (CCM_PRE_ROOT20_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8A70 Access Control Register (CCM_ACCESS_CTRL20) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8A74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT20_SET) 549
Access Control Register 5.1.7.28/
3038_8A78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT20_CLR) 552
Access Control Register 5.1.7.29/
3038_8A7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT20_TOG) 554
5.1.7.10/
3038_8A80 Target Register (CCM_TARGET_ROOT21) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8A84 Target Register (CCM_TARGET_ROOT21_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8A88 Target Register (CCM_TARGET_ROOT21_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8A8C Target Register (CCM_TARGET_ROOT21_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8A90 Miscellaneous Register (CCM_MISC21) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8A94 Miscellaneous Register (CCM_MISC_ROOT21_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8A98 Miscellaneous Register (CCM_MISC_ROOT21_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8A9C Miscellaneous Register (CCM_MISC_ROOT21_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8AA0 Post Divider Register (CCM_POST21) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8AA4 Post Divider Register (CCM_POST_ROOT21_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8AA8 Post Divider Register (CCM_POST_ROOT21_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8AAC Post Divider Register (CCM_POST_ROOT21_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8AB0 Pre Divider Register (CCM_PRE21) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8AB4 Pre Divider Register (CCM_PRE_ROOT21_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8AB8 Pre Divider Register (CCM_PRE_ROOT21_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

384 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_8ABC Pre Divider Register (CCM_PRE_ROOT21_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8AF0 Access Control Register (CCM_ACCESS_CTRL21) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8AF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT21_SET) 549
Access Control Register 5.1.7.28/
3038_8AF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT21_CLR) 552
Access Control Register 5.1.7.29/
3038_8AFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT21_TOG) 554
5.1.7.10/
3038_8B00 Target Register (CCM_TARGET_ROOT22) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8B04 Target Register (CCM_TARGET_ROOT22_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8B08 Target Register (CCM_TARGET_ROOT22_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8B0C Target Register (CCM_TARGET_ROOT22_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8B10 Miscellaneous Register (CCM_MISC22) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8B14 Miscellaneous Register (CCM_MISC_ROOT22_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8B18 Miscellaneous Register (CCM_MISC_ROOT22_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8B1C Miscellaneous Register (CCM_MISC_ROOT22_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8B20 Post Divider Register (CCM_POST22) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8B24 Post Divider Register (CCM_POST_ROOT22_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8B28 Post Divider Register (CCM_POST_ROOT22_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8B2C Post Divider Register (CCM_POST_ROOT22_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8B30 Pre Divider Register (CCM_PRE22) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8B34 Pre Divider Register (CCM_PRE_ROOT22_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8B38 Pre Divider Register (CCM_PRE_ROOT22_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8B3C Pre Divider Register (CCM_PRE_ROOT22_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8B70 Access Control Register (CCM_ACCESS_CTRL22) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 385
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_8B74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT22_SET) 549
Access Control Register 5.1.7.28/
3038_8B78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT22_CLR) 552
Access Control Register 5.1.7.29/
3038_8B7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT22_TOG) 554
5.1.7.10/
3038_8B80 Target Register (CCM_TARGET_ROOT23) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8B84 Target Register (CCM_TARGET_ROOT23_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8B88 Target Register (CCM_TARGET_ROOT23_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8B8C Target Register (CCM_TARGET_ROOT23_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8B90 Miscellaneous Register (CCM_MISC23) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8B94 Miscellaneous Register (CCM_MISC_ROOT23_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8B98 Miscellaneous Register (CCM_MISC_ROOT23_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8B9C Miscellaneous Register (CCM_MISC_ROOT23_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8BA0 Post Divider Register (CCM_POST23) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8BA4 Post Divider Register (CCM_POST_ROOT23_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8BA8 Post Divider Register (CCM_POST_ROOT23_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8BAC Post Divider Register (CCM_POST_ROOT23_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8BB0 Pre Divider Register (CCM_PRE23) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8BB4 Pre Divider Register (CCM_PRE_ROOT23_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8BB8 Pre Divider Register (CCM_PRE_ROOT23_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8BBC Pre Divider Register (CCM_PRE_ROOT23_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8BF0 Access Control Register (CCM_ACCESS_CTRL23) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8BF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT23_SET) 549
Access Control Register 5.1.7.28/
3038_8BF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT23_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

386 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_8BFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT23_TOG) 554
5.1.7.10/
3038_8C00 Target Register (CCM_TARGET_ROOT24) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8C04 Target Register (CCM_TARGET_ROOT24_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8C08 Target Register (CCM_TARGET_ROOT24_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8C0C Target Register (CCM_TARGET_ROOT24_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8C10 Miscellaneous Register (CCM_MISC24) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8C14 Miscellaneous Register (CCM_MISC_ROOT24_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8C18 Miscellaneous Register (CCM_MISC_ROOT24_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8C1C Miscellaneous Register (CCM_MISC_ROOT24_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8C20 Post Divider Register (CCM_POST24) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8C24 Post Divider Register (CCM_POST_ROOT24_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8C28 Post Divider Register (CCM_POST_ROOT24_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8C2C Post Divider Register (CCM_POST_ROOT24_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8C30 Pre Divider Register (CCM_PRE24) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8C34 Pre Divider Register (CCM_PRE_ROOT24_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8C38 Pre Divider Register (CCM_PRE_ROOT24_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8C3C Pre Divider Register (CCM_PRE_ROOT24_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8C70 Access Control Register (CCM_ACCESS_CTRL24) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8C74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT24_SET) 549
Access Control Register 5.1.7.28/
3038_8C78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT24_CLR) 552
Access Control Register 5.1.7.29/
3038_8C7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT24_TOG) 554
5.1.7.10/
3038_8C80 Target Register (CCM_TARGET_ROOT25) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 387
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_8C84 Target Register (CCM_TARGET_ROOT25_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8C88 Target Register (CCM_TARGET_ROOT25_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8C8C Target Register (CCM_TARGET_ROOT25_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8C90 Miscellaneous Register (CCM_MISC25) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8C94 Miscellaneous Register (CCM_MISC_ROOT25_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8C98 Miscellaneous Register (CCM_MISC_ROOT25_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8C9C Miscellaneous Register (CCM_MISC_ROOT25_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8CA0 Post Divider Register (CCM_POST25) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8CA4 Post Divider Register (CCM_POST_ROOT25_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8CA8 Post Divider Register (CCM_POST_ROOT25_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8CAC Post Divider Register (CCM_POST_ROOT25_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8CB0 Pre Divider Register (CCM_PRE25) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8CB4 Pre Divider Register (CCM_PRE_ROOT25_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8CB8 Pre Divider Register (CCM_PRE_ROOT25_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8CBC Pre Divider Register (CCM_PRE_ROOT25_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8CF0 Access Control Register (CCM_ACCESS_CTRL25) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8CF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT25_SET) 549
Access Control Register 5.1.7.28/
3038_8CF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT25_CLR) 552
Access Control Register 5.1.7.29/
3038_8CFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT25_TOG) 554
5.1.7.10/
3038_8D00 Target Register (CCM_TARGET_ROOT26) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8D04 Target Register (CCM_TARGET_ROOT26_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8D08 Target Register (CCM_TARGET_ROOT26_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

388 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_8D0C Target Register (CCM_TARGET_ROOT26_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8D10 Miscellaneous Register (CCM_MISC26) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8D14 Miscellaneous Register (CCM_MISC_ROOT26_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8D18 Miscellaneous Register (CCM_MISC_ROOT26_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8D1C Miscellaneous Register (CCM_MISC_ROOT26_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8D20 Post Divider Register (CCM_POST26) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8D24 Post Divider Register (CCM_POST_ROOT26_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8D28 Post Divider Register (CCM_POST_ROOT26_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8D2C Post Divider Register (CCM_POST_ROOT26_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8D30 Pre Divider Register (CCM_PRE26) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8D34 Pre Divider Register (CCM_PRE_ROOT26_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8D38 Pre Divider Register (CCM_PRE_ROOT26_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8D3C Pre Divider Register (CCM_PRE_ROOT26_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8D70 Access Control Register (CCM_ACCESS_CTRL26) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8D74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT26_SET) 549
Access Control Register 5.1.7.28/
3038_8D78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT26_CLR) 552
Access Control Register 5.1.7.29/
3038_8D7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT26_TOG) 554
5.1.7.10/
3038_8D80 Target Register (CCM_TARGET_ROOT27) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8D84 Target Register (CCM_TARGET_ROOT27_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8D88 Target Register (CCM_TARGET_ROOT27_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8D8C Target Register (CCM_TARGET_ROOT27_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8D90 Miscellaneous Register (CCM_MISC27) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 389
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_8D94 Miscellaneous Register (CCM_MISC_ROOT27_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8D98 Miscellaneous Register (CCM_MISC_ROOT27_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8D9C Miscellaneous Register (CCM_MISC_ROOT27_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8DA0 Post Divider Register (CCM_POST27) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8DA4 Post Divider Register (CCM_POST_ROOT27_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8DA8 Post Divider Register (CCM_POST_ROOT27_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8DAC Post Divider Register (CCM_POST_ROOT27_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8DB0 Pre Divider Register (CCM_PRE27) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8DB4 Pre Divider Register (CCM_PRE_ROOT27_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8DB8 Pre Divider Register (CCM_PRE_ROOT27_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8DBC Pre Divider Register (CCM_PRE_ROOT27_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8DF0 Access Control Register (CCM_ACCESS_CTRL27) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8DF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT27_SET) 549
Access Control Register 5.1.7.28/
3038_8DF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT27_CLR) 552
Access Control Register 5.1.7.29/
3038_8DFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT27_TOG) 554
5.1.7.10/
3038_8E00 Target Register (CCM_TARGET_ROOT28) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8E04 Target Register (CCM_TARGET_ROOT28_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8E08 Target Register (CCM_TARGET_ROOT28_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8E0C Target Register (CCM_TARGET_ROOT28_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8E10 Miscellaneous Register (CCM_MISC28) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8E14 Miscellaneous Register (CCM_MISC_ROOT28_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8E18 Miscellaneous Register (CCM_MISC_ROOT28_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

390 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_8E1C Miscellaneous Register (CCM_MISC_ROOT28_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8E20 Post Divider Register (CCM_POST28) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8E24 Post Divider Register (CCM_POST_ROOT28_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8E28 Post Divider Register (CCM_POST_ROOT28_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8E2C Post Divider Register (CCM_POST_ROOT28_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8E30 Pre Divider Register (CCM_PRE28) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8E34 Pre Divider Register (CCM_PRE_ROOT28_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8E38 Pre Divider Register (CCM_PRE_ROOT28_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8E3C Pre Divider Register (CCM_PRE_ROOT28_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8E70 Access Control Register (CCM_ACCESS_CTRL28) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8E74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT28_SET) 549
Access Control Register 5.1.7.28/
3038_8E78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT28_CLR) 552
Access Control Register 5.1.7.29/
3038_8E7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT28_TOG) 554
5.1.7.10/
3038_8E80 Target Register (CCM_TARGET_ROOT29) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8E84 Target Register (CCM_TARGET_ROOT29_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8E88 Target Register (CCM_TARGET_ROOT29_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8E8C Target Register (CCM_TARGET_ROOT29_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8E90 Miscellaneous Register (CCM_MISC29) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8E94 Miscellaneous Register (CCM_MISC_ROOT29_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8E98 Miscellaneous Register (CCM_MISC_ROOT29_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8E9C Miscellaneous Register (CCM_MISC_ROOT29_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8EA0 Post Divider Register (CCM_POST29) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 391
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_8EA4 Post Divider Register (CCM_POST_ROOT29_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8EA8 Post Divider Register (CCM_POST_ROOT29_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8EAC Post Divider Register (CCM_POST_ROOT29_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8EB0 Pre Divider Register (CCM_PRE29) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8EB4 Pre Divider Register (CCM_PRE_ROOT29_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8EB8 Pre Divider Register (CCM_PRE_ROOT29_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8EBC Pre Divider Register (CCM_PRE_ROOT29_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8EF0 Access Control Register (CCM_ACCESS_CTRL29) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8EF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT29_SET) 549
Access Control Register 5.1.7.28/
3038_8EF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT29_CLR) 552
Access Control Register 5.1.7.29/
3038_8EFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT29_TOG) 554
5.1.7.10/
3038_8F00 Target Register (CCM_TARGET_ROOT30) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8F04 Target Register (CCM_TARGET_ROOT30_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8F08 Target Register (CCM_TARGET_ROOT30_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8F0C Target Register (CCM_TARGET_ROOT30_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8F10 Miscellaneous Register (CCM_MISC30) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8F14 Miscellaneous Register (CCM_MISC_ROOT30_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8F18 Miscellaneous Register (CCM_MISC_ROOT30_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8F1C Miscellaneous Register (CCM_MISC_ROOT30_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8F20 Post Divider Register (CCM_POST30) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8F24 Post Divider Register (CCM_POST_ROOT30_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8F28 Post Divider Register (CCM_POST_ROOT30_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

392 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_8F2C Post Divider Register (CCM_POST_ROOT30_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8F30 Pre Divider Register (CCM_PRE30) 32 R/W 1000_0000h
535
5.1.7.23/
3038_8F34 Pre Divider Register (CCM_PRE_ROOT30_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8F38 Pre Divider Register (CCM_PRE_ROOT30_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8F3C Pre Divider Register (CCM_PRE_ROOT30_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8F70 Access Control Register (CCM_ACCESS_CTRL30) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8F74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT30_SET) 549
Access Control Register 5.1.7.28/
3038_8F78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT30_CLR) 552
Access Control Register 5.1.7.29/
3038_8F7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT30_TOG) 554
5.1.7.10/
3038_8F80 Target Register (CCM_TARGET_ROOT31) 32 R/W 1000_0000h
511
5.1.7.11/
3038_8F84 Target Register (CCM_TARGET_ROOT31_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_8F88 Target Register (CCM_TARGET_ROOT31_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_8F8C Target Register (CCM_TARGET_ROOT31_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_8F90 Miscellaneous Register (CCM_MISC31) 32 R/W 0000_0000h
519
5.1.7.15/
3038_8F94 Miscellaneous Register (CCM_MISC_ROOT31_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_8F98 Miscellaneous Register (CCM_MISC_ROOT31_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_8F9C Miscellaneous Register (CCM_MISC_ROOT31_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_8FA0 Post Divider Register (CCM_POST31) 32 R/W 0000_0000h
523
5.1.7.19/
3038_8FA4 Post Divider Register (CCM_POST_ROOT31_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_8FA8 Post Divider Register (CCM_POST_ROOT31_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_8FAC Post Divider Register (CCM_POST_ROOT31_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_8FB0 Pre Divider Register (CCM_PRE31) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 393
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_8FB4 Pre Divider Register (CCM_PRE_ROOT31_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_8FB8 Pre Divider Register (CCM_PRE_ROOT31_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_8FBC Pre Divider Register (CCM_PRE_ROOT31_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_8FF0 Access Control Register (CCM_ACCESS_CTRL31) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_8FF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT31_SET) 549
Access Control Register 5.1.7.28/
3038_8FF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT31_CLR) 552
Access Control Register 5.1.7.29/
3038_8FFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT31_TOG) 554
5.1.7.10/
3038_9000 Target Register (CCM_TARGET_ROOT32) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9004 Target Register (CCM_TARGET_ROOT32_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9008 Target Register (CCM_TARGET_ROOT32_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_900C Target Register (CCM_TARGET_ROOT32_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9010 Miscellaneous Register (CCM_MISC32) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9014 Miscellaneous Register (CCM_MISC_ROOT32_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9018 Miscellaneous Register (CCM_MISC_ROOT32_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_901C Miscellaneous Register (CCM_MISC_ROOT32_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9020 Post Divider Register (CCM_POST32) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9024 Post Divider Register (CCM_POST_ROOT32_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9028 Post Divider Register (CCM_POST_ROOT32_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_902C Post Divider Register (CCM_POST_ROOT32_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9030 Pre Divider Register (CCM_PRE32) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9034 Pre Divider Register (CCM_PRE_ROOT32_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9038 Pre Divider Register (CCM_PRE_ROOT32_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

394 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_903C Pre Divider Register (CCM_PRE_ROOT32_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9070 Access Control Register (CCM_ACCESS_CTRL32) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9074 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT32_SET) 549
Access Control Register 5.1.7.28/
3038_9078 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT32_CLR) 552
Access Control Register 5.1.7.29/
3038_907C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT32_TOG) 554
5.1.7.10/
3038_9080 Target Register (CCM_TARGET_ROOT33) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9084 Target Register (CCM_TARGET_ROOT33_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9088 Target Register (CCM_TARGET_ROOT33_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_908C Target Register (CCM_TARGET_ROOT33_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9090 Miscellaneous Register (CCM_MISC33) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9094 Miscellaneous Register (CCM_MISC_ROOT33_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9098 Miscellaneous Register (CCM_MISC_ROOT33_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_909C Miscellaneous Register (CCM_MISC_ROOT33_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_90A0 Post Divider Register (CCM_POST33) 32 R/W 0000_0000h
523
5.1.7.19/
3038_90A4 Post Divider Register (CCM_POST_ROOT33_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_90A8 Post Divider Register (CCM_POST_ROOT33_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_90AC Post Divider Register (CCM_POST_ROOT33_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_90B0 Pre Divider Register (CCM_PRE33) 32 R/W 1000_0000h
535
5.1.7.23/
3038_90B4 Pre Divider Register (CCM_PRE_ROOT33_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_90B8 Pre Divider Register (CCM_PRE_ROOT33_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_90BC Pre Divider Register (CCM_PRE_ROOT33_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_90F0 Access Control Register (CCM_ACCESS_CTRL33) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 395
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_90F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT33_SET) 549
Access Control Register 5.1.7.28/
3038_90F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT33_CLR) 552
Access Control Register 5.1.7.29/
3038_90FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT33_TOG) 554
5.1.7.10/
3038_9100 Target Register (CCM_TARGET_ROOT34) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9104 Target Register (CCM_TARGET_ROOT34_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9108 Target Register (CCM_TARGET_ROOT34_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_910C Target Register (CCM_TARGET_ROOT34_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9110 Miscellaneous Register (CCM_MISC34) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9114 Miscellaneous Register (CCM_MISC_ROOT34_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9118 Miscellaneous Register (CCM_MISC_ROOT34_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_911C Miscellaneous Register (CCM_MISC_ROOT34_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9120 Post Divider Register (CCM_POST34) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9124 Post Divider Register (CCM_POST_ROOT34_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9128 Post Divider Register (CCM_POST_ROOT34_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_912C Post Divider Register (CCM_POST_ROOT34_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9130 Pre Divider Register (CCM_PRE34) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9134 Pre Divider Register (CCM_PRE_ROOT34_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9138 Pre Divider Register (CCM_PRE_ROOT34_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_913C Pre Divider Register (CCM_PRE_ROOT34_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9170 Access Control Register (CCM_ACCESS_CTRL34) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9174 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT34_SET) 549
Access Control Register 5.1.7.28/
3038_9178 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT34_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

396 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_917C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT34_TOG) 554
5.1.7.10/
3038_9180 Target Register (CCM_TARGET_ROOT35) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9184 Target Register (CCM_TARGET_ROOT35_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9188 Target Register (CCM_TARGET_ROOT35_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_918C Target Register (CCM_TARGET_ROOT35_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9190 Miscellaneous Register (CCM_MISC35) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9194 Miscellaneous Register (CCM_MISC_ROOT35_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9198 Miscellaneous Register (CCM_MISC_ROOT35_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_919C Miscellaneous Register (CCM_MISC_ROOT35_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_91A0 Post Divider Register (CCM_POST35) 32 R/W 0000_0000h
523
5.1.7.19/
3038_91A4 Post Divider Register (CCM_POST_ROOT35_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_91A8 Post Divider Register (CCM_POST_ROOT35_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_91AC Post Divider Register (CCM_POST_ROOT35_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_91B0 Pre Divider Register (CCM_PRE35) 32 R/W 1000_0000h
535
5.1.7.23/
3038_91B4 Pre Divider Register (CCM_PRE_ROOT35_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_91B8 Pre Divider Register (CCM_PRE_ROOT35_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_91BC Pre Divider Register (CCM_PRE_ROOT35_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_91F0 Access Control Register (CCM_ACCESS_CTRL35) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_91F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT35_SET) 549
Access Control Register 5.1.7.28/
3038_91F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT35_CLR) 552
Access Control Register 5.1.7.29/
3038_91FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT35_TOG) 554
5.1.7.10/
3038_9200 Target Register (CCM_TARGET_ROOT36) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 397
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_9204 Target Register (CCM_TARGET_ROOT36_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9208 Target Register (CCM_TARGET_ROOT36_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_920C Target Register (CCM_TARGET_ROOT36_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9210 Miscellaneous Register (CCM_MISC36) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9214 Miscellaneous Register (CCM_MISC_ROOT36_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9218 Miscellaneous Register (CCM_MISC_ROOT36_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_921C Miscellaneous Register (CCM_MISC_ROOT36_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9220 Post Divider Register (CCM_POST36) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9224 Post Divider Register (CCM_POST_ROOT36_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9228 Post Divider Register (CCM_POST_ROOT36_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_922C Post Divider Register (CCM_POST_ROOT36_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9230 Pre Divider Register (CCM_PRE36) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9234 Pre Divider Register (CCM_PRE_ROOT36_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9238 Pre Divider Register (CCM_PRE_ROOT36_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_923C Pre Divider Register (CCM_PRE_ROOT36_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9270 Access Control Register (CCM_ACCESS_CTRL36) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9274 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT36_SET) 549
Access Control Register 5.1.7.28/
3038_9278 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT36_CLR) 552
Access Control Register 5.1.7.29/
3038_927C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT36_TOG) 554
5.1.7.10/
3038_9280 Target Register (CCM_TARGET_ROOT37) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9284 Target Register (CCM_TARGET_ROOT37_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9288 Target Register (CCM_TARGET_ROOT37_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

398 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_928C Target Register (CCM_TARGET_ROOT37_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9290 Miscellaneous Register (CCM_MISC37) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9294 Miscellaneous Register (CCM_MISC_ROOT37_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9298 Miscellaneous Register (CCM_MISC_ROOT37_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_929C Miscellaneous Register (CCM_MISC_ROOT37_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_92A0 Post Divider Register (CCM_POST37) 32 R/W 0000_0000h
523
5.1.7.19/
3038_92A4 Post Divider Register (CCM_POST_ROOT37_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_92A8 Post Divider Register (CCM_POST_ROOT37_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_92AC Post Divider Register (CCM_POST_ROOT37_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_92B0 Pre Divider Register (CCM_PRE37) 32 R/W 1000_0000h
535
5.1.7.23/
3038_92B4 Pre Divider Register (CCM_PRE_ROOT37_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_92B8 Pre Divider Register (CCM_PRE_ROOT37_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_92BC Pre Divider Register (CCM_PRE_ROOT37_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_92F0 Access Control Register (CCM_ACCESS_CTRL37) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_92F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT37_SET) 549
Access Control Register 5.1.7.28/
3038_92F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT37_CLR) 552
Access Control Register 5.1.7.29/
3038_92FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT37_TOG) 554
5.1.7.10/
3038_9300 Target Register (CCM_TARGET_ROOT38) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9304 Target Register (CCM_TARGET_ROOT38_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9308 Target Register (CCM_TARGET_ROOT38_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_930C Target Register (CCM_TARGET_ROOT38_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9310 Miscellaneous Register (CCM_MISC38) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 399
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_9314 Miscellaneous Register (CCM_MISC_ROOT38_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9318 Miscellaneous Register (CCM_MISC_ROOT38_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_931C Miscellaneous Register (CCM_MISC_ROOT38_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9320 Post Divider Register (CCM_POST38) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9324 Post Divider Register (CCM_POST_ROOT38_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9328 Post Divider Register (CCM_POST_ROOT38_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_932C Post Divider Register (CCM_POST_ROOT38_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9330 Pre Divider Register (CCM_PRE38) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9334 Pre Divider Register (CCM_PRE_ROOT38_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9338 Pre Divider Register (CCM_PRE_ROOT38_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_933C Pre Divider Register (CCM_PRE_ROOT38_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9370 Access Control Register (CCM_ACCESS_CTRL38) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9374 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT38_SET) 549
Access Control Register 5.1.7.28/
3038_9378 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT38_CLR) 552
Access Control Register 5.1.7.29/
3038_937C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT38_TOG) 554
5.1.7.10/
3038_9380 Target Register (CCM_TARGET_ROOT39) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9384 Target Register (CCM_TARGET_ROOT39_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9388 Target Register (CCM_TARGET_ROOT39_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_938C Target Register (CCM_TARGET_ROOT39_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9390 Miscellaneous Register (CCM_MISC39) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9394 Miscellaneous Register (CCM_MISC_ROOT39_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9398 Miscellaneous Register (CCM_MISC_ROOT39_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

400 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_939C Miscellaneous Register (CCM_MISC_ROOT39_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_93A0 Post Divider Register (CCM_POST39) 32 R/W 0000_0000h
523
5.1.7.19/
3038_93A4 Post Divider Register (CCM_POST_ROOT39_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_93A8 Post Divider Register (CCM_POST_ROOT39_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_93AC Post Divider Register (CCM_POST_ROOT39_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_93B0 Pre Divider Register (CCM_PRE39) 32 R/W 1000_0000h
535
5.1.7.23/
3038_93B4 Pre Divider Register (CCM_PRE_ROOT39_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_93B8 Pre Divider Register (CCM_PRE_ROOT39_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_93BC Pre Divider Register (CCM_PRE_ROOT39_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_93F0 Access Control Register (CCM_ACCESS_CTRL39) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_93F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT39_SET) 549
Access Control Register 5.1.7.28/
3038_93F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT39_CLR) 552
Access Control Register 5.1.7.29/
3038_93FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT39_TOG) 554
5.1.7.10/
3038_9400 Target Register (CCM_TARGET_ROOT40) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9404 Target Register (CCM_TARGET_ROOT40_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9408 Target Register (CCM_TARGET_ROOT40_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_940C Target Register (CCM_TARGET_ROOT40_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9410 Miscellaneous Register (CCM_MISC40) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9414 Miscellaneous Register (CCM_MISC_ROOT40_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9418 Miscellaneous Register (CCM_MISC_ROOT40_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_941C Miscellaneous Register (CCM_MISC_ROOT40_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9420 Post Divider Register (CCM_POST40) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 401
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_9424 Post Divider Register (CCM_POST_ROOT40_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9428 Post Divider Register (CCM_POST_ROOT40_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_942C Post Divider Register (CCM_POST_ROOT40_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9430 Pre Divider Register (CCM_PRE40) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9434 Pre Divider Register (CCM_PRE_ROOT40_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9438 Pre Divider Register (CCM_PRE_ROOT40_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_943C Pre Divider Register (CCM_PRE_ROOT40_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9470 Access Control Register (CCM_ACCESS_CTRL40) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9474 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT40_SET) 549
Access Control Register 5.1.7.28/
3038_9478 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT40_CLR) 552
Access Control Register 5.1.7.29/
3038_947C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT40_TOG) 554
5.1.7.10/
3038_9480 Target Register (CCM_TARGET_ROOT41) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9484 Target Register (CCM_TARGET_ROOT41_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9488 Target Register (CCM_TARGET_ROOT41_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_948C Target Register (CCM_TARGET_ROOT41_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9490 Miscellaneous Register (CCM_MISC41) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9494 Miscellaneous Register (CCM_MISC_ROOT41_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9498 Miscellaneous Register (CCM_MISC_ROOT41_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_949C Miscellaneous Register (CCM_MISC_ROOT41_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_94A0 Post Divider Register (CCM_POST41) 32 R/W 0000_0000h
523
5.1.7.19/
3038_94A4 Post Divider Register (CCM_POST_ROOT41_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_94A8 Post Divider Register (CCM_POST_ROOT41_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

402 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_94AC Post Divider Register (CCM_POST_ROOT41_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_94B0 Pre Divider Register (CCM_PRE41) 32 R/W 1000_0000h
535
5.1.7.23/
3038_94B4 Pre Divider Register (CCM_PRE_ROOT41_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_94B8 Pre Divider Register (CCM_PRE_ROOT41_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_94BC Pre Divider Register (CCM_PRE_ROOT41_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_94F0 Access Control Register (CCM_ACCESS_CTRL41) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_94F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT41_SET) 549
Access Control Register 5.1.7.28/
3038_94F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT41_CLR) 552
Access Control Register 5.1.7.29/
3038_94FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT41_TOG) 554
5.1.7.10/
3038_9500 Target Register (CCM_TARGET_ROOT42) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9504 Target Register (CCM_TARGET_ROOT42_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9508 Target Register (CCM_TARGET_ROOT42_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_950C Target Register (CCM_TARGET_ROOT42_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9510 Miscellaneous Register (CCM_MISC42) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9514 Miscellaneous Register (CCM_MISC_ROOT42_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9518 Miscellaneous Register (CCM_MISC_ROOT42_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_951C Miscellaneous Register (CCM_MISC_ROOT42_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9520 Post Divider Register (CCM_POST42) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9524 Post Divider Register (CCM_POST_ROOT42_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9528 Post Divider Register (CCM_POST_ROOT42_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_952C Post Divider Register (CCM_POST_ROOT42_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9530 Pre Divider Register (CCM_PRE42) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 403
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_9534 Pre Divider Register (CCM_PRE_ROOT42_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9538 Pre Divider Register (CCM_PRE_ROOT42_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_953C Pre Divider Register (CCM_PRE_ROOT42_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9570 Access Control Register (CCM_ACCESS_CTRL42) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9574 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT42_SET) 549
Access Control Register 5.1.7.28/
3038_9578 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT42_CLR) 552
Access Control Register 5.1.7.29/
3038_957C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT42_TOG) 554
5.1.7.10/
3038_9580 Target Register (CCM_TARGET_ROOT43) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9584 Target Register (CCM_TARGET_ROOT43_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9588 Target Register (CCM_TARGET_ROOT43_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_958C Target Register (CCM_TARGET_ROOT43_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9590 Miscellaneous Register (CCM_MISC43) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9594 Miscellaneous Register (CCM_MISC_ROOT43_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9598 Miscellaneous Register (CCM_MISC_ROOT43_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_959C Miscellaneous Register (CCM_MISC_ROOT43_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_95A0 Post Divider Register (CCM_POST43) 32 R/W 0000_0000h
523
5.1.7.19/
3038_95A4 Post Divider Register (CCM_POST_ROOT43_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_95A8 Post Divider Register (CCM_POST_ROOT43_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_95AC Post Divider Register (CCM_POST_ROOT43_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_95B0 Pre Divider Register (CCM_PRE43) 32 R/W 1000_0000h
535
5.1.7.23/
3038_95B4 Pre Divider Register (CCM_PRE_ROOT43_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_95B8 Pre Divider Register (CCM_PRE_ROOT43_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

404 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_95BC Pre Divider Register (CCM_PRE_ROOT43_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_95F0 Access Control Register (CCM_ACCESS_CTRL43) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_95F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT43_SET) 549
Access Control Register 5.1.7.28/
3038_95F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT43_CLR) 552
Access Control Register 5.1.7.29/
3038_95FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT43_TOG) 554
5.1.7.10/
3038_9600 Target Register (CCM_TARGET_ROOT44) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9604 Target Register (CCM_TARGET_ROOT44_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9608 Target Register (CCM_TARGET_ROOT44_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_960C Target Register (CCM_TARGET_ROOT44_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9610 Miscellaneous Register (CCM_MISC44) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9614 Miscellaneous Register (CCM_MISC_ROOT44_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9618 Miscellaneous Register (CCM_MISC_ROOT44_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_961C Miscellaneous Register (CCM_MISC_ROOT44_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9620 Post Divider Register (CCM_POST44) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9624 Post Divider Register (CCM_POST_ROOT44_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9628 Post Divider Register (CCM_POST_ROOT44_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_962C Post Divider Register (CCM_POST_ROOT44_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9630 Pre Divider Register (CCM_PRE44) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9634 Pre Divider Register (CCM_PRE_ROOT44_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9638 Pre Divider Register (CCM_PRE_ROOT44_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_963C Pre Divider Register (CCM_PRE_ROOT44_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9670 Access Control Register (CCM_ACCESS_CTRL44) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 405
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_9674 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT44_SET) 549
Access Control Register 5.1.7.28/
3038_9678 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT44_CLR) 552
Access Control Register 5.1.7.29/
3038_967C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT44_TOG) 554
5.1.7.10/
3038_9680 Target Register (CCM_TARGET_ROOT45) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9684 Target Register (CCM_TARGET_ROOT45_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9688 Target Register (CCM_TARGET_ROOT45_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_968C Target Register (CCM_TARGET_ROOT45_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9690 Miscellaneous Register (CCM_MISC45) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9694 Miscellaneous Register (CCM_MISC_ROOT45_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9698 Miscellaneous Register (CCM_MISC_ROOT45_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_969C Miscellaneous Register (CCM_MISC_ROOT45_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_96A0 Post Divider Register (CCM_POST45) 32 R/W 0000_0000h
523
5.1.7.19/
3038_96A4 Post Divider Register (CCM_POST_ROOT45_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_96A8 Post Divider Register (CCM_POST_ROOT45_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_96AC Post Divider Register (CCM_POST_ROOT45_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_96B0 Pre Divider Register (CCM_PRE45) 32 R/W 1000_0000h
535
5.1.7.23/
3038_96B4 Pre Divider Register (CCM_PRE_ROOT45_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_96B8 Pre Divider Register (CCM_PRE_ROOT45_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_96BC Pre Divider Register (CCM_PRE_ROOT45_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_96F0 Access Control Register (CCM_ACCESS_CTRL45) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_96F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT45_SET) 549
Access Control Register 5.1.7.28/
3038_96F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT45_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

406 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_96FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT45_TOG) 554
5.1.7.10/
3038_9700 Target Register (CCM_TARGET_ROOT46) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9704 Target Register (CCM_TARGET_ROOT46_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9708 Target Register (CCM_TARGET_ROOT46_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_970C Target Register (CCM_TARGET_ROOT46_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9710 Miscellaneous Register (CCM_MISC46) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9714 Miscellaneous Register (CCM_MISC_ROOT46_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9718 Miscellaneous Register (CCM_MISC_ROOT46_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_971C Miscellaneous Register (CCM_MISC_ROOT46_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9720 Post Divider Register (CCM_POST46) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9724 Post Divider Register (CCM_POST_ROOT46_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9728 Post Divider Register (CCM_POST_ROOT46_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_972C Post Divider Register (CCM_POST_ROOT46_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9730 Pre Divider Register (CCM_PRE46) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9734 Pre Divider Register (CCM_PRE_ROOT46_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9738 Pre Divider Register (CCM_PRE_ROOT46_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_973C Pre Divider Register (CCM_PRE_ROOT46_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9770 Access Control Register (CCM_ACCESS_CTRL46) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9774 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT46_SET) 549
Access Control Register 5.1.7.28/
3038_9778 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT46_CLR) 552
Access Control Register 5.1.7.29/
3038_977C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT46_TOG) 554
5.1.7.10/
3038_9780 Target Register (CCM_TARGET_ROOT47) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 407
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_9784 Target Register (CCM_TARGET_ROOT47_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9788 Target Register (CCM_TARGET_ROOT47_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_978C Target Register (CCM_TARGET_ROOT47_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9790 Miscellaneous Register (CCM_MISC47) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9794 Miscellaneous Register (CCM_MISC_ROOT47_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9798 Miscellaneous Register (CCM_MISC_ROOT47_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_979C Miscellaneous Register (CCM_MISC_ROOT47_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_97A0 Post Divider Register (CCM_POST47) 32 R/W 0000_0000h
523
5.1.7.19/
3038_97A4 Post Divider Register (CCM_POST_ROOT47_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_97A8 Post Divider Register (CCM_POST_ROOT47_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_97AC Post Divider Register (CCM_POST_ROOT47_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_97B0 Pre Divider Register (CCM_PRE47) 32 R/W 1000_0000h
535
5.1.7.23/
3038_97B4 Pre Divider Register (CCM_PRE_ROOT47_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_97B8 Pre Divider Register (CCM_PRE_ROOT47_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_97BC Pre Divider Register (CCM_PRE_ROOT47_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_97F0 Access Control Register (CCM_ACCESS_CTRL47) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_97F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT47_SET) 549
Access Control Register 5.1.7.28/
3038_97F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT47_CLR) 552
Access Control Register 5.1.7.29/
3038_97FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT47_TOG) 554
5.1.7.10/
3038_9800 Target Register (CCM_TARGET_ROOT48) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9804 Target Register (CCM_TARGET_ROOT48_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9808 Target Register (CCM_TARGET_ROOT48_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

408 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_980C Target Register (CCM_TARGET_ROOT48_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9810 Miscellaneous Register (CCM_MISC48) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9814 Miscellaneous Register (CCM_MISC_ROOT48_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9818 Miscellaneous Register (CCM_MISC_ROOT48_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_981C Miscellaneous Register (CCM_MISC_ROOT48_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9820 Post Divider Register (CCM_POST48) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9824 Post Divider Register (CCM_POST_ROOT48_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9828 Post Divider Register (CCM_POST_ROOT48_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_982C Post Divider Register (CCM_POST_ROOT48_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9830 Pre Divider Register (CCM_PRE48) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9834 Pre Divider Register (CCM_PRE_ROOT48_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9838 Pre Divider Register (CCM_PRE_ROOT48_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_983C Pre Divider Register (CCM_PRE_ROOT48_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9870 Access Control Register (CCM_ACCESS_CTRL48) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9874 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT48_SET) 549
Access Control Register 5.1.7.28/
3038_9878 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT48_CLR) 552
Access Control Register 5.1.7.29/
3038_987C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT48_TOG) 554
5.1.7.10/
3038_9880 Target Register (CCM_TARGET_ROOT49) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9884 Target Register (CCM_TARGET_ROOT49_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9888 Target Register (CCM_TARGET_ROOT49_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_988C Target Register (CCM_TARGET_ROOT49_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9890 Miscellaneous Register (CCM_MISC49) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 409
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_9894 Miscellaneous Register (CCM_MISC_ROOT49_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9898 Miscellaneous Register (CCM_MISC_ROOT49_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_989C Miscellaneous Register (CCM_MISC_ROOT49_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_98A0 Post Divider Register (CCM_POST49) 32 R/W 0000_0000h
523
5.1.7.19/
3038_98A4 Post Divider Register (CCM_POST_ROOT49_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_98A8 Post Divider Register (CCM_POST_ROOT49_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_98AC Post Divider Register (CCM_POST_ROOT49_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_98B0 Pre Divider Register (CCM_PRE49) 32 R/W 1000_0000h
535
5.1.7.23/
3038_98B4 Pre Divider Register (CCM_PRE_ROOT49_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_98B8 Pre Divider Register (CCM_PRE_ROOT49_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_98BC Pre Divider Register (CCM_PRE_ROOT49_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_98F0 Access Control Register (CCM_ACCESS_CTRL49) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_98F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT49_SET) 549
Access Control Register 5.1.7.28/
3038_98F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT49_CLR) 552
Access Control Register 5.1.7.29/
3038_98FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT49_TOG) 554
5.1.7.10/
3038_9900 Target Register (CCM_TARGET_ROOT50) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9904 Target Register (CCM_TARGET_ROOT50_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9908 Target Register (CCM_TARGET_ROOT50_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_990C Target Register (CCM_TARGET_ROOT50_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9910 Miscellaneous Register (CCM_MISC50) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9914 Miscellaneous Register (CCM_MISC_ROOT50_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9918 Miscellaneous Register (CCM_MISC_ROOT50_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

410 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_991C Miscellaneous Register (CCM_MISC_ROOT50_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9920 Post Divider Register (CCM_POST50) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9924 Post Divider Register (CCM_POST_ROOT50_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9928 Post Divider Register (CCM_POST_ROOT50_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_992C Post Divider Register (CCM_POST_ROOT50_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9930 Pre Divider Register (CCM_PRE50) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9934 Pre Divider Register (CCM_PRE_ROOT50_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9938 Pre Divider Register (CCM_PRE_ROOT50_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_993C Pre Divider Register (CCM_PRE_ROOT50_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9970 Access Control Register (CCM_ACCESS_CTRL50) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9974 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT50_SET) 549
Access Control Register 5.1.7.28/
3038_9978 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT50_CLR) 552
Access Control Register 5.1.7.29/
3038_997C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT50_TOG) 554
5.1.7.10/
3038_9980 Target Register (CCM_TARGET_ROOT51) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9984 Target Register (CCM_TARGET_ROOT51_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9988 Target Register (CCM_TARGET_ROOT51_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_998C Target Register (CCM_TARGET_ROOT51_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9990 Miscellaneous Register (CCM_MISC51) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9994 Miscellaneous Register (CCM_MISC_ROOT51_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9998 Miscellaneous Register (CCM_MISC_ROOT51_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_999C Miscellaneous Register (CCM_MISC_ROOT51_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_99A0 Post Divider Register (CCM_POST51) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 411
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_99A4 Post Divider Register (CCM_POST_ROOT51_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_99A8 Post Divider Register (CCM_POST_ROOT51_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_99AC Post Divider Register (CCM_POST_ROOT51_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_99B0 Pre Divider Register (CCM_PRE51) 32 R/W 1000_0000h
535
5.1.7.23/
3038_99B4 Pre Divider Register (CCM_PRE_ROOT51_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_99B8 Pre Divider Register (CCM_PRE_ROOT51_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_99BC Pre Divider Register (CCM_PRE_ROOT51_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_99F0 Access Control Register (CCM_ACCESS_CTRL51) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_99F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT51_SET) 549
Access Control Register 5.1.7.28/
3038_99F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT51_CLR) 552
Access Control Register 5.1.7.29/
3038_99FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT51_TOG) 554
5.1.7.10/
3038_9A00 Target Register (CCM_TARGET_ROOT52) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9A04 Target Register (CCM_TARGET_ROOT52_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9A08 Target Register (CCM_TARGET_ROOT52_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9A0C Target Register (CCM_TARGET_ROOT52_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9A10 Miscellaneous Register (CCM_MISC52) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9A14 Miscellaneous Register (CCM_MISC_ROOT52_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9A18 Miscellaneous Register (CCM_MISC_ROOT52_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9A1C Miscellaneous Register (CCM_MISC_ROOT52_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9A20 Post Divider Register (CCM_POST52) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9A24 Post Divider Register (CCM_POST_ROOT52_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9A28 Post Divider Register (CCM_POST_ROOT52_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

412 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_9A2C Post Divider Register (CCM_POST_ROOT52_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9A30 Pre Divider Register (CCM_PRE52) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9A34 Pre Divider Register (CCM_PRE_ROOT52_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9A38 Pre Divider Register (CCM_PRE_ROOT52_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9A3C Pre Divider Register (CCM_PRE_ROOT52_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9A70 Access Control Register (CCM_ACCESS_CTRL52) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9A74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT52_SET) 549
Access Control Register 5.1.7.28/
3038_9A78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT52_CLR) 552
Access Control Register 5.1.7.29/
3038_9A7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT52_TOG) 554
5.1.7.10/
3038_9A80 Target Register (CCM_TARGET_ROOT53) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9A84 Target Register (CCM_TARGET_ROOT53_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9A88 Target Register (CCM_TARGET_ROOT53_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9A8C Target Register (CCM_TARGET_ROOT53_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9A90 Miscellaneous Register (CCM_MISC53) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9A94 Miscellaneous Register (CCM_MISC_ROOT53_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9A98 Miscellaneous Register (CCM_MISC_ROOT53_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9A9C Miscellaneous Register (CCM_MISC_ROOT53_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9AA0 Post Divider Register (CCM_POST53) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9AA4 Post Divider Register (CCM_POST_ROOT53_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9AA8 Post Divider Register (CCM_POST_ROOT53_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9AAC Post Divider Register (CCM_POST_ROOT53_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9AB0 Pre Divider Register (CCM_PRE53) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 413
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_9AB4 Pre Divider Register (CCM_PRE_ROOT53_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9AB8 Pre Divider Register (CCM_PRE_ROOT53_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9ABC Pre Divider Register (CCM_PRE_ROOT53_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9AF0 Access Control Register (CCM_ACCESS_CTRL53) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9AF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT53_SET) 549
Access Control Register 5.1.7.28/
3038_9AF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT53_CLR) 552
Access Control Register 5.1.7.29/
3038_9AFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT53_TOG) 554
5.1.7.10/
3038_9B00 Target Register (CCM_TARGET_ROOT54) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9B04 Target Register (CCM_TARGET_ROOT54_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9B08 Target Register (CCM_TARGET_ROOT54_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9B0C Target Register (CCM_TARGET_ROOT54_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9B10 Miscellaneous Register (CCM_MISC54) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9B14 Miscellaneous Register (CCM_MISC_ROOT54_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9B18 Miscellaneous Register (CCM_MISC_ROOT54_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9B1C Miscellaneous Register (CCM_MISC_ROOT54_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9B20 Post Divider Register (CCM_POST54) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9B24 Post Divider Register (CCM_POST_ROOT54_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9B28 Post Divider Register (CCM_POST_ROOT54_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9B2C Post Divider Register (CCM_POST_ROOT54_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9B30 Pre Divider Register (CCM_PRE54) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9B34 Pre Divider Register (CCM_PRE_ROOT54_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9B38 Pre Divider Register (CCM_PRE_ROOT54_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

414 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_9B3C Pre Divider Register (CCM_PRE_ROOT54_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9B70 Access Control Register (CCM_ACCESS_CTRL54) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9B74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT54_SET) 549
Access Control Register 5.1.7.28/
3038_9B78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT54_CLR) 552
Access Control Register 5.1.7.29/
3038_9B7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT54_TOG) 554
5.1.7.10/
3038_9B80 Target Register (CCM_TARGET_ROOT55) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9B84 Target Register (CCM_TARGET_ROOT55_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9B88 Target Register (CCM_TARGET_ROOT55_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9B8C Target Register (CCM_TARGET_ROOT55_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9B90 Miscellaneous Register (CCM_MISC55) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9B94 Miscellaneous Register (CCM_MISC_ROOT55_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9B98 Miscellaneous Register (CCM_MISC_ROOT55_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9B9C Miscellaneous Register (CCM_MISC_ROOT55_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9BA0 Post Divider Register (CCM_POST55) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9BA4 Post Divider Register (CCM_POST_ROOT55_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9BA8 Post Divider Register (CCM_POST_ROOT55_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9BAC Post Divider Register (CCM_POST_ROOT55_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9BB0 Pre Divider Register (CCM_PRE55) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9BB4 Pre Divider Register (CCM_PRE_ROOT55_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9BB8 Pre Divider Register (CCM_PRE_ROOT55_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9BBC Pre Divider Register (CCM_PRE_ROOT55_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9BF0 Access Control Register (CCM_ACCESS_CTRL55) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 415
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_9BF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT55_SET) 549
Access Control Register 5.1.7.28/
3038_9BF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT55_CLR) 552
Access Control Register 5.1.7.29/
3038_9BFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT55_TOG) 554
5.1.7.10/
3038_9C00 Target Register (CCM_TARGET_ROOT56) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9C04 Target Register (CCM_TARGET_ROOT56_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9C08 Target Register (CCM_TARGET_ROOT56_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9C0C Target Register (CCM_TARGET_ROOT56_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9C10 Miscellaneous Register (CCM_MISC56) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9C14 Miscellaneous Register (CCM_MISC_ROOT56_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9C18 Miscellaneous Register (CCM_MISC_ROOT56_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9C1C Miscellaneous Register (CCM_MISC_ROOT56_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9C20 Post Divider Register (CCM_POST56) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9C24 Post Divider Register (CCM_POST_ROOT56_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9C28 Post Divider Register (CCM_POST_ROOT56_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9C2C Post Divider Register (CCM_POST_ROOT56_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9C30 Pre Divider Register (CCM_PRE56) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9C34 Pre Divider Register (CCM_PRE_ROOT56_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9C38 Pre Divider Register (CCM_PRE_ROOT56_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9C3C Pre Divider Register (CCM_PRE_ROOT56_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9C70 Access Control Register (CCM_ACCESS_CTRL56) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9C74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT56_SET) 549
Access Control Register 5.1.7.28/
3038_9C78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT56_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

416 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_9C7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT56_TOG) 554
5.1.7.10/
3038_9C80 Target Register (CCM_TARGET_ROOT57) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9C84 Target Register (CCM_TARGET_ROOT57_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9C88 Target Register (CCM_TARGET_ROOT57_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9C8C Target Register (CCM_TARGET_ROOT57_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9C90 Miscellaneous Register (CCM_MISC57) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9C94 Miscellaneous Register (CCM_MISC_ROOT57_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9C98 Miscellaneous Register (CCM_MISC_ROOT57_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9C9C Miscellaneous Register (CCM_MISC_ROOT57_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9CA0 Post Divider Register (CCM_POST57) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9CA4 Post Divider Register (CCM_POST_ROOT57_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9CA8 Post Divider Register (CCM_POST_ROOT57_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9CAC Post Divider Register (CCM_POST_ROOT57_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9CB0 Pre Divider Register (CCM_PRE57) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9CB4 Pre Divider Register (CCM_PRE_ROOT57_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9CB8 Pre Divider Register (CCM_PRE_ROOT57_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9CBC Pre Divider Register (CCM_PRE_ROOT57_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9CF0 Access Control Register (CCM_ACCESS_CTRL57) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9CF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT57_SET) 549
Access Control Register 5.1.7.28/
3038_9CF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT57_CLR) 552
Access Control Register 5.1.7.29/
3038_9CFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT57_TOG) 554
5.1.7.10/
3038_9D00 Target Register (CCM_TARGET_ROOT58) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 417
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_9D04 Target Register (CCM_TARGET_ROOT58_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9D08 Target Register (CCM_TARGET_ROOT58_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9D0C Target Register (CCM_TARGET_ROOT58_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9D10 Miscellaneous Register (CCM_MISC58) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9D14 Miscellaneous Register (CCM_MISC_ROOT58_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9D18 Miscellaneous Register (CCM_MISC_ROOT58_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9D1C Miscellaneous Register (CCM_MISC_ROOT58_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9D20 Post Divider Register (CCM_POST58) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9D24 Post Divider Register (CCM_POST_ROOT58_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9D28 Post Divider Register (CCM_POST_ROOT58_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9D2C Post Divider Register (CCM_POST_ROOT58_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9D30 Pre Divider Register (CCM_PRE58) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9D34 Pre Divider Register (CCM_PRE_ROOT58_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9D38 Pre Divider Register (CCM_PRE_ROOT58_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9D3C Pre Divider Register (CCM_PRE_ROOT58_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9D70 Access Control Register (CCM_ACCESS_CTRL58) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9D74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT58_SET) 549
Access Control Register 5.1.7.28/
3038_9D78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT58_CLR) 552
Access Control Register 5.1.7.29/
3038_9D7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT58_TOG) 554
5.1.7.10/
3038_9D80 Target Register (CCM_TARGET_ROOT59) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9D84 Target Register (CCM_TARGET_ROOT59_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9D88 Target Register (CCM_TARGET_ROOT59_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

418 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_9D8C Target Register (CCM_TARGET_ROOT59_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9D90 Miscellaneous Register (CCM_MISC59) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9D94 Miscellaneous Register (CCM_MISC_ROOT59_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9D98 Miscellaneous Register (CCM_MISC_ROOT59_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9D9C Miscellaneous Register (CCM_MISC_ROOT59_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9DA0 Post Divider Register (CCM_POST59) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9DA4 Post Divider Register (CCM_POST_ROOT59_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9DA8 Post Divider Register (CCM_POST_ROOT59_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9DAC Post Divider Register (CCM_POST_ROOT59_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9DB0 Pre Divider Register (CCM_PRE59) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9DB4 Pre Divider Register (CCM_PRE_ROOT59_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9DB8 Pre Divider Register (CCM_PRE_ROOT59_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9DBC Pre Divider Register (CCM_PRE_ROOT59_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9DF0 Access Control Register (CCM_ACCESS_CTRL59) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9DF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT59_SET) 549
Access Control Register 5.1.7.28/
3038_9DF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT59_CLR) 552
Access Control Register 5.1.7.29/
3038_9DFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT59_TOG) 554
5.1.7.10/
3038_9E00 Target Register (CCM_TARGET_ROOT60) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9E04 Target Register (CCM_TARGET_ROOT60_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9E08 Target Register (CCM_TARGET_ROOT60_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9E0C Target Register (CCM_TARGET_ROOT60_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9E10 Miscellaneous Register (CCM_MISC60) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 419
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_9E14 Miscellaneous Register (CCM_MISC_ROOT60_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9E18 Miscellaneous Register (CCM_MISC_ROOT60_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9E1C Miscellaneous Register (CCM_MISC_ROOT60_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9E20 Post Divider Register (CCM_POST60) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9E24 Post Divider Register (CCM_POST_ROOT60_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9E28 Post Divider Register (CCM_POST_ROOT60_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9E2C Post Divider Register (CCM_POST_ROOT60_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9E30 Pre Divider Register (CCM_PRE60) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9E34 Pre Divider Register (CCM_PRE_ROOT60_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9E38 Pre Divider Register (CCM_PRE_ROOT60_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9E3C Pre Divider Register (CCM_PRE_ROOT60_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9E70 Access Control Register (CCM_ACCESS_CTRL60) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9E74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT60_SET) 549
Access Control Register 5.1.7.28/
3038_9E78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT60_CLR) 552
Access Control Register 5.1.7.29/
3038_9E7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT60_TOG) 554
5.1.7.10/
3038_9E80 Target Register (CCM_TARGET_ROOT61) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9E84 Target Register (CCM_TARGET_ROOT61_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9E88 Target Register (CCM_TARGET_ROOT61_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9E8C Target Register (CCM_TARGET_ROOT61_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9E90 Miscellaneous Register (CCM_MISC61) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9E94 Miscellaneous Register (CCM_MISC_ROOT61_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9E98 Miscellaneous Register (CCM_MISC_ROOT61_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

420 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_9E9C Miscellaneous Register (CCM_MISC_ROOT61_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9EA0 Post Divider Register (CCM_POST61) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9EA4 Post Divider Register (CCM_POST_ROOT61_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9EA8 Post Divider Register (CCM_POST_ROOT61_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9EAC Post Divider Register (CCM_POST_ROOT61_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9EB0 Pre Divider Register (CCM_PRE61) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9EB4 Pre Divider Register (CCM_PRE_ROOT61_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9EB8 Pre Divider Register (CCM_PRE_ROOT61_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9EBC Pre Divider Register (CCM_PRE_ROOT61_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9EF0 Access Control Register (CCM_ACCESS_CTRL61) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9EF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT61_SET) 549
Access Control Register 5.1.7.28/
3038_9EF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT61_CLR) 552
Access Control Register 5.1.7.29/
3038_9EFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT61_TOG) 554
5.1.7.10/
3038_9F00 Target Register (CCM_TARGET_ROOT62) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9F04 Target Register (CCM_TARGET_ROOT62_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9F08 Target Register (CCM_TARGET_ROOT62_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9F0C Target Register (CCM_TARGET_ROOT62_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9F10 Miscellaneous Register (CCM_MISC62) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9F14 Miscellaneous Register (CCM_MISC_ROOT62_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9F18 Miscellaneous Register (CCM_MISC_ROOT62_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9F1C Miscellaneous Register (CCM_MISC_ROOT62_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9F20 Post Divider Register (CCM_POST62) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 421
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_9F24 Post Divider Register (CCM_POST_ROOT62_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9F28 Post Divider Register (CCM_POST_ROOT62_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_9F2C Post Divider Register (CCM_POST_ROOT62_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9F30 Pre Divider Register (CCM_PRE62) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9F34 Pre Divider Register (CCM_PRE_ROOT62_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9F38 Pre Divider Register (CCM_PRE_ROOT62_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9F3C Pre Divider Register (CCM_PRE_ROOT62_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9F70 Access Control Register (CCM_ACCESS_CTRL62) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9F74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT62_SET) 549
Access Control Register 5.1.7.28/
3038_9F78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT62_CLR) 552
Access Control Register 5.1.7.29/
3038_9F7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT62_TOG) 554
5.1.7.10/
3038_9F80 Target Register (CCM_TARGET_ROOT63) 32 R/W 1000_0000h
511
5.1.7.11/
3038_9F84 Target Register (CCM_TARGET_ROOT63_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_9F88 Target Register (CCM_TARGET_ROOT63_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_9F8C Target Register (CCM_TARGET_ROOT63_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_9F90 Miscellaneous Register (CCM_MISC63) 32 R/W 0000_0000h
519
5.1.7.15/
3038_9F94 Miscellaneous Register (CCM_MISC_ROOT63_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_9F98 Miscellaneous Register (CCM_MISC_ROOT63_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_9F9C Miscellaneous Register (CCM_MISC_ROOT63_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_9FA0 Post Divider Register (CCM_POST63) 32 R/W 0000_0000h
523
5.1.7.19/
3038_9FA4 Post Divider Register (CCM_POST_ROOT63_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_9FA8 Post Divider Register (CCM_POST_ROOT63_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

422 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_9FAC Post Divider Register (CCM_POST_ROOT63_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_9FB0 Pre Divider Register (CCM_PRE63) 32 R/W 1000_0000h
535
5.1.7.23/
3038_9FB4 Pre Divider Register (CCM_PRE_ROOT63_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_9FB8 Pre Divider Register (CCM_PRE_ROOT63_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_9FBC Pre Divider Register (CCM_PRE_ROOT63_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_9FF0 Access Control Register (CCM_ACCESS_CTRL63) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_9FF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT63_SET) 549
Access Control Register 5.1.7.28/
3038_9FF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT63_CLR) 552
Access Control Register 5.1.7.29/
3038_9FFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT63_TOG) 554
5.1.7.10/
3038_A000 Target Register (CCM_TARGET_ROOT64) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A004 Target Register (CCM_TARGET_ROOT64_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A008 Target Register (CCM_TARGET_ROOT64_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A00C Target Register (CCM_TARGET_ROOT64_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A010 Miscellaneous Register (CCM_MISC64) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A014 Miscellaneous Register (CCM_MISC_ROOT64_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A018 Miscellaneous Register (CCM_MISC_ROOT64_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A01C Miscellaneous Register (CCM_MISC_ROOT64_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A020 Post Divider Register (CCM_POST64) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A024 Post Divider Register (CCM_POST_ROOT64_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A028 Post Divider Register (CCM_POST_ROOT64_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A02C Post Divider Register (CCM_POST_ROOT64_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A030 Pre Divider Register (CCM_PRE64) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 423
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_A034 Pre Divider Register (CCM_PRE_ROOT64_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A038 Pre Divider Register (CCM_PRE_ROOT64_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A03C Pre Divider Register (CCM_PRE_ROOT64_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A070 Access Control Register (CCM_ACCESS_CTRL64) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A074 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT64_SET) 549
Access Control Register 5.1.7.28/
3038_A078 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT64_CLR) 552
Access Control Register 5.1.7.29/
3038_A07C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT64_TOG) 554
5.1.7.10/
3038_A080 Target Register (CCM_TARGET_ROOT65) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A084 Target Register (CCM_TARGET_ROOT65_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A088 Target Register (CCM_TARGET_ROOT65_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A08C Target Register (CCM_TARGET_ROOT65_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A090 Miscellaneous Register (CCM_MISC65) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A094 Miscellaneous Register (CCM_MISC_ROOT65_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A098 Miscellaneous Register (CCM_MISC_ROOT65_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A09C Miscellaneous Register (CCM_MISC_ROOT65_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A0A0 Post Divider Register (CCM_POST65) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A0A4 Post Divider Register (CCM_POST_ROOT65_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A0A8 Post Divider Register (CCM_POST_ROOT65_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A0AC Post Divider Register (CCM_POST_ROOT65_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A0B0 Pre Divider Register (CCM_PRE65) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A0B4 Pre Divider Register (CCM_PRE_ROOT65_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A0B8 Pre Divider Register (CCM_PRE_ROOT65_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

424 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_A0BC Pre Divider Register (CCM_PRE_ROOT65_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A0F0 Access Control Register (CCM_ACCESS_CTRL65) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A0F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT65_SET) 549
Access Control Register 5.1.7.28/
3038_A0F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT65_CLR) 552
Access Control Register 5.1.7.29/
3038_A0FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT65_TOG) 554
5.1.7.10/
3038_A100 Target Register (CCM_TARGET_ROOT66) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A104 Target Register (CCM_TARGET_ROOT66_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A108 Target Register (CCM_TARGET_ROOT66_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A10C Target Register (CCM_TARGET_ROOT66_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A110 Miscellaneous Register (CCM_MISC66) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A114 Miscellaneous Register (CCM_MISC_ROOT66_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A118 Miscellaneous Register (CCM_MISC_ROOT66_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A11C Miscellaneous Register (CCM_MISC_ROOT66_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A120 Post Divider Register (CCM_POST66) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A124 Post Divider Register (CCM_POST_ROOT66_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A128 Post Divider Register (CCM_POST_ROOT66_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A12C Post Divider Register (CCM_POST_ROOT66_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A130 Pre Divider Register (CCM_PRE66) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A134 Pre Divider Register (CCM_PRE_ROOT66_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A138 Pre Divider Register (CCM_PRE_ROOT66_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A13C Pre Divider Register (CCM_PRE_ROOT66_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A170 Access Control Register (CCM_ACCESS_CTRL66) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 425
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_A174 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT66_SET) 549
Access Control Register 5.1.7.28/
3038_A178 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT66_CLR) 552
Access Control Register 5.1.7.29/
3038_A17C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT66_TOG) 554
5.1.7.10/
3038_A180 Target Register (CCM_TARGET_ROOT67) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A184 Target Register (CCM_TARGET_ROOT67_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A188 Target Register (CCM_TARGET_ROOT67_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A18C Target Register (CCM_TARGET_ROOT67_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A190 Miscellaneous Register (CCM_MISC67) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A194 Miscellaneous Register (CCM_MISC_ROOT67_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A198 Miscellaneous Register (CCM_MISC_ROOT67_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A19C Miscellaneous Register (CCM_MISC_ROOT67_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A1A0 Post Divider Register (CCM_POST67) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A1A4 Post Divider Register (CCM_POST_ROOT67_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A1A8 Post Divider Register (CCM_POST_ROOT67_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A1AC Post Divider Register (CCM_POST_ROOT67_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A1B0 Pre Divider Register (CCM_PRE67) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A1B4 Pre Divider Register (CCM_PRE_ROOT67_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A1B8 Pre Divider Register (CCM_PRE_ROOT67_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A1BC Pre Divider Register (CCM_PRE_ROOT67_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A1F0 Access Control Register (CCM_ACCESS_CTRL67) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A1F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT67_SET) 549
Access Control Register 5.1.7.28/
3038_A1F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT67_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

426 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_A1FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT67_TOG) 554
5.1.7.10/
3038_A200 Target Register (CCM_TARGET_ROOT68) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A204 Target Register (CCM_TARGET_ROOT68_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A208 Target Register (CCM_TARGET_ROOT68_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A20C Target Register (CCM_TARGET_ROOT68_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A210 Miscellaneous Register (CCM_MISC68) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A214 Miscellaneous Register (CCM_MISC_ROOT68_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A218 Miscellaneous Register (CCM_MISC_ROOT68_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A21C Miscellaneous Register (CCM_MISC_ROOT68_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A220 Post Divider Register (CCM_POST68) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A224 Post Divider Register (CCM_POST_ROOT68_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A228 Post Divider Register (CCM_POST_ROOT68_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A22C Post Divider Register (CCM_POST_ROOT68_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A230 Pre Divider Register (CCM_PRE68) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A234 Pre Divider Register (CCM_PRE_ROOT68_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A238 Pre Divider Register (CCM_PRE_ROOT68_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A23C Pre Divider Register (CCM_PRE_ROOT68_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A270 Access Control Register (CCM_ACCESS_CTRL68) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A274 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT68_SET) 549
Access Control Register 5.1.7.28/
3038_A278 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT68_CLR) 552
Access Control Register 5.1.7.29/
3038_A27C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT68_TOG) 554
5.1.7.10/
3038_A280 Target Register (CCM_TARGET_ROOT69) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 427
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_A284 Target Register (CCM_TARGET_ROOT69_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A288 Target Register (CCM_TARGET_ROOT69_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A28C Target Register (CCM_TARGET_ROOT69_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A290 Miscellaneous Register (CCM_MISC69) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A294 Miscellaneous Register (CCM_MISC_ROOT69_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A298 Miscellaneous Register (CCM_MISC_ROOT69_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A29C Miscellaneous Register (CCM_MISC_ROOT69_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A2A0 Post Divider Register (CCM_POST69) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A2A4 Post Divider Register (CCM_POST_ROOT69_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A2A8 Post Divider Register (CCM_POST_ROOT69_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A2AC Post Divider Register (CCM_POST_ROOT69_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A2B0 Pre Divider Register (CCM_PRE69) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A2B4 Pre Divider Register (CCM_PRE_ROOT69_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A2B8 Pre Divider Register (CCM_PRE_ROOT69_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A2BC Pre Divider Register (CCM_PRE_ROOT69_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A2F0 Access Control Register (CCM_ACCESS_CTRL69) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A2F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT69_SET) 549
Access Control Register 5.1.7.28/
3038_A2F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT69_CLR) 552
Access Control Register 5.1.7.29/
3038_A2FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT69_TOG) 554
5.1.7.10/
3038_A300 Target Register (CCM_TARGET_ROOT70) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A304 Target Register (CCM_TARGET_ROOT70_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A308 Target Register (CCM_TARGET_ROOT70_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

428 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_A30C Target Register (CCM_TARGET_ROOT70_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A310 Miscellaneous Register (CCM_MISC70) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A314 Miscellaneous Register (CCM_MISC_ROOT70_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A318 Miscellaneous Register (CCM_MISC_ROOT70_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A31C Miscellaneous Register (CCM_MISC_ROOT70_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A320 Post Divider Register (CCM_POST70) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A324 Post Divider Register (CCM_POST_ROOT70_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A328 Post Divider Register (CCM_POST_ROOT70_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A32C Post Divider Register (CCM_POST_ROOT70_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A330 Pre Divider Register (CCM_PRE70) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A334 Pre Divider Register (CCM_PRE_ROOT70_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A338 Pre Divider Register (CCM_PRE_ROOT70_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A33C Pre Divider Register (CCM_PRE_ROOT70_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A370 Access Control Register (CCM_ACCESS_CTRL70) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A374 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT70_SET) 549
Access Control Register 5.1.7.28/
3038_A378 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT70_CLR) 552
Access Control Register 5.1.7.29/
3038_A37C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT70_TOG) 554
5.1.7.10/
3038_A380 Target Register (CCM_TARGET_ROOT71) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A384 Target Register (CCM_TARGET_ROOT71_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A388 Target Register (CCM_TARGET_ROOT71_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A38C Target Register (CCM_TARGET_ROOT71_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A390 Miscellaneous Register (CCM_MISC71) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 429
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_A394 Miscellaneous Register (CCM_MISC_ROOT71_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A398 Miscellaneous Register (CCM_MISC_ROOT71_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A39C Miscellaneous Register (CCM_MISC_ROOT71_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A3A0 Post Divider Register (CCM_POST71) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A3A4 Post Divider Register (CCM_POST_ROOT71_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A3A8 Post Divider Register (CCM_POST_ROOT71_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A3AC Post Divider Register (CCM_POST_ROOT71_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A3B0 Pre Divider Register (CCM_PRE71) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A3B4 Pre Divider Register (CCM_PRE_ROOT71_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A3B8 Pre Divider Register (CCM_PRE_ROOT71_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A3BC Pre Divider Register (CCM_PRE_ROOT71_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A3F0 Access Control Register (CCM_ACCESS_CTRL71) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A3F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT71_SET) 549
Access Control Register 5.1.7.28/
3038_A3F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT71_CLR) 552
Access Control Register 5.1.7.29/
3038_A3FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT71_TOG) 554
5.1.7.10/
3038_A400 Target Register (CCM_TARGET_ROOT72) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A404 Target Register (CCM_TARGET_ROOT72_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A408 Target Register (CCM_TARGET_ROOT72_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A40C Target Register (CCM_TARGET_ROOT72_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A410 Miscellaneous Register (CCM_MISC72) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A414 Miscellaneous Register (CCM_MISC_ROOT72_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A418 Miscellaneous Register (CCM_MISC_ROOT72_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

430 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_A41C Miscellaneous Register (CCM_MISC_ROOT72_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A420 Post Divider Register (CCM_POST72) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A424 Post Divider Register (CCM_POST_ROOT72_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A428 Post Divider Register (CCM_POST_ROOT72_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A42C Post Divider Register (CCM_POST_ROOT72_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A430 Pre Divider Register (CCM_PRE72) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A434 Pre Divider Register (CCM_PRE_ROOT72_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A438 Pre Divider Register (CCM_PRE_ROOT72_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A43C Pre Divider Register (CCM_PRE_ROOT72_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A470 Access Control Register (CCM_ACCESS_CTRL72) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A474 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT72_SET) 549
Access Control Register 5.1.7.28/
3038_A478 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT72_CLR) 552
Access Control Register 5.1.7.29/
3038_A47C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT72_TOG) 554
5.1.7.10/
3038_A480 Target Register (CCM_TARGET_ROOT73) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A484 Target Register (CCM_TARGET_ROOT73_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A488 Target Register (CCM_TARGET_ROOT73_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A48C Target Register (CCM_TARGET_ROOT73_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A490 Miscellaneous Register (CCM_MISC73) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A494 Miscellaneous Register (CCM_MISC_ROOT73_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A498 Miscellaneous Register (CCM_MISC_ROOT73_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A49C Miscellaneous Register (CCM_MISC_ROOT73_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A4A0 Post Divider Register (CCM_POST73) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 431
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_A4A4 Post Divider Register (CCM_POST_ROOT73_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A4A8 Post Divider Register (CCM_POST_ROOT73_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A4AC Post Divider Register (CCM_POST_ROOT73_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A4B0 Pre Divider Register (CCM_PRE73) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A4B4 Pre Divider Register (CCM_PRE_ROOT73_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A4B8 Pre Divider Register (CCM_PRE_ROOT73_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A4BC Pre Divider Register (CCM_PRE_ROOT73_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A4F0 Access Control Register (CCM_ACCESS_CTRL73) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A4F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT73_SET) 549
Access Control Register 5.1.7.28/
3038_A4F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT73_CLR) 552
Access Control Register 5.1.7.29/
3038_A4FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT73_TOG) 554
5.1.7.10/
3038_A500 Target Register (CCM_TARGET_ROOT74) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A504 Target Register (CCM_TARGET_ROOT74_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A508 Target Register (CCM_TARGET_ROOT74_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A50C Target Register (CCM_TARGET_ROOT74_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A510 Miscellaneous Register (CCM_MISC74) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A514 Miscellaneous Register (CCM_MISC_ROOT74_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A518 Miscellaneous Register (CCM_MISC_ROOT74_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A51C Miscellaneous Register (CCM_MISC_ROOT74_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A520 Post Divider Register (CCM_POST74) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A524 Post Divider Register (CCM_POST_ROOT74_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A528 Post Divider Register (CCM_POST_ROOT74_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

432 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_A52C Post Divider Register (CCM_POST_ROOT74_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A530 Pre Divider Register (CCM_PRE74) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A534 Pre Divider Register (CCM_PRE_ROOT74_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A538 Pre Divider Register (CCM_PRE_ROOT74_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A53C Pre Divider Register (CCM_PRE_ROOT74_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A570 Access Control Register (CCM_ACCESS_CTRL74) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A574 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT74_SET) 549
Access Control Register 5.1.7.28/
3038_A578 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT74_CLR) 552
Access Control Register 5.1.7.29/
3038_A57C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT74_TOG) 554
5.1.7.10/
3038_A580 Target Register (CCM_TARGET_ROOT75) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A584 Target Register (CCM_TARGET_ROOT75_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A588 Target Register (CCM_TARGET_ROOT75_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A58C Target Register (CCM_TARGET_ROOT75_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A590 Miscellaneous Register (CCM_MISC75) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A594 Miscellaneous Register (CCM_MISC_ROOT75_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A598 Miscellaneous Register (CCM_MISC_ROOT75_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A59C Miscellaneous Register (CCM_MISC_ROOT75_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A5A0 Post Divider Register (CCM_POST75) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A5A4 Post Divider Register (CCM_POST_ROOT75_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A5A8 Post Divider Register (CCM_POST_ROOT75_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A5AC Post Divider Register (CCM_POST_ROOT75_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A5B0 Pre Divider Register (CCM_PRE75) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 433
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_A5B4 Pre Divider Register (CCM_PRE_ROOT75_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A5B8 Pre Divider Register (CCM_PRE_ROOT75_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A5BC Pre Divider Register (CCM_PRE_ROOT75_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A5F0 Access Control Register (CCM_ACCESS_CTRL75) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A5F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT75_SET) 549
Access Control Register 5.1.7.28/
3038_A5F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT75_CLR) 552
Access Control Register 5.1.7.29/
3038_A5FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT75_TOG) 554
5.1.7.10/
3038_A600 Target Register (CCM_TARGET_ROOT76) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A604 Target Register (CCM_TARGET_ROOT76_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A608 Target Register (CCM_TARGET_ROOT76_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A60C Target Register (CCM_TARGET_ROOT76_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A610 Miscellaneous Register (CCM_MISC76) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A614 Miscellaneous Register (CCM_MISC_ROOT76_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A618 Miscellaneous Register (CCM_MISC_ROOT76_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A61C Miscellaneous Register (CCM_MISC_ROOT76_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A620 Post Divider Register (CCM_POST76) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A624 Post Divider Register (CCM_POST_ROOT76_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A628 Post Divider Register (CCM_POST_ROOT76_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A62C Post Divider Register (CCM_POST_ROOT76_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A630 Pre Divider Register (CCM_PRE76) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A634 Pre Divider Register (CCM_PRE_ROOT76_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A638 Pre Divider Register (CCM_PRE_ROOT76_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

434 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_A63C Pre Divider Register (CCM_PRE_ROOT76_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A670 Access Control Register (CCM_ACCESS_CTRL76) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A674 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT76_SET) 549
Access Control Register 5.1.7.28/
3038_A678 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT76_CLR) 552
Access Control Register 5.1.7.29/
3038_A67C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT76_TOG) 554
5.1.7.10/
3038_A680 Target Register (CCM_TARGET_ROOT77) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A684 Target Register (CCM_TARGET_ROOT77_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A688 Target Register (CCM_TARGET_ROOT77_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A68C Target Register (CCM_TARGET_ROOT77_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A690 Miscellaneous Register (CCM_MISC77) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A694 Miscellaneous Register (CCM_MISC_ROOT77_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A698 Miscellaneous Register (CCM_MISC_ROOT77_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A69C Miscellaneous Register (CCM_MISC_ROOT77_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A6A0 Post Divider Register (CCM_POST77) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A6A4 Post Divider Register (CCM_POST_ROOT77_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A6A8 Post Divider Register (CCM_POST_ROOT77_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A6AC Post Divider Register (CCM_POST_ROOT77_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A6B0 Pre Divider Register (CCM_PRE77) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A6B4 Pre Divider Register (CCM_PRE_ROOT77_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A6B8 Pre Divider Register (CCM_PRE_ROOT77_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A6BC Pre Divider Register (CCM_PRE_ROOT77_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A6F0 Access Control Register (CCM_ACCESS_CTRL77) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 435
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_A6F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT77_SET) 549
Access Control Register 5.1.7.28/
3038_A6F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT77_CLR) 552
Access Control Register 5.1.7.29/
3038_A6FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT77_TOG) 554
5.1.7.10/
3038_A700 Target Register (CCM_TARGET_ROOT78) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A704 Target Register (CCM_TARGET_ROOT78_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A708 Target Register (CCM_TARGET_ROOT78_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A70C Target Register (CCM_TARGET_ROOT78_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A710 Miscellaneous Register (CCM_MISC78) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A714 Miscellaneous Register (CCM_MISC_ROOT78_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A718 Miscellaneous Register (CCM_MISC_ROOT78_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A71C Miscellaneous Register (CCM_MISC_ROOT78_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A720 Post Divider Register (CCM_POST78) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A724 Post Divider Register (CCM_POST_ROOT78_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A728 Post Divider Register (CCM_POST_ROOT78_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A72C Post Divider Register (CCM_POST_ROOT78_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A730 Pre Divider Register (CCM_PRE78) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A734 Pre Divider Register (CCM_PRE_ROOT78_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A738 Pre Divider Register (CCM_PRE_ROOT78_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A73C Pre Divider Register (CCM_PRE_ROOT78_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A770 Access Control Register (CCM_ACCESS_CTRL78) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A774 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT78_SET) 549
Access Control Register 5.1.7.28/
3038_A778 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT78_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

436 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_A77C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT78_TOG) 554
5.1.7.10/
3038_A780 Target Register (CCM_TARGET_ROOT79) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A784 Target Register (CCM_TARGET_ROOT79_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A788 Target Register (CCM_TARGET_ROOT79_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A78C Target Register (CCM_TARGET_ROOT79_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A790 Miscellaneous Register (CCM_MISC79) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A794 Miscellaneous Register (CCM_MISC_ROOT79_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A798 Miscellaneous Register (CCM_MISC_ROOT79_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A79C Miscellaneous Register (CCM_MISC_ROOT79_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A7A0 Post Divider Register (CCM_POST79) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A7A4 Post Divider Register (CCM_POST_ROOT79_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A7A8 Post Divider Register (CCM_POST_ROOT79_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A7AC Post Divider Register (CCM_POST_ROOT79_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A7B0 Pre Divider Register (CCM_PRE79) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A7B4 Pre Divider Register (CCM_PRE_ROOT79_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A7B8 Pre Divider Register (CCM_PRE_ROOT79_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A7BC Pre Divider Register (CCM_PRE_ROOT79_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A7F0 Access Control Register (CCM_ACCESS_CTRL79) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A7F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT79_SET) 549
Access Control Register 5.1.7.28/
3038_A7F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT79_CLR) 552
Access Control Register 5.1.7.29/
3038_A7FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT79_TOG) 554
5.1.7.10/
3038_A800 Target Register (CCM_TARGET_ROOT80) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 437
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_A804 Target Register (CCM_TARGET_ROOT80_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A808 Target Register (CCM_TARGET_ROOT80_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A80C Target Register (CCM_TARGET_ROOT80_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A810 Miscellaneous Register (CCM_MISC80) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A814 Miscellaneous Register (CCM_MISC_ROOT80_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A818 Miscellaneous Register (CCM_MISC_ROOT80_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A81C Miscellaneous Register (CCM_MISC_ROOT80_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A820 Post Divider Register (CCM_POST80) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A824 Post Divider Register (CCM_POST_ROOT80_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A828 Post Divider Register (CCM_POST_ROOT80_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A82C Post Divider Register (CCM_POST_ROOT80_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A830 Pre Divider Register (CCM_PRE80) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A834 Pre Divider Register (CCM_PRE_ROOT80_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A838 Pre Divider Register (CCM_PRE_ROOT80_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A83C Pre Divider Register (CCM_PRE_ROOT80_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A870 Access Control Register (CCM_ACCESS_CTRL80) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A874 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT80_SET) 549
Access Control Register 5.1.7.28/
3038_A878 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT80_CLR) 552
Access Control Register 5.1.7.29/
3038_A87C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT80_TOG) 554
5.1.7.10/
3038_A880 Target Register (CCM_TARGET_ROOT81) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A884 Target Register (CCM_TARGET_ROOT81_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A888 Target Register (CCM_TARGET_ROOT81_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

438 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_A88C Target Register (CCM_TARGET_ROOT81_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A890 Miscellaneous Register (CCM_MISC81) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A894 Miscellaneous Register (CCM_MISC_ROOT81_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A898 Miscellaneous Register (CCM_MISC_ROOT81_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A89C Miscellaneous Register (CCM_MISC_ROOT81_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A8A0 Post Divider Register (CCM_POST81) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A8A4 Post Divider Register (CCM_POST_ROOT81_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A8A8 Post Divider Register (CCM_POST_ROOT81_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A8AC Post Divider Register (CCM_POST_ROOT81_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A8B0 Pre Divider Register (CCM_PRE81) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A8B4 Pre Divider Register (CCM_PRE_ROOT81_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A8B8 Pre Divider Register (CCM_PRE_ROOT81_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A8BC Pre Divider Register (CCM_PRE_ROOT81_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A8F0 Access Control Register (CCM_ACCESS_CTRL81) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A8F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT81_SET) 549
Access Control Register 5.1.7.28/
3038_A8F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT81_CLR) 552
Access Control Register 5.1.7.29/
3038_A8FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT81_TOG) 554
5.1.7.10/
3038_A900 Target Register (CCM_TARGET_ROOT82) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A904 Target Register (CCM_TARGET_ROOT82_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A908 Target Register (CCM_TARGET_ROOT82_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A90C Target Register (CCM_TARGET_ROOT82_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A910 Miscellaneous Register (CCM_MISC82) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 439
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_A914 Miscellaneous Register (CCM_MISC_ROOT82_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A918 Miscellaneous Register (CCM_MISC_ROOT82_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_A91C Miscellaneous Register (CCM_MISC_ROOT82_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A920 Post Divider Register (CCM_POST82) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A924 Post Divider Register (CCM_POST_ROOT82_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A928 Post Divider Register (CCM_POST_ROOT82_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A92C Post Divider Register (CCM_POST_ROOT82_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A930 Pre Divider Register (CCM_PRE82) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A934 Pre Divider Register (CCM_PRE_ROOT82_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A938 Pre Divider Register (CCM_PRE_ROOT82_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A93C Pre Divider Register (CCM_PRE_ROOT82_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A970 Access Control Register (CCM_ACCESS_CTRL82) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A974 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT82_SET) 549
Access Control Register 5.1.7.28/
3038_A978 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT82_CLR) 552
Access Control Register 5.1.7.29/
3038_A97C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT82_TOG) 554
5.1.7.10/
3038_A980 Target Register (CCM_TARGET_ROOT83) 32 R/W 1000_0000h
511
5.1.7.11/
3038_A984 Target Register (CCM_TARGET_ROOT83_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_A988 Target Register (CCM_TARGET_ROOT83_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_A98C Target Register (CCM_TARGET_ROOT83_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_A990 Miscellaneous Register (CCM_MISC83) 32 R/W 0000_0000h
519
5.1.7.15/
3038_A994 Miscellaneous Register (CCM_MISC_ROOT83_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_A998 Miscellaneous Register (CCM_MISC_ROOT83_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

440 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_A99C Miscellaneous Register (CCM_MISC_ROOT83_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_A9A0 Post Divider Register (CCM_POST83) 32 R/W 0000_0000h
523
5.1.7.19/
3038_A9A4 Post Divider Register (CCM_POST_ROOT83_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_A9A8 Post Divider Register (CCM_POST_ROOT83_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_A9AC Post Divider Register (CCM_POST_ROOT83_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_A9B0 Pre Divider Register (CCM_PRE83) 32 R/W 1000_0000h
535
5.1.7.23/
3038_A9B4 Pre Divider Register (CCM_PRE_ROOT83_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_A9B8 Pre Divider Register (CCM_PRE_ROOT83_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_A9BC Pre Divider Register (CCM_PRE_ROOT83_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_A9F0 Access Control Register (CCM_ACCESS_CTRL83) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_A9F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT83_SET) 549
Access Control Register 5.1.7.28/
3038_A9F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT83_CLR) 552
Access Control Register 5.1.7.29/
3038_A9FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT83_TOG) 554
5.1.7.10/
3038_AA00 Target Register (CCM_TARGET_ROOT84) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AA04 Target Register (CCM_TARGET_ROOT84_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AA08 Target Register (CCM_TARGET_ROOT84_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AA0C Target Register (CCM_TARGET_ROOT84_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AA10 Miscellaneous Register (CCM_MISC84) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AA14 Miscellaneous Register (CCM_MISC_ROOT84_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AA18 Miscellaneous Register (CCM_MISC_ROOT84_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AA1C Miscellaneous Register (CCM_MISC_ROOT84_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AA20 Post Divider Register (CCM_POST84) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 441
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_AA24 Post Divider Register (CCM_POST_ROOT84_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AA28 Post Divider Register (CCM_POST_ROOT84_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AA2C Post Divider Register (CCM_POST_ROOT84_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AA30 Pre Divider Register (CCM_PRE84) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AA34 Pre Divider Register (CCM_PRE_ROOT84_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AA38 Pre Divider Register (CCM_PRE_ROOT84_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AA3C Pre Divider Register (CCM_PRE_ROOT84_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AA70 Access Control Register (CCM_ACCESS_CTRL84) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AA74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT84_SET) 549
Access Control Register 5.1.7.28/
3038_AA78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT84_CLR) 552
Access Control Register 5.1.7.29/
3038_AA7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT84_TOG) 554
5.1.7.10/
3038_AA80 Target Register (CCM_TARGET_ROOT85) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AA84 Target Register (CCM_TARGET_ROOT85_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AA88 Target Register (CCM_TARGET_ROOT85_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AA8C Target Register (CCM_TARGET_ROOT85_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AA90 Miscellaneous Register (CCM_MISC85) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AA94 Miscellaneous Register (CCM_MISC_ROOT85_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AA98 Miscellaneous Register (CCM_MISC_ROOT85_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AA9C Miscellaneous Register (CCM_MISC_ROOT85_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AAA0 Post Divider Register (CCM_POST85) 32 R/W 0000_0000h
523
5.1.7.19/
3038_AAA4 Post Divider Register (CCM_POST_ROOT85_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AAA8 Post Divider Register (CCM_POST_ROOT85_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

442 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_AAAC Post Divider Register (CCM_POST_ROOT85_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AAB0 Pre Divider Register (CCM_PRE85) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AAB4 Pre Divider Register (CCM_PRE_ROOT85_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AAB8 Pre Divider Register (CCM_PRE_ROOT85_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AABC Pre Divider Register (CCM_PRE_ROOT85_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AAF0 Access Control Register (CCM_ACCESS_CTRL85) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AAF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT85_SET) 549
Access Control Register 5.1.7.28/
3038_AAF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT85_CLR) 552
Access Control Register 5.1.7.29/
3038_AAFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT85_TOG) 554
5.1.7.10/
3038_AB00 Target Register (CCM_TARGET_ROOT86) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AB04 Target Register (CCM_TARGET_ROOT86_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AB08 Target Register (CCM_TARGET_ROOT86_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AB0C Target Register (CCM_TARGET_ROOT86_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AB10 Miscellaneous Register (CCM_MISC86) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AB14 Miscellaneous Register (CCM_MISC_ROOT86_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AB18 Miscellaneous Register (CCM_MISC_ROOT86_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AB1C Miscellaneous Register (CCM_MISC_ROOT86_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AB20 Post Divider Register (CCM_POST86) 32 R/W 0000_0000h
523
5.1.7.19/
3038_AB24 Post Divider Register (CCM_POST_ROOT86_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AB28 Post Divider Register (CCM_POST_ROOT86_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AB2C Post Divider Register (CCM_POST_ROOT86_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AB30 Pre Divider Register (CCM_PRE86) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 443
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_AB34 Pre Divider Register (CCM_PRE_ROOT86_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AB38 Pre Divider Register (CCM_PRE_ROOT86_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AB3C Pre Divider Register (CCM_PRE_ROOT86_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AB70 Access Control Register (CCM_ACCESS_CTRL86) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AB74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT86_SET) 549
Access Control Register 5.1.7.28/
3038_AB78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT86_CLR) 552
Access Control Register 5.1.7.29/
3038_AB7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT86_TOG) 554
5.1.7.10/
3038_AB80 Target Register (CCM_TARGET_ROOT87) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AB84 Target Register (CCM_TARGET_ROOT87_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AB88 Target Register (CCM_TARGET_ROOT87_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AB8C Target Register (CCM_TARGET_ROOT87_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AB90 Miscellaneous Register (CCM_MISC87) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AB94 Miscellaneous Register (CCM_MISC_ROOT87_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AB98 Miscellaneous Register (CCM_MISC_ROOT87_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AB9C Miscellaneous Register (CCM_MISC_ROOT87_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_ABA0 Post Divider Register (CCM_POST87) 32 R/W 0000_0000h
523
5.1.7.19/
3038_ABA4 Post Divider Register (CCM_POST_ROOT87_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_ABA8 Post Divider Register (CCM_POST_ROOT87_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_ABAC Post Divider Register (CCM_POST_ROOT87_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_ABB0 Pre Divider Register (CCM_PRE87) 32 R/W 1000_0000h
535
5.1.7.23/
3038_ABB4 Pre Divider Register (CCM_PRE_ROOT87_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_ABB8 Pre Divider Register (CCM_PRE_ROOT87_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

444 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_ABBC Pre Divider Register (CCM_PRE_ROOT87_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_ABF0 Access Control Register (CCM_ACCESS_CTRL87) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_ABF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT87_SET) 549
Access Control Register 5.1.7.28/
3038_ABF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT87_CLR) 552
Access Control Register 5.1.7.29/
3038_ABFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT87_TOG) 554
5.1.7.10/
3038_AC00 Target Register (CCM_TARGET_ROOT88) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AC04 Target Register (CCM_TARGET_ROOT88_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AC08 Target Register (CCM_TARGET_ROOT88_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AC0C Target Register (CCM_TARGET_ROOT88_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AC10 Miscellaneous Register (CCM_MISC88) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AC14 Miscellaneous Register (CCM_MISC_ROOT88_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AC18 Miscellaneous Register (CCM_MISC_ROOT88_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AC1C Miscellaneous Register (CCM_MISC_ROOT88_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AC20 Post Divider Register (CCM_POST88) 32 R/W 0000_0000h
523
5.1.7.19/
3038_AC24 Post Divider Register (CCM_POST_ROOT88_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AC28 Post Divider Register (CCM_POST_ROOT88_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AC2C Post Divider Register (CCM_POST_ROOT88_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AC30 Pre Divider Register (CCM_PRE88) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AC34 Pre Divider Register (CCM_PRE_ROOT88_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AC38 Pre Divider Register (CCM_PRE_ROOT88_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AC3C Pre Divider Register (CCM_PRE_ROOT88_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AC70 Access Control Register (CCM_ACCESS_CTRL88) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 445
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_AC74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT88_SET) 549
Access Control Register 5.1.7.28/
3038_AC78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT88_CLR) 552
Access Control Register 5.1.7.29/
3038_AC7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT88_TOG) 554
5.1.7.10/
3038_AC80 Target Register (CCM_TARGET_ROOT89) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AC84 Target Register (CCM_TARGET_ROOT89_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AC88 Target Register (CCM_TARGET_ROOT89_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AC8C Target Register (CCM_TARGET_ROOT89_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AC90 Miscellaneous Register (CCM_MISC89) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AC94 Miscellaneous Register (CCM_MISC_ROOT89_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AC98 Miscellaneous Register (CCM_MISC_ROOT89_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AC9C Miscellaneous Register (CCM_MISC_ROOT89_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_ACA0 Post Divider Register (CCM_POST89) 32 R/W 0000_0000h
523
5.1.7.19/
3038_ACA4 Post Divider Register (CCM_POST_ROOT89_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_ACA8 Post Divider Register (CCM_POST_ROOT89_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_ACAC Post Divider Register (CCM_POST_ROOT89_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_ACB0 Pre Divider Register (CCM_PRE89) 32 R/W 1000_0000h
535
5.1.7.23/
3038_ACB4 Pre Divider Register (CCM_PRE_ROOT89_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_ACB8 Pre Divider Register (CCM_PRE_ROOT89_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_ACBC Pre Divider Register (CCM_PRE_ROOT89_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_ACF0 Access Control Register (CCM_ACCESS_CTRL89) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_ACF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT89_SET) 549
Access Control Register 5.1.7.28/
3038_ACF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT89_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

446 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_ACFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT89_TOG) 554
5.1.7.10/
3038_AD00 Target Register (CCM_TARGET_ROOT90) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AD04 Target Register (CCM_TARGET_ROOT90_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AD08 Target Register (CCM_TARGET_ROOT90_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AD0C Target Register (CCM_TARGET_ROOT90_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AD10 Miscellaneous Register (CCM_MISC90) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AD14 Miscellaneous Register (CCM_MISC_ROOT90_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AD18 Miscellaneous Register (CCM_MISC_ROOT90_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AD1C Miscellaneous Register (CCM_MISC_ROOT90_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AD20 Post Divider Register (CCM_POST90) 32 R/W 0000_0000h
523
5.1.7.19/
3038_AD24 Post Divider Register (CCM_POST_ROOT90_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AD28 Post Divider Register (CCM_POST_ROOT90_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AD2C Post Divider Register (CCM_POST_ROOT90_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AD30 Pre Divider Register (CCM_PRE90) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AD34 Pre Divider Register (CCM_PRE_ROOT90_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AD38 Pre Divider Register (CCM_PRE_ROOT90_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AD3C Pre Divider Register (CCM_PRE_ROOT90_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AD70 Access Control Register (CCM_ACCESS_CTRL90) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AD74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT90_SET) 549
Access Control Register 5.1.7.28/
3038_AD78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT90_CLR) 552
Access Control Register 5.1.7.29/
3038_AD7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT90_TOG) 554
5.1.7.10/
3038_AD80 Target Register (CCM_TARGET_ROOT91) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 447
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_AD84 Target Register (CCM_TARGET_ROOT91_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AD88 Target Register (CCM_TARGET_ROOT91_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AD8C Target Register (CCM_TARGET_ROOT91_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AD90 Miscellaneous Register (CCM_MISC91) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AD94 Miscellaneous Register (CCM_MISC_ROOT91_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AD98 Miscellaneous Register (CCM_MISC_ROOT91_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AD9C Miscellaneous Register (CCM_MISC_ROOT91_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_ADA0 Post Divider Register (CCM_POST91) 32 R/W 0000_0000h
523
5.1.7.19/
3038_ADA4 Post Divider Register (CCM_POST_ROOT91_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_ADA8 Post Divider Register (CCM_POST_ROOT91_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_ADAC Post Divider Register (CCM_POST_ROOT91_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_ADB0 Pre Divider Register (CCM_PRE91) 32 R/W 1000_0000h
535
5.1.7.23/
3038_ADB4 Pre Divider Register (CCM_PRE_ROOT91_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_ADB8 Pre Divider Register (CCM_PRE_ROOT91_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_ADBC Pre Divider Register (CCM_PRE_ROOT91_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_ADF0 Access Control Register (CCM_ACCESS_CTRL91) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_ADF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT91_SET) 549
Access Control Register 5.1.7.28/
3038_ADF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT91_CLR) 552
Access Control Register 5.1.7.29/
3038_ADFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT91_TOG) 554
5.1.7.10/
3038_AE00 Target Register (CCM_TARGET_ROOT92) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AE04 Target Register (CCM_TARGET_ROOT92_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AE08 Target Register (CCM_TARGET_ROOT92_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

448 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_AE0C Target Register (CCM_TARGET_ROOT92_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AE10 Miscellaneous Register (CCM_MISC92) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AE14 Miscellaneous Register (CCM_MISC_ROOT92_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AE18 Miscellaneous Register (CCM_MISC_ROOT92_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AE1C Miscellaneous Register (CCM_MISC_ROOT92_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AE20 Post Divider Register (CCM_POST92) 32 R/W 0000_0000h
523
5.1.7.19/
3038_AE24 Post Divider Register (CCM_POST_ROOT92_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AE28 Post Divider Register (CCM_POST_ROOT92_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AE2C Post Divider Register (CCM_POST_ROOT92_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AE30 Pre Divider Register (CCM_PRE92) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AE34 Pre Divider Register (CCM_PRE_ROOT92_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AE38 Pre Divider Register (CCM_PRE_ROOT92_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AE3C Pre Divider Register (CCM_PRE_ROOT92_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AE70 Access Control Register (CCM_ACCESS_CTRL92) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AE74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT92_SET) 549
Access Control Register 5.1.7.28/
3038_AE78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT92_CLR) 552
Access Control Register 5.1.7.29/
3038_AE7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT92_TOG) 554
5.1.7.10/
3038_AE80 Target Register (CCM_TARGET_ROOT93) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AE84 Target Register (CCM_TARGET_ROOT93_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AE88 Target Register (CCM_TARGET_ROOT93_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AE8C Target Register (CCM_TARGET_ROOT93_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AE90 Miscellaneous Register (CCM_MISC93) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 449
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_AE94 Miscellaneous Register (CCM_MISC_ROOT93_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AE98 Miscellaneous Register (CCM_MISC_ROOT93_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AE9C Miscellaneous Register (CCM_MISC_ROOT93_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AEA0 Post Divider Register (CCM_POST93) 32 R/W 0000_0000h
523
5.1.7.19/
3038_AEA4 Post Divider Register (CCM_POST_ROOT93_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AEA8 Post Divider Register (CCM_POST_ROOT93_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AEAC Post Divider Register (CCM_POST_ROOT93_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AEB0 Pre Divider Register (CCM_PRE93) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AEB4 Pre Divider Register (CCM_PRE_ROOT93_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AEB8 Pre Divider Register (CCM_PRE_ROOT93_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AEBC Pre Divider Register (CCM_PRE_ROOT93_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AEF0 Access Control Register (CCM_ACCESS_CTRL93) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AEF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT93_SET) 549
Access Control Register 5.1.7.28/
3038_AEF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT93_CLR) 552
Access Control Register 5.1.7.29/
3038_AEFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT93_TOG) 554
5.1.7.10/
3038_AF00 Target Register (CCM_TARGET_ROOT94) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AF04 Target Register (CCM_TARGET_ROOT94_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AF08 Target Register (CCM_TARGET_ROOT94_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AF0C Target Register (CCM_TARGET_ROOT94_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AF10 Miscellaneous Register (CCM_MISC94) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AF14 Miscellaneous Register (CCM_MISC_ROOT94_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AF18 Miscellaneous Register (CCM_MISC_ROOT94_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

450 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_AF1C Miscellaneous Register (CCM_MISC_ROOT94_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AF20 Post Divider Register (CCM_POST94) 32 R/W 0000_0000h
523
5.1.7.19/
3038_AF24 Post Divider Register (CCM_POST_ROOT94_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AF28 Post Divider Register (CCM_POST_ROOT94_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AF2C Post Divider Register (CCM_POST_ROOT94_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AF30 Pre Divider Register (CCM_PRE94) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AF34 Pre Divider Register (CCM_PRE_ROOT94_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AF38 Pre Divider Register (CCM_PRE_ROOT94_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AF3C Pre Divider Register (CCM_PRE_ROOT94_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AF70 Access Control Register (CCM_ACCESS_CTRL94) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AF74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT94_SET) 549
Access Control Register 5.1.7.28/
3038_AF78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT94_CLR) 552
Access Control Register 5.1.7.29/
3038_AF7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT94_TOG) 554
5.1.7.10/
3038_AF80 Target Register (CCM_TARGET_ROOT95) 32 R/W 1000_0000h
511
5.1.7.11/
3038_AF84 Target Register (CCM_TARGET_ROOT95_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_AF88 Target Register (CCM_TARGET_ROOT95_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_AF8C Target Register (CCM_TARGET_ROOT95_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_AF90 Miscellaneous Register (CCM_MISC95) 32 R/W 0000_0000h
519
5.1.7.15/
3038_AF94 Miscellaneous Register (CCM_MISC_ROOT95_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_AF98 Miscellaneous Register (CCM_MISC_ROOT95_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_AF9C Miscellaneous Register (CCM_MISC_ROOT95_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_AFA0 Post Divider Register (CCM_POST95) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 451
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_AFA4 Post Divider Register (CCM_POST_ROOT95_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_AFA8 Post Divider Register (CCM_POST_ROOT95_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_AFAC Post Divider Register (CCM_POST_ROOT95_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_AFB0 Pre Divider Register (CCM_PRE95) 32 R/W 1000_0000h
535
5.1.7.23/
3038_AFB4 Pre Divider Register (CCM_PRE_ROOT95_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_AFB8 Pre Divider Register (CCM_PRE_ROOT95_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_AFBC Pre Divider Register (CCM_PRE_ROOT95_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_AFF0 Access Control Register (CCM_ACCESS_CTRL95) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_AFF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT95_SET) 549
Access Control Register 5.1.7.28/
3038_AFF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT95_CLR) 552
Access Control Register 5.1.7.29/
3038_AFFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT95_TOG) 554
5.1.7.10/
3038_B000 Target Register (CCM_TARGET_ROOT96) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B004 Target Register (CCM_TARGET_ROOT96_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B008 Target Register (CCM_TARGET_ROOT96_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B00C Target Register (CCM_TARGET_ROOT96_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B010 Miscellaneous Register (CCM_MISC96) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B014 Miscellaneous Register (CCM_MISC_ROOT96_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B018 Miscellaneous Register (CCM_MISC_ROOT96_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B01C Miscellaneous Register (CCM_MISC_ROOT96_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B020 Post Divider Register (CCM_POST96) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B024 Post Divider Register (CCM_POST_ROOT96_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B028 Post Divider Register (CCM_POST_ROOT96_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

452 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_B02C Post Divider Register (CCM_POST_ROOT96_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B030 Pre Divider Register (CCM_PRE96) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B034 Pre Divider Register (CCM_PRE_ROOT96_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B038 Pre Divider Register (CCM_PRE_ROOT96_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B03C Pre Divider Register (CCM_PRE_ROOT96_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B070 Access Control Register (CCM_ACCESS_CTRL96) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B074 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT96_SET) 549
Access Control Register 5.1.7.28/
3038_B078 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT96_CLR) 552
Access Control Register 5.1.7.29/
3038_B07C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT96_TOG) 554
5.1.7.10/
3038_B080 Target Register (CCM_TARGET_ROOT97) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B084 Target Register (CCM_TARGET_ROOT97_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B088 Target Register (CCM_TARGET_ROOT97_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B08C Target Register (CCM_TARGET_ROOT97_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B090 Miscellaneous Register (CCM_MISC97) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B094 Miscellaneous Register (CCM_MISC_ROOT97_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B098 Miscellaneous Register (CCM_MISC_ROOT97_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B09C Miscellaneous Register (CCM_MISC_ROOT97_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B0A0 Post Divider Register (CCM_POST97) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B0A4 Post Divider Register (CCM_POST_ROOT97_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B0A8 Post Divider Register (CCM_POST_ROOT97_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B0AC Post Divider Register (CCM_POST_ROOT97_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B0B0 Pre Divider Register (CCM_PRE97) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 453
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_B0B4 Pre Divider Register (CCM_PRE_ROOT97_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B0B8 Pre Divider Register (CCM_PRE_ROOT97_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B0BC Pre Divider Register (CCM_PRE_ROOT97_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B0F0 Access Control Register (CCM_ACCESS_CTRL97) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B0F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT97_SET) 549
Access Control Register 5.1.7.28/
3038_B0F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT97_CLR) 552
Access Control Register 5.1.7.29/
3038_B0FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT97_TOG) 554
5.1.7.10/
3038_B100 Target Register (CCM_TARGET_ROOT98) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B104 Target Register (CCM_TARGET_ROOT98_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B108 Target Register (CCM_TARGET_ROOT98_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B10C Target Register (CCM_TARGET_ROOT98_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B110 Miscellaneous Register (CCM_MISC98) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B114 Miscellaneous Register (CCM_MISC_ROOT98_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B118 Miscellaneous Register (CCM_MISC_ROOT98_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B11C Miscellaneous Register (CCM_MISC_ROOT98_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B120 Post Divider Register (CCM_POST98) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B124 Post Divider Register (CCM_POST_ROOT98_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B128 Post Divider Register (CCM_POST_ROOT98_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B12C Post Divider Register (CCM_POST_ROOT98_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B130 Pre Divider Register (CCM_PRE98) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B134 Pre Divider Register (CCM_PRE_ROOT98_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B138 Pre Divider Register (CCM_PRE_ROOT98_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

454 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_B13C Pre Divider Register (CCM_PRE_ROOT98_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B170 Access Control Register (CCM_ACCESS_CTRL98) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B174 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT98_SET) 549
Access Control Register 5.1.7.28/
3038_B178 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT98_CLR) 552
Access Control Register 5.1.7.29/
3038_B17C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT98_TOG) 554
5.1.7.10/
3038_B180 Target Register (CCM_TARGET_ROOT99) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B184 Target Register (CCM_TARGET_ROOT99_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B188 Target Register (CCM_TARGET_ROOT99_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B18C Target Register (CCM_TARGET_ROOT99_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B190 Miscellaneous Register (CCM_MISC99) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B194 Miscellaneous Register (CCM_MISC_ROOT99_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B198 Miscellaneous Register (CCM_MISC_ROOT99_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B19C Miscellaneous Register (CCM_MISC_ROOT99_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B1A0 Post Divider Register (CCM_POST99) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B1A4 Post Divider Register (CCM_POST_ROOT99_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B1A8 Post Divider Register (CCM_POST_ROOT99_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B1AC Post Divider Register (CCM_POST_ROOT99_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B1B0 Pre Divider Register (CCM_PRE99) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B1B4 Pre Divider Register (CCM_PRE_ROOT99_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B1B8 Pre Divider Register (CCM_PRE_ROOT99_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B1BC Pre Divider Register (CCM_PRE_ROOT99_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B1F0 Access Control Register (CCM_ACCESS_CTRL99) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 455
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_B1F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT99_SET) 549
Access Control Register 5.1.7.28/
3038_B1F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT99_CLR) 552
Access Control Register 5.1.7.29/
3038_B1FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT99_TOG) 554
5.1.7.10/
3038_B200 Target Register (CCM_TARGET_ROOT100) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B204 Target Register (CCM_TARGET_ROOT100_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B208 Target Register (CCM_TARGET_ROOT100_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B20C Target Register (CCM_TARGET_ROOT100_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B210 Miscellaneous Register (CCM_MISC100) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B214 Miscellaneous Register (CCM_MISC_ROOT100_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B218 Miscellaneous Register (CCM_MISC_ROOT100_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B21C Miscellaneous Register (CCM_MISC_ROOT100_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B220 Post Divider Register (CCM_POST100) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B224 Post Divider Register (CCM_POST_ROOT100_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B228 Post Divider Register (CCM_POST_ROOT100_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B22C Post Divider Register (CCM_POST_ROOT100_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B230 Pre Divider Register (CCM_PRE100) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B234 Pre Divider Register (CCM_PRE_ROOT100_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B238 Pre Divider Register (CCM_PRE_ROOT100_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B23C Pre Divider Register (CCM_PRE_ROOT100_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B270 Access Control Register (CCM_ACCESS_CTRL100) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B274 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT100_SET) 549
Access Control Register 5.1.7.28/
3038_B278 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT100_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

456 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_B27C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT100_TOG) 554
5.1.7.10/
3038_B280 Target Register (CCM_TARGET_ROOT101) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B284 Target Register (CCM_TARGET_ROOT101_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B288 Target Register (CCM_TARGET_ROOT101_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B28C Target Register (CCM_TARGET_ROOT101_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B290 Miscellaneous Register (CCM_MISC101) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B294 Miscellaneous Register (CCM_MISC_ROOT101_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B298 Miscellaneous Register (CCM_MISC_ROOT101_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B29C Miscellaneous Register (CCM_MISC_ROOT101_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B2A0 Post Divider Register (CCM_POST101) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B2A4 Post Divider Register (CCM_POST_ROOT101_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B2A8 Post Divider Register (CCM_POST_ROOT101_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B2AC Post Divider Register (CCM_POST_ROOT101_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B2B0 Pre Divider Register (CCM_PRE101) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B2B4 Pre Divider Register (CCM_PRE_ROOT101_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B2B8 Pre Divider Register (CCM_PRE_ROOT101_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B2BC Pre Divider Register (CCM_PRE_ROOT101_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B2F0 Access Control Register (CCM_ACCESS_CTRL101) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B2F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT101_SET) 549
Access Control Register 5.1.7.28/
3038_B2F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT101_CLR) 552
Access Control Register 5.1.7.29/
3038_B2FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT101_TOG) 554
5.1.7.10/
3038_B300 Target Register (CCM_TARGET_ROOT102) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 457
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_B304 Target Register (CCM_TARGET_ROOT102_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B308 Target Register (CCM_TARGET_ROOT102_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B30C Target Register (CCM_TARGET_ROOT102_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B310 Miscellaneous Register (CCM_MISC102) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B314 Miscellaneous Register (CCM_MISC_ROOT102_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B318 Miscellaneous Register (CCM_MISC_ROOT102_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B31C Miscellaneous Register (CCM_MISC_ROOT102_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B320 Post Divider Register (CCM_POST102) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B324 Post Divider Register (CCM_POST_ROOT102_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B328 Post Divider Register (CCM_POST_ROOT102_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B32C Post Divider Register (CCM_POST_ROOT102_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B330 Pre Divider Register (CCM_PRE102) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B334 Pre Divider Register (CCM_PRE_ROOT102_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B338 Pre Divider Register (CCM_PRE_ROOT102_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B33C Pre Divider Register (CCM_PRE_ROOT102_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B370 Access Control Register (CCM_ACCESS_CTRL102) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B374 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT102_SET) 549
Access Control Register 5.1.7.28/
3038_B378 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT102_CLR) 552
Access Control Register 5.1.7.29/
3038_B37C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT102_TOG) 554
5.1.7.10/
3038_B380 Target Register (CCM_TARGET_ROOT103) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B384 Target Register (CCM_TARGET_ROOT103_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B388 Target Register (CCM_TARGET_ROOT103_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

458 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_B38C Target Register (CCM_TARGET_ROOT103_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B390 Miscellaneous Register (CCM_MISC103) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B394 Miscellaneous Register (CCM_MISC_ROOT103_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B398 Miscellaneous Register (CCM_MISC_ROOT103_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B39C Miscellaneous Register (CCM_MISC_ROOT103_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B3A0 Post Divider Register (CCM_POST103) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B3A4 Post Divider Register (CCM_POST_ROOT103_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B3A8 Post Divider Register (CCM_POST_ROOT103_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B3AC Post Divider Register (CCM_POST_ROOT103_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B3B0 Pre Divider Register (CCM_PRE103) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B3B4 Pre Divider Register (CCM_PRE_ROOT103_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B3B8 Pre Divider Register (CCM_PRE_ROOT103_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B3BC Pre Divider Register (CCM_PRE_ROOT103_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B3F0 Access Control Register (CCM_ACCESS_CTRL103) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B3F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT103_SET) 549
Access Control Register 5.1.7.28/
3038_B3F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT103_CLR) 552
Access Control Register 5.1.7.29/
3038_B3FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT103_TOG) 554
5.1.7.10/
3038_B400 Target Register (CCM_TARGET_ROOT104) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B404 Target Register (CCM_TARGET_ROOT104_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B408 Target Register (CCM_TARGET_ROOT104_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B40C Target Register (CCM_TARGET_ROOT104_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B410 Miscellaneous Register (CCM_MISC104) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 459
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_B414 Miscellaneous Register (CCM_MISC_ROOT104_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B418 Miscellaneous Register (CCM_MISC_ROOT104_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B41C Miscellaneous Register (CCM_MISC_ROOT104_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B420 Post Divider Register (CCM_POST104) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B424 Post Divider Register (CCM_POST_ROOT104_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B428 Post Divider Register (CCM_POST_ROOT104_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B42C Post Divider Register (CCM_POST_ROOT104_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B430 Pre Divider Register (CCM_PRE104) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B434 Pre Divider Register (CCM_PRE_ROOT104_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B438 Pre Divider Register (CCM_PRE_ROOT104_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B43C Pre Divider Register (CCM_PRE_ROOT104_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B470 Access Control Register (CCM_ACCESS_CTRL104) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B474 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT104_SET) 549
Access Control Register 5.1.7.28/
3038_B478 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT104_CLR) 552
Access Control Register 5.1.7.29/
3038_B47C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT104_TOG) 554
5.1.7.10/
3038_B480 Target Register (CCM_TARGET_ROOT105) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B484 Target Register (CCM_TARGET_ROOT105_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B488 Target Register (CCM_TARGET_ROOT105_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B48C Target Register (CCM_TARGET_ROOT105_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B490 Miscellaneous Register (CCM_MISC105) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B494 Miscellaneous Register (CCM_MISC_ROOT105_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B498 Miscellaneous Register (CCM_MISC_ROOT105_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

460 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_B49C Miscellaneous Register (CCM_MISC_ROOT105_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B4A0 Post Divider Register (CCM_POST105) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B4A4 Post Divider Register (CCM_POST_ROOT105_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B4A8 Post Divider Register (CCM_POST_ROOT105_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B4AC Post Divider Register (CCM_POST_ROOT105_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B4B0 Pre Divider Register (CCM_PRE105) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B4B4 Pre Divider Register (CCM_PRE_ROOT105_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B4B8 Pre Divider Register (CCM_PRE_ROOT105_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B4BC Pre Divider Register (CCM_PRE_ROOT105_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B4F0 Access Control Register (CCM_ACCESS_CTRL105) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B4F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT105_SET) 549
Access Control Register 5.1.7.28/
3038_B4F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT105_CLR) 552
Access Control Register 5.1.7.29/
3038_B4FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT105_TOG) 554
5.1.7.10/
3038_B500 Target Register (CCM_TARGET_ROOT106) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B504 Target Register (CCM_TARGET_ROOT106_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B508 Target Register (CCM_TARGET_ROOT106_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B50C Target Register (CCM_TARGET_ROOT106_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B510 Miscellaneous Register (CCM_MISC106) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B514 Miscellaneous Register (CCM_MISC_ROOT106_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B518 Miscellaneous Register (CCM_MISC_ROOT106_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B51C Miscellaneous Register (CCM_MISC_ROOT106_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B520 Post Divider Register (CCM_POST106) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 461
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_B524 Post Divider Register (CCM_POST_ROOT106_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B528 Post Divider Register (CCM_POST_ROOT106_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B52C Post Divider Register (CCM_POST_ROOT106_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B530 Pre Divider Register (CCM_PRE106) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B534 Pre Divider Register (CCM_PRE_ROOT106_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B538 Pre Divider Register (CCM_PRE_ROOT106_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B53C Pre Divider Register (CCM_PRE_ROOT106_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B570 Access Control Register (CCM_ACCESS_CTRL106) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B574 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT106_SET) 549
Access Control Register 5.1.7.28/
3038_B578 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT106_CLR) 552
Access Control Register 5.1.7.29/
3038_B57C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT106_TOG) 554
5.1.7.10/
3038_B580 Target Register (CCM_TARGET_ROOT107) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B584 Target Register (CCM_TARGET_ROOT107_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B588 Target Register (CCM_TARGET_ROOT107_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B58C Target Register (CCM_TARGET_ROOT107_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B590 Miscellaneous Register (CCM_MISC107) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B594 Miscellaneous Register (CCM_MISC_ROOT107_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B598 Miscellaneous Register (CCM_MISC_ROOT107_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B59C Miscellaneous Register (CCM_MISC_ROOT107_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B5A0 Post Divider Register (CCM_POST107) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B5A4 Post Divider Register (CCM_POST_ROOT107_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B5A8 Post Divider Register (CCM_POST_ROOT107_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

462 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_B5AC Post Divider Register (CCM_POST_ROOT107_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B5B0 Pre Divider Register (CCM_PRE107) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B5B4 Pre Divider Register (CCM_PRE_ROOT107_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B5B8 Pre Divider Register (CCM_PRE_ROOT107_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B5BC Pre Divider Register (CCM_PRE_ROOT107_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B5F0 Access Control Register (CCM_ACCESS_CTRL107) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B5F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT107_SET) 549
Access Control Register 5.1.7.28/
3038_B5F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT107_CLR) 552
Access Control Register 5.1.7.29/
3038_B5FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT107_TOG) 554
5.1.7.10/
3038_B600 Target Register (CCM_TARGET_ROOT108) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B604 Target Register (CCM_TARGET_ROOT108_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B608 Target Register (CCM_TARGET_ROOT108_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B60C Target Register (CCM_TARGET_ROOT108_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B610 Miscellaneous Register (CCM_MISC108) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B614 Miscellaneous Register (CCM_MISC_ROOT108_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B618 Miscellaneous Register (CCM_MISC_ROOT108_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B61C Miscellaneous Register (CCM_MISC_ROOT108_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B620 Post Divider Register (CCM_POST108) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B624 Post Divider Register (CCM_POST_ROOT108_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B628 Post Divider Register (CCM_POST_ROOT108_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B62C Post Divider Register (CCM_POST_ROOT108_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B630 Pre Divider Register (CCM_PRE108) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 463
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_B634 Pre Divider Register (CCM_PRE_ROOT108_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B638 Pre Divider Register (CCM_PRE_ROOT108_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B63C Pre Divider Register (CCM_PRE_ROOT108_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B670 Access Control Register (CCM_ACCESS_CTRL108) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B674 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT108_SET) 549
Access Control Register 5.1.7.28/
3038_B678 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT108_CLR) 552
Access Control Register 5.1.7.29/
3038_B67C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT108_TOG) 554
5.1.7.10/
3038_B680 Target Register (CCM_TARGET_ROOT109) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B684 Target Register (CCM_TARGET_ROOT109_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B688 Target Register (CCM_TARGET_ROOT109_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B68C Target Register (CCM_TARGET_ROOT109_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B690 Miscellaneous Register (CCM_MISC109) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B694 Miscellaneous Register (CCM_MISC_ROOT109_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B698 Miscellaneous Register (CCM_MISC_ROOT109_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B69C Miscellaneous Register (CCM_MISC_ROOT109_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B6A0 Post Divider Register (CCM_POST109) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B6A4 Post Divider Register (CCM_POST_ROOT109_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B6A8 Post Divider Register (CCM_POST_ROOT109_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B6AC Post Divider Register (CCM_POST_ROOT109_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B6B0 Pre Divider Register (CCM_PRE109) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B6B4 Pre Divider Register (CCM_PRE_ROOT109_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B6B8 Pre Divider Register (CCM_PRE_ROOT109_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

464 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_B6BC Pre Divider Register (CCM_PRE_ROOT109_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B6F0 Access Control Register (CCM_ACCESS_CTRL109) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B6F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT109_SET) 549
Access Control Register 5.1.7.28/
3038_B6F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT109_CLR) 552
Access Control Register 5.1.7.29/
3038_B6FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT109_TOG) 554
5.1.7.10/
3038_B700 Target Register (CCM_TARGET_ROOT110) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B704 Target Register (CCM_TARGET_ROOT110_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B708 Target Register (CCM_TARGET_ROOT110_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B70C Target Register (CCM_TARGET_ROOT110_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B710 Miscellaneous Register (CCM_MISC110) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B714 Miscellaneous Register (CCM_MISC_ROOT110_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B718 Miscellaneous Register (CCM_MISC_ROOT110_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B71C Miscellaneous Register (CCM_MISC_ROOT110_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B720 Post Divider Register (CCM_POST110) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B724 Post Divider Register (CCM_POST_ROOT110_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B728 Post Divider Register (CCM_POST_ROOT110_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B72C Post Divider Register (CCM_POST_ROOT110_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B730 Pre Divider Register (CCM_PRE110) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B734 Pre Divider Register (CCM_PRE_ROOT110_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B738 Pre Divider Register (CCM_PRE_ROOT110_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B73C Pre Divider Register (CCM_PRE_ROOT110_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B770 Access Control Register (CCM_ACCESS_CTRL110) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 465
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_B774 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT110_SET) 549
Access Control Register 5.1.7.28/
3038_B778 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT110_CLR) 552
Access Control Register 5.1.7.29/
3038_B77C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT110_TOG) 554
5.1.7.10/
3038_B780 Target Register (CCM_TARGET_ROOT111) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B784 Target Register (CCM_TARGET_ROOT111_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B788 Target Register (CCM_TARGET_ROOT111_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B78C Target Register (CCM_TARGET_ROOT111_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B790 Miscellaneous Register (CCM_MISC111) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B794 Miscellaneous Register (CCM_MISC_ROOT111_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B798 Miscellaneous Register (CCM_MISC_ROOT111_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B79C Miscellaneous Register (CCM_MISC_ROOT111_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B7A0 Post Divider Register (CCM_POST111) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B7A4 Post Divider Register (CCM_POST_ROOT111_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B7A8 Post Divider Register (CCM_POST_ROOT111_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B7AC Post Divider Register (CCM_POST_ROOT111_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B7B0 Pre Divider Register (CCM_PRE111) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B7B4 Pre Divider Register (CCM_PRE_ROOT111_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B7B8 Pre Divider Register (CCM_PRE_ROOT111_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B7BC Pre Divider Register (CCM_PRE_ROOT111_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B7F0 Access Control Register (CCM_ACCESS_CTRL111) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B7F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT111_SET) 549
Access Control Register 5.1.7.28/
3038_B7F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT111_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

466 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_B7FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT111_TOG) 554
5.1.7.10/
3038_B800 Target Register (CCM_TARGET_ROOT112) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B804 Target Register (CCM_TARGET_ROOT112_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B808 Target Register (CCM_TARGET_ROOT112_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B80C Target Register (CCM_TARGET_ROOT112_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B810 Miscellaneous Register (CCM_MISC112) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B814 Miscellaneous Register (CCM_MISC_ROOT112_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B818 Miscellaneous Register (CCM_MISC_ROOT112_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B81C Miscellaneous Register (CCM_MISC_ROOT112_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B820 Post Divider Register (CCM_POST112) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B824 Post Divider Register (CCM_POST_ROOT112_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B828 Post Divider Register (CCM_POST_ROOT112_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B82C Post Divider Register (CCM_POST_ROOT112_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B830 Pre Divider Register (CCM_PRE112) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B834 Pre Divider Register (CCM_PRE_ROOT112_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B838 Pre Divider Register (CCM_PRE_ROOT112_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B83C Pre Divider Register (CCM_PRE_ROOT112_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B870 Access Control Register (CCM_ACCESS_CTRL112) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B874 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT112_SET) 549
Access Control Register 5.1.7.28/
3038_B878 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT112_CLR) 552
Access Control Register 5.1.7.29/
3038_B87C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT112_TOG) 554
5.1.7.10/
3038_B880 Target Register (CCM_TARGET_ROOT113) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 467
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_B884 Target Register (CCM_TARGET_ROOT113_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B888 Target Register (CCM_TARGET_ROOT113_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B88C Target Register (CCM_TARGET_ROOT113_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B890 Miscellaneous Register (CCM_MISC113) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B894 Miscellaneous Register (CCM_MISC_ROOT113_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B898 Miscellaneous Register (CCM_MISC_ROOT113_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B89C Miscellaneous Register (CCM_MISC_ROOT113_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B8A0 Post Divider Register (CCM_POST113) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B8A4 Post Divider Register (CCM_POST_ROOT113_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B8A8 Post Divider Register (CCM_POST_ROOT113_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B8AC Post Divider Register (CCM_POST_ROOT113_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B8B0 Pre Divider Register (CCM_PRE113) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B8B4 Pre Divider Register (CCM_PRE_ROOT113_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B8B8 Pre Divider Register (CCM_PRE_ROOT113_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B8BC Pre Divider Register (CCM_PRE_ROOT113_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B8F0 Access Control Register (CCM_ACCESS_CTRL113) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B8F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT113_SET) 549
Access Control Register 5.1.7.28/
3038_B8F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT113_CLR) 552
Access Control Register 5.1.7.29/
3038_B8FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT113_TOG) 554
5.1.7.10/
3038_B900 Target Register (CCM_TARGET_ROOT114) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B904 Target Register (CCM_TARGET_ROOT114_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B908 Target Register (CCM_TARGET_ROOT114_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

468 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_B90C Target Register (CCM_TARGET_ROOT114_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B910 Miscellaneous Register (CCM_MISC114) 32 R/W 0000_0000h
519
5.1.7.15/
3038_B914 Miscellaneous Register (CCM_MISC_ROOT114_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B918 Miscellaneous Register (CCM_MISC_ROOT114_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B91C Miscellaneous Register (CCM_MISC_ROOT114_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B920 Post Divider Register (CCM_POST114) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B924 Post Divider Register (CCM_POST_ROOT114_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B928 Post Divider Register (CCM_POST_ROOT114_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B92C Post Divider Register (CCM_POST_ROOT114_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B930 Pre Divider Register (CCM_PRE114) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B934 Pre Divider Register (CCM_PRE_ROOT114_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B938 Pre Divider Register (CCM_PRE_ROOT114_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B93C Pre Divider Register (CCM_PRE_ROOT114_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B970 Access Control Register (CCM_ACCESS_CTRL114) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B974 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT114_SET) 549
Access Control Register 5.1.7.28/
3038_B978 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT114_CLR) 552
Access Control Register 5.1.7.29/
3038_B97C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT114_TOG) 554
5.1.7.10/
3038_B980 Target Register (CCM_TARGET_ROOT115) 32 R/W 1000_0000h
511
5.1.7.11/
3038_B984 Target Register (CCM_TARGET_ROOT115_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_B988 Target Register (CCM_TARGET_ROOT115_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_B98C Target Register (CCM_TARGET_ROOT115_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_B990 Miscellaneous Register (CCM_MISC115) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 469
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_B994 Miscellaneous Register (CCM_MISC_ROOT115_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_B998 Miscellaneous Register (CCM_MISC_ROOT115_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_B99C Miscellaneous Register (CCM_MISC_ROOT115_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_B9A0 Post Divider Register (CCM_POST115) 32 R/W 0000_0000h
523
5.1.7.19/
3038_B9A4 Post Divider Register (CCM_POST_ROOT115_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_B9A8 Post Divider Register (CCM_POST_ROOT115_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_B9AC Post Divider Register (CCM_POST_ROOT115_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_B9B0 Pre Divider Register (CCM_PRE115) 32 R/W 1000_0000h
535
5.1.7.23/
3038_B9B4 Pre Divider Register (CCM_PRE_ROOT115_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_B9B8 Pre Divider Register (CCM_PRE_ROOT115_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_B9BC Pre Divider Register (CCM_PRE_ROOT115_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_B9F0 Access Control Register (CCM_ACCESS_CTRL115) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_B9F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT115_SET) 549
Access Control Register 5.1.7.28/
3038_B9F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT115_CLR) 552
Access Control Register 5.1.7.29/
3038_B9FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT115_TOG) 554
5.1.7.10/
3038_BA00 Target Register (CCM_TARGET_ROOT116) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BA04 Target Register (CCM_TARGET_ROOT116_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BA08 Target Register (CCM_TARGET_ROOT116_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BA0C Target Register (CCM_TARGET_ROOT116_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BA10 Miscellaneous Register (CCM_MISC116) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BA14 Miscellaneous Register (CCM_MISC_ROOT116_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BA18 Miscellaneous Register (CCM_MISC_ROOT116_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

470 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_BA1C Miscellaneous Register (CCM_MISC_ROOT116_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BA20 Post Divider Register (CCM_POST116) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BA24 Post Divider Register (CCM_POST_ROOT116_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BA28 Post Divider Register (CCM_POST_ROOT116_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BA2C Post Divider Register (CCM_POST_ROOT116_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BA30 Pre Divider Register (CCM_PRE116) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BA34 Pre Divider Register (CCM_PRE_ROOT116_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BA38 Pre Divider Register (CCM_PRE_ROOT116_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BA3C Pre Divider Register (CCM_PRE_ROOT116_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BA70 Access Control Register (CCM_ACCESS_CTRL116) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BA74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT116_SET) 549
Access Control Register 5.1.7.28/
3038_BA78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT116_CLR) 552
Access Control Register 5.1.7.29/
3038_BA7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT116_TOG) 554
5.1.7.10/
3038_BA80 Target Register (CCM_TARGET_ROOT117) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BA84 Target Register (CCM_TARGET_ROOT117_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BA88 Target Register (CCM_TARGET_ROOT117_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BA8C Target Register (CCM_TARGET_ROOT117_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BA90 Miscellaneous Register (CCM_MISC117) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BA94 Miscellaneous Register (CCM_MISC_ROOT117_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BA98 Miscellaneous Register (CCM_MISC_ROOT117_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BA9C Miscellaneous Register (CCM_MISC_ROOT117_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BAA0 Post Divider Register (CCM_POST117) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 471
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_BAA4 Post Divider Register (CCM_POST_ROOT117_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BAA8 Post Divider Register (CCM_POST_ROOT117_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BAAC Post Divider Register (CCM_POST_ROOT117_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BAB0 Pre Divider Register (CCM_PRE117) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BAB4 Pre Divider Register (CCM_PRE_ROOT117_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BAB8 Pre Divider Register (CCM_PRE_ROOT117_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BABC Pre Divider Register (CCM_PRE_ROOT117_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BAF0 Access Control Register (CCM_ACCESS_CTRL117) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BAF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT117_SET) 549
Access Control Register 5.1.7.28/
3038_BAF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT117_CLR) 552
Access Control Register 5.1.7.29/
3038_BAFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT117_TOG) 554
5.1.7.10/
3038_BB00 Target Register (CCM_TARGET_ROOT118) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BB04 Target Register (CCM_TARGET_ROOT118_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BB08 Target Register (CCM_TARGET_ROOT118_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BB0C Target Register (CCM_TARGET_ROOT118_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BB10 Miscellaneous Register (CCM_MISC118) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BB14 Miscellaneous Register (CCM_MISC_ROOT118_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BB18 Miscellaneous Register (CCM_MISC_ROOT118_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BB1C Miscellaneous Register (CCM_MISC_ROOT118_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BB20 Post Divider Register (CCM_POST118) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BB24 Post Divider Register (CCM_POST_ROOT118_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BB28 Post Divider Register (CCM_POST_ROOT118_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

472 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_BB2C Post Divider Register (CCM_POST_ROOT118_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BB30 Pre Divider Register (CCM_PRE118) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BB34 Pre Divider Register (CCM_PRE_ROOT118_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BB38 Pre Divider Register (CCM_PRE_ROOT118_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BB3C Pre Divider Register (CCM_PRE_ROOT118_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BB70 Access Control Register (CCM_ACCESS_CTRL118) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BB74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT118_SET) 549
Access Control Register 5.1.7.28/
3038_BB78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT118_CLR) 552
Access Control Register 5.1.7.29/
3038_BB7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT118_TOG) 554
5.1.7.10/
3038_BB80 Target Register (CCM_TARGET_ROOT119) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BB84 Target Register (CCM_TARGET_ROOT119_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BB88 Target Register (CCM_TARGET_ROOT119_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BB8C Target Register (CCM_TARGET_ROOT119_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BB90 Miscellaneous Register (CCM_MISC119) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BB94 Miscellaneous Register (CCM_MISC_ROOT119_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BB98 Miscellaneous Register (CCM_MISC_ROOT119_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BB9C Miscellaneous Register (CCM_MISC_ROOT119_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BBA0 Post Divider Register (CCM_POST119) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BBA4 Post Divider Register (CCM_POST_ROOT119_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BBA8 Post Divider Register (CCM_POST_ROOT119_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BBAC Post Divider Register (CCM_POST_ROOT119_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BBB0 Pre Divider Register (CCM_PRE119) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 473
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_BBB4 Pre Divider Register (CCM_PRE_ROOT119_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BBB8 Pre Divider Register (CCM_PRE_ROOT119_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BBBC Pre Divider Register (CCM_PRE_ROOT119_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BBF0 Access Control Register (CCM_ACCESS_CTRL119) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BBF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT119_SET) 549
Access Control Register 5.1.7.28/
3038_BBF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT119_CLR) 552
Access Control Register 5.1.7.29/
3038_BBFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT119_TOG) 554
5.1.7.10/
3038_BC00 Target Register (CCM_TARGET_ROOT120) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BC04 Target Register (CCM_TARGET_ROOT120_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BC08 Target Register (CCM_TARGET_ROOT120_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BC0C Target Register (CCM_TARGET_ROOT120_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BC10 Miscellaneous Register (CCM_MISC120) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BC14 Miscellaneous Register (CCM_MISC_ROOT120_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BC18 Miscellaneous Register (CCM_MISC_ROOT120_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BC1C Miscellaneous Register (CCM_MISC_ROOT120_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BC20 Post Divider Register (CCM_POST120) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BC24 Post Divider Register (CCM_POST_ROOT120_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BC28 Post Divider Register (CCM_POST_ROOT120_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BC2C Post Divider Register (CCM_POST_ROOT120_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BC30 Pre Divider Register (CCM_PRE120) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BC34 Pre Divider Register (CCM_PRE_ROOT120_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BC38 Pre Divider Register (CCM_PRE_ROOT120_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

474 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_BC3C Pre Divider Register (CCM_PRE_ROOT120_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BC70 Access Control Register (CCM_ACCESS_CTRL120) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BC74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT120_SET) 549
Access Control Register 5.1.7.28/
3038_BC78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT120_CLR) 552
Access Control Register 5.1.7.29/
3038_BC7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT120_TOG) 554
5.1.7.10/
3038_BC80 Target Register (CCM_TARGET_ROOT121) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BC84 Target Register (CCM_TARGET_ROOT121_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BC88 Target Register (CCM_TARGET_ROOT121_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BC8C Target Register (CCM_TARGET_ROOT121_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BC90 Miscellaneous Register (CCM_MISC121) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BC94 Miscellaneous Register (CCM_MISC_ROOT121_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BC98 Miscellaneous Register (CCM_MISC_ROOT121_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BC9C Miscellaneous Register (CCM_MISC_ROOT121_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BCA0 Post Divider Register (CCM_POST121) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BCA4 Post Divider Register (CCM_POST_ROOT121_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BCA8 Post Divider Register (CCM_POST_ROOT121_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BCAC Post Divider Register (CCM_POST_ROOT121_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BCB0 Pre Divider Register (CCM_PRE121) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BCB4 Pre Divider Register (CCM_PRE_ROOT121_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BCB8 Pre Divider Register (CCM_PRE_ROOT121_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BCBC Pre Divider Register (CCM_PRE_ROOT121_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BCF0 Access Control Register (CCM_ACCESS_CTRL121) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 475
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_BCF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT121_SET) 549
Access Control Register 5.1.7.28/
3038_BCF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT121_CLR) 552
Access Control Register 5.1.7.29/
3038_BCFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT121_TOG) 554
5.1.7.10/
3038_BD00 Target Register (CCM_TARGET_ROOT122) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BD04 Target Register (CCM_TARGET_ROOT122_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BD08 Target Register (CCM_TARGET_ROOT122_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BD0C Target Register (CCM_TARGET_ROOT122_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BD10 Miscellaneous Register (CCM_MISC122) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BD14 Miscellaneous Register (CCM_MISC_ROOT122_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BD18 Miscellaneous Register (CCM_MISC_ROOT122_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BD1C Miscellaneous Register (CCM_MISC_ROOT122_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BD20 Post Divider Register (CCM_POST122) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BD24 Post Divider Register (CCM_POST_ROOT122_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BD28 Post Divider Register (CCM_POST_ROOT122_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BD2C Post Divider Register (CCM_POST_ROOT122_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BD30 Pre Divider Register (CCM_PRE122) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BD34 Pre Divider Register (CCM_PRE_ROOT122_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BD38 Pre Divider Register (CCM_PRE_ROOT122_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BD3C Pre Divider Register (CCM_PRE_ROOT122_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BD70 Access Control Register (CCM_ACCESS_CTRL122) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BD74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT122_SET) 549
Access Control Register 5.1.7.28/
3038_BD78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT122_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

476 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_BD7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT122_TOG) 554
5.1.7.10/
3038_BD80 Target Register (CCM_TARGET_ROOT123) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BD84 Target Register (CCM_TARGET_ROOT123_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BD88 Target Register (CCM_TARGET_ROOT123_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BD8C Target Register (CCM_TARGET_ROOT123_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BD90 Miscellaneous Register (CCM_MISC123) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BD94 Miscellaneous Register (CCM_MISC_ROOT123_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BD98 Miscellaneous Register (CCM_MISC_ROOT123_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BD9C Miscellaneous Register (CCM_MISC_ROOT123_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BDA0 Post Divider Register (CCM_POST123) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BDA4 Post Divider Register (CCM_POST_ROOT123_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BDA8 Post Divider Register (CCM_POST_ROOT123_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BDAC Post Divider Register (CCM_POST_ROOT123_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BDB0 Pre Divider Register (CCM_PRE123) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BDB4 Pre Divider Register (CCM_PRE_ROOT123_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BDB8 Pre Divider Register (CCM_PRE_ROOT123_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BDBC Pre Divider Register (CCM_PRE_ROOT123_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BDF0 Access Control Register (CCM_ACCESS_CTRL123) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BDF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT123_SET) 549
Access Control Register 5.1.7.28/
3038_BDF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT123_CLR) 552
Access Control Register 5.1.7.29/
3038_BDFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT123_TOG) 554
5.1.7.10/
3038_BE00 Target Register (CCM_TARGET_ROOT124) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 477
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_BE04 Target Register (CCM_TARGET_ROOT124_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BE08 Target Register (CCM_TARGET_ROOT124_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BE0C Target Register (CCM_TARGET_ROOT124_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BE10 Miscellaneous Register (CCM_MISC124) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BE14 Miscellaneous Register (CCM_MISC_ROOT124_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BE18 Miscellaneous Register (CCM_MISC_ROOT124_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BE1C Miscellaneous Register (CCM_MISC_ROOT124_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BE20 Post Divider Register (CCM_POST124) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BE24 Post Divider Register (CCM_POST_ROOT124_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BE28 Post Divider Register (CCM_POST_ROOT124_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BE2C Post Divider Register (CCM_POST_ROOT124_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BE30 Pre Divider Register (CCM_PRE124) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BE34 Pre Divider Register (CCM_PRE_ROOT124_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BE38 Pre Divider Register (CCM_PRE_ROOT124_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BE3C Pre Divider Register (CCM_PRE_ROOT124_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BE70 Access Control Register (CCM_ACCESS_CTRL124) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BE74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT124_SET) 549
Access Control Register 5.1.7.28/
3038_BE78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT124_CLR) 552
Access Control Register 5.1.7.29/
3038_BE7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT124_TOG) 554
5.1.7.10/
3038_BE80 Target Register (CCM_TARGET_ROOT125) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BE84 Target Register (CCM_TARGET_ROOT125_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BE88 Target Register (CCM_TARGET_ROOT125_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

478 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_BE8C Target Register (CCM_TARGET_ROOT125_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BE90 Miscellaneous Register (CCM_MISC125) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BE94 Miscellaneous Register (CCM_MISC_ROOT125_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BE98 Miscellaneous Register (CCM_MISC_ROOT125_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BE9C Miscellaneous Register (CCM_MISC_ROOT125_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BEA0 Post Divider Register (CCM_POST125) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BEA4 Post Divider Register (CCM_POST_ROOT125_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BEA8 Post Divider Register (CCM_POST_ROOT125_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BEAC Post Divider Register (CCM_POST_ROOT125_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BEB0 Pre Divider Register (CCM_PRE125) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BEB4 Pre Divider Register (CCM_PRE_ROOT125_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BEB8 Pre Divider Register (CCM_PRE_ROOT125_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BEBC Pre Divider Register (CCM_PRE_ROOT125_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BEF0 Access Control Register (CCM_ACCESS_CTRL125) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BEF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT125_SET) 549
Access Control Register 5.1.7.28/
3038_BEF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT125_CLR) 552
Access Control Register 5.1.7.29/
3038_BEFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT125_TOG) 554
5.1.7.10/
3038_BF00 Target Register (CCM_TARGET_ROOT126) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BF04 Target Register (CCM_TARGET_ROOT126_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BF08 Target Register (CCM_TARGET_ROOT126_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BF0C Target Register (CCM_TARGET_ROOT126_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BF10 Miscellaneous Register (CCM_MISC126) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 479
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_BF14 Miscellaneous Register (CCM_MISC_ROOT126_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BF18 Miscellaneous Register (CCM_MISC_ROOT126_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_BF1C Miscellaneous Register (CCM_MISC_ROOT126_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BF20 Post Divider Register (CCM_POST126) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BF24 Post Divider Register (CCM_POST_ROOT126_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BF28 Post Divider Register (CCM_POST_ROOT126_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BF2C Post Divider Register (CCM_POST_ROOT126_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BF30 Pre Divider Register (CCM_PRE126) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BF34 Pre Divider Register (CCM_PRE_ROOT126_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BF38 Pre Divider Register (CCM_PRE_ROOT126_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BF3C Pre Divider Register (CCM_PRE_ROOT126_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BF70 Access Control Register (CCM_ACCESS_CTRL126) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BF74 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT126_SET) 549
Access Control Register 5.1.7.28/
3038_BF78 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT126_CLR) 552
Access Control Register 5.1.7.29/
3038_BF7C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT126_TOG) 554
5.1.7.10/
3038_BF80 Target Register (CCM_TARGET_ROOT127) 32 R/W 1000_0000h
511
5.1.7.11/
3038_BF84 Target Register (CCM_TARGET_ROOT127_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_BF88 Target Register (CCM_TARGET_ROOT127_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_BF8C Target Register (CCM_TARGET_ROOT127_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_BF90 Miscellaneous Register (CCM_MISC127) 32 R/W 0000_0000h
519
5.1.7.15/
3038_BF94 Miscellaneous Register (CCM_MISC_ROOT127_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_BF98 Miscellaneous Register (CCM_MISC_ROOT127_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

480 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_BF9C Miscellaneous Register (CCM_MISC_ROOT127_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_BFA0 Post Divider Register (CCM_POST127) 32 R/W 0000_0000h
523
5.1.7.19/
3038_BFA4 Post Divider Register (CCM_POST_ROOT127_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_BFA8 Post Divider Register (CCM_POST_ROOT127_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_BFAC Post Divider Register (CCM_POST_ROOT127_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_BFB0 Pre Divider Register (CCM_PRE127) 32 R/W 1000_0000h
535
5.1.7.23/
3038_BFB4 Pre Divider Register (CCM_PRE_ROOT127_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_BFB8 Pre Divider Register (CCM_PRE_ROOT127_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_BFBC Pre Divider Register (CCM_PRE_ROOT127_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_BFF0 Access Control Register (CCM_ACCESS_CTRL127) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_BFF4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT127_SET) 549
Access Control Register 5.1.7.28/
3038_BFF8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT127_CLR) 552
Access Control Register 5.1.7.29/
3038_BFFC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT127_TOG) 554
5.1.7.10/
3038_C000 Target Register (CCM_TARGET_ROOT128) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C004 Target Register (CCM_TARGET_ROOT128_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C008 Target Register (CCM_TARGET_ROOT128_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C00C Target Register (CCM_TARGET_ROOT128_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C010 Miscellaneous Register (CCM_MISC128) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C014 Miscellaneous Register (CCM_MISC_ROOT128_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C018 Miscellaneous Register (CCM_MISC_ROOT128_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C01C Miscellaneous Register (CCM_MISC_ROOT128_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C020 Post Divider Register (CCM_POST128) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 481
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_C024 Post Divider Register (CCM_POST_ROOT128_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C028 Post Divider Register (CCM_POST_ROOT128_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C02C Post Divider Register (CCM_POST_ROOT128_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C030 Pre Divider Register (CCM_PRE128) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C034 Pre Divider Register (CCM_PRE_ROOT128_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C038 Pre Divider Register (CCM_PRE_ROOT128_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C03C Pre Divider Register (CCM_PRE_ROOT128_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C070 Access Control Register (CCM_ACCESS_CTRL128) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C074 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT128_SET) 549
Access Control Register 5.1.7.28/
3038_C078 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT128_CLR) 552
Access Control Register 5.1.7.29/
3038_C07C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT128_TOG) 554
5.1.7.10/
3038_C080 Target Register (CCM_TARGET_ROOT129) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C084 Target Register (CCM_TARGET_ROOT129_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C088 Target Register (CCM_TARGET_ROOT129_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C08C Target Register (CCM_TARGET_ROOT129_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C090 Miscellaneous Register (CCM_MISC129) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C094 Miscellaneous Register (CCM_MISC_ROOT129_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C098 Miscellaneous Register (CCM_MISC_ROOT129_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C09C Miscellaneous Register (CCM_MISC_ROOT129_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C0A0 Post Divider Register (CCM_POST129) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C0A4 Post Divider Register (CCM_POST_ROOT129_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C0A8 Post Divider Register (CCM_POST_ROOT129_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

482 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_C0AC Post Divider Register (CCM_POST_ROOT129_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C0B0 Pre Divider Register (CCM_PRE129) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C0B4 Pre Divider Register (CCM_PRE_ROOT129_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C0B8 Pre Divider Register (CCM_PRE_ROOT129_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C0BC Pre Divider Register (CCM_PRE_ROOT129_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C0F0 Access Control Register (CCM_ACCESS_CTRL129) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C0F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT129_SET) 549
Access Control Register 5.1.7.28/
3038_C0F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT129_CLR) 552
Access Control Register 5.1.7.29/
3038_C0FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT129_TOG) 554
5.1.7.10/
3038_C100 Target Register (CCM_TARGET_ROOT130) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C104 Target Register (CCM_TARGET_ROOT130_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C108 Target Register (CCM_TARGET_ROOT130_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C10C Target Register (CCM_TARGET_ROOT130_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C110 Miscellaneous Register (CCM_MISC130) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C114 Miscellaneous Register (CCM_MISC_ROOT130_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C118 Miscellaneous Register (CCM_MISC_ROOT130_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C11C Miscellaneous Register (CCM_MISC_ROOT130_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C120 Post Divider Register (CCM_POST130) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C124 Post Divider Register (CCM_POST_ROOT130_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C128 Post Divider Register (CCM_POST_ROOT130_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C12C Post Divider Register (CCM_POST_ROOT130_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C130 Pre Divider Register (CCM_PRE130) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 483
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_C134 Pre Divider Register (CCM_PRE_ROOT130_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C138 Pre Divider Register (CCM_PRE_ROOT130_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C13C Pre Divider Register (CCM_PRE_ROOT130_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C170 Access Control Register (CCM_ACCESS_CTRL130) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C174 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT130_SET) 549
Access Control Register 5.1.7.28/
3038_C178 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT130_CLR) 552
Access Control Register 5.1.7.29/
3038_C17C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT130_TOG) 554
5.1.7.10/
3038_C180 Target Register (CCM_TARGET_ROOT131) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C184 Target Register (CCM_TARGET_ROOT131_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C188 Target Register (CCM_TARGET_ROOT131_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C18C Target Register (CCM_TARGET_ROOT131_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C190 Miscellaneous Register (CCM_MISC131) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C194 Miscellaneous Register (CCM_MISC_ROOT131_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C198 Miscellaneous Register (CCM_MISC_ROOT131_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C19C Miscellaneous Register (CCM_MISC_ROOT131_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C1A0 Post Divider Register (CCM_POST131) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C1A4 Post Divider Register (CCM_POST_ROOT131_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C1A8 Post Divider Register (CCM_POST_ROOT131_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C1AC Post Divider Register (CCM_POST_ROOT131_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C1B0 Pre Divider Register (CCM_PRE131) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C1B4 Pre Divider Register (CCM_PRE_ROOT131_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C1B8 Pre Divider Register (CCM_PRE_ROOT131_CLR) 32 R/W 0000_0000h
541
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

484 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.25/
3038_C1BC Pre Divider Register (CCM_PRE_ROOT131_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C1F0 Access Control Register (CCM_ACCESS_CTRL131) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C1F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT131_SET) 549
Access Control Register 5.1.7.28/
3038_C1F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT131_CLR) 552
Access Control Register 5.1.7.29/
3038_C1FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT131_TOG) 554
5.1.7.10/
3038_C200 Target Register (CCM_TARGET_ROOT132) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C204 Target Register (CCM_TARGET_ROOT132_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C208 Target Register (CCM_TARGET_ROOT132_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C20C Target Register (CCM_TARGET_ROOT132_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C210 Miscellaneous Register (CCM_MISC132) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C214 Miscellaneous Register (CCM_MISC_ROOT132_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C218 Miscellaneous Register (CCM_MISC_ROOT132_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C21C Miscellaneous Register (CCM_MISC_ROOT132_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C220 Post Divider Register (CCM_POST132) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C224 Post Divider Register (CCM_POST_ROOT132_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C228 Post Divider Register (CCM_POST_ROOT132_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C22C Post Divider Register (CCM_POST_ROOT132_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C230 Pre Divider Register (CCM_PRE132) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C234 Pre Divider Register (CCM_PRE_ROOT132_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C238 Pre Divider Register (CCM_PRE_ROOT132_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C23C Pre Divider Register (CCM_PRE_ROOT132_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C270 Access Control Register (CCM_ACCESS_CTRL132) 32 R/W 0000_0000h
547
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 485
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.27/
3038_C274 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT132_SET) 549
Access Control Register 5.1.7.28/
3038_C278 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT132_CLR) 552
Access Control Register 5.1.7.29/
3038_C27C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT132_TOG) 554
5.1.7.10/
3038_C280 Target Register (CCM_TARGET_ROOT133) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C284 Target Register (CCM_TARGET_ROOT133_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C288 Target Register (CCM_TARGET_ROOT133_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C28C Target Register (CCM_TARGET_ROOT133_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C290 Miscellaneous Register (CCM_MISC133) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C294 Miscellaneous Register (CCM_MISC_ROOT133_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C298 Miscellaneous Register (CCM_MISC_ROOT133_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C29C Miscellaneous Register (CCM_MISC_ROOT133_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C2A0 Post Divider Register (CCM_POST133) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C2A4 Post Divider Register (CCM_POST_ROOT133_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C2A8 Post Divider Register (CCM_POST_ROOT133_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C2AC Post Divider Register (CCM_POST_ROOT133_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C2B0 Pre Divider Register (CCM_PRE133) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C2B4 Pre Divider Register (CCM_PRE_ROOT133_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C2B8 Pre Divider Register (CCM_PRE_ROOT133_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C2BC Pre Divider Register (CCM_PRE_ROOT133_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C2F0 Access Control Register (CCM_ACCESS_CTRL133) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C2F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT133_SET) 549
Access Control Register 5.1.7.28/
3038_C2F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT133_CLR) 552
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

486 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register 5.1.7.29/
3038_C2FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT133_TOG) 554
5.1.7.10/
3038_C300 Target Register (CCM_TARGET_ROOT134) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C304 Target Register (CCM_TARGET_ROOT134_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C308 Target Register (CCM_TARGET_ROOT134_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C30C Target Register (CCM_TARGET_ROOT134_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C310 Miscellaneous Register (CCM_MISC134) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C314 Miscellaneous Register (CCM_MISC_ROOT134_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C318 Miscellaneous Register (CCM_MISC_ROOT134_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C31C Miscellaneous Register (CCM_MISC_ROOT134_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C320 Post Divider Register (CCM_POST134) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C324 Post Divider Register (CCM_POST_ROOT134_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C328 Post Divider Register (CCM_POST_ROOT134_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C32C Post Divider Register (CCM_POST_ROOT134_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C330 Pre Divider Register (CCM_PRE134) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C334 Pre Divider Register (CCM_PRE_ROOT134_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C338 Pre Divider Register (CCM_PRE_ROOT134_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C33C Pre Divider Register (CCM_PRE_ROOT134_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C370 Access Control Register (CCM_ACCESS_CTRL134) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C374 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT134_SET) 549
Access Control Register 5.1.7.28/
3038_C378 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT134_CLR) 552
Access Control Register 5.1.7.29/
3038_C37C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT134_TOG) 554
5.1.7.10/
3038_C380 Target Register (CCM_TARGET_ROOT135) 32 R/W 1000_0000h
511
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 487
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.11/
3038_C384 Target Register (CCM_TARGET_ROOT135_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C388 Target Register (CCM_TARGET_ROOT135_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C38C Target Register (CCM_TARGET_ROOT135_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C390 Miscellaneous Register (CCM_MISC135) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C394 Miscellaneous Register (CCM_MISC_ROOT135_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C398 Miscellaneous Register (CCM_MISC_ROOT135_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C39C Miscellaneous Register (CCM_MISC_ROOT135_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C3A0 Post Divider Register (CCM_POST135) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C3A4 Post Divider Register (CCM_POST_ROOT135_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C3A8 Post Divider Register (CCM_POST_ROOT135_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C3AC Post Divider Register (CCM_POST_ROOT135_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C3B0 Pre Divider Register (CCM_PRE135) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C3B4 Pre Divider Register (CCM_PRE_ROOT135_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C3B8 Pre Divider Register (CCM_PRE_ROOT135_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C3BC Pre Divider Register (CCM_PRE_ROOT135_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C3F0 Access Control Register (CCM_ACCESS_CTRL135) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C3F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT135_SET) 549
Access Control Register 5.1.7.28/
3038_C3F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT135_CLR) 552
Access Control Register 5.1.7.29/
3038_C3FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT135_TOG) 554
5.1.7.10/
3038_C400 Target Register (CCM_TARGET_ROOT136) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C404 Target Register (CCM_TARGET_ROOT136_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C408 Target Register (CCM_TARGET_ROOT136_CLR) 32 R/W 0000_0000h
515
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

488 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.13/
3038_C40C Target Register (CCM_TARGET_ROOT136_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C410 Miscellaneous Register (CCM_MISC136) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C414 Miscellaneous Register (CCM_MISC_ROOT136_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C418 Miscellaneous Register (CCM_MISC_ROOT136_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C41C Miscellaneous Register (CCM_MISC_ROOT136_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C420 Post Divider Register (CCM_POST136) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C424 Post Divider Register (CCM_POST_ROOT136_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C428 Post Divider Register (CCM_POST_ROOT136_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C42C Post Divider Register (CCM_POST_ROOT136_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C430 Pre Divider Register (CCM_PRE136) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C434 Pre Divider Register (CCM_PRE_ROOT136_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C438 Pre Divider Register (CCM_PRE_ROOT136_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C43C Pre Divider Register (CCM_PRE_ROOT136_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C470 Access Control Register (CCM_ACCESS_CTRL136) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C474 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT136_SET) 549
Access Control Register 5.1.7.28/
3038_C478 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT136_CLR) 552
Access Control Register 5.1.7.29/
3038_C47C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT136_TOG) 554
5.1.7.10/
3038_C480 Target Register (CCM_TARGET_ROOT137) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C484 Target Register (CCM_TARGET_ROOT137_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C488 Target Register (CCM_TARGET_ROOT137_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C48C Target Register (CCM_TARGET_ROOT137_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C490 Miscellaneous Register (CCM_MISC137) 32 R/W 0000_0000h
519
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 489
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.15/
3038_C494 Miscellaneous Register (CCM_MISC_ROOT137_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C498 Miscellaneous Register (CCM_MISC_ROOT137_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C49C Miscellaneous Register (CCM_MISC_ROOT137_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C4A0 Post Divider Register (CCM_POST137) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C4A4 Post Divider Register (CCM_POST_ROOT137_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C4A8 Post Divider Register (CCM_POST_ROOT137_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C4AC Post Divider Register (CCM_POST_ROOT137_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C4B0 Pre Divider Register (CCM_PRE137) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C4B4 Pre Divider Register (CCM_PRE_ROOT137_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C4B8 Pre Divider Register (CCM_PRE_ROOT137_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C4BC Pre Divider Register (CCM_PRE_ROOT137_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C4F0 Access Control Register (CCM_ACCESS_CTRL137) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C4F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT137_SET) 549
Access Control Register 5.1.7.28/
3038_C4F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT137_CLR) 552
Access Control Register 5.1.7.29/
3038_C4FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT137_TOG) 554
5.1.7.10/
3038_C500 Target Register (CCM_TARGET_ROOT138) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C504 Target Register (CCM_TARGET_ROOT138_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C508 Target Register (CCM_TARGET_ROOT138_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C50C Target Register (CCM_TARGET_ROOT138_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C510 Miscellaneous Register (CCM_MISC138) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C514 Miscellaneous Register (CCM_MISC_ROOT138_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C518 Miscellaneous Register (CCM_MISC_ROOT138_CLR) 32 R/W 0000_0000h
521
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

490 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.17/
3038_C51C Miscellaneous Register (CCM_MISC_ROOT138_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C520 Post Divider Register (CCM_POST138) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C524 Post Divider Register (CCM_POST_ROOT138_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C528 Post Divider Register (CCM_POST_ROOT138_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C52C Post Divider Register (CCM_POST_ROOT138_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C530 Pre Divider Register (CCM_PRE138) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C534 Pre Divider Register (CCM_PRE_ROOT138_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C538 Pre Divider Register (CCM_PRE_ROOT138_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C53C Pre Divider Register (CCM_PRE_ROOT138_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C570 Access Control Register (CCM_ACCESS_CTRL138) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C574 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT138_SET) 549
Access Control Register 5.1.7.28/
3038_C578 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT138_CLR) 552
Access Control Register 5.1.7.29/
3038_C57C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT138_TOG) 554
5.1.7.10/
3038_C580 Target Register (CCM_TARGET_ROOT139) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C584 Target Register (CCM_TARGET_ROOT139_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C588 Target Register (CCM_TARGET_ROOT139_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C58C Target Register (CCM_TARGET_ROOT139_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C590 Miscellaneous Register (CCM_MISC139) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C594 Miscellaneous Register (CCM_MISC_ROOT139_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C598 Miscellaneous Register (CCM_MISC_ROOT139_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C59C Miscellaneous Register (CCM_MISC_ROOT139_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C5A0 Post Divider Register (CCM_POST139) 32 R/W 0000_0000h
523
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 491
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.19/
3038_C5A4 Post Divider Register (CCM_POST_ROOT139_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C5A8 Post Divider Register (CCM_POST_ROOT139_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C5AC Post Divider Register (CCM_POST_ROOT139_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C5B0 Pre Divider Register (CCM_PRE139) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C5B4 Pre Divider Register (CCM_PRE_ROOT139_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C5B8 Pre Divider Register (CCM_PRE_ROOT139_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C5BC Pre Divider Register (CCM_PRE_ROOT139_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C5F0 Access Control Register (CCM_ACCESS_CTRL139) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C5F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT139_SET) 549
Access Control Register 5.1.7.28/
3038_C5F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT139_CLR) 552
Access Control Register 5.1.7.29/
3038_C5FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT139_TOG) 554
5.1.7.10/
3038_C600 Target Register (CCM_TARGET_ROOT140) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C604 Target Register (CCM_TARGET_ROOT140_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C608 Target Register (CCM_TARGET_ROOT140_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C60C Target Register (CCM_TARGET_ROOT140_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C610 Miscellaneous Register (CCM_MISC140) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C614 Miscellaneous Register (CCM_MISC_ROOT140_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C618 Miscellaneous Register (CCM_MISC_ROOT140_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C61C Miscellaneous Register (CCM_MISC_ROOT140_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C620 Post Divider Register (CCM_POST140) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C624 Post Divider Register (CCM_POST_ROOT140_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C628 Post Divider Register (CCM_POST_ROOT140_CLR) 32 R/W 0000_0000h
529
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

492 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.21/
3038_C62C Post Divider Register (CCM_POST_ROOT140_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C630 Pre Divider Register (CCM_PRE140) 32 R/W 1000_0000h
535
5.1.7.23/
3038_C634 Pre Divider Register (CCM_PRE_ROOT140_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C638 Pre Divider Register (CCM_PRE_ROOT140_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C63C Pre Divider Register (CCM_PRE_ROOT140_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C670 Access Control Register (CCM_ACCESS_CTRL140) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C674 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT140_SET) 549
Access Control Register 5.1.7.28/
3038_C678 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT140_CLR) 552
Access Control Register 5.1.7.29/
3038_C67C 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT140_TOG) 554
5.1.7.10/
3038_C680 Target Register (CCM_TARGET_ROOT141) 32 R/W 1000_0000h
511
5.1.7.11/
3038_C684 Target Register (CCM_TARGET_ROOT141_SET) 32 R/W 0000_0000h
513
5.1.7.12/
3038_C688 Target Register (CCM_TARGET_ROOT141_CLR) 32 R/W 0000_0000h
515
5.1.7.13/
3038_C68C Target Register (CCM_TARGET_ROOT141_TOG) 32 R/W 0000_0000h
517
5.1.7.14/
3038_C690 Miscellaneous Register (CCM_MISC141) 32 R/W 0000_0000h
519
5.1.7.15/
3038_C694 Miscellaneous Register (CCM_MISC_ROOT141_SET) 32 R/W 0000_0000h
520
5.1.7.16/
3038_C698 Miscellaneous Register (CCM_MISC_ROOT141_CLR) 32 R/W 0000_0000h
521
5.1.7.17/
3038_C69C Miscellaneous Register (CCM_MISC_ROOT141_TOG) 32 R/W 0000_0000h
522
5.1.7.18/
3038_C6A0 Post Divider Register (CCM_POST141) 32 R/W 0000_0000h
523
5.1.7.19/
3038_C6A4 Post Divider Register (CCM_POST_ROOT141_SET) 32 R/W 0000_0000h
526
5.1.7.20/
3038_C6A8 Post Divider Register (CCM_POST_ROOT141_CLR) 32 R/W 0000_0000h
529
5.1.7.21/
3038_C6AC Post Divider Register (CCM_POST_ROOT141_TOG) 32 R/W 0000_0000h
532
5.1.7.22/
3038_C6B0 Pre Divider Register (CCM_PRE141) 32 R/W 1000_0000h
535
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 493
Clock Control Module (CCM)

CCM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.1.7.23/
3038_C6B4 Pre Divider Register (CCM_PRE_ROOT141_SET) 32 R/W 0000_0000h
538
5.1.7.24/
3038_C6B8 Pre Divider Register (CCM_PRE_ROOT141_CLR) 32 R/W 0000_0000h
541
5.1.7.25/
3038_C6BC Pre Divider Register (CCM_PRE_ROOT141_TOG) 32 R/W 0000_0000h
544
5.1.7.26/
3038_C6F0 Access Control Register (CCM_ACCESS_CTRL141) 32 R/W 0000_0000h
547
Access Control Register 5.1.7.27/
3038_C6F4 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT141_SET) 549
Access Control Register 5.1.7.28/
3038_C6F8 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT141_CLR) 552
Access Control Register 5.1.7.29/
3038_C6FC 32 R/W 0000_0000h
(CCM_ACCESS_CTRL_ROOT141_TOG) 554

5.1.7.1 General Purpose Register (CCM_GPR0n)

GPR0
Address: 3038_0000h base + 0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GP0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_GPR0n field descriptions

Field Description
GP0 Timeout cycle count of ipg_clk, when perform read and write.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

494 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.2 CCM PLL Control Register (CCM_PLL_CTRLn)

See Input Clocks for PLL control mapping.

NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 800h offset + (16d × i), where i=0d to 38d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_PLL_CTRLn field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 495
Clock Control Module (CCM)

CCM_PLL_CTRLn field descriptions (continued)

Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

496 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.3 CCM PLL Control Register (CCM_PLL_CTRLn_SET)

See Input Clocks for PLL control mapping.

NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 804h offset + (16d × i), where i=0d to 38d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_PLL_CTRLn_SET field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 497
Clock Control Module (CCM)

CCM_PLL_CTRLn_SET field descriptions (continued)

Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

498 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.4 CCM PLL Control Register (CCM_PLL_CTRLn_CLR)

See Input Clocks for PLL control mapping.

NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 808h offset + (16d × i), where i=0d to 38d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_PLL_CTRLn_CLR field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 499
Clock Control Module (CCM)

CCM_PLL_CTRLn_CLR field descriptions (continued)

Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

500 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.5 CCM PLL Control Register (CCM_PLL_CTRLn_TOG)

See Input Clocks for PLL control mapping.

NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 80Ch offset + (16d × i), where i=0d to 38d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_PLL_CTRLn_TOG field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 501
Clock Control Module (CCM)

CCM_PLL_CTRLn_TOG field descriptions (continued)

Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

5.1.7.6 CCM Clock Gating Register (CCM_CCGRn)

NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

502 NXP Semiconductors
 Chapter 5 Clocks and Power Management

NOTE
Sec_debug clock gating (CCGR60) must be active in low
power mode. DO NOT gate this clock in low power mode to
guarantee the low power mode functions such as stop WDOG
counting.
Address: 3038_0000h base + 4000h offset + (16d × i), where i=0d to 191d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_CCGRn field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 503
Clock Control Module (CCM)

CCM_CCGRn field descriptions (continued)

Field Description
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

504 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.7 CCM Clock Gating Register (CCM_CCGRn_SET)

NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.
Address: 3038_0000h base + 4004h offset + (16d × i), where i=0d to 191d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_CCGRn_SET field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 505
Clock Control Module (CCM)

CCM_CCGRn_SET field descriptions (continued)

Field Description
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

506 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.8 CCM Clock Gating Register (CCM_CCGRn_CLR)

NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.
Address: 3038_0000h base + 4008h offset + (16d × i), where i=0d to 191d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_CCGRn_CLR field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 507
Clock Control Module (CCM)

CCM_CCGRn_CLR field descriptions (continued)

Field Description
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

508 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.9 CCM Clock Gating Register (CCM_CCGRn_TOG)

NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.
Address: 3038_0000h base + 400Ch offset + (16d × i), where i=0d to 191d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
SETTING3 SETTING2 SETTING1 SETTING0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CCM_CCGRn_TOG field descriptions

Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 509
Clock Control Module (CCM)

CCM_CCGRn_TOG field descriptions (continued)

Field Description
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.

00 Domain clocks not needed

01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

510 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.10 Target Register (CCM_TARGET_ROOTn)

See Target Interface for more information.

NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 8000h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
ENABLE

Reserved MUX Reserved PRE_PODF

Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_TARGET_ROOTn field descriptions

Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 511
Clock Control Module (CCM)

CCM_TARGET_ROOTn field descriptions (continued)

Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divider divide the number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

512 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.11 Target Register (CCM_TARGET_ROOTn_SET)

See Target Interface for more information.

NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 8004h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
ENABLE

Reserved MUX Reserved PRE_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_TARGET_ROOTn_SET field descriptions

Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 513
Clock Control Module (CCM)

CCM_TARGET_ROOTn_SET field descriptions (continued)

Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divider divide the number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

514 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.12 Target Register (CCM_TARGET_ROOTn_CLR)

See Target Interface for more information.

NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 8008h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
ENABLE

Reserved MUX Reserved PRE_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_TARGET_ROOTn_CLR field descriptions

Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 515
Clock Control Module (CCM)

CCM_TARGET_ROOTn_CLR field descriptions (continued)

Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divider divide the number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

516 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.13 Target Register (CCM_TARGET_ROOTn_TOG)

See Target Interface for more information.

NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 800Ch offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
ENABLE

Reserved MUX Reserved PRE_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_TARGET_ROOTn_TOG field descriptions

Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 517
Clock Control Module (CCM)

CCM_TARGET_ROOTn_TOG field descriptions (continued)

Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divide divide number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

518 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.14 Miscellaneous Register (CCM_MISCn)

MISC
Address: 3038_0000h base + 8010h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUTHEN_FAIL
R

TIMEOUT
VIOLATE
Reserved Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_MISCn field descriptions

Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 519
Clock Control Module (CCM)

5.1.7.15 Miscellaneous Register (CCM_MISC_ROOTn_SET)

Misc
Address: 3038_0000h base + 8014h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUTHEN_FAIL
R

TIMEOUT
VIOLATE
Reserved Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_MISC_ROOTn_SET field descriptions

Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

520 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.16 Miscellaneous Register (CCM_MISC_ROOTn_CLR)

MISC
Address: 3038_0000h base + 8018h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUTHEN_FAIL
R

TIMEOUT
VIOLATE
Reserved Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_MISC_ROOTn_CLR field descriptions

Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 521
Clock Control Module (CCM)

5.1.7.17 Miscellaneous Register (CCM_MISC_ROOTn_TOG)

MISC
Address: 3038_0000h base + 801Ch offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUTHEN_FAIL
R

TIMEOUT
VIOLATE
Reserved Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_MISC_ROOTn_TOG field descriptions

Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

522 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.18 Post Divider Register (CCM_POSTn)

Post Register
Address: 3038_0000h base + 8020h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2

R
SELECT

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 523
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1
R

Reserved
Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_POSTn field descriptions

Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice

0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

524 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_POSTn field descriptions (continued)

Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 525
Clock Control Module (CCM)

5.1.7.19 Post Divider Register (CCM_POST_ROOTn_SET)

Post Divider Register

Address: 3038_0000h base + 8024h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2

R
SELECT

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

526 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1
R

Reserved
Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_POST_ROOTn_SET field descriptions

Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice

0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 527
Clock Control Module (CCM)

CCM_POST_ROOTn_SET field descriptions (continued)

Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

528 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.20 Post Divider Register (CCM_POST_ROOTn_CLR)

Post Root Register

Address: 3038_0000h base + 8028h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2

R
SELECT

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 529
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1
R

Reserved
Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_POST_ROOTn_CLR field descriptions

Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice

0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

530 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_POST_ROOTn_CLR field descriptions (continued)

Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 531
Clock Control Module (CCM)

5.1.7.21 Post Divider Register (CCM_POST_ROOTn_TOG)

Post Root Register

Address: 3038_0000h base + 802Ch offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2

R
SELECT

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

532 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1
R

Reserved
Reserved POST_PODF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_POST_ROOTn_TOG field descriptions

Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice

0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 533
Clock Control Module (CCM)

CCM_POST_ROOTn_TOG field descriptions (continued)

Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM

000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

534 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.22 Pre Divider Register (CCM_PREn)

Pre Register
Address: 3038_0000h base + 8030h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4

BUSY3
R
Reserved
EN_A

Reserved MUX_A Reserved PRE_PODF_A

Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 535
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1

BUSY0
R

Reserved

Reserved EN_B MUX_B Reserved PRE_PODF_B

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_PREn field descriptions

Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM

0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

536 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_PREn field descriptions (continued)

Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM

0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch a is applying
BUSY0
field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 537
Clock Control Module (CCM)

5.1.7.23 Pre Divider Register (CCM_PRE_ROOTn_SET)

Pre Divider Register

Address: 3038_0000h base + 8034h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4

BUSY3
R
Reserved
EN_A

Reserved MUX_A Reserved PRE_PODF_A

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

538 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1

BUSY0
R

Reserved

Reserved EN_B MUX_B Reserved PRE_PODF_B

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_PRE_ROOTn_SET field descriptions

Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM

0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 539
Clock Control Module (CCM)

CCM_PRE_ROOTn_SET field descriptions (continued)

Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM

0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch A is applying
BUSY0
field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

540 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.24 Pre Divider Register (CCM_PRE_ROOTn_CLR)

Pree Root Register

Address: 3038_0000h base + 8038h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4

BUSY3
R
Reserved
EN_A

Reserved MUX_A Reserved PRE_PODF_A

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 541
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1

BUSY0
R

Reserved

Reserved EN_B MUX_B Reserved PRE_PODF_B

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_PRE_ROOTn_CLR field descriptions

Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM

0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

542 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_PRE_ROOTn_CLR field descriptions (continued)

Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM

0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch A is applied
BUSY0
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 543
Clock Control Module (CCM)

5.1.7.25 Pre Divider Register (CCM_PRE_ROOTn_TOG)

Pre Root Register

Address: 3038_0000h base + 803Ch offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4

BUSY3
R
Reserved
EN_A

Reserved MUX_A Reserved PRE_PODF_A

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

544 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUSY1

BUSY0
R

Reserved

Reserved EN_B MUX_B Reserved PRE_PODF_B

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_PRE_ROOTn_TOG field descriptions

Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM

0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 545
Clock Control Module (CCM)

CCM_PRE_ROOTn_TOG field descriptions (continued)

Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM

0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch a is applied
BUSY0
field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM

000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

546 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.7.26 Access Control Register (CCM_ACCESS_CTRLn)

Access Control Register

Address: 3038_0000h base + 8070h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DOMAIN3_WHITELIST

DOMAIN2_WHITELIST

DOMAIN1_WHITELIST

DOMAIN0_WHITELIST
R OWNER_ID
SEMA_EN

MUTEX
LOCK

Reserved Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ACCESS_CTRLn field descriptions

Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.

0 Access control inactive

1 Access control active
30–29 This field is reserved.
- Reserved
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 547
Clock Control Module (CCM)

CCM_ACCESS_CTRLn field descriptions (continued)

Field Description
0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0

0 domaino
1 domain1
2 domain2
3 domain3
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

548 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ACCESS_CTRLn field descriptions (continued)

Field Description
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0

5.1.7.27 Access Control Register

(CCM_ACCESS_CTRL_ROOTn_SET)

Access Control Register

Address: 3038_0000h base + 8074h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3_WHITELIST

DOMAIN2_WHITELIST

DOMAIN1_WHITELIST

DOMAIN0_WHITELIST

R OWNER_ID
SEMA_EN

MUTEX
LOCK

Reserved Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ACCESS_CTRL_ROOTn_SET field descriptions

Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 549
Clock Control Module (CCM)

CCM_ACCESS_CTRL_ROOTn_SET field descriptions (continued)

Field Description
0 Access control inactive
1 Access control active
30–29 This field is reserved.
- Reserved
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1

0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0

0 domaino
1 domain1
2 domain2
3 domain3

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

550 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ACCESS_CTRL_ROOTn_SET field descriptions (continued)

Field Description
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 551
Clock Control Module (CCM)

5.1.7.28 Access Control Register

(CCM_ACCESS_CTRL_ROOTn_CLR)

Access Control Register

Address: 3038_0000h base + 8078h offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DOMAIN3_WHITELIST

DOMAIN2_WHITELIST

DOMAIN1_WHITELIST

DOMAIN0_WHITELIST
R OWNER_ID
SEMA_EN

MUTEX
LOCK

Reserved Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ACCESS_CTRL_ROOTn_CLR field descriptions

Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.

0 Access control inactive

1 Access control active
30–29 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

552 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ACCESS_CTRL_ROOTn_CLR field descriptions (continued)

Field Description
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1

0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0

0 domaino
1 domain1
2 domain2
3 domain3
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 553
Clock Control Module (CCM)

CCM_ACCESS_CTRL_ROOTn_CLR field descriptions (continued)

Field Description
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0

5.1.7.29 Access Control Register

(CCM_ACCESS_CTRL_ROOTn_TOG)

Access Control Register

Address: 3038_0000h base + 807Ch offset + (128d × i), where i=0d to 141d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3_WHITELIST

DOMAIN2_WHITELIST

DOMAIN1_WHITELIST

DOMAIN0_WHITELIST

R OWNER_ID
SEMA_EN

MUTEX
LOCK

Reserved Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

554 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ACCESS_CTRL_ROOTn_TOG field descriptions

Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.

0 Access control inactive

1 Access control active
30–29 This field is reserved.
- Reserved
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1

0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0

0 domaino
1 domain1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 555
Clock Control Module (CCM)

CCM_ACCESS_CTRL_ROOTn_TOG field descriptions (continued)

Field Description
2 domain2
3 domain3
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0

5.1.8 CCM Analog Memory Map/Register Definition

CCM_ANALOG memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
AUDIO PLL1 General Function Control Register 5.1.8.1/
3036_0000 32 R/W 0000_2010h
(CCM_ANALOG_AUDIO_PLL1_GEN_CTRL) 559
AUDIO PLL1 Divide and Fraction Data Control 0 Register 5.1.8.2/
3036_0004 32 R/W 0014_5032h
(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0) 561
AUDIO PLL1 Divide and Fraction Data Control 1 Register 5.1.8.3/
3036_0008 32 R/W 0000_0000h
(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1) 562
AUDIO PLL1 PLL SSCG Control Register 5.1.8.4/
3036_000C 32 R/W 0000_0000h
(CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL) 562
AUDIO PLL1 PLL Monitoring Control Register 5.1.8.5/
3036_0010 32 R/W 0010_0103h
(CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL) 564
AUDIO PLL2 General Function Control Register 5.1.8.6/
3036_0014 32 R/W 0000_2010h
(CCM_ANALOG_AUDIO_PLL2_GEN_CTRL) 566
AUDIO PLL2 Divide and Fraction Data Control 0 Register 5.1.8.7/
3036_0018 32 R/W 0014_5032h
(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0) 568
AUDIO PLL2 Divide and Fraction Data Control 1 Register 5.1.8.8/
3036_001C 32 R/W 0000_0000h
(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1) 569
AUDIO PLL2 PLL SSCG Control Register 5.1.8.9/
3036_0020 32 R/W 0000_0000h
(CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL) 569
AUDIO PLL2 PLL Monitoring Control Register 5.1.8.10/
3036_0024 32 R/W 0010_0103h
(CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL) 571
VIDEO PLL1 General Function Control Register 5.1.8.11/
3036_0028 32 R/W 0000_2010h
(CCM_ANALOG_VIDEO_PLL1_GEN_CTRL) 573
VIDEO PLL1 Divide and Fraction Data Control 0 Register 5.1.8.12/
3036_002C 32 R/W 0014_5032h
(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0) 575
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

556 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
VIDEO PLL1 Divide and Fraction Data Control 1 Register 5.1.8.13/
3036_0030 32 R/W 0000_0000h
(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1) 576
VIDEO PLL1 PLL SSCG Control Register 5.1.8.14/
3036_0034 32 R/W 0000_0000h
(CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL) 576
VIDEO PLL1 PLL Monitoring Control Register 5.1.8.15/
3036_0038 32 R/W 0010_0103h
(CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL) 578
DRAM PLL General Function Control Register 5.1.8.16/
3036_0050 32 R/W 0000_2010h
(CCM_ANALOG_DRAM_PLL_GEN_CTRL) 580
DRAM PLL Divide and Fraction Data Control 0 Register 5.1.8.17/
3036_0054 32 R/W 0012_C032h
(CCM_ANALOG_DRAM_PLL_FDIV_CTL0) 582
DRAM PLL Divide and Fraction Data Control 1 Register 5.1.8.18/
3036_0058 32 R/W 0000_0000h
(CCM_ANALOG_DRAM_PLL_FDIV_CTL1) 583
DRAM PLL PLL SSCG Control Register 5.1.8.19/
3036_005C 32 R/W 0000_0000h
(CCM_ANALOG_DRAM_PLL_SSCG_CTRL) 583
DRAM PLL PLL Monitoring Control Register 5.1.8.20/
3036_0060 32 R/W 0010_0103h
(CCM_ANALOG_DRAM_PLL_MNIT_CTRL) 585
GPU PLL General Function Control Register 5.1.8.21/
3036_0064 32 R/W 0000_0810h
(CCM_ANALOG_GPU_PLL_GEN_CTRL) 587
GPU PLL Divide and Fraction Data Control 0 Register 5.1.8.22/
3036_0068 32 R/W 000C_8031h
(CCM_ANALOG_GPU_PLL_FDIV_CTL0) 589
PLL Lock Detector Control Register 5.1.8.23/
3036_006C 32 R/W 0010_003Fh
(CCM_ANALOG_GPU_PLL_LOCKD_CTRL) 590
PLL Monitoring Control Register 5.1.8.24/
3036_0070 32 R/W 0028_0081h
(CCM_ANALOG_GPU_PLL_MNIT_CTRL) 591
VPU PLL General Function Control Register 5.1.8.25/
3036_0074 32 R/W 0000_0810h
(CCM_ANALOG_VPU_PLL_GEN_CTRL) 593
VPU PLL Divide and Fraction Data Control 0 Register 5.1.8.26/
3036_0078 32 R/W 0012_C032h
(CCM_ANALOG_VPU_PLL_FDIV_CTL0) 595
PLL Lock Detector Control Register 5.1.8.23/
3036_007C 32 R/W 0010_003Fh
(CCM_ANALOG_VPU_PLL_LOCKD_CTRL) 590
PLL Monitoring Control Register 5.1.8.24/
3036_0080 32 R/W 0028_0081h
(CCM_ANALOG_VPU_PLL_MNIT_CTRL) 591
ARM PLL General Function Control Register 5.1.8.27/
3036_0084 32 R/W 0000_0810h
(CCM_ANALOG_ARM_PLL_GEN_CTRL) 597
ARM PLL Divide and Fraction Data Control 0 Register 5.1.8.28/
3036_0088 32 R/W 000F_A030h
(CCM_ANALOG_ARM_PLL_FDIV_CTL0) 599
PLL Lock Detector Control Register 5.1.8.23/
3036_008C 32 R/W 0010_003Fh
(CCM_ANALOG_ARM_PLL_LOCKD_CTRL) 590
PLL Monitoring Control Register 5.1.8.24/
3036_0090 32 R/W 0028_0081h
(CCM_ANALOG_ARM_PLL_MNIT_CTRL) 591
SYS PLL1 General Function Control Register 5.1.8.29/
3036_0094 32 R/W 0AAA_A810h
(CCM_ANALOG_SYS_PLL1_GEN_CTRL) 601
SYS PLL1 Divide and Fraction Data Control 0 Register 5.1.8.30/
3036_0098 32 R/W 0019_0032h
(CCM_ANALOG_SYS_PLL1_FDIV_CTL0) 604
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 557
Clock Control Module (CCM)

CCM_ANALOG memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
PLL Lock Detector Control Register 5.1.8.23/
3036_009C 32 R/W 0010_003Fh
(CCM_ANALOG_SYS_PLL1_LOCKD_CTRL) 590
PLL Monitoring Control Register 5.1.8.31/
3036_0100 32 R/W 0028_0081h
(CCM_ANALOG_SYS_PLL1_MNIT_CTRL) 605
SYS PLL2 General Function Control Register 5.1.8.32/
3036_0104 32 R/W 0AAA_A810h
(CCM_ANALOG_SYS_PLL2_GEN_CTRL) 607
SYS PLL2 Divide and Fraction Data Control 0 Register 5.1.8.33/
3036_0108 32 R/W 000F_A031h
(CCM_ANALOG_SYS_PLL2_FDIV_CTL0) 610
PLL Lock Detector Control Register 5.1.8.34/
3036_010C 32 R/W 0010_003Fh
(CCM_ANALOG_SYS_PLL2_LOCKD_CTRL) 611
PLL Monitoring Control Register 5.1.8.31/
3036_0110 32 R/W 0028_0081h
(CCM_ANALOG_SYS_PLL2_MNIT_CTRL) 605
SYS PLL3 General Function Control Register 5.1.8.35/
3036_0114 32 R/W 0000_0810h
(CCM_ANALOG_SYS_PLL3_GEN_CTRL) 612
SYS PLL3 Divide and Fraction Data Control 0 Register 5.1.8.36/
3036_0118 32 R/W 000F_A031h
(CCM_ANALOG_SYS_PLL3_FDIV_CTL0) 614
PLL Lock Detector Control Register 5.1.8.34/
3036_011C 32 R/W 0010_003Fh
(CCM_ANALOG_SYS_PLL3_LOCKD_CTRL) 611
PLL Monitoring Control Register 5.1.8.31/
3036_0120 32 R/W 0028_0081h
(CCM_ANALOG_SYS_PLL3_MNIT_CTRL) 605
Osc Misc Configuration Register 5.1.8.37/
3036_0124 32 R/W 0000_0000h
(CCM_ANALOG_OSC_MISC_CFG) 615
PLL Clock Output for Test Enable and Select Register 5.1.8.38/
3036_0128 32 R/W 0000_0000h
(CCM_ANALOG_ANAMIX_PLL_MNIT_CTL) 616
5.1.8.39/
3036_0800 DIGPROG Register (CCM_ANALOG_DIGPROG) 32 R 0082_4010h
618

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

558 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.1 AUDIO PLL1 General Function Control Register

(CCM_ANALOG_AUDIO_PLL1_GEN_CTRL)

AUDIO PLL1 General Function Control Register

Address: 3036_0000h base + 0h offset = 3036_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

PLL_EXT_BYPASS
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

R
PLL_BYPASS
PLL_CLKE

PLL_ PAD_CLK_ PLL_REF_

Reserved Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_AUDIO_PLL1_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 559
Clock Control Module (CCM)

CCM_ANALOG_AUDIO_PLL1_GEN_CTRL field descriptions (continued)

Field Description
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

560 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.2 AUDIO PLL1 Divide and Fraction Data Control 0 Register

(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0)

AUDIO PLL1 Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 4h offset = 3036_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0

CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 561
Clock Control Module (CCM)

5.1.8.3 AUDIO PLL1 Divide and Fraction Data Control 1 Register

(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1)

AUDIO PLL1 Divide and Fraction Data Control 1 Register

Address: 3036_0000h base + 8h offset = 3036_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM

5.1.8.4 AUDIO PLL1 PLL SSCG Control Register

(CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL)

AUDIO PLL1 PLL SSCG Control Register

Address: 3036_0000h base + Ch offset = 3036_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN

Reserved PLL_MFREQ_CTL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

562 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL field descriptions

Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(2^5) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr x mrr /m /(2^6) x 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control

00 Down spread
01 Up spread
1x Center spread

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 563
Clock Control Module (CCM)

5.1.8.5 AUDIO PLL1 PLL Monitoring Control Register

(CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL)

AUDIO PLL1 PLL Monitoring Control Register

Address: 3036_0000h base + 10h offset = 3036_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBIAS_CTRL_EN
R

AFCINIT_SEL
PBIAS_CTRL
AFC_SEL

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
FEED_EN

AFC_EN
FSEL Reserved EXTAFC ICP

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1

CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL field descriptions

Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

564 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL field descriptions (continued)

Field Description
0 nominal delay
1 nominal delay * 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 565
Clock Control Module (CCM)

5.1.8.6 AUDIO PLL2 General Function Control Register

(CCM_ANALOG_AUDIO_PLL2_GEN_CTRL)

AUDIO PLL2 General Function Control Register

Address: 3036_0000h base + 14h offset = 3036_0014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

PLL_EXT_BYPASS
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

R
PLL_BYPASS
PLL_CLKE

PLL_ PAD_CLK_ PLL_REF_

Reserved Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_AUDIO_PLL2_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

566 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_AUDIO_PLL2_GEN_CTRL field descriptions (continued)

Field Description
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 567
Clock Control Module (CCM)

5.1.8.7 AUDIO PLL2 Divide and Fraction Data Control 0 Register

(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0)

AUDIO PLL2 Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 18h offset = 3036_0018h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0

CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

568 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.8 AUDIO PLL2 Divide and Fraction Data Control 1 Register

(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1)

AUDIO PLL2 Divide and Fraction Data Control 1 Register

Address: 3036_0000h base + 1Ch offset = 3036_001Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM

5.1.8.9 AUDIO PLL2 PLL SSCG Control Register

(CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL)

AUDIO PLL2 PLL SSCG Control Register

Address: 3036_0000h base + 20h offset = 3036_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN

Reserved PLL_MFREQ_CTL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 569
Clock Control Module (CCM)

CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL field descriptions

Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(2^5) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr x mrr /m /(2^6) x 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control

00 Down spread
01 Up spread
1x Center spread

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

570 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.10 AUDIO PLL2 PLL Monitoring Control Register

(CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL)

AUDIO PLL2 PLL Monitoring Control Register

Address: 3036_0000h base + 24h offset = 3036_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBIAS_CTRL_EN
R

AFCINIT_SEL
PBIAS_CTRL
AFC_SEL

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
FEED_EN

AFC_EN
FSEL Reserved EXTAFC ICP

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1

CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL field descriptions

Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 571
Clock Control Module (CCM)

CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL field descriptions (continued)

Field Description
0 nominal delay
1 nominal delay * 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

572 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.11 VIDEO PLL1 General Function Control Register

(CCM_ANALOG_VIDEO_PLL1_GEN_CTRL)

VIDEO PLL1 General Function Control Register

Address: 3036_0000h base + 28h offset = 3036_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

PLL_EXT_BYPASS
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

R
PLL_BYPASS
PLL_CLKE

PLL_ PAD_CLK_ PLL_REF_

Reserved Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_VIDEO_PLL1_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 573
Clock Control Module (CCM)

CCM_ANALOG_VIDEO_PLL1_GEN_CTRL field descriptions (continued)

Field Description
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

574 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.12 VIDEO PLL1 Divide and Fraction Data Control 0 Register

(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0)

VIDEO PLL1 Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 2Ch offset = 3036_002Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0

CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 575
Clock Control Module (CCM)

5.1.8.13 VIDEO PLL1 Divide and Fraction Data Control 1 Register

(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1)

VIDEO PLL1 Divide and Fraction Data Control 1 Register

Address: 3036_0000h base + 30h offset = 3036_0030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM

5.1.8.14 VIDEO PLL1 PLL SSCG Control Register

(CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL)

VIDEO PLL1 PLL SSCG Control Register

Address: 3036_0000h base + 34h offset = 3036_0034h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN

Reserved PLL_MFREQ_CTL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

576 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL field descriptions

Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(2^5) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr x mrr /m /(2^6) x 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control

00 Down spread
01 Up spread
1x Center spread

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 577
Clock Control Module (CCM)

5.1.8.15 VIDEO PLL1 PLL Monitoring Control Register

(CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL)

VIDEO PLL1 PLL Monitoring Control Register

Address: 3036_0000h base + 38h offset = 3036_0038h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBIAS_CTRL_EN
R

AFCINIT_SEL
PBIAS_CTRL
AFC_SEL

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
FEED_EN

AFC_EN
FSEL Reserved EXTAFC ICP

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1

CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL field descriptions

Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

578 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL field descriptions (continued)

Field Description
0 nominal delay
1 nominal delay * 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 579
Clock Control Module (CCM)

5.1.8.16 DRAM PLL General Function Control Register

(CCM_ANALOG_DRAM_PLL_GEN_CTRL)

DRAM PLL General Function Control Register

Address: 3036_0000h base + 50h offset = 3036_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

PLL_EXT_BYPASS
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

R
PLL_BYPASS
PLL_CLKE

PLL_ PAD_CLK_ PLL_REF_

Reserved Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_DRAM_PLL_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

580 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_DRAM_PLL_GEN_CTRL field descriptions (continued)

Field Description
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 581
Clock Control Module (CCM)

5.1.8.17 DRAM PLL Divide and Fraction Data Control 0 Register

(CCM_ANALOG_DRAM_PLL_FDIV_CTL0)

DRAM PLL Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 54h offset = 3036_0054h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0

CCM_ANALOG_DRAM_PLL_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

582 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.18 DRAM PLL Divide and Fraction Data Control 1 Register

(CCM_ANALOG_DRAM_PLL_FDIV_CTL1)

DRAM PLL Divide and Fraction Data Control 1 Register

Address: 3036_0000h base + 58h offset = 3036_0058h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_DRAM_PLL_FDIV_CTL1 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM

5.1.8.19 DRAM PLL PLL SSCG Control Register

(CCM_ANALOG_DRAM_PLL_SSCG_CTRL)

DRAM PLL PLL SSCG Control Register

Address: 3036_0000h base + 5Ch offset = 3036_005Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN

Reserved PLL_MFREQ_CTL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 583
Clock Control Module (CCM)

CCM_ANALOG_DRAM_PLL_SSCG_CTRL field descriptions

Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(2^5) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr x mrr /m /(2^6) x 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control

00 Down spread
01 Up spread
1x Center spread

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

584 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.20 DRAM PLL PLL Monitoring Control Register

(CCM_ANALOG_DRAM_PLL_MNIT_CTRL)

DRAM PLL PLL Monitoring Control Register

Address: 3036_0000h base + 60h offset = 3036_0060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBIAS_CTRL_EN
R

AFCINIT_SEL
PBIAS_CTRL
AFC_SEL

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
FEED_EN

AFC_EN
FSEL Reserved EXTAFC ICP

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1

CCM_ANALOG_DRAM_PLL_MNIT_CTRL field descriptions

Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 585
Clock Control Module (CCM)

CCM_ANALOG_DRAM_PLL_MNIT_CTRL field descriptions (continued)

Field Description
0 nominal delay
1 nominal delay * 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

586 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.21 GPU PLL General Function Control Register

(CCM_ANALOG_GPU_PLL_GEN_CTRL)

GPU PLL General Function Control Register

Address: 3036_0000h base + 64h offset = 3036_0064h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 587
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_GPU_PLL_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

588 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_GPU_PLL_GEN_CTRL field descriptions (continued)

Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

5.1.8.22 GPU PLL Divide and Fraction Data Control 0 Register

(CCM_ANALOG_GPU_PLL_FDIV_CTL0)

GPU PLL Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 68h offset = 3036_0068h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 589
Clock Control Module (CCM)

CCM_ANALOG_GPU_PLL_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

5.1.8.23 PLL Lock Detector Control Register

(CCM_ANALOG_nLOCKD_CTRL)

PLL Lock Detector Control Register

Address: 3036_0000h base + 6Ch offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R LOCK LOCK LOCK

_ _ _
Reserved
CON_ CON_ CON_
W DLY OUT IN

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

CCM_ANALOG_nLOCKD_CTRL field descriptions

Field Description
31–6 This field is reserved.
- Reserved
5–4 Lock detector setting of the detection resolution
LOCK_CON_
DLY
3–2 Lock detector setting of the output margin
LOCK_CON_
OUT
LOCK_CON_IN Lock detector setting of the input margin

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

590 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.24 PLL Monitoring Control Register

(CCM_ANALOG_nMNIT_CTRL)

PLL Monitoring Control Register

Address: 3036_0000h base + 70h offset + (16d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBIAS_CTRL_EN
R

AFCINIT_SEL
FOUT_MASK

PBIAS_CTRL
AFC_SEL
LRD_EN
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
FEED_EN
Reserved

AFC_EN
FSEL Reserved EXTAFC ICP

Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1

CCM_ANALOG_nMNIT_CTRL field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21 Monitoring pin. AFC operation mode select pin
LRD_EN
20 Scaler's re-initialization time control pin[3]
FOUT_MASK
19 AFC Mode select
AFC_SEL
18 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 591
Clock Control Module (CCM)

CCM_ANALOG_nMNIT_CTRL field descriptions (continued)

Field Description
17 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
16 AFC initial delay select pin
AFCINIT_SEL
0 nominal delay
1 nominal delay * 2
15 This field is reserved.
- Reserved
14 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
13 FEED_OUT enable pin
FEED_EN
12–8 This field is reserved.
- Reserved
7–3 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
2 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

592 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.25 VPU PLL General Function Control Register

(CCM_ANALOG_VPU_PLL_GEN_CTRL)

VPU PLL General Function Control Register

Address: 3036_0000h base + 74h offset = 3036_0074h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 593
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_VPU_PLL_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

594 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_VPU_PLL_GEN_CTRL field descriptions (continued)

Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

5.1.8.26 VPU PLL Divide and Fraction Data Control 0 Register

(CCM_ANALOG_VPU_PLL_FDIV_CTL0)

VPU PLL Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 78h offset = 3036_0078h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 595
Clock Control Module (CCM)

CCM_ANALOG_VPU_PLL_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

596 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.27 ARM PLL General Function Control Register

(CCM_ANALOG_ARM_PLL_GEN_CTRL)

ARM PLL General Function Control Register

Address: 3036_0000h base + 84h offset = 3036_0084h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 597
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_ARM_PLL_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

598 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_ARM_PLL_GEN_CTRL field descriptions (continued)

Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

5.1.8.28 ARM PLL Divide and Fraction Data Control 0 Register

(CCM_ANALOG_ARM_PLL_FDIV_CTL0)

ARM PLL Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 88h offset = 3036_0088h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 599
Clock Control Module (CCM)

CCM_ANALOG_ARM_PLL_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

600 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.29 SYS PLL1 General Function Control Register

(CCM_ANALOG_SYS_PLL1_GEN_CTRL)

SYS PLL1 General Function Control Register

Address: 3036_0000h base + 94h offset = 3036_0094h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

PLL_DIV20_CLKE_OVERRIDE

PLL_DIV10_CLKE_OVERRIDE

PLL_DIV8_CLKE_OVERRIDE

PLL_DIV6_CLKE_OVERRIDE

PLL_DIV5_CLKE_OVERRIDE

PLL_DIV4_CLKE_OVERRIDE
R
PLL_EXT_BYPASS

PLL_DIV20_CLKE

PLL_DIV10_CLKE

PLL_DIV8_CLKE

PLL_DIV6_CLKE

PLL_DIV5_CLKE

PLL_DIV4_CLKE
PLL_LOCK_SEL
Reserved

Reset 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 601
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PLL_DIV3_CLKE_OVERRIDE

PLL_DIV2_CLKE_OVERRIDE

PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE
PLL_DIV3_CLKE

PLL_DIV2_CLKE

PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved
RST SEL CLK_SEL

Reset 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_SYS_PLL1_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27 PLL clock divided by 20 output gating enable
PLL_DIV20_
CLKE
26 PLL clock divided by 20 output gating enable overrided by CCM
PLL_DIV20_
CLKE_
OVERRIDE
25 PLL clock divided by 10 output gating enable
PLL_DIV10_
CLKE
24 PLL clock divided by 10 output gating enable overrided by CCM
PLL_DIV10_
CLKE_
OVERRIDE
23 PLL clock divided by 8 output gating enable
PLL_DIV8_CLKE

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

602 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_SYS_PLL1_GEN_CTRL field descriptions (continued)

Field Description
22 PLL clock divided by 8 output gating enable overrided by CCM
PLL_DIV8_
CLKE_
OVERRIDE
21 PLL clock divided by 6 output gating enable
PLL_DIV6_CLKE
20 PLL clock divided by 6 output gating enable overrided by CCM
PLL_DIV6_
CLKE_
OVERRIDE
19 PLL clock divided by 5 output gating enable
PLL_DIV5_CLKE
18 PLL clock divided by 5 output gating enable overrided by CCM
PLL_DIV5_
CLKE_
OVERRIDE
17 PLL clock divided by 4 output gating enable
PLL_DIV4_CLKE
16 PLL clock divided by 4 output gating enable overrided by CCM
PLL_DIV4_
CLKE_
OVERRIDE
15 PLL clock divided by 3 output gating enable
PLL_DIV3_CLKE
14 PLL clock divided by 3 output gating enable overrided by CCM
PLL_DIV3_
CLKE_
OVERRIDE
13 PLL clock divided by 2 output gating enable
PLL_DIV2_CLKE
12 PLL clock divided by 2 output gating enable overrided by CCM
PLL_DIV2_
CLKE_
OVERRIDE
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 603
Clock Control Module (CCM)

CCM_ANALOG_SYS_PLL1_GEN_CTRL field descriptions (continued)

Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

5.1.8.30 SYS PLL1 Divide and Fraction Data Control 0 Register

(CCM_ANALOG_SYS_PLL1_FDIV_CTL0)

SYS PLL1 Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 98h offset = 3036_0098h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

604 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_SYS_PLL1_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

5.1.8.31 PLL Monitoring Control Register

(CCM_ANALOG_nMNIT_CTRL)

PLL Monitoring Control Register

Address: 3036_0000h base + 100h offset + (16d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PBIAS_CTRL_EN
R

AFCINIT_SEL
FOUT_MASK

PBIAS_CTRL
AFC_SEL
LRD_EN

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
FEED_EN
Reserved

AFC_EN

FSEL Reserved EXTAFC ICP

Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 605
Clock Control Module (CCM)

CCM_ANALOG_nMNIT_CTRL field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21 Monitoring pin. AFC operation mode select pin
LRD_EN
20 Scaler's re-initialization time control pin[3]
FOUT_MASK
19 AFC Mode select
AFC_SEL
18 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
17 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
16 AFC initial delay select pin
AFCINIT_SEL
0 nominal delay
1 nominal delay * 2
15 This field is reserved.
- Reserved
14 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
13 FEED_OUT enable pin
FEED_EN
12–8 This field is reserved.
- Reserved
7–3 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
2 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

606 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.1.8.32 SYS PLL2 General Function Control Register

(CCM_ANALOG_SYS_PLL2_GEN_CTRL)

SYS PLL2 General Function Control Register

Address: 3036_0000h base + 104h offset = 3036_0104h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

PLL_DIV20_CLKE_OVERRIDE

PLL_DIV10_CLKE_OVERRIDE

PLL_DIV8_CLKE_OVERRIDE

PLL_DIV6_CLKE_OVERRIDE

PLL_DIV5_CLKE_OVERRIDE

PLL_DIV4_CLKE_OVERRIDE
R
PLL_EXT_BYPASS

PLL_DIV20_CLKE

PLL_DIV10_CLKE

PLL_DIV8_CLKE

PLL_DIV6_CLKE

PLL_DIV5_CLKE

PLL_DIV4_CLKE
PLL_LOCK_SEL
Reserved

Reset 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 607
Clock Control Module (CCM)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PLL_DIV3_CLKE_OVERRIDE

PLL_DIV2_CLKE_OVERRIDE

PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE
PLL_DIV3_CLKE

PLL_DIV2_CLKE

PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved
RST SEL CLK_SEL

Reset 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_SYS_PLL2_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27 PLL clock divided by 20 output gating enable
PLL_DIV20_
CLKE
26 PLL clock divided by 20 output gating enable overrided by CCM
PLL_DIV20_
CLKE_
OVERRIDE
25 PLL clock divided by 10 output gating enable
PLL_DIV10_
CLKE
24 PLL clock divided by 10 output gating enable overrided by CCM
PLL_DIV10_
CLKE_
OVERRIDE
23 PLL clock divided by 8 output gating enable
PLL_DIV8_CLKE

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

608 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_SYS_PLL2_GEN_CTRL field descriptions (continued)

Field Description
22 PLL clock divided by 8 output gating enable overrided by CCM
PLL_DIV8_
CLKE_
OVERRIDE
21 PLL clock divided by 6 output gating enable
PLL_DIV6_CLKE
20 PLL clock divided by 6 output gating enable overrided by CCM
PLL_DIV6_
CLKE_
OVERRIDE
19 PLL clock divided by 5 output gating enable
PLL_DIV5_CLKE
18 PLL clock divided by 5 output gating enable overrided by CCM
PLL_DIV5_
CLKE_
OVERRIDE
17 PLL clock divided by 4 output gating enable
PLL_DIV4_CLKE
16 PLL clock divided by 4 output gating enable overrided by CCM
PLL_DIV4_
CLKE_
OVERRIDE
15 PLL clock divided by 3 output gating enable
PLL_DIV3_CLKE
14 PLL clock divided by 3 output gating enable overrided by CCM
PLL_DIV3_
CLKE_
OVERRIDE
13 PLL clock divided by 2 output gating enable
PLL_DIV2_CLKE
12 PLL clock divided by 2 output gating enable overrided by CCM
PLL_DIV2_
CLKE_
OVERRIDE
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 609
Clock Control Module (CCM)

CCM_ANALOG_SYS_PLL2_GEN_CTRL field descriptions (continued)

Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

5.1.8.33 SYS PLL2 Divide and Fraction Data Control 0 Register

(CCM_ANALOG_SYS_PLL2_FDIV_CTL0)

SYS PLL2 Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 108h offset = 3036_0108h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

610 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_SYS_PLL2_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

5.1.8.34 PLL Lock Detector Control Register

(CCM_ANALOG_nLOCKD_CTRL)

PLL Lock Detector Control Register

Address: 3036_0000h base + 10Ch offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R LOCK LOCK LOCK

_ _ _
Reserved
CON_ CON_ CON_
W DLY OUT IN

Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

CCM_ANALOG_nLOCKD_CTRL field descriptions

Field Description
31–6 This field is reserved.
- Reserved
5–4 Lock detector setting of the detection resolution
LOCK_CON_
DLY
3–2 Lock detector setting of the output margin
LOCK_CON_
OUT
LOCK_CON_IN Lock detector setting of the input margin

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 611
Clock Control Module (CCM)

5.1.8.35 SYS PLL3 General Function Control Register

(CCM_ANALOG_SYS_PLL3_GEN_CTRL)

SYS PLL3 General Function Control Register

Address: 3036_0000h base + 114h offset = 3036_0114h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK

R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

612 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_CLKE_OVERRIDE

PLL_RST_OVERRIDE

PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL

Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_SYS_PLL3_GEN_CTRL field descriptions

Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 613
Clock Control Module (CCM)

CCM_ANALOG_SYS_PLL3_GEN_CTRL field descriptions (continued)

Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.

00 CLKIN1 XOR CLKIN2

01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved

5.1.8.36 SYS PLL3 Divide and Fraction Data Control 0 Register

(CCM_ANALOG_SYS_PLL3_FDIV_CTL0)

SYS PLL3 Divide and Fraction Data Control 0 Register

Address: 3036_0000h base + 118h offset = 3036_0118h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PLL_MAIN_DIV

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV

Reset 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

614 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_SYS_PLL3_FDIV_CTL0 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider

5.1.8.37 Osc Misc Configuration Register

(CCM_ANALOG_OSC_MISC_CFG)

Osc Misc Register

Address: 3036_0000h base + 124h offset = 3036_0124h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OSC_32K_SEL
R

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_OSC_MISC_CFG field descriptions

Field Description
31–1 This field is reserved.
- Reserved
0 32KHz OSC input select
OSC_32K_SEL
0 Divided by 24M clock
1 32K Oscillator

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 615
Clock Control Module (CCM)

5.1.8.38 PLL Clock Output for Test Enable and Select Register
(CCM_ANALOG_ANAMIX_PLL_MNIT_CTL)

PLL Clock Output for Test Enable and Select Register

Address: 3036_0000h base + 128h offset = 3036_0128h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OUTPUT_CKE
R

CLKOUT2_
CLKOUT2_OUTPUT_DIV_
Reserved CLKOUT2_OUTPUT_SEL
VAL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTPUT_CKE

R
CLKOUT1_

CLKOUT1_OUTPUT_DIV_
Reserved CLKOUT1_OUTPUT_SEL
VAL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCM_ANALOG_ANAMIX_PLL_MNIT_CTL field descriptions

Field Description
31–25 This field is reserved.
- Reserved
24 CLKOUT2 Monitor output enable
CLKOUT2_
OUTPUT_CKE
23–20 CLKOUT2 Monitor output clock select
CLKOUT2_
4'b0000 : audio_pll1_clk
OUTPUT_SEL
4'b0001 : audio_pll2_clk
4'b0010 : video_pll1_clk
4'b0011 : reserved
4'b0100 : misc_mnit_clk
4'b0101 : gpu_pll_clk
4'b0110 : vpu_pll_clk
4'b0111 : arm_pll_clk
4'b1000 : system_pll1_clk
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

616 NXP Semiconductors
 Chapter 5 Clocks and Power Management

CCM_ANALOG_ANAMIX_PLL_MNIT_CTL field descriptions (continued)

Field Description
4'b1001 : system_pll2_clk
4'b1010 : system_pll3_clk
4'b1011 : CLKIN1
4'b1100 : CLKIN2
4'b1101 : sysosc_24m_clk
4'b1110 : reserved
4'b1111 : osc_32k_clk
19–16 CLKOUT2 output divide value
CLKOUT2_
OUTPUT_DIV_
VAL
15–9 This field is reserved.
- Reserved
8 CLKOUT1 Monitor output enable
CLKOUT1_
OUTPUT_CKE
7–4 CLKOUT1 Monitor output clock select
CLKOUT1_
4'b0000 : audio_pll1_clk
OUTPUT_SEL
4'b0001 : audio_pll2_clk
4'b0010 : video_pll1_clk
4'b0011 : reserved
4'b0100 : misc_mnit_clk
4'b0101 : gpu_pll_clk
4'b0110 : vpu_pll_clk
4'b0111 : arm_pll_clk
4'b1000 : system_pll1_clk
4'b1001 : system_pll2_clk
4'b1010 : system_pll3_clk
4'b1011 : CLKIN1
4'b1100 : CLKIN2
4'b1101 : sysosc_24m_clk
4'b1110 : reserved
4'b1111 : osc_32k_clk
CLKOUT1_ CLKOUT1 output divide value
OUTPUT_DIV_
VAL

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 617
General Power Controller (GPC)

5.1.8.39 DIGPROG Register (CCM_ANALOG_DIGPROG)

DIGPROG Register
Address: 3036_0000h base + 800h offset = 3036_0800h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R DIGPROG_MAJOR_UPPER DIGPROG_MAJOR_LOWER DIGPROG_MINOR

Reserved
W

Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0

CCM_ANALOG_DIGPROG field descriptions

Field Description
31–24 This field is reserved.
- Reserved
23–16 Bit[7:4] is 0x8, stands for “i.MX8” Bit[3:0] is 0x2, stands for ”M”
DIGPROG_
MAJOR_UPPER
15–8 Bit[7:4] is 0x4, stands for “Quad” Bit[3:0] is 0x1, stands for “Mini”
DIGPROG_
MAJOR_LOWER
DIGPROG_ Bit[7:4] is the base layer revision, Bit[3:0] is the metal layer revision 0x10 stands for Tapeout 1.0
MINOR

5.2 General Power Controller (GPC)

5.2.1 Overview
The General Power Controller (GPC) module controls the following functions:
• Provide low power mode control for A53 and M4 platform
• Provide Power domain management all Arm and SOC power domain
• Provide domain control mechanism based on A53 and M4 CPU domain
• Provide handshake with CCM for clock management in low power mode
• Provide handshake with SRC for power down and power up sequence
• Provide handshake with Analog for Deep Sleep Mode control

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

618 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.2 Features
The General Power Controller (GPC) module controls the following functions:
• Support programmable feature for WAIT/STOP/DSM low power mode
• Support time slot based power domain control
• Support flexible sleep and wakeup condition
• Support domain control for multi CPU platforms system
• All register accessed by IP bus
• Interface for the following IPs:
• CCM – clock controller module
• SRC – system reset controller
• ANALOG – miscellaneous analog control

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 619
General Power Controller (GPC)

5.2.3 Block Diagram

Handshake with
analog and PMIC

interrupt
LPM Quad A53 LPM M4

wfi

DSM Control

SMC

Power state Clock handshake Power handshake

Power state

Clock handshake Domain

Control
Logic
PGC_1
Handshake with SRC

Timeslot PGC_2

...
Control

PGC_PDN
PGTSC

Power signal

Figure 5-10. GPC Block Diagram

The GPC module contains two sub-modules: System Mode Controller (SMC) and Power
Gating Time Slot Control (PGTSC):
• GPC Top: the top level GPC. It also includes the top memory map and registers,
domain control information, and memory low power control.
• System Mode Controller (SMC):
• The SMC supports two low power modes (LPM), WAIT and STOP. Each LPM
corresponds to one mode for A53 platform and one mode for M4 platform.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

620 NXP Semiconductors
 Chapter 5 Clocks and Power Management

• SMC controls the power sequence in Deep Sleep Mode (DSM)

• SMC support the power up and power down of A53 core0/core1/core2/core3 by
IRQ/WFI signals without LPM triggered
• SMC can translate the LPM request for A53 and M4 platform to power up and
power down request to PGTSC.
• Power Gating Time Slot Control (PGTSC):
• The Power Gating Controller (PGC) is a power management component that
controls the power-down and power-up sequencing of individual
subsystems. For subsystems to be completely powered down in low power
modes, a specific sequence of power control signals must be followed. The
sequence timing is programmable using the PGC control registers.
• There are 20 PGCs in the chip, all of them can be power down/up with a
software trigger and all of them can be mapped to 20 timing slots and
power-up and power down by request from SMC.

5.2.4 Functional Description

5.2.4.1 RUN mode

This is the normal/functional operating mode. In this mode, the CPU runs in its normal
operational mode.

5.2.4.2 Low power mode

There are two CPU platforms (each of them represents a CPU domain): Quad core Cortex
A53 platform and Cortex M4 platform. Each platform supports two low power modes:
WAIT mode and STOP mode.

5.2.4.2.1 WAIT mode

In this low power mode:
• LPCG can be defined to be shut off or not in wait mode for each CPU domain
• PLL can be defined to be shut off or not in wait mode for each CPU domain
NOTE
The PLLs will only been closed in non-fast wake-up mode,
relevant bit are

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 621
General Power Controller (GPC)

GPC_SLPCR[EN_A53_FASTWUP_WAIT_MODE] and
GPC_SLPCR[EN_M4_FASTWUP_WAIT_MODE]
• CPU clock can be defined been shut off or not in wait for each CPU platform.
(GPC_LPCR_A53_BSC[CPU_CLK_ON_LPM] and
GPC_LPCR_M4[CPU_CLK_ON_LPM])
• Power of different power domain can be defined be shut off or not in wait mode for
each platform domain
• Some peripherals may go to wait mode along with A53 or M4 platform.

5.2.4.2.2 STOP mode

In this low power mode:
• LPCG can be defined been shut off or not in stop mode for each CPU domain
• PLL can be defined been shut off or not in stop mode for each CPU domain
NOTE
The PLLs will only been closed in non-fast wake-up mode,
relevant bit are
GPC_SLPCR[EN_A53_FASTWUP_STOP_MODE] and
GPC_SLPCR[EN_M4_FASTWUP_STOP_MODE]
• CPU clock can be defined been shut off or not in stop for each CPU
(GPC_LPCR_A53_BSC[CPU_CLK_ON_LPM] and
GPC_LPCR_M4[CPU_CLK_ON_LPM])
• Power of different power domain can be defined be shut off or not in stop mode for
each platform domain
• Some peripherals may go to stop mode along with A53 or M4 platform.

5.2.4.3 Deep Sleep Mode

The Deep Sleep Mode (DSM) is a system low power mode.
In this mode:
• On-chip OSC can be defined to be shut off or not in DSM (GPC_SLPCR[SBYOS])
• PMIC can be defined to be stand-by mode or not in DSM (GPC_SLPCR[VSTBY])
• Regulator can be defined to be BYPASS mode or not in DSM
(GPC_SLPCR[RBC_EN])
• Memory can be defined to go to retention mode or not in
DSM(GPC_MLPCR[MEMLP_CTL_DIS])
• A53 platform power (VDD_ARM) can be defined to be shut off or not in DSM.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

622 NXP Semiconductors
 Chapter 5 Clocks and Power Management

NOTE
CCM configuration must make sure close all PLLs before
system goes to DSM
NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.

5.2.4.4 LPM Sleep Process

CPU platform will go to WAIT/STOP under the following conditions:
• LPM registers (GPC_LPCR_A53_BSC[LPM0], GPC_LPCR_A53_BSC[LPM1],
GPC_LPCR_A53_BSC2[LPM2], GPC_LPCR_A53_BSC2[LPM3],
GPC_LPCR_M4[LPM]) are set to WAIT or STOP.
NOTE
Since A53 platform has four cores, the so each core has its
own LPM register: GPC_LPCR_A53_BSC[LPM0] and
GPC_LPCR_A53_BSC[LPM1],
GPC_LPCR_A53_BSC2[LPM2] and
GPC_LPCR_A53_BSC2[LPM3]. The unified LPM of A53
will be generated with the lower LPM of the cores.
• Asserting the WFI signal will trigger CPU sleep process. There are five WFIs that
come from A53 platform: WFI_core0, WFI_core1, WFI_core2, WFI_core3, and
WFI_scu. The A53 platform will go to LPM when all WFIs are asserted. If the
GPC_LPCR_A53_AD[EN_C0_WFI_PDN] or
GPC_LPCR_A53_AD[EN_C1_WFI_PDN] or
GPC_LPCR_A53_AD[EN_C2_WFI_PDN] or
GPC_LPCR_A53_AD[EN_C3_WFI_PDN] bit is set, the LPM trigger condition will
be a little different. See Power control for A53 Platform for more information. Only
one WFI comes from M4 platform. The M4 platform will go to LPM when WFI_M4
asserted.
NOTE
WFI condition can be masked by register bits
GPC_LPCR_A53_BSC[MASK_n_WFI] and
GPC_LPCR_M4[MASK_M4_WFI]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 623
General Power Controller (GPC)

RUN
LPM = 10
AND ~dsm_request
dsm_request LPM = 01 OR
AND AND dsm_wakeup
~dsm_wakeup ~dsm_request dsm_request
OR AND
dsm_wakeup ~dsm_wakeup

STOP WAIT

dsm_request dsm_request
AND gpc_pup_ack AND gpc_pup_ack
~dsm_wakeup ~dsm_wakeup

STOP_PGC WAIT_PGC

Figure 5-11. LPM transition inside CPU platform

System will go to DSM under the following conditions:

• Both A53 and M4 are STOP mode.
• Both GPC_SLPCR[EN_A53_FASTWUP_STOP_MODE] and
GPC_SLPCR[EN_M4_FASTWUP_STOP_MODE] are not set.
• GPC_SLPCR[EN_DSM] is set.
NOTE
If GPC_LPCR_M4[MASK_DSM_TRIGGER] is set, the
system will go to DSM when A53 goes STOP mode and
GPC_SLPCR[EN_A53_FASTWUP_STOP_MODE] is not
set. If GPC_LPCR_A53_BSC[MASK_DSM_TRIGGER]
is set, the system will go to DSM when M4 goes to STOP
mode and
GPC_SLPCR[EN_M4_FASTWUP_STOP_MODE] not
set. GPC_LPCR_M4[MASK_DSM_TRIGGER] and
GPC_LPCR_A53_BSC[MASK_DSM_TRIGGER] cannot
be set at the same time.

5.2.4.5 LPM Wake Up Process

DSM, STOP, WAIT mode will be woken up by interrupts:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

624 NXP Semiconductors
 Chapter 5 Clocks and Power Management

• The CPU platforms share the same IRQ sources in this chip. Software can use
GPC_IMRn_CORE0_A53, GPC_IMRn_CORE1_A53, GPC_IMRn_CORE2_A53,
GPC_IMRn_CORE3_A53, and GPC_IMRn_M4 to separate the 128 bits IRQ
sources to A53 core0, core1, core2, and core3, and M4 platform.
• The A53 core0, core1, core2, and core3 IRQ can also be from GIC source (defined
by GPC_LPCR_A53_BSC[IRQ_SRC_C3], GPC_LPCR_A53_BSC[IRQ_SRC_C2],
GPC_LPCR_A53_BSC[IRQ_SRC_C1], and
GPC_LPCR_A53_BSC[IRQ_SRC_C0]) and if it is chosen from GIC source the
GPC_IMRn_x_A53 will lose its function. See Power control for A53 Platform for
more information.
• Interrupts for both A53 and M4 will cause the system wake up from DSM, A53
interrupt will wake up A53 from LPM, M4 interrupt will wake up M4 from LPM.

5.2.5 Power Gating Controller (PGC) Overview

The Power Gating Controller (PGC) is a power management component that controls the
power-down and power-up sequencing of individual subsystems. For subsystems to be
completely powered down in low power modes, a specific sequence of power control
signals must be followed. The sequence timing is programmable using the PGC control
registers.

Power-Management and Clock-Control Subsystem

PGC
Higher-level pdn_req isolation
Componenet Target
pup_req
Subsystem
pdn_ack switch_b
pup_ack

module_clk pwrgate_rst_b
enable_clk

Figure 5-12. Power Gating Controller (PGC)

5.2.5.1 PGC power domains

The following table lists the PGCs in the chip and the corresponding power domain.
There are three types of PGC - CPU, MIX, and PU. The power for the PUs (Power Units)
can be controlled by the GPC.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 625
General Power Controller (GPC)

PGC type Type Power domain

PGC_C0 CPU Core0 of A53 platform
PGC_C1 CPU Core1 of A53 platform
PGC_C2 CPU Core2 of A53 platform
PGC_C3 CPU Core3 of A53 platform
PGC_SCU CPU SCU/L2 cache RAM of A53 platform
PGC_NOC MIX NOC
PGC_PCIE PU PCIE PHY
PGC_OTG1 PU USB OTG1 PHY
PGC_OTG2 PU USB OTG2 PHY
PGC_DDR1 PU DDR1
PGC_DISPMIX PU DISPMIXMIX
GPC_MIPI PU MIPI PHY
PGC_GPUMIX PU GPUMIX
PGC_GPU_3D PU GPU_3D
PGC_GPU_2D PU GPU_2D
PGC_VPUMIX PU VPUMIX
PGC_VPU_G1 PU VPU_G1
PGC_VPU_G2 PU VPU_G2
PGC_VPU_H1 PU VPU_H1

5.2.5.2 Trigger to PGC: Hardware and Software Requests

All PGCs can be power up/down by hardware or software request.
The LPM controller for each platform can generate hardware power down or power up
request. All hardware requests will be mapped to “timeslot controller” before they goes to
relevant PGC (see “Time slot control for PGCs” for more information).
The CPU can also generate software power up or power down request to relevant PGCs.
The software trigger will not be mapped to timeslot control. If there are PGCs in software
PDN/PUP sequence the request from LPM will be masked. The software trigger will also
be failed if the timeslot control is in “busy” state.
All power up/down request to PGCs will be mapped to domain control module (see
“Domain control for PGCs ”).
PGC_C0, PGC_C1, PGC_C2, and PGC_C3 can be triggered by its own “WFI/IRQ”
without LPM trigger and time slot. See Power control for A53 Platform for more
information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

626 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.5.3 Time slot control mechanism for PGCs

GPC uses a time slot controller to control the PGC sub-systems, such as the PGC in
CPU0, CPU1,CPU2, CPU3, MIX, PCIE PHY, etc. We use it for below reasons when
system wakes from low power mode.
1. Support flexible power down/up sequence for different sub-system
2. Sub-system can be power up in different slot to avoid large ramping up current in
case they start ramping up at the same time
There are a total of 20 time slots used in the chip, one or more PGCs are used for power
up or power down in each of these slots. The time slot controller will sample power up/
down requests at slot0. If there are power up/down requests from SMC, it will scan from
slot0 to slot19. When the scan process comes to one slot which has a defined power up or
power down for one or more PGCs (defined by “SLTn_CFG”), the power up/down
sequence of relevant PGCs will happen in that slot. Otherwise, the relevant slot will be
skipped.
The next slot will not begin until the all PGCs finish their power up or power down
process in current time slot. When all the 20 slots are finished, slot controller will jump to
IDLE state and monitor new request from SMC.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 627
General Power Controller (GPC)

IDLE

sample hw_*_req, total 20 requests

any No
hw_*_req asserted

Yes

slot0 check slt0_cfg, power-up/down PGC if request asserted, ACK to hw_*_req

if slt0_cfg is 18'h0, stay in slot0 one cycle, then jumps to slot1

slot1 check slt1_cfg, power-up/down PGC if request asserted, ACK to hw_*_req

if slt1_cfg is 18'h0, stay in slot1 one cycle, then jumps to slot2

.....

slot19 check slt19_cfg, power-up/down PGC if request asserted, ACK to hw_*_req

if slt19_cfg is 18'h0, stay in slot19 one cycle, then jumps to IDLE

Figure 5-13. Slot controller processing flow

NOTE
PGC_SCU should be “always-on” to PGC_C0 PGC_C1,
PGC_C2, and PGC_C3. This means PGC_SCU should be
power up earlier than PGC_C0/PGC_C1/PGC_C2/PGC_C3
and should be power down later than PGC_C0/PGC_C1/
PGC_C2/PGC_C3 (see example code 1 and 2). If we arrange
A53 Cx/A53 SCU power down/up in same slot, special setting
is required (see example code 2).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

628 NXP Semiconductors
 Chapter 5 Clocks and Power Management

NOTE
When the system enters/exists ALL_OFF or L2_RETENTION
mode, PGC_MF should be power up earlier than PGC_C0/
PGC_C1/PGC_C2/PGC_C3/PGC_SCU. We can arrange MIX
PGC power up in earlier slot than A53 Cx/SCU power up slot
(See example code 1 and 2).

5.2.5.4 Handshake between LPM controller and time slot controller

The figure below shows an example of A53 “into” LPM sequence. We want to power up
A53 SCU and A53 core0 in time slot0 /slot1/slot2 respectively. Request from low power
mode controller will be mapped to relevant PGCs according to the rules listed above. We
choose acknowledge from PGC_core0 as the acknowledge for A53 LPM power down
request (relevant register bits are defined in “PGC_ACK_SEL_A53”). The A53 LPM
will regard the three PGCs as a virtual big PGC and it will cancel all power up request
when it receive the acknowledge signals from PGC_core0.

slot0 slot1 slot2

pup_req
PGC_mf
time

Low power mode pup_req pup_req

logic PGC_plat
controller for
A53 platform
pup_req
PGC_c0

pup_ack Virtual PGC for A53 Platform

Figure 5-14. A53 into LPM sequence

NOTE
If a PGC is mapped to two CPU domain (refer to “Domain
control for PGCs ”for more information), it cannot be selected
as the power down acknowledge for both of the CPU platform.
“PGC_ACK_SEL_A53”, "PGC_ACK_SEL_A53_PU", and
“PGC_ACK_SEL_M4” are should be chosen for the last PGC
in power up or power down sequence in the time slot. If there is
no PGC be power up/power down with LPM sequence, the
“dummy” acknowledge should be selected. Only one PGC

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 629
General Power Controller (GPC)

should be selected for power down or power up acknowledge

for one CPU platform.

5.2.6 Power control for A53 Platform

5.2.6.1 A53 Platform power domains and power modes

There are four power domains inside SEC dual core Cortex A53 platform: Core0, Core1,
Core2, Core3, SCU, and L2 RAM. There are six power states in A53 platform:
Power State PDCPU0 PDCPU1 PDCPU2 PDCPU3 PDPLAT PDL2 VDD_ARM
ALL_ON ON ON ON ON ON ON ON
THREE_CPU 3 CPUs are ON, 1 CPU is OFF ON ON ON
_ON
TWO_CPU_O 2 CPUs are ON, 2 CPUs are OFF ON ON ON
N
ONE_CPU_O 1 CPU is ON, 3 CPUs are OFF ON ON ON
N
ALL_CPU_OF OFF OFF OFF OFF ON ON ON
F
L2_RETENTI OFF OFF OFF OFF OFF RET ON
ON
ALL_OFF OFF OFF OFF OFF OFF OFF ON
POWER_DO OFF OFF OFF OFF OFF OFF OFF
WN

NOTE
In all six power states, “ALL_ON”, “THREE_CPU_ON",
"TWO_CPU_ON", and "ONE_CPU_ON" can exist in all RUN,
WAIT or STOP mode of A53 platform. “L2_RETENTION”
and “ALL_OFF” can only exist in WAIT or STOP mode of
A53 platform.

5.2.6.2 Power down process for the A53 Platform

5.2.6.2.1 Power down of Core0, Core1, Core2, and Core3 in the A53
Platform
The power of core0, core1, core2, and core3 can be shut off along with the LPM process,
as show in the following figure:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

630 NXP Semiconductors
 Chapter 5 Clocks and Power Management

SCU WFI

Core0 WFI Core1 WFI

&
Core2 WFI Core3 WFI

WAIT/STOP

Core0 Core3
Power-down Power-down
Core1 Core2
Power-down Power-down

WAIT_PGC
STOP_PGC

Figure 5-15. Power down of Core0, Core1, Core2, and Core3

WFIs from A53 platform will trigger the A53 platform LPM and the power of core0,
core1, core2, or core3 will be shut off when “lpcr_a53_ad.en_c0_pdn”,
“lpcr_a53_ad.en_c1_pdn”, “lpcr_a53_ad.en_c2_pdn”, or “lpcr_a53_ad.en_c3_pdn”
enabled in this process. This mode should be used when core0 is used as the leading core
of A53 platform.
The power of core0, core1, core2, and core3 can also be shut off in RUN mode: in this
mode “LPCR_A53_AD.en_c0_wfi_pdn”, “LPCR_A53_AD.en_c1_wfi_pdn”,
“LPCR_A53_AD.en_c2_wfi_pdn”, and “LPCR_A53_AD.en_c3_wfi_pdn” should be set
and the condition to trigger A53 LPM will be some different:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 631
General Power Controller (GPC)

Core0 Core1
Power-down Power-down
ACK ACK
Core2 SCU WFI Core3
Power-down Power-down
ACK ACK

Core0 Core1
Power-down Power-down

Core2 Core3
Power-down Power-down

&

WAIT/STOP

WAIT_PGC
STOP_PGC

Figure 5-16. Power down of Core0, Core1, Core2, and Core3 in RUN mode

In this mode, core0/core1/core2/core3 power down process should not be disturbed by

IRQs.

5.2.6.2.2 Power down of SCU and L2 Cache RAM

Power domain SCU and L2 cache RAM is controlled by one PGC – “PGC_PLAT” and
they can only be power down in LPM process (when “LPCR_A53_AD.en_plat_pdn” is
set). There is another bit “LPCR_A53_AD.l2pge” which will decide if L2 cache RAM
need to be in retention mode when SCU domain is power down.

5.2.6.3 Power up process for the A53 Platform

• The core0, core1, core2, and core3 can be powered up with the exit of A53 LPM.
The relevant bits are “LPCR_A53_AD.en_c0_pup”, “LPCR_A53_AD.en_c1_pup”,
“LPCR_A53_AD.en_c2_pup”, and “LPCR_A53_AD.en_c3_pup”.
• The core0, core1, core2, and core3 can also be powered up by interrupt signal in
RUN mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

632 NXP Semiconductors
 Chapter 5 Clocks and Power Management

• The relevant bit are “LPCR_A53_AD.en_c0_irq_pup”,

“LPCR_A53_AD.en_c1_irq_pup”, “LPCR_A53_AD.en_c2_irq_pup”, and
“LPCR_A53_AD.en_c3_irq_pup”.
• The interrupt signal can be chosen from GIC or directly from IRQ with mask in
GPCv2.
• The relevant select bits are “LPCR_A53_BSC.irq_src_c0”,
“LPCR_A53_BSC.irq_src_c1”, “LPCR_A53_BSC.irq_src_c2”,
“LPCR_A53_BSC.irq_src_c3”, and “LPCR_A53_BSC.irq_src_a53_wup”.
(LPCR_A53_BSC[30],LPCR_A53_BSC[23:22],LPCR_A53_BSC.)
{LPCR_A53_BSC[30],LPCR_A53_BS Usage Restriction
C[23:22],LPCR_A53_BSC[29:28]}
5'b00000 Use IRQ trigger A53 LPM and use IRQ None
to power up core0 to core3
5'b01111 Use GIC trigger A53 LPM and GIC to SCU cannot power down in LPM, CPU
power up core0 to core3 clock cannot stop in LPM
5'b11111 Use IRQ trigger A53 LPM and GIC to SCU cannot power down in LPM
power up core0 to core3

As show in the table above, core0/core1/core2/core3 can only be power up by its own
interrupt in RUN mode of A53 platform.
There are three combination of
{LPCR_A53_BSC[30],LPCR_A53_BSC[23:22],LPCR_A53_BSC[29:28]}:
1. In the first case, “IMRn_CORE0_A53, IMRn_CORE1_A53, IMRn_CORE2_A53,
IMRn_CORE3_A53“ are used to separate the 128 bits interrupts for core0, core1,
core2, and core3 of A53 platform and also used as the interrupt mask for A53 LPM.
2. In the second case, “IMRn_CORE0_A53, IMRn_CORE1_A53,
IMRn_CORE2_A53, IMRn_CORE3_A53” are not used, GIC setting are used to
separate interrupts for core0, core1, core2, and core3 of A53 platform and also used
as the interrupt mask for A53 LPM.
3. In the third case, “IMRn_CORE0_A53, IMRn_CORE1_A53, IMRn_CORE2_A53,
IMRn_CORE3_A53” is used as the mask for interrupt for A53 LPM, GIC setting are
used to separate interrupts for core0, core1, core2, and core3.

5.2.7 Power control for the M4 Platform

M4 LPM is same as A53 LPM. M4 platform doesn’t have its own power domain. There
is a virtual PGC reserved for M4, the virtual PGC will do nothing else except generating
an acknowledge signal and this signal can be chosen as the acknowledge signal for M4
platform.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 633
General Power Controller (GPC)

5.2.8 Domain control for PGCs

The following rules are used for PGC power up/down with domain mapping control:
1. For PGCs inside CPU platform (since M4 doesn’t have its own power domain, only
PGCs in A53 platform are referred): for hardware trigger (including both power up
and power down) only the LPM request from its own platform will take effect; for
software trigger (including both power up and power down) (the relevant register bit
are “CPU_PGC_SW_PUP_REQ” and “CPU_PGC_SW_PDN_REQ”), only the
software running in its own platform will take effect.
2. For PGCs outside CPU platform(MIX and PU PGCs), register bits
“PGC_CPU_MAPPING” will map MIX and PU PGCs to A53 or M4 CPU domain:
• One PGC can be mapped to one or both of A53 and M4 domain;
• For hardware power up request, if a PGC is mapped to any CPU domain, the
PGC will be powered up when the corresponding CPU platform sends out its
power up request.
• For software power up, if a PGC is mapped any CPU platform, the PGC can be
powered up by software running in corresponding CPU.(the relevant register bits
are “MIX_PGC_SW_PUP_REQ” and “PU_PGC_SW_PUP_REQ”)
• For hardware power down, if a power domain is mapped to only one CPU
domain, the relevant PGC can be powered down when the corresponding CPU
platform sends out its power down request; If a power domain is mapped to both
two CPU domain, when one CPU platform sends out its hardware power down
request, the relevant PGC will power down with any of the following condition
satisfied: the other CPU already in LPM; the other CPU want to power down
relevant PGC (the relevant register are “A53_MIX_PDN_FLG,
M4_MIX_PDN_FLG, A53_PU_PDN_FLG, M4_PU_PDN_FLG”)
• For software power down, if a power domain is mapped to only one CPU
domain, the PGC can be powered down by software running in corresponding
CPU. (the relevant register bits are “MIX_PGC_SW_PUP_REQ” and
“PU_PGC_SW_PUP_REQ”). If a power domain is mapped to both two CPU
domain, when one CPU platform sends out its software power down request, the
relevant PGC will power down with any of the following condition satisfied: the
other CPU already in LPM; the other CPU want to power down relevant PGC
(the relevant register are “A53_MIX_PDN_FLG, M4_MIX_PDN_FLG,
A53_PU_PDN_FLG, M4_PU_PDN_FLG”)
• The access of “PGC_CPU_MAPPING” is controlled by domain information
from RDC

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

634 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.9 Example Code

Below are code examples for entering specific power scenarios

5.2.9.1 Example Code 1

//ARM enters into ALL_OFF(STOP) mode and enable DSM :

//after "wfi", MIX/C0/C1/C2/C3 power down in SLOT0, SCU power down in SLOT1 when
//after "GPT1_INT" arrived, MIX power up in SLOT2, SCU power up in SLOT3, C0 power up in
SLOT4
//IMRx_CORE0_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x30, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x34, 0xFF7FFFFF); //[23] : GPT1 used as wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x38, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x3C, 0xFFFFFFFF);
//IMRx_CORE1_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x40, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x44, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x48, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x4C, 0xFFFFFFFF);
//IMRx_CORE2_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1C0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1CC, 0xFFFFFFFF);
//IMRx_CORE3_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1D0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1DC, 0xFFFFFFFF);
//LPCR_A53_BSC
reg32_write(GPC_IPS_BASE_ADDR, 0x0000000A) ;
//[30],[23:22],[29:28] : A53_CO/A53_C1/A53_C2/A53_C3/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode
//LPCR_A53_BSC2
reg32_write(GPC_IPS_BASE_ADDR + 0x108, 0x0000000A) ;
//[3:0] : STOP mode
//LPCR_A53_AD
reg32_write(GPC_IPS_BASE_ADDR + 0x4, 0x0A0A0A1A) ;
//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[27]/[25]/[11]/[9]: A53_C0/A53_C1/A53_C2/A53_C3 power up with A53 LPM PUP REQ
//[4] : A53_SCU power down with A53 LPM PDN REQ
//[19]/[17]/[3]/[1] : A53_C0/A53_C1/A53_C2/A53_C3 powr down with A53 LPM PDN REQ
//LPCR_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x8, 0x80000000) ;
//[31] : DSM ingore to check M4 low power state
//[1:0] : M4 LPM run mode
//SLPCR
reg32_write(GPC_IPS_BASE_ADDR + 0x14,0xe000ffA7) ;
//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake
//PGC_ACK_SEL_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x24,0x00010004) ;
//[2] : A53_SCU PGC as LPM power down ack
//[16] : A53_C0 PGC as LPM power up ack
//SLT_CFG0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 635
General Power Controller (GPC)
reg32_write(GPC_IPS_BASE_ADDR + 0xB0,0x00000055) ;
//[6]/[4]/[2]/[0] : A53_C0/A53_C1/ A53_C2/A53_C3 power down in SLOT0
//SLT_CFG0_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x200,0x0000001) ;
//[0] : power down in SLOT0
//SLT_CFG1
reg32_write(GPC_IPS_BASE_ADDR + 0xB4,0x00000100) ;
//[8] : A53_SCU power down in SLOT1
//SLT_CFG2_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x208,0x00000002) ;
//[1] : power up in SLOT2
//SLT_CFG3
reg32_write(GPC_IPS_BASE_ADDR + 0xBC,0x00000200) ;
//[9] : A53_SCU power up in SLOT3
//SLT_CFG4
reg32_write(GPC_IPS_BASE_ADDR + 0xC0,0x00000002) ;
//[1] : A53_C0 power up in SLOT4, A53_C1/ A53_C2/A53_C3 not power up
//PGC_CPU_MAPPING
reg32_write(GPC_IPS_BASE_ADDR + 0xEC,0x00000001) ;
//[0] : MIX PGC mapping to A53 LPM
//A53 PGC
reg32_write(GPC_IPS_BASE_ADDR +0x800, reg32_read(GPC_IPS_BASE_ADDR +0x800) | 0x00000001) ;
// enable A53_C0 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C1 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x880, reg32_read(GPC_IPS_BASE_ADDR +0x880) | 0x00000001) ;
// enable A53_C2 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x8C0, reg32_read(GPC_IPS_BASE_ADDR +0x8C0) | 0x00000001) ;
// enable A53_C3 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x900, reg32_read(GPC_IPS_BASE_ADDR +0x900) | 0x00000001) ;
// enable A53_SCU PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x910, (0x59 lt:lt: 10) | 0x5B | (0x51 lt:lt: 20) ) ;
// change nL2retn/mempwr/dftram to meet SCU power up timing
// PGC
reg32_write(GPC_IPS_BASE_ADDR +0xA00, reg32_read(GPC_IPS_BASE_ADDR +0xA00) | 0x00000001) ;
// enable MIX PGC power down

5.2.9.2 Example Code 2

//ARM enters into L2_RETENTION(STOP) mode and enable DSM :

//after "wfi", MIX/C0/C1/C2/C3/SCU power down in SLOT0
//after "GPT1_INT" arrived, MIX power up in SLOT1, SCU/C0 power up in SLOT2
//IMRx_CORE0_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x30, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x34, 0xFF7FFFFF);
//[23] : GPT1 used as wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x38, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x3C, 0xFFFFFFFF);
//IMRx_CORE1_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x40, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x44, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x48, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x4C, 0xFFFFFFFF);
//IMRx_CORE2_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1C0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1CC, 0xFFFFFFFF);
//IMRx_CORE3_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1D0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1DC, 0xFFFFFFFF);

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

636 NXP Semiconductors
 Chapter 5 Clocks and Power Management
//LPCR_A53_BSC
reg32_write(GPC_IPS_BASE_ADDR, 0x0000000A) ;
//[30],[23:22],[29:28] : A53_C0/A53_C1/A53_C2/A53_C3/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode
//LPCR_A53_BSC2
reg32_write(GPC_IPS_BASE_ADDR + 0x108, 0x0000000A) ;
//[3:0] : STOP mode
//LPCR_A53_AD
reg32_write(GPC_IPS_BASE_ADDR + 0x4, 0x0A0A0A1A) ;
//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[27]/[25]/[11]/[9]: A53_C0/A53_C1/A53_C2/A53_C3 power up with A53 LPM PUP REQ
//[4] : A53_SCU power down with A53 LPM PDN REQ
//[19]/[17]/[3]/[1] : A53_C0/A53_C1/A53_C2/A53_C3 powr down with A53 LPM PDN REQ
//LPCR_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x8, 0x80000000) ;
//[31] : DSM ingore to check M4 low power state
//[1:0] : M4 LPM run mode
//SLPCR
reg32_write(GPC_IPS_BASE_ADDR + 0x14,0xe000ffA7) ;
//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake
//PGC_ACK_SEL_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x24,0x00010004) ;
//[2] : A53_SCU PGC as LPM power down ack
//[16] : A53_C0 PGC as LPM power up ack
//SLT_CFG0
reg32_write(GPC_IPS_BASE_ADDR + 0xB0,0x00000155) ;
//[6]/[4]/[2]/[0] : A53_C0/A53_C1/ A53_C2/A53_C3 power down in SLOT0
//[8] : A53_SCU power down in SLOT0
//SLT_CFG0_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x200,0x0000001) ;
//[0] : power down in SLOT0
//A53_Cx/SCU are power down in same slot. Special setting is required( see below PGC setting
#A )
//SLT_CFG1_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x204,0x00000002) ;
//[1] : power up in SLOT1
//SLT_CFG2
reg32_write(GPC_IPS_BASE_ADDR + 0xB8,0x00000202) ;
//[9] : A53_SCU power up in SLOT1
//[1] : A53_C0 power up in SLOT1, A53_C1/ A53_C2/ A53_C3 not power up
//A53_Cx/SCU are power up in same slot. Special setting is required( see below PGC setting
#B )
//PGC_CPU_MAPPING
reg32_write(GPC_IPS_BASE_ADDR + 0xEC,0x00000001) ;
//[0] : MIX PGC mapping to A53 LPM
//Special PGC setting #A for C0/C1/C2/C3/SCU power down in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)
reg32_write(GPC_IPS_BASE_ADDR +0x808, (reg32_read(GPC_IPS_BASE_ADDR +0x808) & 0xFFFFC0C0) |
0x0801 ) ;
// set C0.ISO2SW = 8 ; C0.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x848, (reg32_read(GPC_IPS_BASE_ADDR +0x848) & 0xFFFFC0C0) |
0x0801 ) ;
// set C1.ISO2SW = 8 ; C1.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x888, (reg32_read(GPC_IPS_BASE_ADDR +0x888) & 0xFFFFC0C0) |
0x0801 ) ;
// set C2.ISO2SW = 8 ; C2.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x8C8, (reg32_read(GPC_IPS_BASE_ADDR +0x8C8) & 0xFFFFC0C0) |
0x0801 ) ;
// set C3.ISO2SW = 8 ; C3.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x908, (reg32_read(GPC_IPS_BASE_ADDR +0x908) & 0xFFFFC0C0) |
0x1001 ) ;
// set SCU.ISO2SW = 16 ; SCU.ISO = 1;
//Special PGC setting #B for A53_Cx/SCU power up in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 637
General Power Controller (GPC)
reg32_write(GPC_IPS_BASE_ADDR +0x804, (reg32_read(GPC_IPS_BASE_ADDR +0x804) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C0.SW = 0x11 ; C0.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x844, (reg32_read(GPC_IPS_BASE_ADDR +0x844) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C1.SW = 0x11 ; C1.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x884, (reg32_read(GPC_IPS_BASE_ADDR +0x884) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C2.SW = 0x11 ; C2.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x8C4, (reg32_read(GPC_IPS_BASE_ADDR +0x8C4) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C3.SW = 0x11 ; C3.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x904, (reg32_read(GPC_IPS_BASE_ADDR +0x904) & 0xFF800040) |
0x1 | (0x0f lt;lt; 7) ) ;
// set SCU.SW = 0x1 ; SCU.SW2ISO = 0x0f ;
//A53 PGC
reg32_write(GPC_IPS_BASE_ADDR +0x800, reg32_read(GPC_IPS_BASE_ADDR +0x800) | 0x00000001) ;
// enable A53_C0 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C1 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x880, reg32_read(GPC_IPS_BASE_ADDR +0x880) | 0x00000001) ;
// enable A53_C2 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x8C0, reg32_read(GPC_IPS_BASE_ADDR +0x8C0) | 0x00000001) ;
// enable A53_C3 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x900, reg32_read(GPC_IPS_BASE_ADDR +0x900) | 0x00000001) ;
// enable A53_SCU PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x910, (0x59 lt;lt; 10) | 0x5B | (0x51 lt;lt; 20) ) ;
// change nL2retn/mempwr/dftram to meet SCU power up timing
// PGC
reg32_write(GPC_IPS_BASE_ADDR +0xA00, reg32_read(GPC_IPS_BASE_ADDR +0xA00) | 0x00000001) ;
// enable MIX PGC power down

5.2.9.3 Example Code 3

//A53/M4 both enters into low power mode. A53/M4 are in different master domain.
//MIX are mapping to both A53 and M4
//after A53/M4 enters into low power mode, MIX will be also power down.A53/M4 enters into
low power mode any time
//either A53 or M4 exists from low power mode, MIX will be also power up
//IMRx_CORE0_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x30, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x34, 0xFF7FFFFF);
//[23] : GPT1 used as ARM wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x38, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x3C, 0xFFFFFFFF);
//IMRx_CORE1_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x40, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x44, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x48, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x4C, 0xFFFFFFFF);
//IMRx_CORE2_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1C0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1CC, 0xFFFFFFFF);
//IMRx_CORE3_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1D0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1DC, 0xFFFFFFFF);
//IMRx_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x50, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x54, 0xFFBFFFFF);

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

638 NXP Semiconductors
 Chapter 5 Clocks and Power Management
//[22] : GPT2 used as M4 wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x58, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x5C, 0xFFFFFFFF);
//LPCR_A53_BSC
reg32_write(GPC_IPS_BASE_ADDR, 0x0000000A) ;
//[30],[23:22],[29:28] : A53_C0/A53_C1/A53_C2/A53_C3/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode
//LPCR_A53_BSC2
reg32_write(GPC_IPS_BASE_ADDR + 0x108, 0x0000000A) ;
//[3:0] : STOP mode
//LPCR_A53_AD
reg32_write(GPC_IPS_BASE_ADDR + 0x4, 0x0A0A0A1A) ;
//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[27]/[25]/[11]/[9]: A53_C0/A53_C1/A53_C2/A53_C3 power up with A53 LPM PUP REQ
//[4] : A53_SCU power down with A53 LPM PDN REQ
//[19]/[17]/[3]/[1] : A53_C0/A53_C1/A53_C2/A53_C3 powr down with A53 LPM PDN REQ
//LPCR_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x8, 0x00003FFE) ;
//[31] : 0(check M4 low power state to enter into DSM)
//[14] : 0(M4 clock OFF during low power mode)
//[3:2] : enable M4 virtual PGC power up/down with M4 LPM
//[1:0] : M4 LPM STOP mode
//SLPCR
reg32_write(GPC_IPS_BASE_ADDR + 0x14,0xe000ffA7) ;
//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake
//PGC_ACK_SEL_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x24,0x00010004) ;
//[2] : A53_SCU PGC as LPM power down ack
//[16] : A53_C0 PGC as LPM power up ack
//PGC_ACK_SEL_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x28,0x00010001) ;
//[0] : M4 virtual PGC as M4 LPM power down ack
//[16] : M4 virtual PGC as M4 LPM power up ack
//GPC_MISC
reg32_write(GPC_IPS_BASE_ADDR + 0x2C,reg32_read(GPC_IPS_BASE_ADDR + 0x2C) | 0x100) ;
//[8] : not mask M4 power down request to M4 virtual PGC
//SLT_CFG0
reg32_write(GPC_IPS_BASE_ADDR + 0xB0,0x00000155) ;
//[6]/[4]/[2]/[0] : A53_C0/A53_C1/ A53_C2/A53_C3 power down in SLOT0
//[8] : A53_SCU power down in SLOT0
//SLT_CFG0_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x200,0x0001001) ;
//[0] : power down in SLOT0
//[12] : M4 virtual PGC power down in SLOT0
//A53_Cx/SCU are power down in same slot. Special setting is required( see below PGC setting
#A )
//SLT_CFG1_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x204,0x00002002) ;
//[2] : power up in SLOT1
//[13] : M4 virtual PGC power up in SLOT1
//SLT_CFG2
reg32_write(GPC_IPS_BASE_ADDR + 0xB8,0x00000202) ;
//[9] : A53_SCU power up in SLOT1
//[1] : A53_C0 power up in SLOT1, A53_C1/ A53_C2/ A53_C3 not power up
//A53_Cx/SCU are power up in same slot. Special setting is required( see below PGC setting
#B )
//PGC_CPU_MAPPING
reg32_write(GPC_IPS_BASE_ADDR + 0xEC,0x00010001) ;
//[0] : MIX PGC mapping to A53 LPM
//[16] : MIX PGC mapping to M4 LPM
//Special PGC setting #A for C0/C1/SCU power down in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)
reg32_write(GPC_IPS_BASE_ADDR +0x808, (reg32_read(GPC_IPS_BASE_ADDR +0x808) & 0xFFFFC0C0) |
0x0801 ) ;

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 639
General Power Controller (GPC)
// set C0.ISO2SW = 8 ; C0.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x848, (reg32_read(GPC_IPS_BASE_ADDR +0x848) & 0xFFFFC0C0) |
0x0801 ) ;
// set C1.ISO2SW = 8 ; C1.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x848, (reg32_read(GPC_IPS_BASE_ADDR +0x848) & 0xFFFFC0C0) |
0x0801 ) ;
// set C2.ISO2SW = 8 ; C2.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x888, (reg32_read(GPC_IPS_BASE_ADDR +0x888) & 0xFFFFC0C0) |
0x0801 ) ;
// set C3.ISO2SW = 8 ; C3.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x908, (reg32_read(GPC_IPS_BASE_ADDR +0x908) & 0xFFFFC0C0) |
0x1001 ) ;
// set SCU.ISO2SW = 16 ; SCU.ISO = 1;
//Special PGC setting #B for A53_Cx/SCU power up in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)
reg32_write(GPC_IPS_BASE_ADDR +0x804, (reg32_read(GPC_IPS_BASE_ADDR +0x804) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C0.SW = 0x10 ; C0.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x844, (reg32_read(GPC_IPS_BASE_ADDR +0x844) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C1.SW = 0x10 ; C1.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x844, (reg32_read(GPC_IPS_BASE_ADDR +0x844) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C2.SW = 0x10 ; C2.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x884, (reg32_read(GPC_IPS_BASE_ADDR +0x884) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C3.SW = 0x10 ; C3.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x904, (reg32_read(GPC_IPS_BASE_ADDR +0x904) & 0xFF800040) |
0x1 | (0x0f lt:lt: 7) ) ;
// set SCU.SW = 0x1 ; SCU.SW2ISO = 0x0f ;
//A53 PGC
reg32_write(GPC_IPS_BASE_ADDR +0x800, reg32_read(GPC_IPS_BASE_ADDR +0x800) | 0x00000001) ;
// enable A53_C0 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C1 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C2 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x880, reg32_read(GPC_IPS_BASE_ADDR +0x880) | 0x00000001) ;
// enable A53_C3 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x900, reg32_read(GPC_IPS_BASE_ADDR +0x900) | 0x00000001) ;
// enable A53_SCU PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x910, (0x59 lt:lt: 10) | 0x5B | (0x51 lt:lt: 20) ) ;
// change nL2retn/mempwr/dftram to meet SCU power up timing
// PGC
reg32_write(GPC_IPS_BASE_ADDR +0xA00, reg32_read(GPC_IPS_BASE_ADDR +0xA00) | 0x00000001) ;
// enable MIX PGC power down

5.2.9.4 Example Code 4

// software power up/down PCIE PHY

//power up PCIE PHY
reg32_write ( GPC_IPS_BASE_ADDR + 0xEC, reg32_read(GPC_IPS_BASE_ADDR + 0x0EC) | 0x8 );
//map PCIE PGC to A53
reg32_write ( GPC_IPS_BASE_ADDR + 0xF8 , reg32_read(GPC_IPS_BASE_ADDR + 0xF8) | 0x2 );
//trigger sw Power up Request
while( read(GPC_IPS_BASE_ADDR + 0xF8) & 0x2 );
//wait software power up request self clear
//power down PCIE PHY
reg32_write ( GPC_IPS_BASE_ADDR + 0xEC, reg32_read(GPC_IPS_BASE_ADDR + 0x0EC) | 0x8 );
//map PCIE PGC to A53
reg32_write ( GPC_IPS_BASE_ADDR + 0xC40, reg32_read(GPC_IPS_BASE_ADDR + 0xC40) | 0x1 );
// enable PCIE PGC power down
reg32_write ( GPC_IPS_BASE_ADDR + 0x104 , reg32_read(GPC_IPS_BASE_ADDR + 0x104) | 0x2 );

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

640 NXP Semiconductors
 Chapter 5 Clocks and Power Management
//trigger sw Power Down Request
while( read(GPC_IPS_BASE_ADDR + 0x104) & 0x2 );
//wait software power down request self clear

5.2.9.5 Example Code 5

// VPU/GPU/DISP/HSIOMIX power up and power down flow:

reg32_write(0x303A00EC,0x0000ffff); //PGC_CPU_MAPPING
reg32_write(0x303A00F8,0x0000ffff); //Power up all power domains
for(i=0;ilt;14;i++){ //Power domain power down enable
reg32setbit(0x303A0C00+i*0x40,0);
}
reg32_write(0x38330004, 0x7); //VPUMIX sft clock enable
reg32_write(0x32e28000,0x0000007f); //release dispmix sft reset
reg32_write(0x32e28004,0x00001fff); //dispmix sft clock enable
//GPU_2D power off
reg32clrbit(0x303A01FC,10); //power down request to ADB
while((reg32_read(0x303A01FC)) & (0x01lt;lt;28)); //wait ADB ack 0
reg32_write(CCM_CCGR(102),0x00); //clock off
reg32setbit(0x303A0104,6); //PU_PGC_SW_PDN_REQ

//GPU_3D power off

reg32clrbit(0x303A01FC,9); //power down request to ADB
while((reg32_read(0x303A01FC)) & (0x01lt;lt;27)); //wait ADB ack 0
reg32_write(CCM_CCGR(79),0x00); //clock off
reg32setbit(0x303A0104,9); //PU_PGC_SW_PDN_REQ

//GPU power off

reg32clrbit(0x303A01FC,11); //power down request to ADB
while((reg32_read(0x303A01FC)) & (0x01lt;lt;29)); //wait ADB ack 0
reg32_write(CCM_CCGR(87),0x00); //clock off
reg32setbit(0x303A0104,7); //PU_PGC_SW_PDN_REQ

delay(50);

//GPU power on
reg32_write(CCM_CCGR(87),0x02); //bus clock on
delay(20);
reg32_write(CCM_CCGR(87),0x00); //bus clock off
reg32setbit(0x303A00F8,7); //PU_PGC_SW_PUP_REQ
delay(20);
reg32_write(CCM_CCGR(87),0x02); //bus clock on
reg32setbit(0x303A01FC,11); //clear power down request to ADB
while(!((reg32_read(0x303A01FC)) & (0x01lt;lt;29))); //wait ADB ack 1

//GPU_2D power on
reg32_write(CCM_CCGR(102),0x02); //2D clock on
reg32setbit(0x303A00F8,6); //PU_PGC_SW_PUP_REQ
reg32setbit(0x303A01FC,10); //clear power down request to ADB
while(!((reg32_read(0x303A01FC)) & (0x01lt;lt;28))); //wait ADB ack 1

//GPU_3D power on
//Power up flow:
reg32_write(CCM_CCGR(79),0x02); //3D clock on
reg32setbit(0x303A00F8,9); //PU_PGC_SW_PUP_REQ
reg32setbit(0x303A01FC,9); //clear power down request to ADB
while(!((reg32_read(0x303A01FC)) & (0x01lt;lt;27))); //wait ADB ack 1

//VPU_G1 power off

reg32_write(CCM_CCGR(86),0x00); //clock off
reg32setbit(0x303A0104,11); //PU_PGC_SW_PDN_REQ

//VPU_G2 power off

reg32_write(CCM_CCGR(90),0x00); //clock off
reg32setbit(0x303A0104,12); //PU_PGC_SW_PDN_REQ

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 641
General Power Controller (GPC)

//VPU_H1 power off

reg32_write(CCM_CCGR(89),0x00); //clock off
reg32setbit(0x303A0104,13); //PU_PGC_SW_PDN_REQ

//VPU power off

reg32clrbit(0x303A01FC,8); //power down request to ADB
while((reg32_read(0x303A01FC)) & (0x01lt;lt;26)); //wait ADB ack 0
reg32_write(CCM_CCGR(99),0x00); //clock off
reg32setbit(0x303A0104,8); //PU_PGC_SW_PDN_REQ

delay(50);

//VPU: power on
reg32_write(CCM_CCGR(99),0x02); //bus clock on
delay(20);
reg32_write(CCM_CCGR(99),0x00); //bus clock off
reg32setbit(0x303A00F8,8); //PU_PGC_SW_PUP_REQ
delay(20);
reg32_write(CCM_CCGR(99),0x02); //bus clock on
reg32_write(0x38330004, 0x7); //VPUMIX sft clock enable
reg32setbit(0x303A01FC,8); //clear power down request to ADB
while(!((reg32_read(0x303A01FC)) & (0x01lt;lt;26))); //wait ADB ack 1

//VPU_G1 power on
reg32_write(CCM_CCGR(86),0x02); //clock on
reg32setbit(0x303A00F8,11); //PU_PGC_SW_PUP_REQ

//VPU_G2 power on
reg32_write(CCM_CCGR(90),0x02); //clock on
reg32setbit(0x303A00F8,12); //PU_PGC_SW_PUP_REQ

//VPU_H1 power on
reg32_write(CCM_CCGR(89),0x02); //clock on
reg32setbit(0x303A00F8,13); //PU_PGC_SW_PUP_REQ

//PCIE power off

reg32_write(CCM_CCGR(37),0x00); //clock off
reg32setbit(0x303A0104,1); //PU_PGC_SW_PDN_REQ

//USB OTG1 power off

reg32setbit(0x303A0104,2); //PU_PGC_SW_PDN_REQ

//USB OTG2 power off

reg32setbit(0x303A0104,3); //PU_PGC_SW_PDN_REQ

//HSIO MIX low power

reg32clrbit(0x303A01FC,5); //power down request to ADB
while((reg32_read(0x303A01FC)) & (0x01lt;lt;23)); //wait ADB ack 0
reg32clrbit(0x303A01FC,6); //power down request to ADB
while((reg32_read(0x303A01FC)) & (0x01lt;lt;24)); //wait ADB ack 0
reg32_write(CCM_CCGR(77),0x00); //usb_bus clock off
reg32_write(CCM_CCGR(69),0x00); //hsio_bus clock off

delay(50);

//HSIO MIX run

reg32_write(CCM_CCGR(77),0x02); //usb_bus clock on
reg32_write(CCM_CCGR(69),0x02); //hsio_bus clock on
reg32setbit(0x303A01FC,5); //clear power down request to ADB
while(!((reg32_read(0x303A01FC)) & (0x01lt;lt;23))); //wait ADB ack 1
reg32setbit(0x303A01FC,6); //clear power down request to ADB
while(!((reg32_read(0x303A01FC)) & (0x01lt;lt;24))); //wait ADB ack 1

//PCIE power on
reg32_write(CCM_CCGR(37),0x02); //clock on
reg32setbit(0x303A00F8,1); //PU_PGC_SW_PUP_REQ

//USB OTG1 power on

reg32setbit(0x303A00F8,2); //PU_PGC_SW_PUP_REQ

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

642 NXP Semiconductors
 Chapter 5 Clocks and Power Management

//USB OTG2 power on

reg32setbit(0x303A00F8,3); //PU_PGC_SW_PUP_REQ

//MIPI power off

reg32setbit(0x303A0104,0); //PU_PGC_SW_PDN_REQ

//DISP power off

reg32clrbit(0x303A01FC,7); //power down request to ADB
while((reg32_read(0x303A01FC)) & (0x01lt;lt;25)); //wait ADB ack 0
reg32_write(CCM_CCGR(93),0x00); //clock off
reg32setbit(0x303A0104,10); //PU_PGC_SW_PDN_REQ

delay(50);

//DISP power on
reg32_write(CCM_CCGR(93),0x02); //clock on
delay(20);
reg32_write(CCM_CCGR(93),0x00); //clock on
reg32setbit(0x303A00F8,10); //PU_PGC_SW_PUP_REQ
delay(20);
reg32_write(CCM_CCGR(93),0x02); //clock on
reg32_write(0x32e28000,0x0000007f); //release dispmix sft reset
reg32_write(0x32e28004,0x00001fff); //dispmix sft clock enable
reg32setbit(0x303A01FC,7); //clear power down request to ADB
while(!((reg32_read(0x303A01FC)) & (0x01lt;lt;25))); //wait ADB ack 1

//MIPI power on
reg32setbit(0x303A00F8,0); //PU_PGC_SW_PUP_REQ

//DDR power off

reg32clrbit(0x303A01FC,2); //power down request to ADB

delay(50);

//DDR power on
reg32setbit(0x303A00F8,5); //PU_PGC_SW_PUP_REQ

5.2.9.6 Example Code 6

//ARM enters into ALL_OFF(STOP) mode and enable DSM ,NOC POWER DOWN:
//after "wfi", MIX/C0/C1/C2/C3 power down in SLOT0, SCU power down in SLOT1 when
//after "GPT1_INT" arrived, MIX power up in SLOT2, SCU power up in SLOT3, C0 power up in
SLOT4
//IMRx_CORE0_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x30, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x34, 0xFF7FFFFF); //[23] : GPT1 used as wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x38, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x3C, 0xFFFFFFFF);
//IMRx_CORE1_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x40, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x44, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x48, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x4C, 0xFFFFFFFF);
//IMRx_CORE2_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1C0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1CC, 0xFFFFFFFF);
//IMRx_CORE3_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1D0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1DC, 0xFFFFFFFF);

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 643
General Power Controller (GPC)
//LPCR_A53_BSC
reg32_write(GPC_IPS_BASE_ADDR, 0x0000000A) ;
//[30],[23:22],[29:28] : A53_CO/A53_C1/A53_C2/A53_C3/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode
//LPCR_A53_BSC2
reg32_write(GPC_IPS_BASE_ADDR + 0x108, 0x0000000A) ;
//[3:0] : STOP mode
//LPCR_A53_AD
reg32_write(GPC_IPS_BASE_ADDR + 0x4, 0x0A0A0A1A) ;
//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[27]/[25]/[11]/[9]: A53_C0/A53_C1/A53_C2/A53_C3 power up with A53 LPM PUP REQ
//[4] : A53_SCU power down with A53 LPM PDN REQ
//[19]/[17]/[3]/[1] : A53_C0/A53_C1/A53_C2/A53_C3 powr down with A53 LPM PDN REQ
//LPCR_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x8, 0x80000000) ;
//[31] : DSM ingore to check M4 low power state
//[1:0] : M4 LPM run mode
//SLPCR
reg32_write(GPC_IPS_BASE_ADDR + 0x14,0xe000ffA7) ;
//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake
//PGC_ACK_SEL_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x24,0x00010008) ;
//[3] : NOC PGC as LPM power down ack
//[16] : A53_C0 PGC as LPM power up ack
//SLT_CFG0
reg32_write(GPC_IPS_BASE_ADDR + 0xB0,0x00000055) ;
//[6]/[4]/[2]/[0] : A53_C0/A53_C1/ A53_C2/A53_C3 power down in SLOT0
//SLT_CFG1
reg32_write(GPC_IPS_BASE_ADDR + 0xB4,0x00000100) ;
//[8] : A53_SCU power down in SLOT1
//SLT_CFG2
reg32_write(GPC_IPS_BASE_ADDR + 0xB8,0x00000400) ;
//[10] :NOC power down in SLOT2
//SLT_CFG3
reg32_write(GPC_IPS_BASE_ADDR + 0xBC,0x00000800) ;
//[11] :NOC power up in SLOT3
//SLT_CFG4
reg32_write(GPC_IPS_BASE_ADDR + 0xC0,0x00000200) ;
//[9] : A53_SCU power up in SLOT4
//SLT_CFG5
reg32_write(GPC_IPS_BASE_ADDR + 0xC4,0x00000002) ;
//[1] : A53_C0 power up in SLOT4, A53_C1/ A53_C2/A53_C3 not power up
//PGC_CPU_MAPPING
reg32_write(GPC_IPS_BASE_ADDR + 0xEC,0x00000002) ;
//[1] : NOC PGC mapping to A53 LPM
//A53 PGC
reg32_write(GPC_IPS_BASE_ADDR +0x800, reg32_read(GPC_IPS_BASE_ADDR +0x800) | 0x00000001) ;
// enable A53_C0 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C1 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x880, reg32_read(GPC_IPS_BASE_ADDR +0x880) | 0x00000001) ;
// enable A53_C2 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x8C0, reg32_read(GPC_IPS_BASE_ADDR +0x8C0) | 0x00000001) ;
// enable A53_C3 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x900, reg32_read(GPC_IPS_BASE_ADDR +0x900) | 0x00000001) ;
// enable A53_SCU PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x910, (0x59 lt;lt; 10) | 0x5B | (0x51 lt;lt; 20) ) ;
// change nL2retn/mempwr/dftram to meet SCU power up timing
//NOC PGC
reg32_write(GPC_IPS_BASE_ADDR +0xA40, reg32_read(GPC_IPS_BASE_ADDR +0xA40) | 0x00000001) ;
// enable NOC PGC power down

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

644 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10 GPC Memory Map/Register Definition

Detailed descriptions of each register can be found below.

The total GPC memory map is 4KB
Table 5-10. Memory Regions
Address Range(offset) Region
0x000 - 0x3FF GPC configuration register
0x400 - 0x7FF Reserved
0x800 - 0x9FF CPU and SCU type PGC register base address
0xA00 - 0xBFF MIX type PGC register base address
0xC00 - 0xFFF PU type PGC register base address

Each PGC (CPU type, MIX type, PU type) will occupy 64 Bytes address space, the
specific base address of each PGC are listed as below.
• 0x800 ~ 0x83F : PGC for A53 core0
• 0x840 ~ 0x87F: PGC for A53 core1
• 0x880 ~ 0x8BF: PGC for A53 core2
• 0x8C0 ~ 0x8FF: PGC for A53 core3
• 0x900 ~ 0x93F: PGC for A53 SCU
• 0xA00 ~ 0xA3F: Reserved
• 0xA40 ~ 0xA7F: PGC for NOC mix
• 0xC00 ~ 0xC3F: PGC for MIPI PHY
• 0xC40 ~ 0xC7F: PGC for PCIE1 PHY
• 0xC80 ~ 0xCBF: USB_OTG1
• 0xCC0 ~ 0xCFF: USB_OTG2
• 0xD00 ~ 0xD3F: Reserved
• 0xD40 ~ 0xD7F: DDR1
• 0xD80 ~ 0xDBF: GPU_2D
• 0xDC0 ~ 0xDFF: GPUMIX
• 0xE00 ~ 0xE3F: VPUMIX
• 0xE40 ~ 0xE7F: GPU_3D
• 0xE80 ~ 0xEBF: DISPMIX
• 0xEC0 ~ 0xEFF: VPU_G1
• 0xF00 ~ 0xF3F: VPU_G2
• 0xF40 ~ 0xF7F: VPU_H1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 645
General Power Controller (GPC)

For more specific information about PGC register definition, please see the register
definition for each PGC.
GPC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Basic Low power control register of A53 platform 5.2.10.1/
303A_0000 32 R/W 0000_3FF0h
(GPC_LPCR_A53_BSC) 652
Advanced Low power control register of A53 platform 5.2.10.2/
303A_0004 32 R/W 0000_0020h
(GPC_LPCR_A53_AD) 655
5.2.10.3/
303A_0008 Low power control register of CPU1 (GPC_LPCR_M4) 32 R/W 0000_3FF0h
658
5.2.10.4/
303A_0014 System low power control register (GPC_SLPCR) 32 R/W E000_FF82h
660
5.2.10.5/
303A_0018 MASTER LPM Handshake (GPC_MST_CPU_MAPPING) 32 R/W 0000_00FFh
663
5.2.10.6/
303A_0020 Memory low power control register (GPC_MLPCR) 32 R/W 0101_0100h
664
PGC acknowledge signal selection of A53 platform 5.2.10.7/
303A_0024 32 R/W 8000_8000h
(GPC_PGC_ACK_SEL_A53) 665
PGC acknowledge signal selection of M4 platform 5.2.10.8/
303A_0028 32 R/W 8000_8000h
(GPC_PGC_ACK_SEL_M4) 667
5.2.10.9/
303A_002C GPC Miscellaneous register (GPC_MISC) 32 R/W 0000_0021h
668
IRQ masking register 1 of A53 core0 5.2.10.10/
303A_0030 32 R/W 0000_0000h
(GPC_IMR1_CORE0_A53) 669
IRQ masking register 2 of A53 core0 5.2.10.11/
303A_0034 32 R/W 0000_0000h
(GPC_IMR2_CORE0_A53) 670
IRQ masking register 3 of A53 core0 5.2.10.12/
303A_0038 32 R/W 0000_0000h
(GPC_IMR3_CORE0_A53) 670
IRQ masking register 4 of A53 core0 5.2.10.13/
303A_003C 32 R/W 0000_0000h
(GPC_IMR4_CORE0_A53) 671
IRQ masking register 1 of A53 core1 5.2.10.14/
303A_0040 32 R/W 0000_0000h
(GPC_IMR1_CORE1_A53) 671
IRQ masking register 2 of A53 core1 5.2.10.15/
303A_0044 32 R/W 0000_0000h
(GPC_IMR2_CORE1_A53) 671
IRQ masking register 3 of A53 core1 5.2.10.16/
303A_0048 32 R/W 0000_0000h
(GPC_IMR3_CORE1_A53) 672
IRQ masking register 4 of A53 core1 5.2.10.17/
303A_004C 32 R/W 0000_0000h
(GPC_IMR4_CORE1_A53) 672
5.2.10.18/
303A_0050 IRQ masking register 1 of M4 (GPC_IMR1_M4) 32 R/W 0000_0000h
673
5.2.10.19/
303A_0054 IRQ masking register 2 of M4 (GPC_IMR2_M4) 32 R/W 0000_0000h
673
5.2.10.20/
303A_0058 IRQ masking register 3 of M4 (GPC_IMR3_M4) 32 R/W 0000_0000h
673
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

646 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.2.10.21/
303A_005C IRQ masking register 4 of M4 (GPC_IMR4_M4) 32 R/W 0000_0000h
674
5.2.10.22/
303A_0070 IRQ status register 1 of A53 (GPC_ISR1_A53) 32 R 0000_0000h
674
5.2.10.23/
303A_0074 IRQ status register 2 of A53 (GPC_ISR2_A53) 32 R 0000_0000h
675
5.2.10.24/
303A_0078 IRQ status register 3 of A53 (GPC_ISR3_A53) 32 R 0000_0000h
675
5.2.10.25/
303A_007C IRQ status register 4 of A53 (GPC_ISR4_A53) 32 R 0000_0000h
675
5.2.10.26/
303A_0080 IRQ status register 1 of M4 (GPC_ISR1_M4) 32 R 0000_0000h
676
5.2.10.27/
303A_0084 IRQ status register 2 of M4 (GPC_ISR2_M4) 32 R 0000_0000h
676
5.2.10.28/
303A_0088 IRQ status register 3 of M4 (GPC_ISR3_M4) 32 R 0000_0000h
677
5.2.10.29/
303A_008C IRQ status register 4 of M4 (GPC_ISR4_M4) 32 R 0000_0000h
677
5.2.10.30/
303A_00B0 Slot configure register for CPUs (GPC_SLT0_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00B4 Slot configure register for CPUs (GPC_SLT1_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00B8 Slot configure register for CPUs (GPC_SLT2_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00BC Slot configure register for CPUs (GPC_SLT3_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00C0 Slot configure register for CPUs (GPC_SLT4_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00C4 Slot configure register for CPUs (GPC_SLT5_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00C8 Slot configure register for CPUs (GPC_SLT6_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00CC Slot configure register for CPUs (GPC_SLT7_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00D0 Slot configure register for CPUs (GPC_SLT8_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00D4 Slot configure register for CPUs (GPC_SLT9_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00D8 Slot configure register for CPUs (GPC_SLT10_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00DC Slot configure register for CPUs (GPC_SLT11_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00E0 Slot configure register for CPUs (GPC_SLT12_CFG) 32 R/W 0000_0000h
677
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 647
General Power Controller (GPC)

GPC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.2.10.30/
303A_00E4 Slot configure register for CPUs (GPC_SLT13_CFG) 32 R/W 0000_0000h
677
5.2.10.30/
303A_00E8 Slot configure register for CPUs (GPC_SLT14_CFG) 32 R/W 0000_0000h
677
5.2.10.31/
303A_00EC PGC CPU mapping (GPC_PGC_CPU_0_1_MAPPING) 32 R/W 0000_0000h
680
CPU PGC software power up trigger 5.2.10.32/
303A_00F0 32 R/W 0000_0000h
(GPC_CPU_PGC_SW_PUP_REQ) 682
MIX PGC software power up trigger 5.2.10.33/
303A_00F4 32 R/W 0000_0000h
(GPC_MIX_PGC_SW_PUP_REQ) 683
PU PGC software up trigger 5.2.10.34/
303A_00F8 32 R/W 0000_0000h
(GPC_PU_PGC_SW_PUP_REQ) 684
CPU PGC software down trigger 5.2.10.35/
303A_00FC 32 R/W 0000_0000h
(GPC_CPU_PGC_SW_PDN_REQ) 685
MIX PGC software power down trigger 5.2.10.36/
303A_0100 32 R/W 0000_0000h
(GPC_MIX_PGC_SW_PDN_REQ) 686
PU PGC software down trigger 5.2.10.37/
303A_0104 32 R/W 0000_0000h
(GPC_PU_PGC_SW_PDN_REQ) 687
Basic Low power control register of A53 platform 5.2.10.38/
303A_0108 32 R/W 0000_0000h
(GPC_LPCR_A53_BSC2) 689
CPU PGC software up trigger status1 5.2.10.39/
303A_0130 32 R 0000_0000h
(GPC_CPU_PGC_PUP_STATUS1) 690
A53 MIX software up trigger status register 5.2.10.40/
303A_0134 32 R 0000_0000h
(GPC_A53_MIX_PGC_PUP_STATUS0) 692
A53 MIX software up trigger status register 5.2.10.40/
303A_0138 32 R 0000_0000h
(GPC_A53_MIX_PGC_PUP_STATUS1) 692
A53 MIX software up trigger status register 5.2.10.40/
303A_013C 32 R 0000_0000h
(GPC_A53_MIX_PGC_PUP_STATUS2) 692
M4 MIX PGC software up trigger status register 5.2.10.41/
303A_0140 32 R 0000_0000h
(GPC_M4_MIX_PGC_PUP_STATUS0) 693
M4 MIX PGC software up trigger status register 5.2.10.41/
303A_0144 32 R 0000_0000h
(GPC_M4_MIX_PGC_PUP_STATUS1) 693
M4 MIX PGC software up trigger status register 5.2.10.41/
303A_0148 32 R 0000_0000h
(GPC_M4_MIX_PGC_PUP_STATUS2) 693
A53 PU software up trigger status register 5.2.10.42/
303A_014C 32 R 0000_0000h
(GPC_A53_PU_PGC_PUP_STATUS0) 695
A53 PU software up trigger status register 5.2.10.42/
303A_0150 32 R 0000_0000h
(GPC_A53_PU_PGC_PUP_STATUS1) 695
A53 PU software up trigger status register 5.2.10.42/
303A_0154 32 R 0000_0000h
(GPC_A53_PU_PGC_PUP_STATUS2) 695
M4 PU PGC software up trigger status register 5.2.10.43/
303A_0158 32 R 0000_0000h
(GPC_M4_PU_PGC_PUP_STATUS0) 698
M4 PU PGC software up trigger status register 5.2.10.43/
303A_015C 32 R 0000_0000h
(GPC_M4_PU_PGC_PUP_STATUS1) 698
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

648 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
M4 PU PGC software up trigger status register 5.2.10.43/
303A_0160 32 R 0000_0000h
(GPC_M4_PU_PGC_PUP_STATUS2) 698
CPU PGC software dn trigger status1 5.2.10.44/
303A_0170 32 R 0000_0000h
(GPC_CPU_PGC_PDN_STATUS1) 700
A53 MIX software down trigger status register 5.2.10.45/
303A_0174 32 R 0000_0000h
(GPC_A53_MIX_PGC_PDN_STATUS0) 702
A53 MIX software down trigger status register 5.2.10.45/
303A_0178 32 R 0000_0000h
(GPC_A53_MIX_PGC_PDN_STATUS1) 702
A53 MIX software down trigger status register 5.2.10.45/
303A_017C 32 R 0000_0000h
(GPC_A53_MIX_PGC_PDN_STATUS2) 702
M4 MIX PGC software power down trigger status register 5.2.10.46/
303A_0180 32 R 0000_0000h
(GPC_M4_MIX_PGC_PDN_STATUS0) 704
M4 MIX PGC software power down trigger status register 5.2.10.46/
303A_0184 32 R 0000_0000h
(GPC_M4_MIX_PGC_PDN_STATUS1) 704
M4 MIX PGC software power down trigger status register 5.2.10.46/
303A_0188 32 R 0000_0000h
(GPC_M4_MIX_PGC_PDN_STATUS2) 704
A53 PU PGC software down trigger status 5.2.10.47/
303A_018C 32 R 0000_0000h
(GPC_A53_PU_PGC_PDN_STATUS0) 705
A53 PU PGC software down trigger status 5.2.10.47/
303A_0190 32 R 0000_0000h
(GPC_A53_PU_PGC_PDN_STATUS1) 705
A53 PU PGC software down trigger status 5.2.10.47/
303A_0194 32 R 0000_0000h
(GPC_A53_PU_PGC_PDN_STATUS2) 705
M4 PU PGC software down trigger status 5.2.10.48/
303A_0198 32 R 0000_0000h
(GPC_M4_PU_PGC_PDN_STATUS0) 708
M4 PU PGC software down trigger status 5.2.10.48/
303A_019C 32 R 0000_0000h
(GPC_M4_PU_PGC_PDN_STATUS1) 708
M4 PU PGC software down trigger status 5.2.10.48/
303A_01A0 32 R 0000_0000h
(GPC_M4_PU_PGC_PDN_STATUS2) 708
5.2.10.49/
303A_01B0 A53 MIX PDN FLG (GPC_A53_MIX_PDN_FLG) 32 R/W 0000_0000h
711
5.2.10.50/
303A_01B4 A53 PU PDN FLG (GPC_A53_PU_PDN_FLG) 32 R/W 0000_0000h
712
5.2.10.51/
303A_01B8 M4 MIX PDN FLG (GPC_M4_MIX_PDN_FLG) 32 R/W 0000_0000h
713
5.2.10.52/
303A_01BC M4 PU PDN FLG (GPC_M4_PU_PDN_FLG) 32 R/W 0000_0000h
714
IRQ masking register 1 of A53 core2 5.2.10.53/
303A_01C0 32 R/W 0000_0000h
(GPC_IMR1_CORE2_A53) 714
IRQ masking register 2 of A53 core2 5.2.10.54/
303A_01C4 32 R/W 0000_0000h
(GPC_IMR2_CORE2_A53) 715
IRQ masking register 3 of A53 core2 5.2.10.55/
303A_01C8 32 R/W 0000_0000h
(GPC_IMR3_CORE2_A53) 715
IRQ masking register 4 of A53 core2 5.2.10.56/
303A_01CC 32 R/W 0000_0000h
(GPC_IMR4_CORE2_A53) 716
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 649
General Power Controller (GPC)

GPC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
IRQ masking register 1 of A53 core3 5.2.10.57/
303A_01D0 32 R/W 0000_0000h
(GPC_IMR1_CORE3_A53) 716
IRQ masking register 2 of A53 core3 5.2.10.58/
303A_01D4 32 R/W 0000_0000h
(GPC_IMR2_CORE3_A53) 717
IRQ masking register 3 of A53 core3 5.2.10.59/
303A_01D8 32 R/W 0000_0000h
(GPC_IMR3_CORE3_A53) 717
IRQ masking register 4 of A53 core3 5.2.10.60/
303A_01DC 32 R/W 0000_0000h
(GPC_IMR4_CORE3_A53) 718
PGC acknowledge signal selection of A53 platform for PUs 5.2.10.61/
303A_01E0 32 R/W 0000_0000h
(GPC_ACK_SEL_A53_PU) 718
PGC acknowledge signal selection of M4 platform for PUs 5.2.10.62/
303A_01E4 32 R/W 0000_0000h
(GPC_ACK_SEL_M4_PU) 721
5.2.10.63/
303A_01E8 Slot configure register for PGC CPUs (GPC_SLT15_CFG) 32 R/W 0000_0000h
723
5.2.10.63/
303A_01EC Slot configure register for PGC CPUs (GPC_SLT16_CFG) 32 R/W 0000_0000h
723
5.2.10.63/
303A_01F0 Slot configure register for PGC CPUs (GPC_SLT17_CFG) 32 R/W 0000_0000h
723
5.2.10.63/
303A_01F4 Slot configure register for PGC CPUs (GPC_SLT18_CFG) 32 R/W 0000_0000h
723
5.2.10.63/
303A_01F8 Slot configure register for PGC CPUs (GPC_SLT19_CFG) 32 R/W 0000_0000h
723
5.2.10.64/
303A_01FC Power handshake register (GPC_PU_PWRHSK) 32 R/W 0000_FFFFh
726
5.2.10.65/
303A_0200 Slot configure register for PGC PUs (GPC_SLT0_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0208 Slot configure register for PGC PUs (GPC_SLT1_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0210 Slot configure register for PGC PUs (GPC_SLT2_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0218 Slot configure register for PGC PUs (GPC_SLT3_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0220 Slot configure register for PGC PUs (GPC_SLT4_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0228 Slot configure register for PGC PUs (GPC_SLT5_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0230 Slot configure register for PGC PUs (GPC_SLT6_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0238 Slot configure register for PGC PUs (GPC_SLT7_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0240 Slot configure register for PGC PUs (GPC_SLT8_CFG_PU) 32 R/W 0000_0000h
730
5.2.10.65/
303A_0248 Slot configure register for PGC PUs (GPC_SLT9_CFG_PU) 32 R/W 0000_0000h
730
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

650 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Slot configure register for PGC PUs 5.2.10.65/
303A_0250 32 R/W 0000_0000h
(GPC_SLT10_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0258 32 R/W 0000_0000h
(GPC_SLT11_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0260 32 R/W 0000_0000h
(GPC_SLT12_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0268 32 R/W 0000_0000h
(GPC_SLT13_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0270 32 R/W 0000_0000h
(GPC_SLT14_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0278 32 R/W 0000_0000h
(GPC_SLT15_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0280 32 R/W 0000_0000h
(GPC_SLT16_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0288 32 R/W 0000_0000h
(GPC_SLT17_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0290 32 R/W 0000_0000h
(GPC_SLT18_CFG_PU) 730
Slot configure register for PGC PUs 5.2.10.65/
303A_0298 32 R/W 0000_0000h
(GPC_SLT19_CFG_PU) 730

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 651
General Power Controller (GPC)

5.2.10.1 Basic Low power control register of A53 platform

(GPC_LPCR_A53_BSC)

NOTE
LPCR_A53_BSC[CPU_CLK_ON_LPM] should be set 1’b1
when using A53 low power debug feature
NOTE
Always set LPM1/LPM0 with same value
Address: 303A_0000h base + 0h offset = 303A_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK_DSM_TRIGGER

MASK_CORE3_WFI

MASK_CORE2_WFI

MASK_CORE1_WFI

MASK_CORE0_WFI
MASK_L2CC_WFI

R MASK_SCU_WFI
IRQ_
Reserved

Reserved

IRQ_ IRQ_ IRQ_ IRQ_

SRC_
SRC_ SRC_ SRC_ SRC_ Reserved
A53_
C1 C0 C3 C2
WUP
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST2_LPM_HSK_MASK

MST1_LPM_HSK_MASK

MST0_LPM_HSK_MASK
CPU_CLK_ON_LPM

R
Reserved

Reserved Reserved LPM1 LPM0

Reset 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0

GPC_LPCR_A53_BSC field descriptions

Field Description
31 DSM Trigger Mask
MASK_DSM_
TRIGGER 0 DSM trigger of A53 platform will not be masked
1 DSM trigger of A53 platform will be masked
30 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_A53_ LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
WUP the wake up source for A53 LPM and core0/core1/core2/core3 power. See “Power up process for A53
platform” for more specific information.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

652 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_LPCR_A53_BSC field descriptions (continued)

Field Description
0 LPM wakeup source be “OR” result of LPCR_A53_BSC[IRQ_SRC_C0]/
LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3]
setting
1 LPM wakeup source from external INT[127:0], masked by IMR0
29 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C1 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power. See “Power up process for A53
platform” for more specific information.

0 core1 wakeup source from external INT[127:0], masked by IMR1 refer to “Power up process for A53
platform” for more specific information
1 core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power
mode when this bit is set to 1’b1
28 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C0 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power. See “Power up process for A53
platform” for more specific information.

0 core0 wakeup source from external INT[127:0], masked by IMR0 refer to “Power up process for A53
platform” for more specific information
1 core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power
mode when this bit is set to 1’b1
27 This field is reserved.
- Reserved
26 L2 cache controller Wait For Interrupt Mask Register
MASK_L2CC_
WFI 0 WFI for L2 cache controller is not masked
1 WFI for L2 cache controller is masked
25 This field is reserved.
- Reserved
24 SCU Wait For Interrupt Mask Register
MASK_SCU_WFI
0 WFI for SCU is not masked
1 WFI for SCU is masked
23 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C3 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power.

0 core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53
Platform for more specific information.
1 core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during
low power mode when this bit is set to 1'b1.
22 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C2 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power.

0 core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53
Platform for more specific information.
1 core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during
low power mode when this bit is set to 1'b1.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 653
General Power Controller (GPC)

GPC_LPCR_A53_BSC field descriptions (continued)

Field Description
21–20 This field is reserved.
-
19 CORE3 Wait For Interrupt Mask
MASK_CORE3_
WFI 0 WFI for CORE3 is not masked
1 WFI for CORE3 is masked
18 CORE2 Wait For Interrupt Mask
MASK_CORE2_
WFI 0 WFI for CORE2 is not masked
1 WFI for CORE2 is masked
17 CORE1 Wait For Interrupt Mask
MASK_CORE1_
WFI 0 WFI for CORE1 is not masked
1 WFI for CORE1 is masked
16 CORE0 Wait For Interrupt Mask
MASK_CORE0_
WFI 0 WFI for CORE0 is not masked
1 WFI for CORE0 is masked
15 This field is reserved.
- Reserved
14 Define if A53 clocks will be disabled on wait/stop mode.
CPU_CLK_ON_
LPM 0 A53 clock disabled on wait/stop mode
1 A53 clock enabled on wait/stop mode
13–9 This field is reserved.
- Reserved
8 MASTER2 LPM handshake mask
MST2_LPM_
HSK_MASK MASTER2(supermix2noc ADB) will handshake with GPC in LPM, follow this when you want this master
power off. This bit should use together with MST_CPU_MAPPING[2]
If you want power of supermix2noc ADB, use this setting: LPCR_A53_BSC[8]=0;
MST_CPU_MAPPING[2]=1
Otherwise use: LPCR_A53_BSC[8]=1; MST_CPU_MAPPING[2]=0

0 enable MASTER2 LPM handshake, wait ACK from MASTER2

1 disable MASTER2 LPM handshake, mask ACK from MASTER2
7 MASTER1 LPM handshake mask
MST1_LPM_
HSK_MASK MASTER1(supermix2noc ADB) will handshake with GPC in LPM, follow this when you want this master
power off. This bit should use together with MST_CPU_MAPPING[1]
If you want power of supermix2noc ADB, use this setting: LPCR_A53_BSC[7]=0;
MST_CPU_MAPPING[1]=1
Otherwise use: LPCR_A53_BSC[7]=1; MST_CPU_MAPPING[1]=0

0 enable MASTER1 LPM handshake, wait ACK from MASTER1

1 disable MASTER1 LPM handshake, mask ACK from MASTER1
6 MASTER0 LPM handshake mask
MST0_LPM_
HSK_MASK
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

654 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_LPCR_A53_BSC field descriptions (continued)

Field Description
MASTER0(SCU) will handshake with GPC in LPM, follow this when you want this master power off. This
bit should be used together with MST_CPU_MAPPING[0].
If you want power of SCU, use this setting: LPCR_A53_BSC[6]=0; MST_CPU_MAPPING[0]=1
Otherwise use: LPCR_A53_BSC[6]=1; MST_CPU_MAPPING[0]=0

0 enable MASTER0 LPM handshake, wait ACK from MASTER0

1 disable MASTER0 LPM handshake, mask ACK from MASTER0
5–4 This field is reserved.
- Reserved
3–2 CORE1 Setting the low power mode that system will enter on next assertion of dsm_request signal.
LPM1
00 Remain in RUN mode
01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved
LPM0 CORE0 Setting the low power mode that system will enter on next assertion of dsm_request signal.

00 Remain in RUN mode

01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved

5.2.10.2 Advanced Low power control register of A53 platform

(GPC_LPCR_A53_AD)

Address: 303A_0000h base + 4h offset = 303A_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN_C3_WFI_

EN_C2_WFI_

EN_C1_WFI_

EN_C0_WFI_

R
EN_ EN_ EN_ EN_
PDN_DIS

PDN_DIS

PDN_DIS

PDN_DIS

EN_ EN_ EN_ EN_

L2PGE

C3_ C2_ C3_ C2_

Reserved C3_ C2_ C3_ C2_
IRQ_ IRQ_ WFI_ WFI_
PUP PUP PDN PDN
W PUP PUP PDN PDN

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_PLAT_PDN
EN_L2_WFI_

R
EN_ EN_ EN_ EN_
EN_ EN_ EN_ EN_
C1_ C0_ C1_ C0_
PDN

Reserved C1_ C0_ Reserved C1_ C0_

IRQ_ IRQ_ WFI_ WFI_
PUP PUP PDN PDN
W PUP PUP PDN PDN

Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 655
General Power Controller (GPC)

GPC_LPCR_A53_AD field descriptions

Field Description
31 0 L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode)
L2PGE 1 L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF
mode)
30–28 This field is reserved.
- Reserved
27 0 CORE3 will not power up with lower power mode request
EN_C3_PUP 1 CORE3 will power up with low power mode request (only used wake up from CPU_OFF)
26 0 CORE3 will not power up with IRQ request
EN_C3_IRQ_ 1 CORE3 will power up with IRQ request
PUP
25 0 CORE2 will not power up with lower power mode request
EN_C2_PUP 1 CORE2 will power up with low power mode request (only used wake up from CPU_OFF)
24 0 CORE2 will not power up with IRQ request
EN_C2_IRQ_ 1 CORE2 will power up with IRQ request
PUP
23 0 Disable WFI power down core3
EN_C3_WFI_ 1 Enable WFI power down core3
PDN_DIS
22 0 Disable WIFI power down core2
EN_C2_WFI_ 1 Enable WIFI power down core2
PDN_DIS
21 0 Disable WIFI power down core1
EN_C1_WFI_ 1 Enable WIFI power down core1
PDN_DIS
20 0 Disable WIFI power down core0
EN_C0_WFI_ 1 Enable WIFI power down core0
PDN_DIS
19 0 CORE3 will not be power down with low power mode request
EN_C3_PDN 1 CORE3 will be power down with low power mode request
18 0 CORE3 will not be power down with WFI request
EN_C3_WFI_ 1 CORE3 will be power down with WFI request
PDN
17 0 CORE2 will not be power down with low power mode request
EN_C2_PDN 1 CORE2 will be power down with low power mode request
16 0 CORE2 will not be power down with WFI request
EN_C2_WFI_ 1 CORE2 will be power down with WFI request
PDN
15–12 This field is reserved.
- Reserved
11 0 CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode)
EN_C1_PUP 1 CORE1 will power up with low power mode request
10 0 CORE1 will not power up with IRQ request
EN_C1_IRQ_ 1 CORE1 will power up with IRQ request
PUP
9 (only used wake up from CPU01_OFF mode)
EN_C0_PUP
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

656 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_LPCR_A53_AD field descriptions (continued)

Field Description
0 CORE0 will not power up with low power mode request
1 CORE0 will power up with low power mode request
8 0 CORE0 will not power up with IRQ request
EN_C0_IRQ_ 1 CORE0 will power up with IRQ request
PUP
7–6 This field is reserved.
- Reserved
5
EN_L2_WFI_ NOTE: Before reset, L2 WFI is 1 and make GPC generate an error DSM request. This bit is used to
PDN mask the L2 WFI before reset. After reset, L2 WFI change to 0, and functions are OK, SW must
clear this bit at the beginning of code.

0 SCU and L2 will not be power down with WFI request

1 SCU and L2 will be power down with WFI request (default)
4 0 SCU and L2 cache RAM will not be power down with low power mode request
EN_PLAT_PDN 1 SCU and L2 cache RAM will be power down with low power mode request
3 0 CORE1 will not be power down with low power mode request
EN_C1_PDN 1 CORE1 will be power down with low power mode request
2 0 CORE1 will not be power down with WFI request
EN_C1_WFI_ 1 CORE1 will be power down with WFI request
PDN
1 0 CORE0 will not be power down with low power mode request
EN_C0_PDN 1 CORE0 will be power down with low power mode request
0 0 CORE0 will not be power down with WFI request
EN_C0_WFI_ 1 CORE0 will be power down with WFI request
PDN

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 657
General Power Controller (GPC)

5.2.10.3 Low power control register of CPU1 (GPC_LPCR_M4)

NOTE
LPCR_M4[CPU_CLK_ON_LPM] should be set 1’b0 if M4
goes to LPM without trigger power down of related domains
Address: 303A_0000h base + 8h offset = 303A_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK_DSM_TRIGGER

MASK_M4_WFI
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_CLK_ON_LPM

R
Reserved

EN_ EN_
Reserved M4_ M4_ LPM0
PUP PDN
W

Reset 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0

GPC_LPCR_M4 field descriptions

Field Description
31 M4 WFI Mask
MASK_DSM_
TRIGGER 0 DSM trigger of M4 platform will not be masked
1 DSM trigger of M4 platform will be masked
30–17 This field is reserved.
- Reserved
16 M4 WFI Mask
MASK_M4_WFI
0 WFI for M4 is not masked
1 WFI for M4 is masked
15 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

658 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_LPCR_M4 field descriptions (continued)

Field Description
14 Define if M4 clocks will be disabled on wait/stop mode.
CPU_CLK_ON_
LPM 0 M4 clock disabled on wait/stop mode.
1 M4 clock enabled on wait/stop mode.
13–4 This field is reserved.
- Reserved
3 Enable m4 virtual PGC power up with LPM enter
EN_M4_PUP
2 Enable m4 virtual PGC power down with LPM enter
EN_M4_PDN
LPM0 Setting the low power mode that system will enter on next assertion of dsm_request signal.

00 Remain in RUN mode

01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 659
General Power Controller (GPC)

5.2.10.4 System low power control register (GPC_SLPCR)

NOTE
SLPCR[VSTBY] must be set to 1’b1 if SLPCR[RBC_EN] is
set to 1’b1; SLPCR[SBYOS] must be set to 1’b1 if
SLPCR[VSTBY] is set to 1’b1.
Address: 303A_0000h base + 14h offset = 303A_0014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EN_A53_FASTWUP_

EN_A53_FASTWUP_
DISABLE_A53_IS_D

EN_M4_FASTWUP_

EN_M4_FASTWUP_
R

STOP_MODE

STOP_MODE
WAIT_MODE

WAIT_MODE
RBC_EN

EN_

SM
REG_BYPASS_COUNT Reserved
DSM
W

Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COSC_PWRDOWN

BYPASS_PMIC_
R
COSC_EN

SBYOS

READY
VSTBY
OSCCNT STBY_COUNT

Reset 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0

GPC_SLPCR field descriptions

Field Description
31 DSM enable
EN_DSM
0 DSM disabled
1 DSM enabled
30 Enable for REG_BYPASS_COUNTER. If enabled, REG_BYPASS signal will be asserted after
RBC_EN REG_BYPASS_COUNT clocks of CKIL, after standby voltage is requested. If standby voltage is not
requested REG_BYPASS won’t be asserted, even if counter is enabled.

0 REG_BYPASS_COUNTER disabled
1 REG_BYPASS_COUNTER enabled
29–24 Counter for REG_BYPASS signal assertion after standby voltage request by PMIC_STBY_REQ.
REG_BYPASS_
COUNT NOTE: When RBC enabled, interrupt will be masked until the counter counts to the value set in
GPC_SLPCR[REG_BYPASS_COUNT], this can ignore the unexpected interrupts before CPU
enter LPM mode, avoid the process interruption.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

660 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_SLPCR field descriptions (continued)

Field Description
000000 no delay
000001 1 CKIL clock period delay
111111 63 CKIL clock period delay
23 0 Enable A53 isolation signal in DSM
DISABLE_A53_I 1 Disable A53 isolation signal in DSM
S_DSM
22–20 This field is reserved.
- Reserved
19 Enable M4 fast wake up stop mode, relevant PLLs will not be closed in this mode.
EN_M4_FASTW
UP_STOP_MOD
E
18 Enable M4 fast wake up wait mode, relevant PLLs will not be closed in this mode.
EN_M4_FASTW
UP_WAIT_MOD
E
17 Enable A53 fast wake up stop mode, relevant PLLs will not be closed in this mode.
EN_A53_FASTW
UP_STOP_MOD
E
16 Enable A53 fast wake up wait mode, relevant PLLs will not be closed in this mode.
EN_A53_FASTW
UP_WAIT_MOD
E
15–8 Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for
OSCCNT oscillator lock time. This is used for oscillator lock time. Current estimation is ~5ms. This counter will be
used in sequence out of DSM and if sbyos bit was defined. GPC will wait the “OSCCNT” number of cycles
before it notify CCM to open the relevant PLLs.

00000000 count 1 ckil

11111111 count 256 ckils
7 On-chip oscillator enable bit - this bit value is reflected on the output cosc_en. The system will start with
COSC_EN on-chip oscillator enabled to supply source for the PLLs. Software can change this bit if a transition to the
bypass PLL clocks was performed for all the PLLs. In cases that this bit is changed from ‘0’ to ‘1’ then
GPC will enable the on-chip oscillator and after counting oscnt ckil clock cycles before it notify CCM to
open the relevant PLLs . The cosc_en bit should be changed only when on-chip oscillator is not chosen as
the clock source.

0 Disable on-chip oscillator

1 Enable on-chip oscillator
6 In run mode, software can manually control powering down of on chip oscillator, i.e. generating ‘1’ on
COSC_ cosc_pwrdown signal. If software manually powered down the on chip oscillator, then sbyos functionality
PWRDOWN for on-chip oscillator will be bypassed.
The manual closing of on-chip oscillator should be performed only in case the reference oscillator is not
the source of all the clocks generation.

0 On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0

1 On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 661
General Power Controller (GPC)

GPC_SLPCR field descriptions (continued)

Field Description
5–3 Standby counter definition. These two bits define, in the case of stop exit (if VSTBY bit was set), the
STBY_COUNT amount of time GPC will wait between PMIC_STBY_REQ negation and the check of assertion of
PMIC_READY.

000 GPC will wait 4 ckil clock cycles

001 GPC will wait 8 ckil clock cycles
010 GPC will wait 16 ckil clock cycles
011 GPC will wait 32 ckil clock cycles
100 GPC will wait 64 ckil clock cycles
101 GPC will wait 128 ckil clock cycles
110 GPC will wait 256 ckil clock cycles
111 GPC will wait 512 ckil clock cycles
2 Voltage standby request bit. This bit defines if PMIC_STBY_REQ pin, which notifies external power
VSTBY management IC to move from functional voltage to standby voltage, will be asserted in stop mode.

0 Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ
will remain negated - ‘0’)
1 Voltage will be changed to standby voltage after next entrance to stop mode.
1 Standby clock oscillator bit. This bit defines if cosc_pwrdown, which power down the on chip oscillator, will
SBYOS be asserted in DSM.

0 On chip oscillator will not be powered down, after next entrance to DSM.
1 On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM,
external oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after
oscnt count GPC will continue with the exit from DSM process.
0 By asserting this bit GPC will bypass waiting for PMIC_READY signal when coming out of DSM. This
BYPASS_PMIC_ should be used for PMIC’s that don’t support the PMIC_READY signal.
READY
0 Don’t bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if
standby voltage was enabled
1 Bypass the PMIC_READY signal - GPC will not wait for its assertion during exit of low power mode if
standby voltage was enabled

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

662 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.5 MASTER LPM Handshake (GPC_MST_CPU_MAPPING)

Address: 303A_0000h base + 18h offset = 303A_0018h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MST2_CPU_

MST1_CPU_

MST0_CPU_
R

MAPPING

MAPPING

MAPPING
Reserved
W

Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

GPC_MST_CPU_MAPPING field descriptions

Field Description
31–3 This field is reserved.
- Reserved
2 MASTER2 CPU Mapping
MST2_CPU_
MAPPING noc2supermix ADB LPM handshake mask. This bit should be used together with LPCR_A53_BSC[8].
If you want power of SCU, use this setting: LPCR_A53_BSC[8]=0; MST_CPU_MAPPING[2]=1
Otherwise, use this: LPCR_A53_BSC[8]=1; MST_CPU_MAPPING[2]=0

0 GPC will not send out power off requirement

1 GPC will send out power off requirement
1 MASTER1 CPU Mapping
MST1_CPU_
MAPPING Supermix2noc ADB LPM handshake mask. This bit should be used together with LPCR_A53_BSC[7].
If you want power of SCU, use this setting: LPCR_A53_BSC[7]=0; MST_CPU_MAPPING[1]=1
Otherwise, use this: LPCR_A53_BSC[7]=1; MST_CPU_MAPPING[1]=0

0 GPC will not send out power off requirement

1 GPC will send out power off requirement
0 MASTER0 CPU Mapping
MST0_CPU_
MAPPING SCU LPM handshake mask. This bit should be used together with LPCR_A7_BSC[6].
If you want power of SCU, use this setting: LPCR_A7_BSC[6]=0; MST_CPU_MAPPING[0]=1
Otherwise, use this: LPCR_A7_BSC[6]=1; MST_CPU_MAPPING[0]=0

0 GPC will not send out power off requirement

1 GPC will send out power off requirement

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 663
General Power Controller (GPC)

5.2.10.6 Memory low power control register (GPC_MLPCR)

Address: 303A_0000h base + 20h offset = 303A_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MEMLP_RET_PGEN MEM_EXT_CNT
W

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ROMLP_PDN_

MEMLP_RET_

MEMLP_CTL_
R

SEL
DIS

DIS
MEMLP_ENT_CNT Reserved
W

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

GPC_MLPCR field descriptions

Field Description
31–24 Delay counter for “retnx” and “pgen”
MEMLP_RET_
PGEN
23–16 Delay counter to start existing from memory low power
MEM_EXT_CNT
15–8 Delay counter to make sure all clock off after pll_dis_req is issued by smc
MEMLP_ENT_
CNT
7–3 This field is reserved.
- Reserved
2 ROM shut down control
ROMLP_PDN_
DIS 0 Enable ROM shut down control(should also enable RAM low power control);
1 Disable ROM shut down control
1 Retention select
MEMLP_RET_
SEL 0 retention mode 2
1 retention mode 1
0 RAM low-power control
MEMLP_CTL_
DIS 0 Enable RAM low power control
1 Disable RAM low power control

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

664 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.7 PGC acknowledge signal selection of A53 platform

(GPC_PGC_ACK_SEL_A53)

The register can only be accessed by A53 platform

Address: 303A_0000h base + 24h offset = 303A_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NOC_PGC_PUP_

A53_PLAT_PGC_
A53_PGC_PUP_

A53_C3_PGC_

A53_C2_PGC_

A53_C1_PGC_

A53_C0_PGC_
R
PUP_ACK

PUP_ACK

PUP_ACK

PUP_ACK

PUP_ACK
ACK

ACK
Reserved

Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NOC_PGC_PDN_

A53_PLAT_PGC_
A53_PGC_PDN_

A53_C3_PGC_

A53_C2_PGC_

A53_C1_PGC_

A53_C0_PGC_
R
PDN_ACK

PDN_ACK

PDN_ACK

PDN_ACK

PDN_ACK
ACK

ACK
Reserved

Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_PGC_ACK_SEL_A53 field descriptions

Field Description
31 Select power up acknowledge signal of A53 (dummy) PGC as the power up acknowledge for A53 LPM.
A53_PGC_PUP_
ACK
30 Select power up acknowledge signal of A53 CORE3 PGC as the power up acknowledge for A53 LPM.
A53_C3_PGC_
PUP_ACK
29 Select power up acknowledge signal of A53 CORE2 PGC as the power up acknowledge for A53 LPM.
A53_C2_PGC_
PUP_ACK
28–20 This field is reserved.
- Reserved
19 Select power up acknowledge signal of NOC PGC as the power up acknowledge for A53 LPM.
NOC_PGC_
PUP_ACK
18 Select power up acknowledge signal of A53 PLATFORM PGC as the power up acknowledge for A53
A53_PLAT_ LPM.
PGC_PUP_ACK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 665
General Power Controller (GPC)

GPC_PGC_ACK_SEL_A53 field descriptions (continued)

Field Description
17 Select power up acknowledge signal of A53 CORE1 PGC as the power up acknowledge for A53 LPM.
A53_C1_PGC_
PUP_ACK
16 Select power up acknowledge signal of A53 CORE0 PGC as the power up acknowledge for A53 LPM.
A53_C0_PGC_
PUP_ACK
15 Select power down acknowledge signal of A53 (dummy) PGC as the power down acknowledge for A53
A53_PGC_PDN_ LPM.
ACK
14 Select power down acknowledge signal of A53 CORE3 PGC as the power down acknowledge for A53
A53_C3_PGC_ LPM.
PDN_ACK
13 Select power down acknowledge signal of A53 CORE2 PGC as the power down acknowledge for A53
A53_C2_PGC_ LPM.
PDN_ACK
12–4 This field is reserved.
- Reserved
3 Select power down acknowledge signal of NOC PGC as the power down acknowledge for A53 LPM.
NOC_PGC_
PDN_ACK
2 Select power down acknowledge signal of A53 PLATFORM PGC as the power down acknowledge for
A53_PLAT_ A53 LPM.
PGC_PDN_ACK
1 Select power down acknowledge signal of A53 CORE1 PGC as the power down acknowledge for A53
A53_C1_PGC_ LPM.
PDN_ACK
0 Select power down acknowledge signal of A53 CORE0 PGC as the power down acknowledge for A53
A53_C0_PGC_ LPM.
PDN_ACK

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

666 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.8 PGC acknowledge signal selection of M4 platform

(GPC_PGC_ACK_SEL_M4)

This register can only be accessed by the M4 platform.

NOTE
“dummy” PGC cannot be mapped to time slot control. “virtual”
PGC can be mapped to time slot control. When virtual PGC is
used, below setting is required -
GPC_MISC[M4_PDN_REQ_MASK] should be set to 1’b1 and
arrange virtual GPC in same slot with MIX. power/up slot (See
example code 3). MIX PGC may possibly power down later
than A53 platform power down when virtual PGC is used.
Address: 303A_0000h base + 28h offset = 303A_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

M4_VIRTUAL_PGC_
M4_DUMMY_PGC_

NOC_PGC_PUP_
R
PUP_ACK

PUP_ACK
ACK
Reserved

Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M4_VIRTUAL_PGC_
M4_DUMMY_PGC_

NOC_PGC_PDN_
R
PDN_ACK

PDN_ACK
ACK
Reserved

Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_PGC_ACK_SEL_M4 field descriptions

Field Description
31 Select power up acknowledge signal of M4 (dummy) PGC as the power up acknowledge for M4 LPM.
M4_DUMMY_
PGC_PUP_ACK
30–18 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 667
General Power Controller (GPC)

GPC_PGC_ACK_SEL_M4 field descriptions (continued)

Field Description
17 Select power up acknowledge signal of NOC PGC as the power up acknowledge for M4 LPM.
NOC_PGC_
PUP_ACK
16 Select power up acknowledge signal of M4 virtual PGC as the power up acknowledge for M4 LPM. M4
M4_VIRTUAL_ virtual PGC only acknowledge power up request in the end of current slot time
PGC_PUP_ACK
15 Select power down acknowledge signal of M4 (dummy) PGC as the power down acknowledge for M4
M4_DUMMY_ LPM.
PGC_PDN_ACK
14–2 This field is reserved.
- Reserved
1 Select power down acknowledge signal of NOC PGC as the power down acknowledge for M4 LPM.
NOC_PGC_
PDN_ACK
0 Select power down acknowledge signal of M4 virtual PGC as the power down acknowledge for M4 LPM.
M4_VIRTUAL_ M4 virtual PGC only acknowledge power down request in the end of current slot time
PGC_PDN_ACK

5.2.10.9 GPC Miscellaneous register (GPC_MISC)

Address: 303A_0000h base + 2Ch offset = 303A_002Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M4_BYPASS_PUP

A53_BYPASS_

R
PUP_MASK
_MASK

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M4_PDN_REQ_MA

M4_SLEEP_HOLD
GPC_IRQ_MASK

HOLD_REQ_B
A53_SLEEP_

R
_REQ_B
SK

Reserved Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

668 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_MISC field descriptions

Field Description
31–26 This field is reserved.
- Reserved
25
M4_BYPASS_PU
P_MASK
24
A53_BYPASS_
PUP_MASK
23–9 This field is reserved.
- Reserved
8 M4 power-down mask
M4_PDN_REQ_
MASK 0 M4 power down request to virtual M4 PGC will be masked.
1 M4 power down request to virtual M4 PGC will not be masked. Set this bit to 1’b1 when M4 virtual
PGC is used.
7–6 This field is reserved.
- Reserved
5 GPC interrupt/event masking
GPC_IRQ_MASK
0 Not masked
1 Interrupt / event is masked
4–2 This field is reserved.
- Reserved
1 A53 sleep hold
A53_SLEEP_
HOLD_REQ_B 0 Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform.
1 Don’t hold A53 platform in sleep mode.
0 M4 sleep hold
M4_SLEEP_HOL
D_REQ_B 0 Hold M4 platform in sleep mode. This bit is a software control bit to M4 platform.
1 Don’t hold M4 platform in sleep mode.

5.2.10.10 IRQ masking register 1 of A53 core0

(GPC_IMR1_CORE0_A53)

The four IMRn_CORE0_A53 (n = 1,2,3,4) registers are used as interrupt mask for A53
core0.
Address: 303A_0000h base + 30h offset = 303A_0030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 669
General Power Controller (GPC)

GPC_IMR1_CORE0_A53 field descriptions

Field Description
IMR1_CORE0_A A53 core0 IRQ[31:0] masking bits:
53
0 IRQ not masked
1 IRQ masked

5.2.10.11 IRQ masking register 2 of A53 core0

(GPC_IMR2_CORE0_A53)

Address: 303A_0000h base + 34h offset = 303A_0034h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR2_CORE0_A53 field descriptions

Field Description
IMR2_CORE0_A A53 core0 IRQ[63:32] masking bits:
53
0 IRQ not masked
1 IRQ masked

5.2.10.12 IRQ masking register 3 of A53 core0

(GPC_IMR3_CORE0_A53)

Address: 303A_0000h base + 38h offset = 303A_0038h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR3_CORE0_A53 field descriptions

Field Description
IMR3_CORE0_A A53 core0 IRQ[95:64] masking bits:
53
0 IRQ not masked
1 IRQ masked

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

670 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.13 IRQ masking register 4 of A53 core0

(GPC_IMR4_CORE0_A53)

Address: 303A_0000h base + 3Ch offset = 303A_003Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR4_CORE0_A53 field descriptions

Field Description
IMR4_CORE0_A A53 core0 IRQ[127:96] masking bits:
53
0 IRQ not masked
1 IRQ masked

5.2.10.14 IRQ masking register 1 of A53 core1

(GPC_IMR1_CORE1_A53)

The four IMRn_CORE1_A53 (n = 1,2,3,4) registers are used as interrupt mask for A53
core1.
Address: 303A_0000h base + 40h offset = 303A_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR1_CORE1_A53 field descriptions

Field Description
IMR1_CORE1_A A53 core1 IRQ[31:0] masking bits:
53
0 IRQ not masked
1 IRQ masked

5.2.10.15 IRQ masking register 2 of A53 core1

(GPC_IMR2_CORE1_A53)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 671
General Power Controller (GPC)

Address: 303A_0000h base + 44h offset = 303A_0044h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR2_CORE1_A53 field descriptions

Field Description
IMR2_CORE1_A A53 core1 IRQ[63:32] masking bits:
53
0 IRQ not masked
1 IRQ masked

5.2.10.16 IRQ masking register 3 of A53 core1

(GPC_IMR3_CORE1_A53)

Address: 303A_0000h base + 48h offset = 303A_0048h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR3_CORE1_A53 field descriptions

Field Description
IMR3_CORE1_A A53 core1 IRQ[95:64] masking bits:
53
0 IRQ not masked
1 IRQ masked

5.2.10.17 IRQ masking register 4 of A53 core1

(GPC_IMR4_CORE1_A53)

Address: 303A_0000h base + 4Ch offset = 303A_004Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR4_CORE1_A53 field descriptions

Field Description
IMR4_CORE1_A A53 core1 IRQ[127:96] masking bits:
53

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

672 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_IMR4_CORE1_A53 field descriptions (continued)

Field Description
0 IRQ not masked
1 IRQ masked

5.2.10.18 IRQ masking register 1 of M4 (GPC_IMR1_M4)

The four IMRn_M4 (n = 1,2,3,4) registers are used as interrupt mask for M4.
Address: 303A_0000h base + 50h offset = 303A_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_M4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR1_M4 field descriptions

Field Description
IMR1_M4 M4 IRQ[31:0] masking bits:

0 IRQ not masked

1 IRQ masked

5.2.10.19 IRQ masking register 2 of M4 (GPC_IMR2_M4)

Address: 303A_0000h base + 54h offset = 303A_0054h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_M4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR2_M4 field descriptions

Field Description
IMR2_M4 M4 IRQ[63:32] masking bits:

0 IRQ not masked

1 IRQ masked

5.2.10.20 IRQ masking register 3 of M4 (GPC_IMR3_M4)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 673
General Power Controller (GPC)

Address: 303A_0000h base + 58h offset = 303A_0058h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_M4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR3_M4 field descriptions

Field Description
IMR3_M4 M4 IRQ[95:64] masking bits:

0 IRQ not masked

1 IRQ masked

5.2.10.21 IRQ masking register 4 of M4 (GPC_IMR4_M4)

Address: 303A_0000h base + 5Ch offset = 303A_005Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_M4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR4_M4 field descriptions

Field Description
IMR4_M4 M4 IRQ[127:96] masking bits:

0 IRQ not masked

1 IRQ masked

5.2.10.22 IRQ status register 1 of A53 (GPC_ISR1_A53)

The four ISRn_A53 (n = 1,2,3,4) registers, all of them are read only register
Address: 303A_0000h base + 70h offset = 303A_0070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR1_A53
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

674 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_ISR1_A53 field descriptions

Field Description
ISR1_A53 A53 IRQ[31:0] status

5.2.10.23 IRQ status register 2 of A53 (GPC_ISR2_A53)

Address: 303A_0000h base + 74h offset = 303A_0074h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR2_A53
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ISR2_A53 field descriptions

Field Description
ISR2_A53 A53 IRQ[63:32] status

5.2.10.24 IRQ status register 3 of A53 (GPC_ISR3_A53)

Address: 303A_0000h base + 78h offset = 303A_0078h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR3_A53
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ISR3_A53 field descriptions

Field Description
ISR3_A53 A53 IRQ[95:64] status

5.2.10.25 IRQ status register 4 of A53 (GPC_ISR4_A53)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 675
General Power Controller (GPC)

Address: 303A_0000h base + 7Ch offset = 303A_007Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR4_A53
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ISR4_A53 field descriptions

Field Description
ISR4_A53 A53 IRQ[127:96] status

5.2.10.26 IRQ status register 1 of M4 (GPC_ISR1_M4)

The four ISRn_M4 (n = 1,2,3,4) registers, all of them are read only register
Address: 303A_0000h base + 80h offset = 303A_0080h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR1_M4
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ISR1_M4 field descriptions

Field Description
ISR1_M4 M4 IRQ[31:0] status

5.2.10.27 IRQ status register 2 of M4 (GPC_ISR2_M4)

Address: 303A_0000h base + 84h offset = 303A_0084h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR2_M4
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ISR2_M4 field descriptions

Field Description
ISR2_M4 M4 IRQ[63:32] status

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

676 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.28 IRQ status register 3 of M4 (GPC_ISR3_M4)

Address: 303A_0000h base + 88h offset = 303A_0088h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR3_M4
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ISR3_M4 field descriptions

Field Description
ISR3_M4 M4 IRQ[95:64] status

5.2.10.29 IRQ status register 4 of M4 (GPC_ISR4_M4)

Address: 303A_0000h base + 8Ch offset = 303A_008Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ISR4_M4
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ISR4_M4 field descriptions

Field Description
ISR4_M4 M4 IRQ[127:96] status

5.2.10.30 Slot configure register for CPUs (GPC_SLTn_CFG)

There are 20 slots in each SLTn_CFG(n = 0~19) that define the power up or power down
behavior of one or more A53 core, NOC, or SCU PGC in each slot. This array contains
slots 0 to 14, see Memory Map for slots 15 to 19.
In each “SLTn_cfg”, 2 bits (slt_cfg[1:0])are reserved for each PGC:
• 2’b01 (slot controller will power down relevant PGC in corresponding slot if
hardware power down request asserted)
• 2’b10 (slot controller will power up relevant PGC in corresponding slot if hardware
power up request asserted)
• 2’b00 or 2’b11 (not power down or power up behavior in relevant slot)
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 677
General Power Controller (GPC)

The specific bits assignment for each PGC is shown in the table below.
PGCx PGCx-1 .. PGC2 PGC1 PGC0
SLT0_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
SLT1_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
: slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
SLTn_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]

Address: 303A_0000h base + B0h offset + (4d × i), where i=0d to 14d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORE3_A53_PDN_

CORE2_A53_PDN_

CORE1_A53_PDN_

CORE0_A53_PDN_
CORE3_A53_PUP_

CORE2_A53_PUP_

CORE1_A53_PUP_

CORE0_A53_PUP_
NOC_PDN_SLOT_
NOC_PUP_SLOT_

SCU_PDN_SLOT_
SCU_PUP_SLOT_

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL
R
CONTROL

CONTROL

CONTROL

CONTROL

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_SLTn_CFG field descriptions

Field Description
31–12 This field is reserved.
-
11 NOC Power-up slot control
NOC_PUP_
SLOT_
CONTROL
10 NOC Power-down slot control
NOC_PDN_
SLOT_
CONTROL
9 SCU Power-up slot control
SCU_PUP_
SLOT_
CONTROL

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

678 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_SLTn_CFG field descriptions (continued)

Field Description
8 SCU Power-down slot control
SCU_PDN_
SLOT_
CONTROL
7 CORE3 A53 Power-up slot control
CORE3_A53_
PUP_SLOT_
CONTROL
6 CORE3 A53 Power-down slot control
CORE3_A53_
PDN_SLOT_
CONTROL
5 CORE2 A53 Power-up slot control
CORE2_A53_
PUP_SLOT_
CONTROL
4 CORE2 A53 Power-down slot control
CORE2_A53_
PDN_SLOT_
CONTROL
3 CORE1 A53 Power-up slot control
CORE1_A53_
PUP_SLOT_
CONTROL
2 CORE1 A53 Power-down slot control
CORE1_A53_
PDN_SLOT_
CONTROL
1 CORE0 A53 Power-up slot control
CORE0_A53_
PUP_SLOT_
CONTROL
0 CORE0 A53 Power-down slot control
CORE0_A53_
PDN_SLOT_
CONTROL

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 679
General Power Controller (GPC)

5.2.10.31 PGC CPU mapping (GPC_PGC_CPU_0_1_MAPPING)

Address: 303A_0000h base + ECh offset = 303A_00ECh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DISPMIX_M4_DOMAIN

GPU_3D_M4_DOMAIN

GPU_2D_M4_DOMAIN
VPU_G2_M4_DOMAIN

VPU_G1_M4_DOMAIN

GPUMIX_M4_DOMAIN
VPU_H1_M4_DOMAIN

VPUMIX_M4_DOMAIN

DDR1_M4_DOMAIN

OTG2_M4_DOMAIN

OTG1_M4_DOMAIN

PCIE_M4_DOMAIN

NOC_M4_DOMAIN
MIPI_M4_DOMAIN

MF_M4_DOMAIN
R

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISPMIX_A53_DOMAIN

GPU_3D_A53_DOMAIN

GPU_2D_A53_DOMAIN
VPU_G2_A53_DOMAIN

VPU_G1_A53_DOMAIN

GPUMIX_A53_DOMAIN
VPU_H1_A53_DOMAIN

VPUMIX_A53_DOMAIN

DDR1_A53_DOMAIN

OTG2_A53_DOMAIN

OTG1_A53_DOMAIN

PCIE_A53_DOMAIN

NOC_A53_DOMAIN
MIPI_A53_DOMAIN

MF_A53_DOMAIN
R

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_PGC_CPU_0_1_MAPPING field descriptions

Field Description
31 VPU_H1_M4_DOMAIN
VPU_H1_M4_DO
MAIN
30 VPU_G2_M4_DOMAIN
VPU_G2_M4_D
OMAIN
29 VPU_G1_M4_DOMAIN
VPU_G1_M4_D
OMAIN
28 DISPMIX_M4_DOMAIN
DISPMIX_M4_D
OMAIN
27 GPU_3D_M4_DOMAIN
GPU_3D_M4_D
OMAIN

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

680 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PGC_CPU_0_1_MAPPING field descriptions (continued)

Field Description
26 VPUMIX_M4_DOMAIN
VPUMIX_M4_DO
MAIN
25 GPUMIX_M4_DOMAIN
GPUMIX_M4_D
OMAIN
24 GPU_2D_M4_DOMAIN
GPU_2D_M4_D
OMAIN
23 DDR1_M4_DOMAIN
DDR1_M4_DOM
AIN
22 This field is reserved.
-
21 OTG2_M4_DOMAIN
OTG2_M4_
DOMAIN
20 OTG1_M4_DOMAIN
OTG1_M4_DOM
AIN
19 PCIE_M4_DOMAIN
PCIE_M4_
DOMAIN
18 MIPI_M4_DOMAIN
MIPI_M4_DOMAI
N
17 NOC_M4_DOMAIN
NOC_M4_DOMA
IN
16 MF_M4_DOMAIN
MF_M4_
DOMAIN
15 VPU_H1_A53_DOMAIN
VPU_H1_A53_D
OMAIN
14 VPU_G2_A53_DOMAIN
VPU_G2_A53_D
OMAIN
13 VPU_G1_A53_DOMAIN
VPU_G1_A53_D
OMAIN
12 DISP_MIXA53_DOMAIN
DISPMIX_A53_D
OMAIN
11 GPU_3D_A53_DOMAIN
GPU_3D_A53_D
OMAIN

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 681
General Power Controller (GPC)

GPC_PGC_CPU_0_1_MAPPING field descriptions (continued)

Field Description
10 VPUMIX_A53_DOMAIN
VPUMIX_A53_D
OMAIN
9 GPUMIX_A53_DOMAIN
GPUMIX_A53_D
OMAIN
8 GPU_2D_A53_DOMAIN
GPU_2D_A53_D
OMAIN
7 DDR1_A53_DOMAIN
DDR1_A53_
DOMAIN
6 This field is reserved.
-
5 OTG2_A53_DOMAIN
OTG2_A53_
DOMAIN
4 OTG1_A53_DOMAIN
OTG1_A53_
DOMAIN
3 PCIE_A53_DOMAIN
PCIE_A53_
DOMAIN
2 MIPI A53 DOMAIN
MIPI_A53_
DOMAIN
1 NOC_A53_DOMAIN
NOC_A53_
DOMAIN
0 MF_A53_DOMAIN
MF_A53_
DOMAIN

5.2.10.32 CPU PGC software power up trigger

(GPC_CPU_PGC_SW_PUP_REQ)

Address: 303A_0000h base + F0h offset = 303A_00F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

682 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SCU_A53_SW_PU

CORE3_A53_SW_

CORE2_A53_SW_

CORE1_A53_SW_

CORE0_A53_SW_
R

PUP_REQ

PUP_REQ

PUP_REQ

PUP_REQ
P_REQ
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_CPU_PGC_SW_PUP_REQ field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software power up trigger for SCU A53 PGC
SCU_A53_SW_P
UP_REQ
3 Software power up trigger for Core3 A53 PGC
CORE3_A53_S
W_PUP_REQ
2 Software power up trigger for Core2 A53
CORE2_A53_S
W_PUP_REQ
1 Software power up trigger for Core1 A53 PGC
CORE1_A53_S
W_PUP_REQ
0 Software power up trigger for Core0 A53 PGC
CORE0_A53_S
W_PUP_REQ

5.2.10.33 MIX PGC software power up trigger

(GPC_MIX_PGC_SW_PUP_REQ)

Address: 303A_0000h base + F4h offset = 303A_00F4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 683
General Power Controller (GPC)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NOC_SW_PUP_

MF_SW_PUP_R
R

REQ

EQ
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_MIX_PGC_SW_PUP_REQ field descriptions

Field Description
31–2 This field is reserved.
- Reserved
1 Software power up trigger for NOC PGC
NOC_SW_PUP_
REQ
0 Software power up trigger for MIX PGC
MF_SW_PUP_R
EQ

5.2.10.34 PU PGC software up trigger (GPC_PU_PGC_SW_PUP_REQ)

Address: 303A_0000h base + F8h offset = 303A_00F8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIPI_DSI_SW_PUP_REQ
DISPMIX_SW_PUP_REQ

GPU_3D_SW_PUP_REQ

GPU_2D_SW_PUP_REQ
VPU_G2_SW_PUP_REQ

VPU_G1_SW_PUP_REQ

GPUMIX_SW_PUP_REQ
VPU_H1_SW_PUP_REQ

USB_OTG2_SW_PUP_R

USB_OTG1_SW_PUP_R
VPUMIX_SW_PUP_REQ

DDR1_SW_PUP_REQ

PCIE_SW_PUP_REQ

R
Reserved

EQ

EQ

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

684 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PU_PGC_SW_PUP_REQ field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13 Software power up trigger for VPU_H1
VPU_H1_SW_P
UP_REQ
12 Software power up trigger for VPU_G2
VPU_G2_SW_P
UP_REQ
11 Software power up trigger for VPU_G1
VPU_G1_SW_P
UP_REQ
10 Software power up trigger for DISPMIX
DISPMIX_SW_P
UP_REQ
9 Software power up trigger for GPU_3D
GPU_3D_SW_P
UP_REQ
8 Software power up trigger for VPUMIX
VPUMIX_SW_P
UP_REQ
7 Software power up trigger for GPUMIX
GPUMIX_SW_P
UP_REQ
6 Software power up trigger for GPU_2D
GPU_2D_SW_P
UP_REQ
5 Software power up trigger for DDR1
DDR1_SW_
PUP_REQ
4 This field is reserved.
-
3 Software power up trigger for USB_OTG2
USB_OTG2_SW
_PUP_REQ
2 Software power up trigger for USB_OTG1
USB_OTG1_SW
_PUP_REQ
1 Software power up trigger for PCIE
PCIE_SW_PUP_
REQ
0 Software power up trigger for MIPI_DSI
MIPI_DSI_SW_P
UP_REQ

5.2.10.35 CPU PGC software down trigger

(GPC_CPU_PGC_SW_PDN_REQ)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 685
General Power Controller (GPC)

Address: 303A_0000h base + FCh offset = 303A_00FCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SCU_A53_SW_PU

CORE3_A53_SW_

CORE2_A53_SW_

CORE1_A53_SW_

CORE0_A53_SW_
R

PDN_REQ

PDN_REQ

PDN_REQ
PUP_REQ
P_REQ
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_CPU_PGC_SW_PDN_REQ field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software power up trigger for SCU A53 PGC
SCU_A53_SW_P
UP_REQ
3 Software power up trigger for Core3 A53 PGC
CORE3_A53_S
W_PUP_REQ
2 Software power down trigger for Core2 A53 PGC
CORE2_A53_S
W_PDN_REQ
1 Software power down trigger for Core1 A53 PGC
CORE1_A53_S
W_PDN_REQ
0 Software power down trigger for Core0 A53 PGC
CORE0_A53_S
W_PDN_REQ

5.2.10.36 MIX PGC software power down trigger

(GPC_MIX_PGC_SW_PDN_REQ)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

686 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Address: 303A_0000h base + 100h offset = 303A_0100h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NOC_SW_PDN_

MF_SW_PDN_R
R

REQ

EQ
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_MIX_PGC_SW_PDN_REQ field descriptions

Field Description
31–2 This field is reserved.
- Reserved
1 Software power down trigger for NOC PGC
NOC_SW_PDN_
REQ
0 Software power down trigger for MIX PGC
MF_SW_PDN_R
EQ

5.2.10.37 PU PGC software down trigger

(GPC_PU_PGC_SW_PDN_REQ)

Address: 303A_0000h base + 104h offset = 303A_0104h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 687
General Power Controller (GPC)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MIPI_DSI_SW_PDN_REQ
DISPMIX_SW_PDN_REQ

GPU_3D_SW_PDN_REQ

GPU_2D_SW_PDN_REQ
VPU_G2_SW_PDN_REQ

VPU_G1_SW_PDN_REQ

GPUMIX_SW_PDN_REQ
VPU_H1_SW_PDN_REQ

USB_OTG2_SW_PDN_R

USB_OTG1_SW_PDN_R
VPUMIX_SW_PDN_REQ

DDR1_SW_PDN_REQ

PCIE_SW_PDN_REQ
R

Reserved

EQ

EQ
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_PU_PGC_SW_PDN_REQ field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13 Software power down trigger for VPU_H1
VPU_H1_SW_P
DN_REQ
12 Software power down trigger for VPU_G2
VPU_G2_SW_P
DN_REQ
11 Software power down trigger for VPU_G1
VPU_G1_SW_P
DN_REQ
10 Software power down trigger for DISPMIX
DISPMIX_SW_P
DN_REQ
9 Software power down trigger for GPU_3D
GPU_3D_SW_P
DN_REQ
8 Software power down trigger for VPUMIX
VPUMIX_SW_P
DN_REQ
7 Software power down trigger for GPUMIX
GPUMIX_SW_P
DN_REQ
6 Software power down trigger for GPU_2D
GPU_2D_SW_P
DN_REQ
5 Software power down trigger for DDR1
DDR1_SW_PDN
_REQ
4 This field is reserved.
-
3 Software power down trigger for USB_OTG2
USB_OTG2_SW
_PDN_REQ

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

688 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PU_PGC_SW_PDN_REQ field descriptions (continued)

Field Description
2 Software power down trigger for USB_OTG1
USB_OTG1_SW
_PDN_REQ
1 Software power down trigger for PCIE
PCIE_SW_PDN_
REQ
0 Software power down trigger for MIPI_DSI
MIPI_DSI_SW_P
DN_REQ

5.2.10.38 Basic Low power control register of A53 platform

(GPC_LPCR_A53_BSC2)
Address: 303A_0000h base + 108h offset = 303A_0108h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved LPM3 LPM2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_LPCR_A53_BSC2 field descriptions

Field Description
31–4 This field is reserved.
- Reserved
3–2 CORE3 Setting the low power mode that system will enter on next assertion of dsm_request signal.
LPM3
00 Remain in RUN mode
01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved
LPM2 CORE2 Setting the low power mode that system will enter on next assertion of dsm_request signal.

00 Remain in RUN mode

01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 689
General Power Controller (GPC)

5.2.10.39 CPU PGC software up trigger status1

(GPC_CPU_PGC_PUP_STATUS1)
CPU_PGC_PUP_STATUS1 is a read only register, represents the results for power up
software trigger for CPU type PGCs.
The field description is show in table below, the value of “1’b1” represent the software
power up trigger failed because the relevant PGC is in a power down process. The
relevant bit will be cleared after a success operation of power up software trigger for
CPU type PGCs.
Address: 303A_0000h base + 130h offset = 303A_0130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

690 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CORE3_A53_PUP_STATUS

CORE2_A53_PUP_STATUS

CORE1_A53_PUP_STATUS

CORE0_A53_PUP_STATUS
SCU_A53_PUP_REQ
R

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_CPU_PGC_PUP_STATUS1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4
SCU_A53_PUP_
REQ
3
CORE3_A53_PU
P_STATUS
2
CORE2_A53_PU
P_STATUS
1
CORE1_A53_PU
P_STATUS
0
CORE0_A53_PU
P_STATUS

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 691
General Power Controller (GPC)

5.2.10.40 A53 MIX software up trigger status register

(GPC_A53_MIX_PGC_PUP_STATUSn)
A53_MIX_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the
results for power up software trigger from A53 platform to MIX type PGCs.
A53_MIX_PGC_PUP_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
A53_MIX_PGC_PUP_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power up software trigger for MIX type PGCs.
A53_MIX_PGC_PUP_STATUS2: value of “1’b1” represent the software power up
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
Address: 303A_0000h base + 134h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

692 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A53_MIX_PGC_PUP_STATUS
R

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_A53_MIX_PGC_PUP_STATUSn field descriptions

Field Description
31–1 This field is reserved.
- Reserved
0
A53_MIX_PGC_
PUP_STATUS

5.2.10.41 M4 MIX PGC software up trigger status register

(GPC_M4_MIX_PGC_PUP_STATUSn)
M4_MIX_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the
results for power up software trigger from M4 platform to MIX type PGCs.
M4_MIX_PGC_PUP_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
M4_MIX_PGC_PUP_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power up software trigger for MIX type PGCs.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 693
General Power Controller (GPC)

M4_MIX_PGC_PUP_STATUS2: value of “1’b1” represent the software power up

trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
Address: 303A_0000h base + 140h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M4_MIX_PGC_PUP_STATUS
R

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

694 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_M4_MIX_PGC_PUP_STATUSn field descriptions

Field Description
31–1 This field is reserved.
- Reserved
0
M4_MIX_PGC_
PUP_STATUS

5.2.10.42 A53 PU software up trigger status register

(GPC_A53_PU_PGC_PUP_STATUSn)
A53_PU_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the results
for power up software trigger from A53 platform to PU type PGCs.
A53_PU_PGC_PUP_STATUS0: value of “1’b1” represent the software power up trigger
failed because domain control condition. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.
A53_PU_PGC_PUP_STATUS1: value of “1’b1” represent the software power up trigger
failed because the relevant PGC is in a power up process. The relevant bit will be cleared
after a success operation of power up software trigger for PU type PGCs.
A53_PU_PGC_PUP_STATUS2: value of “1’b1” represent the software power up trigger
failed because time slot control is busy. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 695
General Power Controller (GPC)

Address: 303A_0000h base + 14Ch offset + (4d × i), where i=0d to 2d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A53_DISPMIX_PUP_STATUS

A53_GPU_3D_PUP_STATUS

A53_GPU_2D_PUP_STATUS
A53_VPU_G2_PUP_STATUS

A53_VPU_G1_PUP_STATUS

A53_GPUMIX_PUP_STATUS
A53_VPU_H1_PUP_STATUS

A53_VPUMIX_PUP_STATUS

A53_DDR1_PUP_STATUS

A53_OTG2_PUP_STATUS

A53_OTG1_PUP_STATUS

A53_PCIE_PUP_STATUS

A53_MIPI_PUP_STATUS
R
Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

696 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_A53_PU_PGC_PUP_STATUSn field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13
A53_VPU_H1_P
UP_STATUS
12
A53_VPU_G2_P
UP_STATUS
11
A53_VPU_G1_P
UP_STATUS
10
A53_DISPMIX_P
UP_STATUS
9
A53_GPU_3D_P
UP_STATUS
8
A53_VPUMIX_P
UP_STATUS
7
A53_GPUMIX_P
UP_STATUS
6
A53_GPU_2D_
PUP_STATUS
5
A53_DDR1_PUP
_STATUS
4 This field is reserved.
-
3
A53_OTG2_PUP
_STATUS
2
A53_OTG1_PUP
_STATUS
1
A53_PCIE_PUP_
STATUS
0
A53_MIPI_PUP_
STATUS

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 697
General Power Controller (GPC)

5.2.10.43 M4 PU PGC software up trigger status register

(GPC_M4_PU_PGC_PUP_STATUSn)
M4_PU_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the results
for power up software trigger from M4 platform to PU type PGCs.
M4_PU_PGC_PUP_STATUS0: value of “1’b1” represent the software power up trigger
failed because domain control condition. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.
M4_PU_PGC_PUP_STATUS1: value of “1’b1” represent the software power up trigger
failed because the relevant PGC is in a power up process. The relevant bit will be cleared
after a success operation of power up software trigger for PU type PGCs.
M4_PU_PGC_PUP_STATUS2: value of “1’b1” represent the software power up trigger
failed because time slot control is busy. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.
Address: 303A_0000h base + 158h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

698 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M4_DISPMIX_PUP_STATUS

M4_GPU_3D_PUP_STATUS

M4_GPU_2D_PUP_STATUS
M4_VPU_G2_PUP_STATUS

M4_VPU_G1_PUP_STATUS

M4_GPUMIX_PUP_STATUS
M4_VPU_H1_PUP_STATUS

M4_VPUMIX_PUP_STATUS

M4_DDR1_PUP_STATUS

M4_OTG2_PUP_STATUS

M4_OTG1_PUP_STATUS

M4_PCIE_PUP_STATUS

M4_MIPI_PUP_STATUS
R

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_M4_PU_PGC_PUP_STATUSn field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13
M4_VPU_H1_PU
P_STATUS
12
M4_VPU_G2_PU
P_STATUS
11
M4_VPU_G1_PU
P_STATUS
10
M4_DISPMIX_P
UP_STATUS
9
M4_GPU_3D_PU
P_STATUS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 699
General Power Controller (GPC)

GPC_M4_PU_PGC_PUP_STATUSn field descriptions (continued)

Field Description
8
M4_VPUMIX_PU
P_STATUS
7
M4_GPUMIX_PU
P_STATUS
6
M4_GPU_2D_
PUP_STATUS
5
M4_DDR1_PUP_
STATUS
4 This field is reserved.
-
3
M4_OTG2_PUP_
STATUS
2
M4_OTG1_PUP_
STATUS
1
M4_PCIE_PUP_
STATUS
0
M4_MIPI_PUP_
STATUS

5.2.10.44 CPU PGC software dn trigger status1

(GPC_CPU_PGC_PDN_STATUS1)
CPU_PGC_PDN_STATUS1 is a read only register, represents the results for power DN
software trigger for CPU type PGCs.
The field description is show in table below, the value of “1’b1” represent the software
power DN trigger failed because the relevant PGC is in a power down process. The
relevant bit will be cleared after a success operation of power DN software trigger for
CPU type PGCs.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

700 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Address: 303A_0000h base + 170h offset = 303A_0170h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CORE3_A53_PDN_STATUS

CORE2_A53_PDN_STATUS

CORE1_A53_PDN_STATUS

CORE0_A53_PDN_STATUS
SCU_A53_PDN_REQ

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 701
General Power Controller (GPC)

GPC_CPU_PGC_PDN_STATUS1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4
SCU_A53_PDN_
REQ
3
CORE3_A53_PD
N_STATUS
2
CORE2_A53_PD
N_STATUS
1
CORE1_A53_PD
N_STATUS
0
CORE0_A53_PD
N_STATUS

5.2.10.45 A53 MIX software down trigger status register

(GPC_A53_MIX_PGC_PDN_STATUSn)
A53_MIX_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the
results for power down software trigger from A53 platform to MIX type PGCs.
A53_MIX_PGC_PDN_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.
A53_MIX_PGC_PDN_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power down software trigger for MIX type PGCs.
A53_MIX_PGC_PDN_STATUS2: value of “1’b1” represent the software power up
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

702 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Address: 303A_0000h base + 174h offset + (4d × i), where i=0d to 2d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A53_MIX_PGC_PDN_STATUS
R

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_A53_MIX_PGC_PDN_STATUSn field descriptions

Field Description
31–1 This field is reserved.
- Reserved
0
A53_MIX_PGC_
PDN_STATUS

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 703
General Power Controller (GPC)

5.2.10.46 M4 MIX PGC software power down trigger status register

(GPC_M4_MIX_PGC_PDN_STATUSn)
M4_MIX_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the
results for power down software trigger from M4 platform to MIX type PGCs.
M4_MIX_PGC_PDN_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.
M4_MIX_PGC_PDN_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power down software trigger for MIX type PGCs.
M4_MIX_PGC_PDN_STATUS2: value of “1’b1” represent the software power up
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.
Address: 303A_0000h base + 180h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

704 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M4_MIX_PGC_PDN_STATUS
R

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_M4_MIX_PGC_PDN_STATUSn field descriptions

Field Description
31–1 This field is reserved.
- Reserved
0
M4_MIX_PGC_
PDN_STATUS

5.2.10.47 A53 PU PGC software down trigger status

(GPC_A53_PU_PGC_PDN_STATUSn)
A53_PU_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the
results for power DN software trigger from A53 platform to PU type PGCs.
A53_PU_PGC_PDN_STATUS0: value of “1’b1” represent the software power DN
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.
A53_PU_PGC_PDN_STATUS1: value of “1’b1” represent the software power DN
trigger failed because the relevant PGC is in a power DN process. The relevant bit will be
cleared after a success operation of power DN software trigger for PU type PGCs.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 705
General Power Controller (GPC)

A53_PU_PGC_PDN_STATUS2: value of “1’b1” represent the software power DN

trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.
Address: 303A_0000h base + 18Ch offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

706 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A53_DISPMIX_PDN_STATUS

A53_GPU_3D_PDN_STATUS

A53_GPU_2D_PDN_STATUS
A53_VPU_G2_PDN_STATUS

A53_VPU_G1_PDN_STATUS

A53_GPUMIX_PDN_STATUS
A53_VPU_H1_PDN_STATUS

A53_VPUMIX_PDN_STATUS

A53_DDR1_PDN_STATUS

A53_OTG2_PDN_STATUS

A53_OTG1_PDN_STATUS

A53_PCIE_PDN_STATUS

A53_MIPI_PDN_STATUS
R

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_A53_PU_PGC_PDN_STATUSn field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13
A53_VPU_H1_P
DN_STATUS
12
A53_VPU_G2_P
DN_STATUS
11
A53_VPU_G1_P
DN_STATUS
10
A53_DISPMIX_P
DN_STATUS
9
A53_GPU_3D_P
DN_STATUS

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 707
General Power Controller (GPC)

GPC_A53_PU_PGC_PDN_STATUSn field descriptions (continued)

Field Description
8
A53_VPUMIX_P
DN_STATUS
7
A53_GPUMIX_P
DN_STATUS
6
A53_GPU_2D_
PDN_STATUS
5
A53_DDR1_PDN
_STATUS
4 This field is reserved.
-
3
A53_OTG2_PDN
_STATUS
2
A53_OTG1_PDN
_STATUS
1
A53_PCIE_PDN_
STATUS
0
A53_MIPI_PDN_
STATUS

5.2.10.48 M4 PU PGC software down trigger status

(GPC_M4_PU_PGC_PDN_STATUSn)
M4_PU_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the results
for power DN software trigger from M4 platform to PU type PGCs.
M4_PU_PGC_PDN_STATUS0: value of “1’b1” represent the software power DN
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.
M4_PU_PGC_PDN_STATUS1: value of “1’b1” represent the software power DN
trigger failed because the relevant PGC is in a power DN process. The relevant bit will be
cleared after a success operation of power DN software trigger for PU type PGCs.
M4_PU_PGC_PDN_STATUS2: value of “1’b1” represent the software power DN
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

708 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Address: 303A_0000h base + 198h offset + (4d × i), where i=0d to 2d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M4_DISPMIX_PDN_STATUS

M4_GPU_3D_PDN_STATUS

M4_GPU_2D_PDN_STATUS
M4_VPU_G2_PDN_STATUS

M4_VPU_G1_PDN_STATUS

M4_GPUMIX_PDN_STATUS
M4_VPU_H1_PDN_STATUS

M4_VPUMIX_PDN_STATUS

M4_DDR1_PDN_STATUS

M4_OTG2_PDN_STATUS

M4_OTG1_PDN_STATUS

M4_PCIE_PDN_STATUS

M4_MIPI_PDN_STATUS
R
Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 709
General Power Controller (GPC)

GPC_M4_PU_PGC_PDN_STATUSn field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13
M4_VPU_H1_PD
N_STATUS
12
M4_VPU_G2_PD
N_STATUS
11
M4_VPU_G1_PD
N_STATUS
10
M4_DISPMIX_P
DN_STATUS
9
M4_GPU_3D_PD
N_STATUS
8
M4_VPUMIX_PD
N_STATUS
7
M4_GPUMIX_PD
N_STATUS
6
M4_GPU_2D_
PDN_STATUS
5
M4_DDR1_PDN_
STATUS
4 This field is reserved.
-
3
M4_OTG2_PDN_
STATUS
2
M4_OTG1_PDN_
STATUS
1
M4_PCIE_PDN_
STATUS
0
M4_MIPI_PDN_
STATUS

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

710 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.49 A53 MIX PDN FLG (GPC_A53_MIX_PDN_FLG)

This is flag bit relevant domain control, represents A53 CPU platform wants to power
down MIX PGC. The register can only be accessed by A53 platform.
Address: 303A_0000h base + 1B0h offset = 303A_01B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A53_MIX_PDN_F
R

LAG
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_A53_MIX_PDN_FLG field descriptions

Field Description
31–1 This field is reserved.
- Reserved
0 A53 MIX power-down flag
A53_MIX_PDN_
FLAG

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 711
General Power Controller (GPC)

5.2.10.50 A53 PU PDN FLG (GPC_A53_PU_PDN_FLG)

The register field is show in the table below. The 1’b1 represents A53 CPU platform
wants to power down certain PU PGC. The register is a read only register. The register
bits will be set when corresponding A53 software power down trigger happens and will
be clear when corresponding A53 software power up trigger happens.
Address: 303A_0000h base + 1B4h offset = 303A_01B4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved A53_PU_PDN_FLG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_A53_PU_PDN_FLG field descriptions

Field Description
31–14 This field is reserved.
- Reserved
A53_PU_PDN_ A53 PGC power-down flag
FLG

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

712 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.51 M4 MIX PDN FLG (GPC_M4_MIX_PDN_FLG)

This is flag bit relevant domain control, represents M4 CPU platform wants to power
down MIX PGC. The register can only be accessed by M4 platform.
Address: 303A_0000h base + 1B8h offset = 303A_01B8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M4_MIX_PDN_
R

FLAG
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_M4_MIX_PDN_FLG field descriptions

Field Description
31–1 This field is reserved.
- Reserved
0 M4_MIX power-down flag
M4_MIX_PDN_
FLAG

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 713
General Power Controller (GPC)

5.2.10.52 M4 PU PDN FLG (GPC_M4_PU_PDN_FLG)

The register field is show in the table below. The 1’b1 represents M4 CPU platform
wants to power down certain PU PGC. The register is a read only register. The register
bits will be set when corresponding M4 software power down trigger happens and will be
clear when corresponding M4 software power up trigger happens.
Address: 303A_0000h base + 1BCh offset = 303A_01BCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved M4_PU_PDN_FLG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_M4_PU_PDN_FLG field descriptions

Field Description
31–14 This field is reserved.
- Reserved
M4_PU_PDN_ M4 power-down flag
FLG

5.2.10.53 IRQ masking register 1 of A53 core2

(GPC_IMR1_CORE2_A53)

The four IMRn_CORE2_A53 (n = 1,2,3,4) registers are used as interrupt mask for A53
core2.
Address: 303A_0000h base + 1C0h offset = 303A_01C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR1_CORE2_A53 field descriptions

Field Description
IMR1_CORE2_ A53 core2 IRQ[31:0] masking bits:
A53
0 IRQ not masked
1 IRQ masked

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

714 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.54 IRQ masking register 2 of A53 core2

(GPC_IMR2_CORE2_A53)

Address: 303A_0000h base + 1C4h offset = 303A_01C4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR2_CORE2_A53 field descriptions

Field Description
IMR2_CORE2_ A53 core2 IRQ[63:32] masking bits:
A53
0 IRQ not masked
1 IRQ masked

5.2.10.55 IRQ masking register 3 of A53 core2

(GPC_IMR3_CORE2_A53)

Address: 303A_0000h base + 1C8h offset = 303A_01C8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR3_CORE2_A53 field descriptions

Field Description
IMR3_CORE2_ A53 core2 IRQ[95:64] masking bits:
A53
0 IRQ not masked
1 IRQ masked

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 715
General Power Controller (GPC)

5.2.10.56 IRQ masking register 4 of A53 core2

(GPC_IMR4_CORE2_A53)

Address: 303A_0000h base + 1CCh offset = 303A_01CCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR4_CORE2_A53 field descriptions

Field Description
IMR4_CORE2_ A53 core2 IRQ[127:96] masking bits:
A53
0 IRQ not masked
1 IRQ masked

5.2.10.57 IRQ masking register 1 of A53 core3

(GPC_IMR1_CORE3_A53)

The four IMRn_CORE2_A53 (n = 1,2,3,4) registers are used as interrupt mask for A53
core3.
Address: 303A_0000h base + 1D0h offset = 303A_01D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR1_CORE3_A53 field descriptions

Field Description
IMR1_CORE3_ A53 core3 IRQ[31:0] masking bits:
A53
0 IRQ not masked
1 IRQ masked

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

716 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.10.58 IRQ masking register 2 of A53 core3

(GPC_IMR2_CORE3_A53)

Address: 303A_0000h base + 1D4h offset = 303A_01D4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR2_CORE3_A53 field descriptions

Field Description
IMR2_CORE3_ A53 core3 IRQ[63:32] masking bits:
A53
0 IRQ not masked
1 IRQ masked

5.2.10.59 IRQ masking register 3 of A53 core3

(GPC_IMR3_CORE3_A53)

Address: 303A_0000h base + 1D8h offset = 303A_01D8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR3_CORE3_A53 field descriptions

Field Description
IMR3_CORE3_ A53 core3 IRQ[95:64] masking bits:
A53
0 IRQ not masked
1 IRQ masked

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 717
General Power Controller (GPC)

5.2.10.60 IRQ masking register 4 of A53 core3

(GPC_IMR4_CORE3_A53)

Address: 303A_0000h base + 1DCh offset = 303A_01DCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_IMR4_CORE3_A53 field descriptions

Field Description
IMR4_CORE3_ A53 core3 IRQ[127:96] masking bits:
A53
0 IRQ not masked
1 IRQ masked

5.2.10.61 PGC acknowledge signal selection of A53 platform for PUs

(GPC_ACK_SEL_A53_PU)

Address: 303A_0000h base + 1E0h offset = 303A_01E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPU_3D_PGC_PUP_ACK

GPU_2D_PGC_PUP_ACK
VPU_G2_PGC_PUP_ACK

VPU_G1_PGC_PUP_ACK

GPUMIX_PGC_PUP_ACK
VPU_H1_PGC_PUP_ACK

VPUMIX_PGC_PUP_ACK
DISPMIX_PGC_PUP_AC

USB_OTG2_PGC_PUP_

USB_OTG1_PGC_PUP_
DDR1_PGC_PUP_ACK

PCIE_PGC_PUP_ACK

MIPI_PGC_PUP_ACK

MF_PGC_PUP_ACK
R
Reserved

Reserved
ACK

ACK
K

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

718 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VPU_G2_PGC_PDN_ACK

VPU_G1_PGC_PDN_ACK

GPUMIX_PGC_PDN_ACK
VPUMIX_PGC_PDN_ACK
VPUMIX_H1_PGC_PDN_

DISPMIX_PGC_PDN_AC

GPU_3D_PGC_PDN_AC

GPU_2D_PGC_PDN_AC

USB_OTG2_PGC_PDN_

USB_OTG1_PGC_PDN_
DDR1_PGC_PDN_ACK

PCIE_PGC_PDN_ACK

MIPI_PGC_PDN_ACK

MF_PGC_PDN_ACK
R

Reserved

Reserved
ACK

ACK

ACK
K

K
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ACK_SEL_A53_PU field descriptions

Field Description
31 Select power down acknowledge signal of VPU_H1 PGC as the power up acknowledge for A53 LPM.
VPU_H1_PGC_P
UP_ACK
30 Select power down acknowledge signal of VPU_G2 PGC as the power up acknowledge for A53 LPM.
VPU_G2_PGC_P
UP_ACK
29 Select power down acknowledge signal of VPU_G1 PGC as the power up acknowledge for A53 LPM.
VPU_G1_PGC_P
UP_ACK
28 Select power down acknowledge signal of DISPMIX PGC as the power up acknowledge for A53 LPM.
DISPMIX_PGC_
PUP_ACK
27 Select power down acknowledge signal of GPU_3D PGC as the power up acknowledge for A53 LPM.
GPU_3D_PGC_
PUP_ACK
26 Select power down acknowledge signal of VPUMIX PGC as the power up acknowledge for A53 LPM.
VPUMIX_PGC_P
UP_ACK
25 Select power down acknowledge signal of GPUMIX PGC as the power up acknowledge for A53 LPM.
GPUMIX_PGC_P
UP_ACK
24 Select power down acknowledge signal of GPU_2D PGC as the power up acknowledge for A53 LPM.
GPU_2D_PGC_
PUP_ACK
23 Select power down acknowledge signal of DDR1 PGC as the power up acknowledge for A53 LPM.
DDR1_PGC_
PUP_ACK
22 This field is reserved.
-
21 Select power down acknowledge signal of USB_OTG2 PGC as the power up acknowledge for A53 LPM.
USB_OTG2_
PGC_PUP_ACK
20 Select power down acknowledge signal of USB_OTG1 PGC as the power up acknowledge for A53 LPM.
USB_OTG1_
PGC_PUP_ACK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 719
General Power Controller (GPC)

GPC_ACK_SEL_A53_PU field descriptions (continued)

Field Description
19 Select power down acknowledge signal of PCIE PGC as the power up acknowledge for A53 LPM.
PCIE_PGC_
PUP_ACK
18 Select power down acknowledge signal of MIPI PGC as the power up acknowledge for A53 LPM.
MIPI_PGC_
PUP_ACK
17 This field is reserved.
-
16 Select power down acknowledge signal of MIX PGC as the power up acknowledge for A53 LPM.
MF_PGC_PUP_
ACK
15 Select power down acknowledge signal of VPUMIX_H1 PGC as the power down acknowledge for A53
VPUMIX_H1_PG LPM.
C_PDN_ACK
14 Select power down acknowledge signal of VPU_G2 PGC as the power down acknowledge for A53 LPM.
VPU_G2_PGC_P
DN_ACK
13 Select power down acknowledge signal of VPU_G1 PGC as the power down acknowledge for A53 LPM.
VPU_G1_PGC_P
DN_ACK
12 Select power down acknowledge signal of DISPMIX PGC as the power down acknowledge for A53 LPM.
DISPMIX_PGC_
PDN_ACK
11 Select power down acknowledge signal of GPU_3D PGC as the power down acknowledge for A53 LPM.
GPU_3D_PGC_
PDN_ACK
10 Select power down acknowledge signal of VPUMIX PGC as the power down acknowledge for A53 LPM.
VPUMIX_PGC_P
DN_ACK
9 Select power down acknowledge signal of GPUMIX PGC as the power down acknowledge for A53 LPM.
GPUMIX_PGC_P
DN_ACK
8 Select power down acknowledge signal of GPU_2D PGC as the power down acknowledge for A53 LPM.
GPU_2D_PGC_
PDN_ACK
7 Select power down acknowledge signal of DDR1 PGC as the power down acknowledge for A53 LPM.
DDR1_PGC_
PDN_ACK
6 This field is reserved.
- Reserved
5 Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for A53
USB_OTG2_ LPM.
PGC_PDN_ACK
4 Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for A53
USB_OTG1_ LPM.
PGC_PDN_ACK
3 Select power down acknowledge signal of PCIE PGC as the power down acknowledge for A53 LPM.
PCIE_PGC_
PDN_ACK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

720 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_ACK_SEL_A53_PU field descriptions (continued)

Field Description
2 Select power down acknowledge signal of MIPI PGC as the power down acknowledge for A53 LPM.
MIPI_PGC_
PDN_ACK
1 This field is reserved.
- Reserved
0 Select power down acknowledge signal of MIX PGC as the power down acknowledge for A53 LPM.
MF_PGC_PDN_
ACK

5.2.10.62 PGC acknowledge signal selection of M4 platform for PUs

(GPC_ACK_SEL_M4_PU)

Address: 303A_0000h base + 1E4h offset = 303A_01E4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPU_3D_PGC_PUP_ACK

GPU_2D_PGC_PUP_ACK
VPU_G2_PGC_PUP_ACK

VPU_G1_PGC_PUP_ACK

GPUMIX_PGC_PUP_ACK
VPU_H1_PGC_PUP_ACK

VPUMIX_PGC_PUP_ACK
DISPMIX_PGC_PUP_AC

USB_OTG2_PGC_PUP_

USB_OTG1_PGC_PUP_
DDR1_PGC_PUP_ACK

PCIE_PGC_PUP_ACK

MIPI_PGC_PUP_ACK

MF_PGC_PUP_ACK
R
Reserved

Reserved
ACK

ACK
K

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPU_G2_PGC_PDN_ACK

VPU_G1_PGC_PDN_ACK

GPUMIX_PGC_PDN_ACK
VPU_H1_PGC_PDN_ACK

VPUMIX_PGC_PDN_ACK
DISPMIX_PGC_PDN_AC

GPU_3D_PGC_PDN_AC

GPU_2D_PGC_PDN_AC

USB_OTG2_PGC_PDN_

USB_OTG1_PGC_PDN_
DDR1_PGC_PDN_ACK

PCIE_PGC_PDN_ACK

MIPI_PGC_PDN_ACK

MF_PGC_PDN_ACK
R
Reserved

Reserved
ACK

ACK
K

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_ACK_SEL_M4_PU field descriptions

Field Description
31 Select power down acknowledge signal of VPU_H1 PGC as the power up acknowledge for M4 LPM.
VPU_H1_PGC_P
UP_ACK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 721
General Power Controller (GPC)

GPC_ACK_SEL_M4_PU field descriptions (continued)

Field Description
30 Select power down acknowledge signal of VPU_G2 PGC as the power up acknowledge for M4 LPM.
VPU_G2_PGC_P
UP_ACK
29 Select power down acknowledge signal of VPU_G1 PGC as the power up acknowledge for M4 LPM.
VPU_G1_PGC_P
UP_ACK
28 Select power down acknowledge signal of DISPMIX PGC as the power up acknowledge for M4 LPM.
DISPMIX_PGC_
PUP_ACK
27 Select power down acknowledge signal of GPU_3D PGC as the power up acknowledge for M4 LPM.
GPU_3D_PGC_
PUP_ACK
26 Select power down acknowledge signal of VPUMIX PGC as the power up acknowledge for M4 LPM.
VPUMIX_PGC_P
UP_ACK
25 Select power down acknowledge signal of GPUMIX PGC as the power up acknowledge for M4 LPM.
GPUMIX_PGC_P
UP_ACK
24 Select power down acknowledge signal of GPU_2D PGC as the power up acknowledge for M4 LPM.
GPU_2D_PGC_
PUP_ACK
23 Select power down acknowledge signal of DDR1 PGC as the power up acknowledge for M4 LPM.
DDR1_PGC_
PUP_ACK
22 This field is reserved.
-
21 Select power down acknowledge signal of USB_OTG2 PGC as the power up acknowledge for M4 LPM.
USB_OTG2_
PGC_PUP_ACK
20 Select power down acknowledge signal of USB_OTG1 PGC as the power up acknowledge for M4 LPM.
USB_OTG1_
PGC_PUP_ACK
19 Select power down acknowledge signal of PCIE PGC as the power up acknowledge for M4 LPM.
PCIE_PGC_
PUP_ACK
18 Select power down acknowledge signal of MIPI PGC as the power up acknowledge for M4 LPM.
MIPI_PGC_
PUP_ACK
17 This field is reserved.
-
16 Select power down acknowledge signal of MIX PGC as the power up acknowledge for M4 LPM.
MF_PGC_PUP_
ACK
15 Select power down acknowledge signal of VPU_H1 PGC as the power down acknowledge for M4 LPM.
VPU_H1_PGC_P
DN_ACK
14 Select power down acknowledge signal of VPU_G2 PGC as the power down acknowledge for M4 LPM.
VPU_G2_PGC_P
DN_ACK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

722 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_ACK_SEL_M4_PU field descriptions (continued)

Field Description
13 Select power down acknowledge signal of VPU_G1 PGC as the power down acknowledge for M4 LPM.
VPU_G1_PGC_P
DN_ACK
12 Select power down acknowledge signal of DISPMIX PGC as the power down acknowledge for M4 LPM.
DISPMIX_PGC_
PDN_ACK
11 Select power down acknowledge signal of GPU_3D PGC as the power down acknowledge for M4 LPM.
GPU_3D_PGC_
PDN_ACK
10 Select power down acknowledge signal of VPUMIX PGC as the power down acknowledge for M4 LPM.
VPUMIX_PGC_P
DN_ACK
9 Select power down acknowledge signal of GPUMIX PGC as the power down acknowledge for M4 LPM.
GPUMIX_PGC_P
DN_ACK
8 Select power down acknowledge signal of GPU_2D PGC as the power down acknowledge for M4 LPM.
GPU_2D_PGC_
PDN_ACK
7 Select power down acknowledge signal of DDR1 PGC as the power down acknowledge for M4 LPM.
DDR1_PGC_
PDN_ACK
6 This field is reserved.
-
5 Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for M4
USB_OTG2_ LPM.
PGC_PDN_ACK
4 Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for M4
USB_OTG1_ LPM.
PGC_PDN_ACK
3 Select power down acknowledge signal of PCIE PGC as the power down acknowledge for M4 LPM.
PCIE_PGC_
PDN_ACK
2 Select power down acknowledge signal of MIPI PGC as the power down acknowledge for M4 LPM.
MIPI_PGC_
PDN_ACK
1 This field is reserved.
-
0 Select power down acknowledge signal of MIX PGC as the power down acknowledge for M4 LPM.
MF_PGC_PDN_
ACK

5.2.10.63 Slot configure register for PGC CPUs (GPC_SLTn_CFG)

There are 20 slots in each SLTn_CFG(n = 0~19) that define the power up or power down
behavior of one or more A53 cores, NOC, or SCU PGC in each slot. This array contains
slots 15 to 19, see Memory Map for slots 0 to 14.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 723
General Power Controller (GPC)

In each “SLTn_cfg”, 2 bits (slt_cfg[1:0])are reserved for each PGC:

• 2’b01 (slot controller will power down relevant PGC in corresponding slot if
hardware power down request asserted)
• 2’b10 (slot controller will power up relevant PGC in corresponding slot if hardware
power up request asserted)
• 2’b00 or 2’b11 (not power down or power up behavior in relevant slot)
The specific bits assignment for each PGC is shown in the table below.
PGCx PGCx-1 .. PGC2 PGC1 PGC0
SLT0_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
SLT1_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
: slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
SLTn_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]

Address: 303A_0000h base + 1E8h offset + (4d × i), where i=0d to 4d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORE3_A53_PDN_

CORE2_A53_PDN_

CORE1_A53_PDN_

CORE0_A53_PDN_
CORE3_A53_PUP_

CORE2_A53_PUP_

CORE1_A53_PUP_

CORE0_A53_PUP_
NOC_PDN_SLOT_
NOC_PUP_SLOT_

SCU_PDN_SLOT_
SCU_PUP_SLOT_

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL

SLOT_CONTROL
R
CONTROL

CONTROL

CONTROL

CONTROL

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_SLTn_CFG field descriptions

Field Description
31–12 This field is reserved.
-
11 NOC Power-up slot control
NOC_PUP_
SLOT_
CONTROL

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

724 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_SLTn_CFG field descriptions (continued)

Field Description
10 NOC Power-down slot control
NOC_PDN_
SLOT_
CONTROL
9 SCU Power-up slot control
SCU_PUP_
SLOT_
CONTROL
8 SCU Power-down slot control
SCU_PDN_
SLOT_
CONTROL
7 CORE3 A53 Power-up slot control
CORE3_A53_
PUP_SLOT_
CONTROL
6 CORE3 A53 Power-down slot control
CORE3_A53_
PDN_SLOT_
CONTROL
5 CORE2 A53 Power-up slot control
CORE2_A53_
PUP_SLOT_
CONTROL
4 CORE2 A53 Power-down slot control
CORE2_A53_
PDN_SLOT_
CONTROL
3 CORE1 A53 Power-up slot control
CORE1_A53_
PUP_SLOT_
CONTROL
2 CORE1 A53 Power-down slot control
CORE1_A53_
PDN_SLOT_
CONTROL
1 CORE0 A53 Power-up slot control
CORE0_A53_
PUP_SLOT_
CONTROL
0 CORE0 A53 Power-down slot control
CORE0_A53_
PDN_SLOT_
CONTROL

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 725
726
W
R

Reset
Bit

0
31

0
30

Reserved

0
29
GPC_NOC2GPUMIX_PWRDNACKN

0
General Power Controller (GPC)

28

GPC_GPUMIX2NOC_2D_PWRDNACKN

0
27

GPC_GPUMIX2NOC_3D_PWRDNACKN

0
26

GPC_VPUMIX_PWRDNACKN

0
25

GPC_DISPMIX_PWRDNACKN
Address: 303A_0000h base + 1FCh offset = 303A_01FCh

0
24

GPC_NOC2HSIOMIX_PWRDNACKN

0
23

GPC_HSIOMIX2NOC_PWRDNACKN

0
22

GPC_NOC2SUPERMIX_PWRDNACKN

0
21

GPC_SUPERMIX2NOC_PWRDNACKN

0
20

GPC_NOC2DDR1_PWRDNACKN

0
19

GPC_DDR1_AXI_CACTIVE
5.2.10.64 Power handshake register (GPC_PU_PWRHSK)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

0
18

GPC_DDR1_AXI_CSYSACK

0
17

GPC_DDR1_CORE_CACTIVE

0
16

GPC_DDR1_CORE_CSYSACK

NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPC_NOC2HSIOMIX_ADBS_PWRDNREQN
GPC_GPUPMIX2NOC_2D_PWRDNREQN

GPC_GPUPMIX2NOC_3D_PWRDNREQN
R

GPC_HSIOMIX_ADBS_PWRDNREQN
GPC_NOC2GPUPMIX_PWRDNREQN

GPC_NOC2DDR_PWRDNREQN
GPC_VPUPMIX_PWRDNREQN

GPC_DDR1_CORE_CSYSREQ
GPC_DISPMIX_PWRDNREQN

GPC_DDR1_AXI_CSYSREQ
Reserved

Reserved
Reserved

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

GPC_PU_PWRHSK field descriptions

Field Description
31–30 This field is reserved.
-
29 NOC2GPUMIX ADB400 power down ack. Active 0
GPC_
NOC2GPUMIX_
PWRDNACKN
28 GPUMIX2NOC(2D) ADB400 power down ack. Active 0
GPC_
GPUMIX2NOC_
2D_PWRDNACKN
27 GPUMIX2NOC(3D) ADB400 power down ack. Active 0
GPC_GPUMIX2NO
C_3D_PWRDNACK
N
26 VPU ADB400 power down ack. Active 0
GPC_VPUMIX_
PWRDNACKN
25 DISPMIX ADB400 power down ack. Active 0
GPC_DISPMIX_
PWRDNACKN

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 727
General Power Controller (GPC)

GPC_PU_PWRHSK field descriptions (continued)

Field Description
24 NOC2HSIOMIX ADB400 power down ack. Active 0
GPC_
NOC2HSIOMIX_
PWRDNACKN
23 HSIOMIX2NOC ADB400 power down ack.Active 0
GPC_
HSIOMIX2NOC_
PWRDNACKN
22 NOC2SUPERMIX ADB400 power down ack. Active 0
GPC_
NOC2SUPERMIX_
PWRDNACKN
21 SUPERMIX2NOC ADB400 power down ack. Active 0
GPC_
SUPERMIX2NOC_
PWRDNACKN
20 NOC2DDR ADB400 power down ack. Active 0
GPC_NOC2DDR1_
PWRDNACKN
19 DDR1 AXI Clock Active
GPC_DDR1_AXI_
CACTIVE
18 DDR1 AXI Low-Power Request ack
GPC_DDR1_AXI_
CSYSACK
17 DDR1 controller Hardware Low-Power Clock active
GPC_DDR1_
CORE_CACTIVE
16 DDR1 controller Hardware Low_Power ack
GPC_DDR1_
CORE_CSYSACK
15–12 This field is reserved.
-
11 NOC2GPUMIX ADB400 power down request. Active 0
GPC_
NOC2GPUPMIX_
PWRDNREQN
10 GPUMIX2NOC 2D ADB400 power down request. Active 0
GPC_
GPUPMIX2NOC_
2D_PWRDNREQN
9 GPUMIX2NOC 3D ADB400 power down request. Active 0
GPC_GPUPMIX2N
OC_3D_PWRDNR
EQN
8 VPUPMIX ADB400 power down request. Active 0
GPC_VPUPMIX_
PWRDNREQN

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

728 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PU_PWRHSK field descriptions (continued)

Field Description
7 DISPMIX ADB400 power down request. Active 0
GPC_DISPMIX_
PWRDNREQN
6 NOC2HSIOMIX ADB400 power down request. Active 0
GPC_
NOC2HSIOMIX_
ADBS_
PWRDNREQN
5 HSIOMIX2NOC ADB400 power down request. Active 0
GPC_HSIOMIX_
ADBS_
PWRDNREQN
4 This field is reserved.
-
3 This field is reserved.
-
2 NOC2DDR ADB400 power down request. Active 0
GPC_NOC2DDR_
PWRDNREQN
1 DDR1 AXI Low-Power Request
GPC_DDR1_AXI_
CSYSREQ
0 DDR1 controller Hardware Low-Power Request
GPC_DDR1_
CORE_CSYSREQ

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 729
General Power Controller (GPC)

5.2.10.65 Slot configure register for PGC PUs (GPC_SLTn_CFG_PU)

There are 20 slots in each SLTn_CFG_PU (n = 0~19) that define the power up or power
down behavior of PU PGC in each slot. See PGC power domains section for list of PGC
PUs.
Address: 303A_0000h base + 200h offset + (8d × i), where i=0d to 19d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DISPMIX_PDN_SLOT
DISPMIX_PUP_SLOT

GPU_3D_PDN_SLOT

GPU_2D_PDN_SLOT
VPU_G2_PDN_SLOT

VPU_G1_PDN_SLOT

GPU_3D_PUP_SLOT

GPUMIX_PDN_SLOT

GPU_2D_PUP_SLOT
VPU_H1_PDN_SLOT

VPU_G2_PUP_SLOT

VPU_G1_PUP_SLOT

GPUMIX_PUP_SLOT
VPU_H1_PUP_SLOT

VPUMIX_PDN_SLOT
VPUMIX_PUP_SLOT
R
_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL

_CONTROL
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M4_PUP_SLOT_CON

M4_PDN_SLOT_CO
DDR1_PDN_SLOT_

OTG2_PDN_SLOT_

OTG1_PDN_SLOT_
DDR1_PUP_SLOT_

OTG2_PUP_SLOT_

OTG1_PUP_SLOT_

PCIE_PDN_SLOT_
PCIE_PUP_SLOT_

MIPI_PDN_SLOT_
MIPI_PUP_SLOT_

MF_PDN_SLOT_
MF_PUP_SLOT_
R
CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL
NTROL
TROL

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPC_SLTn_CFG_PU field descriptions

Field Description
31 VPU_H1 Power-up slot control
VPU_H1_PUP_S
LOT_CONTROL
30 VPU_H1 Power-down slot control
VPU_H1_PDN_S
LOT_CONTROL
29 VPU_G2 Power-up slot control
VPU_G2_PUP_S
LOT_CONTROL
28 VPU_G2 Power-down slot control
VPU_G2_PDN_S
LOT_CONTROL
27 VPU_G1 Power-up slot control
VPU_G1_PUP_S
LOT_CONTROL

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

730 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_SLTn_CFG_PU field descriptions (continued)

Field Description
26 VPU_G1 Power-down slot control
VPU_G1_PDN_S
LOT_CONTROL
25 DISPMIX Power-up slot control
DISPMIX_PUP_S
LOT_CONTROL
24 DISPMIX Power-down slot control
DISPMIX_PDN_
SLOT_CONTRO
L
23 GPU_3D Power-up slot control
GPU_3D_PUP_S
LOT_CONTROL
22 GPU_3D Power-down slot control
GPU_3D_PDN_S
LOT_CONTROL
21 VPUMIX Power-up slot control
VPUMIX_PUP_S
LOT_CONTROL
20 VPUMIX Power-down slot control
VPUMIX_PDN_S
LOT_CONTROL
19 GPUMIX Power-up slot control
GPUMIX_PUP_S
LOT_CONTROL
18 GPUMIX Power-down slot control
GPUMIX_PDN_S
LOT_CONTROL
17 GPU_2D Power-up slot control
GPU_2D_PUP_S
LOT_CONTROL
16 GPU_2D Power-down slot control
GPU_2D_PDN_S
LOT_CONTROL
15 DDR1 Power-up slot control
DDR1_PUP_
SLOT_
CONTROL
14 DDR1 Power-down slot control
DDR1_PDN_
SLOT_
CONTROL
13 M4 Power-up slot control
M4_PUP_SLOT_
CONTROL
12 M4 Power-down slot control
M4_PDN_SLOT_
CONTROL

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 731
General Power Controller (GPC)

GPC_SLTn_CFG_PU field descriptions (continued)

Field Description
11–10 This field is reserved.
-
9 OTG2 Power-up slot control
OTG2_PUP_
SLOT_
CONTROL
8 OTG2 Power-down slot control
OTG2_PDN_
SLOT_
CONTROL
7 OTG1 Power-up slot control
OTG1_PUP_
SLOT_
CONTROL
6 OTG1 Power-down slot control
OTG1_PDN_
SLOT_
CONTROL
5 PCIE Power-up slot control
PCIE_PUP_
SLOT_
CONTROL
4 SCU Power-down slot control
PCIE_PDN_
SLOT_
CONTROL
3 MIPI Power-up slot control
MIPI_PUP_
SLOT_
CONTROL
2 MIPI Power-down slot control
MIPI_PDN_
SLOT_
CONTROL
1 MF Power-up slot control
MF_PUP_SLOT_
CONTROL
0 MF Power-down slot control
MF_PDN_SLOT_
CONTROL

5.2.11 GPC PGC Memory Map/Register Definition

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

732 NXP Semiconductors
 Chapter 5 Clocks and Power Management

There are numerous PGC inside GPCv2, with 4 different types: CPU/SCU/MIX/PU.
Each PGC type has 4 different control words PGC_CTRL, PGC_PUPSCR,
PGC_PDNSCR, and PGC_SR. Different PGC types may have different field definition in
these four registers. There is another extra control word PGC_AUXSW for SCU type
PGC.
The total GPC memory map is 4KB
Table 5-11. Memory Regions
Address Range(offset) Region
0x000 - 0x3FF GPC configuration register
0x400 - 0x7FF Reserved
0x800 - 0x9FF CPU and SCU type PGC register base address
0xA00 - 0xBFF MIX type PGC register base address
0xC00 - 0xFFF PU type PGC register base address

Each PGC (CPU type, MIX type, PU type) will occupy 64 Bytes address space, the
specific base address of each PGC are listed as below.
• 0x800 ~ 0x83F: PGC for A53 core0
• 0x840 ~ 0x87F: PGC for A53 core1
• 0x880 ~ 0x8BF: PGC for A53 core2
• 0x8C0 ~ 0x8FF: PGC for A53 core3
• 0x900 ~ 0x93F: PGC for A53 SCU
• 0xA40 ~ 0xA7F: PGC for NOC mix
• 0xC00 ~ 0xC3F: PGC for MIPI PHY (PU0)
• 0xC40 ~ 0xC7F: PGC for PCIE1 PHY (PU1)
• 0xC80 ~ 0xCBF: USB_OTG1 (PU2)
• 0xCC0 ~ 0xCFF: USB_OTG2 (PU3)
• 0xD00 ~ 0xD3F: Reserved (PU4)
• 0xD40 ~ 0xD7F: DDR1 (PU5)
• 0xD80 ~ 0xDBF: GPU_2D (PU6)
• 0xDC0 ~ 0xDFF: GPUMIX (PU7)
• 0xE00 ~ 0xE3F: VPUMIX (PU8)
• 0xE40 ~ 0xE7F: GPU_3D (PU9)
• 0xE80 ~ 0xEBF: DISPMIX (PU10)
• 0xEC0 ~ 0xEFF: VPU_G1 (PU11)
• 0xF00 ~ 0xF3F: VPU_G2 (PU12)
• 0xF40 ~ 0xF7F: VPU_H1 (PU13)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 733
General Power Controller (GPC)

GPC_PGC memory map

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPC PGC Control Register for PGC CPUs 5.2.11.1/
303A_0800 32 R/W 0604_0202h
(GPC_PGC_A53CORE0_CTRL) 738
GPC PGC Up Sequence Control Register 5.2.11.2/
303A_0804 32 R/W 0009_97C1h
(GPC_PGC_A53CORE0_PUPSCR) 740
GPC PGC Down Sequence Control Register 5.2.11.3/
303A_0808 32 R/W 2100_0801h
(GPC_PGC_A53CORE0_PDNSCR) 741
5.2.11.4/
303A_080C GPC PGC Status Register (GPC_PGC_A53CORE0_SR) 32 R/W 0000_1000h
742
GPC PGC Control Register for PGC CPUs 5.2.11.1/
303A_0840 32 R/W 0604_0202h
(GPC_PGC_A53CORE1_CTRL) 738
GPC PGC Up Sequence Control Register 5.2.11.2/
303A_0844 32 R/W 0009_97C1h
(GPC_PGC_A53CORE1_PUPSCR) 740
GPC PGC Down Sequence Control Register 5.2.11.3/
303A_0848 32 R/W 2100_0801h
(GPC_PGC_A53CORE1_PDNSCR) 741
5.2.11.4/
303A_084C GPC PGC Status Register (GPC_PGC_A53CORE1_SR) 32 R/W 0000_1000h
742
GPC PGC Control Register for PGC CPUs 5.2.11.1/
303A_0880 32 R/W 0604_0202h
(GPC_PGC_A53CORE2_CTRL) 738
GPC PGC Up Sequence Control Register 5.2.11.2/
303A_0884 32 R/W 0009_97C1h
(GPC_PGC_A53CORE2_PUPSCR) 740
GPC PGC Down Sequence Control Register 5.2.11.3/
303A_0888 32 R/W 2100_0801h
(GPC_PGC_A53CORE2_PDNSCR) 741
5.2.11.4/
303A_088C GPC PGC Status Register (GPC_PGC_A53CORE2_SR) 32 R/W 0000_1000h
742
GPC PGC Control Register for PGC CPUs 5.2.11.1/
303A_08C0 32 R/W 0604_0202h
(GPC_PGC_A53CORE3_CTRL) 738
GPC PGC Up Sequence Control Register 5.2.11.2/
303A_08C4 32 R/W 0009_97C1h
(GPC_PGC_A53CORE3_PUPSCR) 740
GPC PGC Down Sequence Control Register 5.2.11.3/
303A_08C8 32 R/W 2100_0801h
(GPC_PGC_A53CORE3_PDNSCR) 741
5.2.11.4/
303A_08CC GPC PGC Status Register (GPC_PGC_A53CORE3_SR) 32 R/W 0000_1000h
742
GPC PGC Control Register for PGC CPUs 5.2.11.1/
303A_0900 32 R/W 0604_0202h
(GPC_PGC_A53SCU_CTRL) 738
GPC PGC Up Sequence Control Register 5.2.11.2/
303A_0904 32 R/W 0009_97C1h
(GPC_PGC_A53SCU_PUPSCR) 740
GPC PGC Down Sequence Control Register 5.2.11.3/
303A_0908 32 R/W 2100_0801h
(GPC_PGC_A53SCU_PDNSCR) 741
5.2.11.4/
303A_090C GPC PGC Status Register (GPC_PGC_A53SCU_SR) 32 R/W 0000_1000h
742
GPC PGC Auxiliary Power Switch Control Register 5.2.11.5/
303A_0910 32 R/W 0000_0131h
(GPC_PGC_A53SCU_AUXSW) 744
GPC PGC Control Register for PGC MIX. 5.2.11.6/
303A_0A40 32 R/W 0604_0202h
(GPC_PGC_NOC_MIX_CTRL) 745
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

734 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PGC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPC PGC Up Sequence Control Register 5.2.11.7/
303A_0A44 32 R/W 0009_97C1h
(GPC_PGC_NOC_MIX_PUPSCR) 747
GPC PGC Down Sequence Control Register 5.2.11.8/
303A_0A48 32 R/W 2100_0801h
(GPC_PGC_NOC_MIX_PDNSCR) 748
5.2.11.9/
303A_0A4C GPC PGC Status Register (GPC_PGC_NOC_MIX_SR) 32 R/W 0000_1000h
749
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0C00 32 R/W 0604_0202h
(GPC_PGC_PU0_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0C04 32 R/W 0009_97C1h
(GPC_PGC_PU0_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0C08 32 R/W 2100_0801h
(GPC_PGC_PU0_PDNSCR) 755
5.2.11.13/
303A_0C0C GPC PGC Status Register (GPC_PGC_PU0_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0C40 32 R/W 0604_0202h
(GPC_PGC_PU1_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0C44 32 R/W 0009_97C1h
(GPC_PGC_PU1_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0C48 32 R/W 2100_0801h
(GPC_PGC_PU1_PDNSCR) 755
5.2.11.13/
303A_0C4C GPC PGC Status Register (GPC_PGC_PU1_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0C80 32 R/W 0604_0202h
(GPC_PGC_PU2_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0C84 32 R/W 0009_97C1h
(GPC_PGC_PU2_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0C88 32 R/W 2100_0801h
(GPC_PGC_PU2_PDNSCR) 755
5.2.11.13/
303A_0C8C GPC PGC Status Register (GPC_PGC_PU2_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0CC0 32 R/W 0604_0202h
(GPC_PGC_PU3_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0CC4 32 R/W 0009_97C1h
(GPC_PGC_PU3_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0CC8 32 R/W 2100_0801h
(GPC_PGC_PU3_PDNSCR) 755
5.2.11.13/
303A_0CCC GPC PGC Status Register (GPC_PGC_PU3_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0D00 32 R/W 0604_0202h
(GPC_PGC_PU4_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0D04 32 R/W 0009_97C1h
(GPC_PGC_PU4_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0D08 32 R/W 2100_0801h
(GPC_PGC_PU4_PDNSCR) 755
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 735
General Power Controller (GPC)

GPC_PGC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.2.11.13/
303A_0D0C GPC PGC Status Register (GPC_PGC_PU4_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0D40 32 R/W 0604_0202h
(GPC_PGC_PU5_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0D44 32 R/W 0009_97C1h
(GPC_PGC_PU5_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0D48 32 R/W 2100_0801h
(GPC_PGC_PU5_PDNSCR) 755
5.2.11.13/
303A_0D4C GPC PGC Status Register (GPC_PGC_PU5_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0D80 32 R/W 0604_0202h
(GPC_PGC_PU6_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0D84 32 R/W 0009_97C1h
(GPC_PGC_PU6_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0D88 32 R/W 2100_0801h
(GPC_PGC_PU6_PDNSCR) 755
5.2.11.13/
303A_0D8C GPC PGC Status Register (GPC_PGC_PU6_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0DC0 32 R/W 0604_0202h
(GPC_PGC_PU7_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0DC4 32 R/W 0009_97C1h
(GPC_PGC_PU7_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0DC8 32 R/W 2100_0801h
(GPC_PGC_PU7_PDNSCR) 755
5.2.11.13/
303A_0DCC GPC PGC Status Register (GPC_PGC_PU7_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0E00 32 R/W 0604_0202h
(GPC_PGC_PU8_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0E04 32 R/W 0009_97C1h
(GPC_PGC_PU8_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0E08 32 R/W 2100_0801h
(GPC_PGC_PU8_PDNSCR) 755
5.2.11.13/
303A_0E0C GPC PGC Status Register (GPC_PGC_PU8_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0E40 32 R/W 0604_0202h
(GPC_PGC_PU9_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0E44 32 R/W 0009_97C1h
(GPC_PGC_PU9_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0E48 32 R/W 2100_0801h
(GPC_PGC_PU9_PDNSCR) 755
5.2.11.13/
303A_0E4C GPC PGC Status Register (GPC_PGC_PU9_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0E80 32 R/W 0604_0202h
(GPC_PGC_PU10_CTRL) 752
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

736 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PGC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0E84 32 R/W 0009_97C1h
(GPC_PGC_PU10_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0E88 32 R/W 2100_0801h
(GPC_PGC_PU10_PDNSCR) 755
5.2.11.13/
303A_0E8C GPC PGC Status Register (GPC_PGC_PU10_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0EC0 32 R/W 0604_0202h
(GPC_PGC_PU11_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0EC4 32 R/W 0009_97C1h
(GPC_PGC_PU11_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0EC8 32 R/W 2100_0801h
(GPC_PGC_PU11_PDNSCR) 755
5.2.11.13/
303A_0ECC GPC PGC Status Register (GPC_PGC_PU11_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0F00 32 R/W 0604_0202h
(GPC_PGC_PU12_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0F04 32 R/W 0009_97C1h
(GPC_PGC_PU12_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0F08 32 R/W 2100_0801h
(GPC_PGC_PU12_PDNSCR) 755
5.2.11.13/
303A_0F0C GPC PGC Status Register (GPC_PGC_PU12_SR) 32 R/W 0000_1000h
756
GPC PGC Control Register for PGC PUs 5.2.11.10/
303A_0F40 32 R/W 0604_0202h
(GPC_PGC_PU13_CTRL) 752
GPC PGC Up Sequence Control Register 5.2.11.11/
303A_0F44 32 R/W 0009_97C1h
(GPC_PGC_PU13_PUPSCR) 754
GPC PGC Down Sequence Control Register 5.2.11.12/
303A_0F48 32 R/W 2100_0801h
(GPC_PGC_PU13_PDNSCR) 755
5.2.11.13/
303A_0F4C GPC PGC Status Register (GPC_PGC_PU13_SR) 32 R/W 0000_1000h
756

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 737
General Power Controller (GPC)

5.2.11.1 GPC PGC Control Register for PGC CPUs

(GPC_PGC_nCTRL)

GPC PGC Control Register for the PGC CPUs. See the PGC Memory Map for the
assignments.
Address: 303A_0000h base + 800h offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved MEMPWR_TCD1_TDR_TRM Reserved L2RETN_TCD1_TDR

Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved DFTRAM_TCD1 L2RSTDIS PCR

Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

GPC_PGC_nCTRL field descriptions

Field Description
31–30 This field is reserved.
- Reserved
29–24
MEMPWR_ After scu pdn_req, count this value to assert A53 mempwr to 1’b1
TCD1_TDR_
TRM NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)

23–22 This field is reserved.

- Reserved
21–16
L2RETN_TCD1_ After scu pdn_req, count this value to assert A53 l2retn to 1’b0
TDR
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
15–14 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

738 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PGC_nCTRL field descriptions (continued)

Field Description
13–8
DFTRAM_TCD1 After scu pdn_req, count this value to assert A53 dftram to 1’b1

NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–1
L2RSTDIS After scu pdn_req, count this value to assert A53 l2rstdis to 1’b1, it will be clear automatically once any of
A53 core0/core1/core2/core3 is wakeup

NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
0
PCR Power Control

NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.

0 Do not switch off power even if pdn_req is asserted.

1 Switch off power when pdn_req is asserted.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 739
General Power Controller (GPC)

5.2.11.2 GPC PGC Up Sequence Control Register

(GPC_PGC_nPUPSCR)

GPC PGC Up Sequence Control Register

Address: 303A_0000h base + 804h offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SW2ISO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

SW2ISO SW

Reset 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1

GPC_PGC_nPUPSCR field descriptions

Field Description
31–23 This field is reserved.
- Reserved
22–7 After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating
SW2ISO isolation.
6 This field is reserved.
- Reserved
SW
After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW
before asserting switch_b

NOTE: SW must not be programmed to zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

740 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.11.3 GPC PGC Down Sequence Control Register

(GPC_PGC_nPDNSCR)

GPC PGC Down Sequence Control Register

Address: 303A_0000h base + 808h offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ISO2SW Reserved ISO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1

GPC_PGC_nPDNSCR field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13–8
ISO2SW After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO2SW before negating switch_b

NOTE: ISO2SW must not be programmed to zero.

7–6 This field is reserved.
- Reserved
ISO
After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO before asserting isolation

NOTE: ISO must not be programmed to zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 741
General Power Controller (GPC)

5.2.11.4 GPC PGC Status Register (GPC_PGC_nSR)

GPC PGC Status Register

Address: 303A_0000h base + 80Ch offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

L2RSTDIS_
Reserved DEASSERT_
CNT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

742 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

L2RETN_FLAG
ALLOFF_FLAG
R PSR

Reserved
L2RSTDIS_DEASSERT_CNT PUP_CLK_DIV_SEL

Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

GPC_PGC_nSR field descriptions

Field Description
31–18 This field is reserved.
- Reserved
17–8
L2RSTDIS_ Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up
DEASSERT_
CNT NOTE: This value can’t be programmed to zero (This register control only for SCU Type PGC)

7 This field is reserved.

- Reserved
6–3 Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC,
PUP_CLK_DIV_ ipg_clk(66MHz) for MIX/PU Type PGC)
SEL
0000 1
0001 1/2 count_clk
0010 1/4 count_clk
0011 1/8 count_clk
0100 1/16 count_clk
0101 1/32 count_clk
0110 1/64 count_clk
0111 1/128 count_clk
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 743
General Power Controller (GPC)

GPC_PGC_nSR field descriptions (continued)

Field Description
1000 1/256 count_clk
1001 1/512 count_clk
1010 1/1024 count_clk
1011 1/2056 count_clk
1100 1/4096 count_clk
1101 1/8192 count_clk
1110 1/16384 count_clk
1111 1/32768 count_clk
2
ALLOFF_FLAG All-off flag.

NOTE: Software should write “1” to clear this flag after A53 is wakeup from ALL_OFF mode, otherwise, it
will always keep to 1 (This register control only for SCU Type PGC)

0 A53 is not wakeup from ALL_OFF mode.

1 A53 is wakeup from ALL_OFF mode.
1
L2RETN_FLAG L2 Retention Flag

NOTE: Software should write “1” to clear this flag after A53 is wakeup from L2 retention mode, otherwise
it will always keep to 1 (This register control only for SCU Type PGC)

0 A53 is not wakeup from L2 retention mode.

1 A53 is wakeup from L2 retention mode.
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one. Write one to clear this bit. Software should
clear this bit after power up; otherwise, PSR continues to reflect the power status of the initial power down.

0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.

5.2.11.5 GPC PGC Auxiliary Power Switch Control Register

(GPC_PGC_A53SCU_AUXSW)

GPC PGC Auxiliary Power Switch Control Register.

Address: 303A_0000h base + 910h offset = 303A_0910h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved MEMPWR_TRC1_TMC L2RETN_RTC1_TMC_TMR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
L2RETN_RTC1_TMC_TMR DFTRAM_TRC1_TMC_TMR_TCD2
Reset 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

744 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PGC_A53SCU_AUXSW field descriptions

Field Description
31–30 This field is reserved.
- Reserved
29–20 After scu starts pup reset, count this value to assert a53 l2 memory switch to 1’b0.
MEMPWR_
TRC1_TMC
19–10 After scu starts pup reset, count this value to assert a53 l2 memory retention to 1’b1.
L2RETN_RTC1_
TMC_TMR
DFTRAM_TRC1_ After scu starts pup reset, count this value to assert a53 l2 memory dftram to 1’b0.
TMC_TMR_
TCD2

5.2.11.6 GPC PGC Control Register for PGC MIX.

(GPC_PGC_NOC_MIX_CTRL)

GPC PGC Control Register.

Address: 303A_0000h base + A40h offset = 303A_0A40h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved MEMPWR_TCD1_TDR_TRM Reserved L2RETN_TCD1_TDR

Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

MIX_
Reserved DFTRAM_TCD1 L2RSTDIS
PCR

Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 745
General Power Controller (GPC)

GPC_PGC_NOC_MIX_CTRL field descriptions

Field Description
31–30 This field is reserved.
- Reserved
29–24
MEMPWR_ After scu pdn_req, count this value to assert A53 mempwr to 1’b1
TCD1_TDR_
TRM NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)

23–22 This field is reserved.

- Reserved
21–16
L2RETN_TCD1_ After scu pdn_req, count this value to assert A53 l2retn to 1’b0
TDR
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
15–14 This field is reserved.
- Reserved
13–8
DFTRAM_TCD1 After scu pdn_req, count this value to assert A53 dftram to 1’b1

NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–1
L2RSTDIS After scu pdn_req, count this value to assert A53 l2rstdis to 1’b1, it will be clear automatically once any of
A53 core0/core1/core2/core3 is wakeup

NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
0
MIX_PCR Power Control

NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.

0 Do not switch off power even if pdn_req is asserted.

1 Switch off power when pdn_req is asserted.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

746 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.11.7 GPC PGC Up Sequence Control Register

(GPC_PGC_NOC_MIX_PUPSCR)

GPC PGC Up Sequence Control Register

Address: 303A_0000h base + A44h offset = 303A_0A44h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SW2ISO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SCALL_OUT
SW2ISO PUP_WAIT_ Reserved

Reset 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1

GPC_PGC_NOC_MIX_PUPSCR field descriptions

Field Description
31–23 This field is reserved.
- Reserved
22–7 After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating
SW2ISO isolation.
6 After SCALL asserting to 1’b0, wait handshake signal SCALL_OUT to return to 1’b0 (This register control
PUP_WAIT_ only for MIX Type PGC)
SCALL_OUT
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 747
General Power Controller (GPC)

5.2.11.8 GPC PGC Down Sequence Control Register

(GPC_PGC_NOC_MIX_PDNSCR)

GPC PGC Down Sequence Control Register

Address: 303A_0000h base + A48h offset = 303A_0A48h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ISO2SW Reserved ISO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1

GPC_PGC_NOC_MIX_PDNSCR field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13–8
ISO2SW After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO2SW before negating switch_b

NOTE: ISO2SW must not be programmed to zero.

7–6 This field is reserved.
- Reserved
ISO
After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO before asserting isolation

NOTE: ISO must not be programmed to zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

748 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.11.9 GPC PGC Status Register (GPC_PGC_NOC_MIX_SR)

GPC PGC Status Register

Address: 303A_0000h base + A4Ch offset = 303A_0A4Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

L2RSTDIS_
Reserved DEASSERT_
CNT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 749
General Power Controller (GPC)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

L2RETN_FLAG
ALLOFF_FLAG
R PSR

Reserved
L2RSTDIS_DEASSERT_CNT PUP_CLK_DIV_SEL

Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

GPC_PGC_NOC_MIX_SR field descriptions

Field Description
31–18 This field is reserved.
- Reserved
17–8
L2RSTDIS_ Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up
DEASSERT_
CNT NOTE: This value can’t be programmed to zero (This register control only for SCU Type PGC)

7 This field is reserved.

- Reserved
6–3 Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC,
PUP_CLK_DIV_ ipg_clk(66MHz) for MIX/PU Type PGC)
SEL
0000 1
0001 1/2 count_clk
0010 1/4 count_clk
0011 1/8 count_clk
0100 1/16 count_clk
0101 1/32 count_clk
0110 1/64 count_clk
0111 1/128 count_clk
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

750 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PGC_NOC_MIX_SR field descriptions (continued)

Field Description
1000 1/256 count_clk
1001 1/512 count_clk
1010 1/1024 count_clk
1011 1/2056 count_clk
1100 1/4096 count_clk
1101 1/8192 count_clk
1110 1/16384 count_clk
1111 1/32768 count_clk
2
ALLOFF_FLAG All-off flag.

NOTE: Software should write “1” to clear this flag after A53 is wakeup from ALL_OFF mode, otherwise, it
will always keep to 1 (This register control only for SCU Type PGC)

0 A53 is not wakeup from ALL_OFF mode.

1 A53 is wakeup from ALL_OFF mode.
1
L2RETN_FLAG L2 Retention Flag

NOTE: Software should write “1” to clear this flag after A53 is wakeup from L2 retention mode, otherwise
it will always keep to 1 (This register control only for SCU Type PGC)

0 A53 is not wakeup from L2 retention mode.

1 A53 is wakeup from L2 retention mode.
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one. Write one to clear this bit. Software should
clear this bit after power up; otherwise, PSR continues to reflect the power status of the initial power down.

0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 751
General Power Controller (GPC)

5.2.11.10 GPC PGC Control Register for PGC PUs

(GPC_PGC_nCTRL)

GPC PGC Control Register for the PUs. See the PGC Memory Map for the assignments.
Address: 303A_0000h base + C00h offset + (64d × i), where i=0d to 13d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved MEMPWR_TCD1_TDR_TRM Reserved L2RETN_TCD1_TDR

Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved DFTRAM_TCD1 L2RSTDIS PCR

Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

GPC_PGC_nCTRL field descriptions

Field Description
31–30 This field is reserved.
- Reserved
29–24
MEMPWR_ After scu pdn_req, count this value to assert A53 mempwr to 1’b1
TCD1_TDR_
TRM NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)

23–22 This field is reserved.

- Reserved
21–16
L2RETN_TCD1_ After scu pdn_req, count this value to assert A53 l2retn to 1’b0
TDR
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
15–14 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

752 NXP Semiconductors
 Chapter 5 Clocks and Power Management

GPC_PGC_nCTRL field descriptions (continued)

Field Description
13–8
DFTRAM_TCD1 After scu pdn_req, count this value to assert A53 dftram to 1’b1

NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–1
L2RSTDIS After scu pdn_req, count this value to assert A53 l2rstdis to 1’b1, it will be clear automatically once any of
A53 core0/core1/core2/core3 is wakeup

NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
0
PCR Power Control

NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.

0 Do not switch off power even if pdn_req is asserted.

1 Switch off power when pdn_req is asserted.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 753
General Power Controller (GPC)

5.2.11.11 GPC PGC Up Sequence Control Register

(GPC_PGC_nPUPSCR)

GPC PGC Up Sequence Control Register

Address: 303A_0000h base + C04h offset + (64d × i), where i=0d to 13d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SW2ISO

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

SW2ISO SW

Reset 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1

GPC_PGC_nPUPSCR field descriptions

Field Description
31–23 This field is reserved.
- Reserved
22–7 After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating
SW2ISO isolation.
6 This field is reserved.
- Reserved
SW
After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW
before asserting switch_b

NOTE: SW must not be programmed to zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

754 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.2.11.12 GPC PGC Down Sequence Control Register

(GPC_PGC_nPDNSCR)

GPC PGC Down Sequence Control Register

Address: 303A_0000h base + C08h offset + (64d × i), where i=0d to 13d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ISO2SW Reserved ISO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1

GPC_PGC_nPDNSCR field descriptions

Field Description
31–14 This field is reserved.
- Reserved
13–8
ISO2SW After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO2SW before negating switch_b

NOTE: ISO2SW must not be programmed to zero.

7–6 This field is reserved.
- Reserved
ISO
After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO before asserting isolation

NOTE: ISO must not be programmed to zero.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 755
General Power Controller (GPC)

5.2.11.13 GPC PGC Status Register (GPC_PGC_nSR)

GPC PGC Status Register

Address: 303A_0000h base + C0Ch offset + (64d × i), where i=0d to 13d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

L2RSTDIS_
Reserved DEASSERT_
CNT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

756 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

L2RETN_FLAG
ALLOFF_FLAG
R PSR

Reserved
L2RSTDIS_DEASSERT_CNT PUP_CLK_DIV_SEL

Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

GPC_PGC_nSR field descriptions

Field Description
31–18 This field is reserved.
- Reserved
17–8
L2RSTDIS_ Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up
DEASSERT_
CNT NOTE: This value can’t be programmed to zero (This register control only for SCU Type PGC)

7 This field is reserved.

- Reserved
6–3 Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC,
PUP_CLK_DIV_ ipg_clk(66MHz) for MIX/PU Type PGC)
SEL
0000 1
0001 1/2 count_clk
0010 1/4 count_clk
0011 1/8 count_clk
0100 1/16 count_clk
0101 1/32 count_clk
0110 1/64 count_clk
0111 1/128 count_clk
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 757
Crystal Oscillator (XTALOSC)

GPC_PGC_nSR field descriptions (continued)

Field Description
1000 1/256 count_clk
1001 1/512 count_clk
1010 1/1024 count_clk
1011 1/2056 count_clk
1100 1/4096 count_clk
1101 1/8192 count_clk
1110 1/16384 count_clk
1111 1/32768 count_clk
2
ALLOFF_FLAG All-off flag.

NOTE: Software should write “1” to clear this flag after A53 is wakeup from ALL_OFF mode, otherwise, it
will always keep to 1 (This register control only for SCU Type PGC)

0 A53 is not wakeup from ALL_OFF mode.

1 A53 is wakeup from ALL_OFF mode.
1
L2RETN_FLAG L2 Retention Flag

NOTE: Software should write “1” to clear this flag after A53 is wakeup from L2 retention mode, otherwise
it will always keep to 1 (This register control only for SCU Type PGC)

0 A53 is not wakeup from L2 retention mode.

1 A53 is wakeup from L2 retention mode.
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one. Write one to clear this bit. Software should
clear this bit after power up; otherwise, PSR continues to reflect the power status of the initial power down.

0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.

5.3 Crystal Oscillator (XTALOSC)

5.3.1 Overview
The chip has two XTAL modules, 24MHz XTAL module and 32KHz XTAL module.
The 24MHz XTAL module is instantiated from the XTAL IP, which includes:
• 24MHz crystal oscillator to generate reference clock
• Digital control logics for the XTAL
The 32KHz XTAL module uses a different IP and it is used as the clock source for the
RTC, located in the SNVS.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

758 NXP Semiconductors
 Chapter 5 Clocks and Power Management

The 24MHz oscillator will be used as the primary clock source for the PLLs to generate
the clock for CPU, BUS, and high-speed interfaces. For all PLLs, the 24MHz clock from
the oscillator can be used as the PLL reference clock directly.
The OSC IP used by the 24MHz XTAL module has three modes, Internal clock
generation mode, External clock receive mode and Retention mode. The figure below
shows the OSC IP integration diagram:

OSC IP

+
–

Internal
Circuitry

PADI PADO
On chip

Rs
Rfb

CL1 CL2

Figure 5-17. OSC IP Integration Diagram

During internal clock generation mode, a suitable quartz crystal is connected between
PADI and PADO to generate the clock signal at the CK pin.
During external clock generation mode, the cell acts like a buffer, reflecting the PADI
signal at CK.
The RTO (retention enable) signal retains the previous state of all the core input control
signals. Logic at the RTO signal enables the retention operation.
Each XTAL module supports the following modes through register configuration:
• Normal oscillator mode - In normal mode, the XTAL IP generates stable square
wave based on the crystal oscillator input.
• Bypass mode - In bypass mode, an external clock can be input through the XTAL
pad.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 759
XTALOSC Memory Map/Register Definition

5.3.2 XTALOSC Memory Map/Register Definition

XTALOSC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
OSC Normal Clock Generation Control Register0 5.3.2.1/
3027_0000 32 R/W 0000_0000h
(XTALOSC_SYS_OSCNML_CTL0) 760
OSC Normal Clock Generation Control Register1 5.3.2.2/
3027_0004 32 R/W 0000_0000h
(XTALOSC_SYS_OSCNML_CTL1) 761

5.3.2.1 OSC Normal Clock Generation Control Register0

(XTALOSC_SYS_OSCNML_CTL0)

OSC Normal Clock Generation Control Register0

Address: 3027_0000h base + 0h offset = 3027_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EN Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved RTO SP SF1 SF0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

760 NXP Semiconductors
 Chapter 5 Clocks and Power Management

XTALOSC_SYS_OSCNML_CTL0 field descriptions

Field Description
31 Enable Oscillator
EN
30–5 This field is reserved.
- Reserved
4 Retention Enable
RTO
3 This field is reserved.
- Reserved
2 Select Power
SP
1 Select Frequency1
SF1
0 Select Frequency0
SF0

5.3.2.2 OSC Normal Clock Generation Control Register1

(XTALOSC_SYS_OSCNML_CTL1)

OSC Normal Clock Generation Control Register1

Address: 3027_0000h base + 4h offset = 3027_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_CKE_OVERRIDE

R
CLK_CKE
Reserved

Reserved

Reserved LOCK_COUNT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 761
Thermal Monitoring Unit (TMU)

XTALOSC_SYS_OSCNML_CTL1 field descriptions

Field Description
31–12 This field is reserved.
- Reserved
11–4 Lock Signal Gen Counter
LOCK_COUNT
3 This field is reserved.
- Reserved
2 Oscillator Clock Gating Enable
CLK_CKE
1 Oscillator Clock Gating Enable Override
CLK_CKE_
OVERRIDE
0 This field is reserved.
- Reserved

5.4 Thermal Monitoring Unit (TMU)

5.4.1 Overview
The chip uses a temperature sensor to monitor the die temperature. The temperature
sensor has a digitizer and local probe, and has the resolution of 1°C.

5.4.2 Features
• Junction temperature sensor function
• 1°C of sensing resolution
• 8-bit output codes with software calibration

5.4.3 Block Diagram

The TMU consists of a reference generation block, a positive TC voltage generator and a
digitizer to convert the sensed voltage to 8-bit output codes.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

762 NXP Semiconductors
 Chapter 5 Clocks and Power Management

OSC 24MHz TMU

clock LPCG

Timing Control FSM

IPS BUS REGISTERS Calibration T_SENSOR

Monitoring

Interrupt Gen

Interrupts

Figure 5-18. Block Diagram

5.4.4 Timing control FSM

The finite-state machine below describes the 8-bit clock input flow.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 763
Thermal Monitoring Unit (TMU)

DISABLE SNESOR

IDLE START

GET_RESULT RESET

CLK0_SENSE CLK7_SENSE

CLK1_SENSE CLK6_SENSE

CLK2_SENSE CLK5_SENSE

CLK3_SENSE CLK4_SENSE

Figure 5-19. Timing Control FSM Diagram

5.4.5 Temperature Sensor Error Correction Method

The following figure shows an example of the difference between a reference curve and a
real measured curve. The reference curve is based on ideal output codes vs. temperature,
and the real measured curve is a waveform with process and mismatch error terms to the
reference curve. There is DC offset between the real measured curve and the reference
curve. In order to correct the error term, the temperature sensor uses software calibration
method.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

764 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Figure 5-20. Reference Curve vs. Real Measured Curve

The software calibration method works as follows.

First, the temperature sensor senses die temperature at 25°C, and then 8-bit output codes
are stored in the 8-bit OTP cells. With 8-bit data stored in OTP cells, the logic block
(from the outside of the temperature sensor) is able to compensate DC offset.
Below equation shows the 1-point calibration method at 25°C.

Next equation shows the 1-point calibration method at 85°C.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 765
Thermal Monitoring Unit (TMU)

where Tsense is the real measured output code including the DC offset, Tcalib is the
calibrated output code of Tsense, TE1 (TE2) is the stored code in the first 8-bit OTP cell
at 25°C (85°C) , and T25 (T85) is the ideal output code at 25°C (85°C). In other words,
the DC offset is the difference between TE1 and T25. When the above equation is
programmed in the glue logic block, the calibrated data is simply obtained by applying
measured Tsense value.
Next equation shows the 2-point calibration method.

where TE1 and TE2 are the temperature values stored in the 8-bit OTP cells from the
25°C and 85°C measurement, respectively. Units of all terms are degree (°C).
According to the above equation, (TE1 – 25) represents DC offset term and

represents slope compensation term. DC offset is simply difference between 25°C and
TE1. Slope compensation term is reciprocal of temperature slope, (85 – 25)/(TE2 – TE1)
times (Tsense – TE1). To obtain calibrated data, TE1 is added to slope compensation
term for the slope error correction and DC offset tem is finally subtracted. If the above
equation is programmed in the software, the calibrated data is simply obtained by
applying measured Tsense value.
By using software slope calibration, it is possible to control a temperature slope of Tcalib.
The software calibration method is below.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

766 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.4.6 Temperature Result Process

When the new sensor result is received, hardware will do 1 point calibration (software
can do 2 points calibration). The calculated results and temperature value will then be
transferred to registers, based on the calibration result and sensor-temperature mapping
relationship. The hardware monitor checks the result effectiveness every time it gets the
new sensor result. Hardware can also generate a normal interrupt or critical interrupt to
the system when one of the three sensors reports a temperature value higher than the
threshold value programmed in the registers

5.4.7 TMU Memory Map/Register Definition

This section provides a detailed description of all accessible TMU memory and registers.
The table below lists the TMU registers. Note that the full register address is comprised
of the programmable CCSRBAR together with the offset listed.
NOTE
The EN bit field of the TMU Enable Register (TMU_TER[EN])
must always be enabled for the part to operate correctly.
TMU memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.4.7.1/
3026_0000 TMU Enable Register (TMU_TER) 32 R/W 0000_0001h
768
5.4.7.2/
3026_0004 TMU Status register (TMU_TSR) 32 R 0000_0000h
769
5.4.7.3/
3026_0008 TMU Interrupt Enable register (TMU_TIER) 32 R/W 0000_0000h
770
5.4.7.4/
3026_000C TMU Interrupt Detect register (TMU_TIDR) 32 w1c 0000_0000h
771
TMU Monitor High Temperature Immediate Threshold 5.4.7.5/
3026_0010 32 R/W 0000_0000h
register (TMU_TMHTITR) 772
TMU Monitor High Temperature Average threshold register 5.4.7.6/
3026_0014 32 R/W 0000_0000h
(TMU_TMHTATR) 773
TMU Monitor High Temperature Average Critical Threshold 5.4.7.7/
3026_0018 32 R/W 0000_0000h
register (TMU_TMHTACTR) 774
5.4.7.8/
3026_001C TMU Sensor Calibration register (TMU_TSCR) 32 R 0000_0000h
774
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 767
TMU Memory Map/Register Definition

TMU memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TMU Report Immediate Temperature Site register n 5.4.7.9/
3026_0020 32 R 0000_0000h
(TMU_TRITSR) 775
TMU Report Average Temperature Site register n 5.4.7.10/
3026_0024 32 R 0000_0000h
(TMU_TRATSR) 776

5.4.7.1 TMU Enable Register (TMU_TER)

Address: 3026_0000h base + 0h offset = 3026_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
EN Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ALPF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

TMU_TER field descriptions

Field Description
31 Enable monitoring the temperature sensor
EN
NOTE: The POR value is disabled, but is enabled in boot. To ensure proper operation, this field must be
enabled.

0 No monitoring
1 Enable monitoring
30–2 This field is reserved.
- Reserved
ALPF Average low pass filter setting.
The average temperature is calculated as: ALPF x Current_Temp + (1 - ALPF) x Average_Temp. If no
previous (average) temperature is valid, current temperature is used. For proper operation, this field
should only change when monitoring is disabled.

00 1.0
01 0.5
10 0.25
11 0.125

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

768 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.4.7.2 TMU Status register (TMU_TSR)

The TMU status register reports the monitoring status during operation.
Address: 3026_0000h base + 4h offset = 3026_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R TB
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TSR field descriptions

Field Description
31 TMU busy.
TB
0 TMU idle.
1 TMU busy. In monitoring mode this indicates a temperature measurement is pending. In calibration
mode, sensor result has not yet been determined based on last given ambient temperature.
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 769
TMU Memory Map/Register Definition

5.4.7.3 TMU Interrupt Enable register (TMU_TIER)

The TMU interrupt enable register determines if a detected status condition should cause
a system interrupt. A system interrupt occurs if a bit in this register is set and the
corresponding bit in the interrupt detect register is also set. To clear the interrupt, write a
1 to the interrupt detect register.
Address: 3026_0000h base + 8h offset = 3026_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
ATCTEIE
ATTEIE
ITTEIE

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TIER field descriptions

Field Description
31 Immediate temperature threshold exceeded interrupt enable.
ITTEIE
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set. Write 1 to this bit will clear bit
TIDR[ITTE].
30 Average temperature threshold exceeded interrupt enable.
ATTEIE
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set. Write 1 to this bit will clear bit
TIDR[ATTE].
29 Average temperature critical threshold exceeded interrupt enable.
ATCTEIE
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set. Write 1 to this bit will clear bit
TIDR[ATCTE].
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

770 NXP Semiconductors
 Chapter 5 Clocks and Power Management

5.4.7.4 TMU Interrupt Detect register (TMU_TIDR)

The TMU interrupt detect register indicates if an status condition was detected that could
generate an interrupt. Write 1 to clear the detected condition and the interrupt, if enabled.
Address: 3026_0000h base + Ch offset = 3026_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATCTE
ATTE
ITTE

R
Reserved

Reserved

W w1c w1c w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 771
TMU Memory Map/Register Definition

TMU_TIDR field descriptions

Field Description
31 This field is reserved.
- Reserved
30 Immediate temperature threshold exceeded. Write 1 to clear.
ITTE
0 No threshold exceeded.
1 Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-
of-range measured temperature above 125°C.
29 Average temperature threshold exceeded. Write 1 to clear.
ATTE
0 No threshold exceeded.
1 Average temperature threshold, as defined by TMHTATR, has been exceeded.
28 Average temperature critical threshold exceeded. Write 1 to clear.
ATCTE
0 No threshold exceeded.
1 Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
- This field is reserved.
Reserved

5.4.7.5 TMU Monitor High Temperature Immediate Threshold register

(TMU_TMHTITR)

This TMU monitor register determines the high current temperature threshold for
generating the TIDR[ITTE] event.
Address: 3026_0000h base + 10h offset = 3026_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
EN Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved TEMP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TMHTITR field descriptions

Field Description
31 Enable threshold.
EN
0 Disabled.
1 Threshold enabled.
30–8 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

772 NXP Semiconductors
 Chapter 5 Clocks and Power Management

TMU_TMHTITR field descriptions (continued)

Field Description
TEMP High temperature immediate threshold value. Determines the current upper temperature threshold when
EN=1.
10-125 °C Sensor range
0-9 and 126-255 °C Reserved

5.4.7.6 TMU Monitor High Temperature Average threshold register

(TMU_TMHTATR)

This TMU monitor register determines the high average temperature threshold for
generating the TIDR[ATTE] event. The low-pass filter setting, TMR[ALPF], determines
the function for calculating average temperature.
Address: 3026_0000h base + 14h offset = 3026_0014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
EN Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved TEMP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TMHTATR field descriptions

Field Description
31 Enable threshold.
EN
0 Disabled.
1 Threshold enabled.
30–8 This field is reserved.
- Reserved
TEMP High temperature average threshold value. Determines the average upper temperature threshold when
EN=1.
10-125 °C Sensor range
0-9 and 126-255 °C Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 773
TMU Memory Map/Register Definition

5.4.7.7 TMU Monitor High Temperature Average Critical Threshold

register (TMU_TMHTACTR)

This TMU monitor register determines the high average critical temperature threshold for
generating the TIDR[ATCTE] event. The low-pass filter setting, TMR[ALPF],
determines the function for calculating average temperature.
Address: 3026_0000h base + 18h offset = 3026_0018h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
EN Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved TEMP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TMHTACTR field descriptions

Field Description
31 Enable threshold.
EN
0 Disabled.
1 Threshold enabled.
30–8 This field is reserved.
- Reserved
TEMP High temperature average critical threshold value. Determines the average upper critical temperature
threshold when EN=1.
10-125 °C Sensor range
0-9 and 126-255 °C Reserved

5.4.7.8 TMU Sensor Calibration register (TMU_TSCR)

The TMU sensor calibration register, in conjunction with the temperature calibration
register, is used to build the internal sensor translation table used during monitoring.
During the calibration phase, TMR[CE]=1, reading this register will return the sensor
reading. After writing the temperature calibration register, user should poll the TSR[TB]
bit to determine when the sensor reading is complete and then read the register. If BSR=1
the sensor reading could not be established due to temperature outside sensor range.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

774 NXP Semiconductors
 Chapter 5 Clocks and Power Management

Address: 3026_0000h base + 1Ch offset = 3026_001Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R BSR
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R SENSOR
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TSCR field descriptions

Field Description
31 Beyond temperature sensor range of 10-125 °C. The sensor reading is invalid. Read-only.
BSR
30–8 This field is reserved.
- Reserved
SENSOR Sensor reading. Read only.

5.4.7.9 TMU Report Immediate Temperature Site register n

(TMU_TRITSR)

This TMU report register returns the last measured temperature at site. The site must be
part of the list of enabled monitored sites as defined by TMR[MSITE].
Address: 3026_0000h base + 20h offset = 3026_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R V
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R TEMP
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TRITSR field descriptions

Field Description
31 Valid measured temperature.
V
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 775
TMU Memory Map/Register Definition

TMU_TRITSR field descriptions (continued)

Field Description
0 Not valid. Temperature out of sensor range or first measurement still pending.
1 Valid.
30–8 This field is reserved.
- Reserved
TEMP Last temperature reading at site when V=1.

5.4.7.10 TMU Report Average Temperature Site register n

(TMU_TRATSR)

This TMU report register returns the average measured temperature at site.
Address: 3026_0000h base + 24h offset = 3026_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R V
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R TEMP
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMU_TRATSR field descriptions

Field Description
31 Valid measured temperature.
V
0 Not valid. Temperature out of sensor range or first measurement still pending.
1 Valid.
30–8 This field is reserved.
- Reserved
TEMP Average temperature reading at site0 when V=1.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

776 NXP Semiconductors
Chapter 6
SNVS, Reset, Fuse, and Boot

6.1 System Boot

6.1.1 Overview
The boot process begins at the Power-On Reset (POR) where the hardware reset logic
forces the Arm core to begin the execution starting from the on-chip boot ROM.
The boot ROM code uses the state of the internal register BOOT_MODE[13:0] as well as
the state of various eFUSEs and/or GPIO settings to determine the boot flow behavior of
the device.
The main features of the ROM include:
• Support for booting from various boot devices
• Serial downloader support (USB OTG)
• Device Configuration Data (DCD) and plugin
• Wake-up from the low-power modes
The boot ROM supports these boot devices:
• Serial NOR Flash via FlexSPI
• NAND flash
• SD/MMC
• Serial (SPI) NOR
The boot ROM uses the state of the BOOT_MODE and eFUSEs to determine the boot
device. For development purposes, the eFUSEs used to determine the boot device may be
overridden using the GPIO pin inputs.
The boot ROM code also allows to download the programs to be run on the device. The
example is a provisioning program that can make further use of the serial connection to
provide a boot device with a new image. Typically, the provisioning program is

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 777
System Boot

downloaded to the internal RAM and allows to program the boot devices, such as the
SD/MMC flash. The ROM serial downloader uses a high-speed USB in a non-stream
mode connection.
The Device Configuration Data (DCD) feature allows the boot ROM code to obtain the
SOC configuration data from an external program image residing on the boot device. As
an example, the DCD can be used to program the DDR controller for optimal settings,
improving the boot performance. The DCD is restricted to the memory areas and
peripheral addresses that are considered essential for the boot purposes (see Write data
command).
A key feature of the boot ROM is the ability to perform a secure boot, also known as a
High-Assurance Boot (HAB). This is supported by the HAB security library which is a
subcomponent of the ROM code. The HAB uses a combination of hardware and software
together with the Public Key Infrastructure (PKI) protocol to protect the system from
executing unauthorized programs. Before the HAB allows the user image to execute, the
image must be signed. The signing process is done during the image build process by the
private key holder and the signatures are then included as a part of the final program
image. If configured to do so, the ROM verifies the signatures using the public keys
included in the program image. A secure boot with HAB can be performed on all boot
devices supported on the chip in addition to the serial downloader. The HAB library in
the boot ROM also provides the API functions, allowing the additional boot chain
components (bootloaders) to extend the secure boot chain. The out-of-fab setting for the
SEC_CONFIG is the open configuration, in which the ROM/HAB performs the image
authentication, but all authentication errors are ignored and the image is still allowed to
execute.

6.1.2 Boot modes

During reset, the chip checks the power gating controller status register.
During boot, the core's behavior is defined by the boot mode pin settings, as described in
Boot mode pin settings. When waking up from the low-power boot mode, the core skips
the clock settings. The boot ROM checks that the PERSISTENT_ENTRY0 (see
Persistent bits) is a pointer to a valid address space (OCRAM, DDR, or EIM). If the
PERSISTENT_ENTRY0 is a pointer to a valid range, it starts the execution using the
entry point from the PERSISTENT_ENTRY0 register. If the PERSISTENT_ENTRY0 is
a pointer to an invalid range, the core performs the system reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

778 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.1.2.1 Boot mode pin settings

The device has four boot modes (one is reserved for NXP use). The boot mode is selected
based on the binary value stored in the internal BOOT_MODE register.
The BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1
inputs on the rising edge of the POR_B. After these inputs are sampled, their subsequent
state does not affect the contents of the BOOT_MODE internal register. The state of the
internal BOOT_MODE register may be read from the IPP_BOOT_MODE[1:0] field of
the SRC Boot Mode Register (SRC_SBMR2). The available boot modes are: Boot From
Fuses, serial boot via USB, and Internal Boot. See this table for settings:
Table 6-1. Boot MODE pin settings
BOOT_MODE[1:0] Boot Type
00 Boot From Fuses
01 Serial Downloader
10 Internal Boot
11 Reserved

6.1.2.2 High-level boot sequence

The figure found here show the high-level boot ROM code flow.

Figure 6-1. Boot flow

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 779
System Boot

6.1.2.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)

A value of 00b in the BOOT_MODE[1:0] register selects the Boot From Fuses mode.
This mode is similar to the Internal Boot mode described in Internal Boot mode
(BOOT_MODE[1:0] = 0b10) with one difference. In this mode, the GPIO boot override
pins are ignored. The boot ROM code uses the boot eFUSE settings only. This mode also
supports a secure boot using HAB.
If set to Boot From Fuses, the boot flow is controlled by the BT_FUSE_SEL eFUSE
value. If BT_FUSE_SEL = 0, indicating that the boot device (for example, flash, SD/
MMC) was not programmed yet, the boot flow jumps directly to the Serial Downloader.
If BT_FUSE_SEL = 1, the normal boot flow is followed, where the ROM attempts to
boot from the selected boot device.
The first time a board is used, the default eFUSEs may be configured incorrectly for the
hardware on the platform. In such case, the Boot ROM code may try to boot from a
device that does not exist. This may cause an electrical/logic violation on some pads.
Using the Boot From Fuses mode addresses this problem.
Setting the BT_FUSE_SEL=0 forces the ROM code to jump directly to the Serial
Downloader. This allows a bootloader to be downloaded which can then provision the
boot device with a program image and blow the BT_FUSE_SEL and the other boot
configuration eFUSEs. After the reset, the boot ROM code determines that the
BT_FUSE_SEL is blown (BT_FUSE_SEL = 1) and the ROM code performs an internal
boot according to the new eFUSE settings. This allows the user to set
BOOT_MODE[1:0]=00b on a production device and burn the fuses on the same device
(by forcing the entry to the Serial Downloader), without changing the value of the
BOOT_MODE[1:0] or the pullups/pulldowns on the BOOT_MODE pins.

6.1.2.4 Serial Downloader

The Serial Downloader provides a means to download a program image to the chip over
the USB serial connection.
In this mode, the ROM programs the WDOG1 for a time-out specified by the fuse
WDOG Time-out Select (See fusemap for details) if the WDOG_ENABLE eFuse is 1
and continuously polls for the USB connection. If no activity is found on the USB OTG1
and the watchdog timer expires, the Arm core is reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

780 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

NOTE
After the downloaded image is loaded, it is responsible for
managing the watchdog resets properly.
This figure shows the USB boot flow:

START

Configure USBOTG1,
, program WDOG for 32 sec timer

Poll USBOTG1 No

WDOG_ENABLE
Activity
No == 1 &&
Detected WDOG timeout

Yes

Yes

Complete USB HID enumeration

Ready for Serial

Reset
Download

Figure 6-2. Serial Downloader boot flow

NOTE
Before going into USB serial mode, Boot ROM detect
SD/MMC card on USDHC2 port. If a card is inserted, ROM
will try to boot from it. This is the so-called Manufacture
SD/MMC boot. This feature can be disabled by blowing fuse
“Disable SD/MMC Manufacture Mode”. See SD/MMC
manufacture mode for details.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 781
System Boot

6.1.2.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10)

A value of 0b10 in the BOOT_MODE[1:0] register selects the Internal Boot mode. In
this mode, the processor continues to execute the boot code from the internal boot ROM.
The boot code performs the hardware initialization, loads the program image from the
chosen boot device, performs the image validation using the HAB library (see Boot
security settings), and then jumps to an address derived from the program image. If an
error occurs during the internal boot, the boot code jumps to the Serial Downloader (see
Serial Downloader). A secure boot using the HAB is possible in all the three boot modes.
When set to the Internal Boot, the boot flow may be controlled by a combination of
eFUSE settings with an option of overriding the fuse settings using the General Purpose
I/O (GPIO) pins. The GPIO Boot Select FUSE (BT_FUSE_SEL) determines whether the
ROM uses the GPIO pins for a selected number of configuration parameters or eFUSEs
in this mode.
• If BT_FUSE_SEL = 1, all boot options are controlled by the eFUSEs described in
Table 6-2.
• If BT_FUSE_SEL = 0, the specific boot configuration parameters may be set using
the GPIO pins rather than eFUSEs. The fuses that can be overridden when in this
mode are indicated in the GPIO column of Table 6-2. Table 6-3 provides the details
of the GPIO pins.
The use of the GPIO overrides is intended for development since these pads are used for
other purposes in the deployed products. NXP recommends controlling the boot
configuration by the eFUSEs in the deployed products and reserving the use of the GPIO
mode for the development and testing purposes only.

6.1.2.6 Boot security settings

The internal boot modes use one of three security configurations.
• Closed: This level is intended for use with shipping-secure products. All HAB
functions are executed and the security hardware is initialized (the Security
Controller or SNVS enters the Secure state), the DCD is processed if present, and the
program image is authenticated by the HAB before its execution. All detected errors
are logged, and the boot flow is aborted with the control being passed to the serial
downloader. At this level, the execution does not leave the internal ROM unless the
target executable image is authenticated.
• Open: This level is intended for use in non-secure products or during the
development phases of a secure product. All HAB functions are executed as for a
closed device. The security hardware is initialized (except for the SNVS which is left

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

782 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

in the Non-Secure state), the DCD is processed if present, and the program image is
authenticated by the HAB before its execution. All detected errors are logged, but
have no influence on the boot flow which continues as if the errors did not occur.
This configuration is useful for a secure product development because the program
image runs even if the authentication data is missing or incorrect, and the error log
can be examined to determine the cause of the authentication failure.
• Field Return: This level is intended for the parts returned from the shipped products.

6.1.3 Device configuration

This section describes the external inputs that control the behavior of the Boot ROM
code.
This includes the boot device selection ( SD, MMC, and so on), boot device
configuration (SD bus width, speed, and so on), and other. In general, the source for this
configuration comes from the eFUSEs embedded inside the chip. However, certain
configuration parameters can be sourced from the GPIO pins (with Internal Boot mode),
allowing further flexibility during the development process.

6.1.3.1 Boot eFUSE descriptions

This table is a comprehensive list of the configuration parameters that the ROM uses.
Table 6-2. Boot eFUSE descriptions
Fuse Config Definition GPIO1 Shipped Settings2
uratio value
n
BT_FUSE_SEL OEM In the Internal Boot mode NA 0 If BOOT_MODE[1:0] = 0b10:
BOOT_MODE[1:0] = 10,
• 0—The bits of the SBMR are
the BT_FUSE_SEL fuse
overridden by the GPIO pins.
determines whether the
boot settings indicated by a • 1—The specific bits of the SBMR are
Yes in the GPIO column are controlled by the eFUSE settings.
controlled by the GPIO pins
or the eFUSE settings in If BOOT_MODE[1:0] = 0b00
the On-Chip OTP Controller • 0—The BOOT configuration eFuses
(OCOTP). are not programmed yet. The boot
In the Boot From Fuse flow jumps to the serial downloader.
mode BOOT_MODE[1:0] =
00, the BT_FUSE_SEL fuse • 1—The BOOT configuration eFuses
indicates whether the bit are programmed. The regular boot
configuration eFuses are flow is performed.
programmed.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 783
System Boot

Table 6-2. Boot eFUSE descriptions

(continued)
Fuse Config Definition GPIO1 Shipped Settings2
uratio value
n
SEC_CONFIG[1:0] SEC_C Security Configuration, as NA 01 00—Reserved
ONFIG[ defined in Boot security
01—Open (allows any program image,
0] - settings
even if the authentication fails)
NXP
1x—Closed (The program image executes
SEC_C
only if authenticated)
ONFIG[
1] -
OEM
FIELD_RETURN OEM Configure device for field 0—Device is in functional/secure mode.
return testing. Fuse burning
1—Device is open for "field-return" testing.
is protected by CSF
command, with proper
parameter passed. Non-
lockable.
BT_DCACHE_DISAB OEM The D Cache disable bit No 0 0— D Cache is enabled by the ROM during
LE used by the boot ROM for the boot.
fast HAB processing.
1— D Cache is disabled by the ROM
during the boot.
L1 I-Cache DISABLE OEM L1 I Cache disable bit used No 0 0—L1 I Cache is enabled by the ROM
by the boot during the entire during the boot.
execution.
1—L1 I Cache is disabled by the ROM
during the boot.
LPB_BOOT OEM USB Low-Power Boot No 0 0x—LPB Disable
10—Divide by 2
11—Divide by 4
BT_LPB_POLARITY OEM USB Low-Power Boot GPIO No 0 0—Low on the GPIO pad indicates the low-
polarity power condition.
1—High on the GPIO pad indicates the
low-power condition.
WDOG_ENABLE OEM Watchdog reset counter No 0 0—The watchdog reset counter is disabled
enable during the serial downloader.
1—The watchdog reset counter is enabled
during the serial downloader.
Recovery Boot Enable OEM SPI recovery boot enable No 0 0—Disabled
1—Enabled
MMC_DLL_DLY[6:0] OEM uSDHC Delay Line settings No 0 uSDHC Delay Line settings
DISABLE_SDMMC_M OEM Disable the SDMMC Yes 0 0—enable the SD/MMC MFG mode
FG manufacture mode
1—disable the SD/MMC MFG mode
USDHC_PAD_SETTI OEM Override values for the No 0 Override the following IO PAD settings:
NGS SD/MMC and NAND boot
[1:0] Driver Strength
modes
NAND_PAD_SETTIN
[2] Slew Rate
GS
[3] Hysteresis
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

784 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-2. Boot eFUSE descriptions

(continued)
Fuse Config Definition GPIO1 Shipped Settings2
uratio value
n
>
[4] Pull/Keeper select
[6:5] Pull up/down config
.
OVERRIDE_HYS_SD OEM Overrides the HYS bit for No 0 Override the IO PAD setting HYS to 1 for
MMC_PADS the SD pads the SD pads.
eMMC_4.4_RESET_T OEM ROM resets the boot device No 0 Applicable for booting from the eMMC 4.4
O_PRE-IDLE_STATE in the pre-idle state using spec or greater version devices. The fuse
the eMMC 4.4 feature, must not be blown for the eMMC 4.3 or
CMD0 with the argument lesser spec version devices.
value 0xf0f0f0f0.

1. This setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See GPIO Boot Overrides for
the corresponding GPIO pin.
2. 0 = intact fuse and 1= blown fuse

6.1.3.2 GPIO boot overrides

This table provides a list of the GPIO boot overrides:
Table 6-3. GPIO override contact assignments
Package pin Direction on reset eFuse
BOOT_MODE1 Input Boot mode selection
BOOT_MODE0 Input
SAI1_RXD0 Input BOOT_CFG[0]
SAI1_RXD1 Input BOOT_CFG[1]
SAI1_RXD2 Input BOOT_CFG[2]
SAI1_RXD3 Input BOOT_CFG[3]
SAI1_RXD4 Input BOOT_CFG[4]
SAI1_RXD5 Input BOOT_CFG[5]
SAI1_RXD6 Input BOOT_CFG[6]
SAI1_RXD7 Input BOOT_CFG[7]
SAI1_TXD0 Input BOOT_CFG[8]
SAI1_TXD1 Input BOOT_CFG[9]
SAI1_TXD2 Input BOOT_CFG[10]
SAI1_TXD3 Input BOOT_CFG[11]
SAI1_TXD4 Input BOOT_CFG[12]

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 785
System Boot

Table 6-3. GPIO override contact assignments (continued)

Package pin Direction on reset eFuse
SAI1_TXD5 Input BOOT_CFG[13]
SAI1_TXD6 Input BOOT_CFG[14]
SAI1_TXD7 Input BOOT_CFG[15]

The input pins provided are sampled at boot, and can be used to override the
corresponding eFUSE values, depending on the setting of the BT_FUSE_SEL fuse.

6.1.3.3 Device Configuration Data (DCD)

The DCD is the configuration information contained in the program image (external to
the ROM) that the ROM interprets to configure various on-chip peripherals. See Device
Configuration Data (DCD) for more details on DCD.

6.1.4 Device initialization

This section describes the details of the ROM and provides the initialization details.
This includes details on:
• The ROM memory map
• The RAM memory map
• On-chip blocks that the ROM must use or change the POR register default values
• Clock initialization
• Enabling the cache
• Exception handling and interrupt handling

6.1.4.1 Internal ROM/RAM memory map

These figures show the iROM memory map:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

786 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

0x0001FFFF 0x0091FFFF
ROM BOOTSTRAP CODE
0x00000960

ROM API TABLE

0x00000900
OCRAM FREE AREA

HAB API TABLE

0x00000880

ROM VERSION AND

COPYRIGHT INFORMATION
0x00000800 0x00910000

ROM BOOTSTRAP CODE

0x00000400
RESERVED FOR ROM

VECTORS
0x00000000 0x00900000

ROM Memory Map OCRAM Memory Map

Figure 6-3. Internal ROM and RAM memory map

NOTE
If no ROM/HAB APIs are being used, the entire OCRAM
region can be used freely after the boot.

6.1.4.2 Boot block activation

The boot ROM affects a number of different hardware blocks which are activated and
play a vital role in the boot flow.
The ROM configures and uses the following blocks (listed in an alphabetical order)
during the boot process. Note that the blocks actually used depend on the boot mode and
the boot device selection:
• APBH—the DMA engine to drive the GPMI module
• BCH—62-bit error correction hardware engine with the AXI bus master and a
private connection to the GPMI
• CCM—Clock Control Module
• ECSPI—Enhanced Configurable Serial Peripheral Interface
• FlexSPI—Flexible SPI Interface which supports serial NOR devices
• GPMI—NAND controller pin interface
• OCOTP_CTRL—On-Chip OTP Controller; the OCOTP contains the eFUSEs

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 787
System Boot

• IOMUXC—I/O Multiplexer Control which allows the GPIO use to override the
eFUSE boot settings;
• IOMUXC GPR—I/O Multiplexer Control General-Purpose Registers
• CAAM—Cryptographic Acceleration and Assurance Module
• SNVS—Secure Non-Volatile Storage
• SRC—System Reset Controller
• USB—used for the serial download of a boot device provisioning program
• USDHC—Ultra-Secure Digital Host Controller
• WDOG-1—Watchdog timer

6.1.4.3 Clocks at boot time

The table below show the various clocks and their sources used by the ROM.
After the reset, each Arm core has access to all peripherals. The ROM code disables the
clocks listed in the following table, except for the boot devices listed in the second
column.
Table 6-4. PLL setting by ROM
PLL name Frequency Comment
ARM_PLL 1000 MHz -
SYS_PLL1 800 MHz -
SYS_PLL2 1000 MHz -
SYS_PLL3 1000 MHz -

NOTE
All other PLLs are in the default status.
Table 6-5. Clock root setting by ROM
Clock Name Frequency (MHz) Source Enable
ARM_A53_ROOT 1000 ARM_PLL_CLK Yes
ARM_M4_CLK_ROOT 200 SYSTEM_PLL2_200M_CLK -
AHB_CLK_ROOT 133 SYSTEM_PLL1_133M_CLK Yes
MAIN_AXI_CLK_ROOT 333 SYSTEM_PLL2_333M_CLK Yes
VPU_A53_CLK_ROOT 800 ARM_PLL_CLK No
DRAM_ALT_CLK_ROOT 800 SYSTEM_PLL1_800M_CLK yes
NAND_CLK_ROOT 500 SYSTEM_PLL2_500M_CLK Enabled by driver
NAND_USDHC_BUS_CLK_R 266 SYSTEM_PLL1_266M_CLK Enabled by driver
OOT
USB_BUS_CLK_ROOT SYSTEM_PLL2_500M_CLK Enabled by driver

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

788 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-5. Clock root setting by ROM (continued)

Clock Name Frequency (MHz) Source Enable
NOC_CLK_ROOT 400 SYSTEM_PLL1_800M_CLK Yes
USDHC1_CLK_ROOT 200 SYSTEM_PLL1_400M_CLK Enabled by driver
USDHC2_CLK_ROOT 200 SYSTEM_PLL1_400M_CLK Enabled by driver
USB_PHY_REF_CLK_ROOT SYSTEM_PLL1_100M_CLK Enabled by driver
ECSPI1_CLK_ROOT 50 SYSTEM_PLL2_200M_CLK No
ECSPI2_CLK_ROOT 50 SYSTEM_PLL2_200M_CLK No
ECSPI3_CLK_ROOT 50 SYSTEM_PLL2_200M_CLK No
WRCLK_CLK_ROOT SYSTEM_PLL1_40M_CLK No

NOTE
All other clock roots are in the default status.
Table 6-6. NAND_CLK_ROOT setting
NAND data rate NAND_CLK_ROOT source Frequency
Async/Legacy NAND SYSTEM_PLL1_400M_CLK 25 MHz
Sync 40M SYSTEM_PLL1_400M_CLK 40 MHz
Toggle/Sync 66M SYSTEM_PLL1_400M_CLK 66 MHz
Toggle 80M SYSTEM_PLL1_400M_CLK 80 MHz
Sync 100M SYSTEM_PLL1_400M_CLK 100 MHz
Toggle/Sync 133M SYSTEM_PLL1_400M_CLK 133 MHz
Sync 160M SYSTEM_PLL1_400M_CLK 133 MHz
Toggle/Sync 200M SYSTEM_PLL1_400M_CLK 200 MHz

NOTE
The NAND_CLK_ROOT source depends on the NAND data
rate.
The ROM code disables the clocks listed in the following table, except for the boot
devices listed in the "Enabled for boot device" column below.
Table 6-7. CCGR setting by ROM
CCGR Register LPCG Enable Enabled for boot device
CCM_CCGR0 Dvfs
CCM_CCGR1 Anamix
CCM_CCGR2 Cpu
CCM_CCGR3 Csu Security related
CCM_CCGR4 debug
CCM_CCGR5 Dram1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 789
System Boot

Table 6-7. CCGR setting by ROM (continued)

CCGR Register LPCG Enable Enabled for boot device
CCM_CCGR6 reserved
CCM_CCGR7 Ecspi1
CCM_CCGR8 Ecspi2
CCM_CCGR9 Ecspi3
CCM_CCGR10 Enet1
CCM_CCGR11 Gpio1 Never gate GPIO clock. uSDHC and test
mode use GPIO.
CCM_CCGR12 Gpio2
CCM_CCGR13 Gpio3
CCM_CCGR14 Gpio4
CCM_CCGR15 Gpio5
CCM_CCGR16 Gpt1 Used by ROM as tick. Keep no changed
so it is 25MHz.
CCM_CCGR17 Gpt2 Can be used in DCD. Keep no changed
so it is 25MHz.
CCM_CCGR18 Gpt3
CCM_CCGR19 Gpt4
CCM_CCGR20 Gpt5
CCM_CCGR21 Gpt6
CCM_CCGR22 Hs
CCM_CCGR23 I2c1 No I2C to be enabled
CCM_CCGR24 I2c2
CCM_CCGR25 I2c3
CCM_CCGR26 I2c4
CCM_CCGR27 Iomux
CCM_CCGR28 Iomux1
CCM_CCGR29 Iomux2
CCM_CCGR30 Iomux3
CCM_CCGR31 Iomux4
CCM_CCGR32 SNVSMIX_IPG_CLK
CCM_CCGR33 Mu
CCM_CCGR34 Ocotp
CCM_CCGR35 Ocram
CCM_CCGR36 Ocram_s
CCM_CCGR37 Pcie
CCM_CCGR38 Perfmon1
CCM_CCGR39 Perfmon2
CCM_CCGR40 Pwm1
CCM_CCGR41 Pwm2
CCM_CCGR42 Pwm3

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

790 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-7. CCGR setting by ROM (continued)

CCGR Register LPCG Enable Enabled for boot device
CCM_CCGR43 Pwm4
CCM_CCGR44 Qos
CCM_CCGR45 Dispmix
CCM_CCGR46 Ethernet
CCM_CCGR47 Qspi
CCM_CCGR48 Rawnand Will be gated on if boot from NAND is
issued.
CCM_CCGR49 Rdc Never used by ROM. Gate it off.
CCM_CCGR50 Rom
CCM_CCGR51 Sai1
CCM_CCGR52 Sai2
CCM_CCGR53 Sai3
CCM_CCGR54 Sai4
CCM_CCGR55 Sai5
CCM_CCGR56 Sai6
CCM_CCGR57 Sctr System counter. Do not gate off.
CCM_CCGR58 Sdma1 Not used by ROM. Gate it off.
CCM_CCGR59 Sdma2
CCM_CCGR60 Sec_debug
CCM_CCGR61 Sema1 Not used by ROM. Gate it off.
CCM_CCGR62 Sema2
CCM_CCGR63 Sim_display Bus clock. Do not gate off.
CCM_CCGR64 Sim_enet Bus clock. Do not gate off.
CCM_CCGR65 Sim_m Bus clock. Do not gate off.
CCM_CCGR66 Sim_main Bus clock. Do not gate off.
CCM_CCGR67 Sim_s Bus clock. Do not gate off.
CCM_CCGR68 Sim_wakeup Bus clock. Do not gate off.
CCM_CCGR69 Sim_usb Bus clock. Do not gate off.
CCM_CCGR70 Sim_vpu Bus clock. Do not gate off.
CCM_CCGR71 Snvs Secure Non-Volatile Storage
CCM_CCGR72 Trace
CCM_CCGR73 Uart1
CCM_CCGR74 Uart2
CCM_CCGR75 Uart3
CCM_CCGR76 Uart4
CCM_CCGR77 Usb_ctrl1 Used by ROM USB driver, to enable
USB clock
CCM_CCGR78 Reserved
CCM_CCGR79 GPU3D
CCM_CCGR80 Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 791
System Boot

Table 6-7. CCGR setting by ROM (continued)

CCGR Register LPCG Enable Enabled for boot device
CCM_CCGR81 Usdhc1 Used by USDHC driver
CCM_CCGR82 Usdhc2 Used by USDHC driver
CCM_CCGR83 Wdog1 WDOG1 used by ROM.
CCM_CCGR84 Wdog2
CCM_CCGR85 Wdog3
CCM_CCGR86 VPUG1
CCM_CCGR87 Gpu
CCM_CCGR88 Reserved
CCM_CCGR89 VPUH1
CCM_CCGR90 VPUG2
CCM_CCGR91 PDM
CCM_CCGR92 Gic Leave on for Software.
CCM_CCGR93 Display
CCM_CCGR94 USDHC3
CCM_CCGR95 SDMA3
CCM_CCGR96 Xtal
CCM_CCGR97 Pll
CCM_CCGR98 Tsensor
CCM_CCGR99 Vpu_dec
CCM_CCGR100 Reserved
CCM_CCGR101 Reserved
CCM_CCGR102 GPU2D

6.1.4.4 Exception handling

The exception vectors located at the start of the ROM are used to map all the Arm
exceptions (except the reset exception) to a duplicate exception vector table in the
internal RAM.
During the boot phase of CPU0, the RAM vectors point to the serial downloader in the
ROM.
After the boot, the program image can overwrite the vectors as required. The code shown
below is used to map the ROM exception vector table to the duplicate exception vector
table in the RAM.
Mapping ROM Exception Vector Table
;; Define linker area for ROM exception vector table
AREA IROM_VECTORS, CODE, READONLY
LDR PC, Reset_Addr

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

792 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP ; Reserved vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr

;; Define exception vector table

Reset_Addr DCD start_address
Undefined_Addr DCD iRAM_Undefined_Handler
SWI_Addr DCD iRAM_SWI_Handler
Prefetch_Addr DCD iRAM_Prefetch_Handler
Abort_Addr DCD iRAM_Abort_Handler
DCD 0 ; Reserved vector
IRQ_Addr DCD iRAM_IRQ_Handler
FIQ_Addr DCD iRAM_FIQ_Handler

start_address DCD start ;reset handler vector

6.1.4.5 Interrupt handling during boot

No special interrupt-handling routines are required during the boot process. The
interrupts are disabled during the boot ROM execution and may be enabled in a later boot
stage.

6.1.4.6 Persistent bits

Some modes of the boot ROM require the registers that keep their values after a warm
reset. The SRC General-Purpose registers are used for this purpose.
See this table for persistent bits list and description:
Table 6-8. Persistent bits
Bit name Bit location Description
PERSIST_SECONDARY_BOOT SRC_GPR10[30] This bit identifies which image must be used—
primary and secondary. Used only for the boot
modes that support redundant boot.
PERSIST_BLOCK_REWRITE SRC_GPR10[29] This bit is used as a warning. It identifies that there
are errors in the NAND blocks that hold the
application image.
See NAND flash for more details.
PERSISTENT_ENTRY0[31:0] SRC_GPR1[31:0] Holds the entry function for the CPU0 to wake up
from the low-power mode.
PERSISTENT_ARG0[31:0] SRC_GPR2[31:0] Holds the argument of entry function for the CPU0
to wake up from the low-power mode.
PERSISTENT_ENTRY1[31:0] SRC_GPR3[31:0] Holds the entry function for the CPU1 to wake up
from the low-power mode.
PERSISTENT_ARG1[31:0] SRC_GPR4[31:0] Holds the argument of the entry function for the
CPU1 to wake up from the low-power mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 793
System Boot

6.1.5 Boot devices (internal boot)

The chip supports these boot flash devices:
• Serial NOR flash via FlexSPI interface
• Raw NAND (MLC and SLC), and Toggle-mode NAND flash through GPMI-2
interface, located at CS0. Page sizes of 2 KB, 4 KB, and 8 KB. The bus widths of 8-
bit with 2 through 62-bit BCH hardware ECC (Error Correction) are supported.
• SD/MMC/eSD/SDXC/eMMC4.4 via USDHC interface, supporting high capacity
cards.
• EEPROM boot via SPI (serial flash).
• EEPROM boot via SPI (serial flash)
The selection of the external boot device type is controlled by the BOOT_CFG eFUSEs.
See this table for more details:
Table 6-9. Boot device selection
BOOT_CFG[14:12] Boot device
001 SD/eSD
010 MMC/eMMC
011 NAND
100 Serial NOR boot via FlexSPI
110 Serial (SPI) NOR

6.1.5.1 Serial NOR Flash Boot via FlexSPI

6.1.5.1.1 Serial NOR eFUSE Configuration

Table 6-10. Fuse definition for Serial NOR over FlexSPI
Fuse Config Config Definitions GPIO Shipped Value Settings
BOOT_CFG[3:0] OEM xSPI FLASH Yes 0 0 – Dummy cycles
Dummy Cycle is auto-probed
Others – Actual
dummy cycles for
Read command
BOOT_CFG[5:4] OEM xSPI FLASH Auto Yes 0 0 – QuadSPI NOR
Probe Type
1 – MXIC Octal
2 – Micron Octal
3 – Adesto Octal

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

794 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-10. Fuse definition for Serial NOR over FlexSPI (continued)
Fuse Config Config Definitions GPIO Shipped Value Settings
BOOT_CFG[7:6] OEM Hold time before Yes 0 0 – 500us
read from device
1 – 1ms
2 – 3ms
3 – 10ms
BOOT_CFG[10:8] OEM Flash Type Yes 0 000b–Device
supports 3B read
by default
001b–Device
supports 4B read
by default
010b–HyperFlash
1V8
011b–HyperFlash
3V3
100b–MXIC Octal
DDR
BOOT_CFG[11] OEM xSPI FLASH Auto Yes 0 0 – Disabled
Probe
1 – Enabled
BOOT_CFG[14:12] OEM Boot device Yes 0 100 – Serial NOR
selection device is selected
as boot device.
0x480[2:0] OEM xSPI FLASH No 0 0 - 100 MHz
(BOOT_CFG_PAR Frequency
1 - 133 MHz
AMETER)
2 - 166 MHz
3 - 200 MHz
4 - 80 MHz
5 - 20 MHz
Others – Reserved

NOTE
If the xSPI FLASH Auto Probe feature is enabled, the
following is the logic how this feature works with other fuse
combinations:
• Flash Type - If Flash type is 0, the "xSPI FLASH Auto
Probe Type" takes effect for the Flash type selection. If
Flash Type is greater than 1, the "Flash Type" Fuse is used
for Flash type selection, ROM will issue specific command
to probe the presence of Serial NOR FLASH.
• xSPI FLASH Frequency - This field is used for specifying
the Flash working frequency.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 795
System Boot

6.1.5.1.2 FlexSPI Serial NOR Flash Boot Operation

The Boot ROM attempts to boot from Serial NOR flash if the BOOT_CFG [7:6] fuses
are programmed to 0b’00 as shown in the Serial NOR eFUSE Configuration table, then
the ROM will initialize FlexSPI1 interface. FlexSPI interface initialization is a two-step
process.
The ROM expects the 512-byte FlexSPI NOR configuration parameters as explained in
next section to be present at offset 0 in Serial NOR flash. The ROM reads these
configuration parameters using the read command specified by BOOT_CFG [5:3] with
Serial clock operating at 30 MHz.
In the second step, ROM configures FlexSPI1 interface with the parameters provided in
configuration block read from Serial NOR flash and starts the boot procedure. Refer to
Table 25-14 for details regarding FlexSPI configuration parameters and to the FlexSPI
NOR boot flow chart for detailed boot flow chart of FlexSPI NOR.
Both booting an XIP and non XIP image are supported from Serial NOR Flash. For XIP
boot, the image has to be built for FlexSPI address space and for non XIP the image can
be built to execute from Internal RAM.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

796 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.1.5.1.3 FlexSPI NOR boot flow chart

Start

Configure FlexSPI Pinmux and

Clock to 30MHz to perform basic
read operation

Get Configuration parameter

Configure IOMUXC, LUT,

controller and clock based on the
configuration parameter read from
Flash device

Configure Flash device to desired

mode based on configuration
parameter

Set boot device parameter( initial

image address, memory range,
etc).

No
Image == XIP Copy image to OCRAM

Yes

Execute the image from FlexSPI1 Execute Image from

address space OCRAM

End

Figure 6-4. FlexSPI NOR boot flow

6.1.5.2 Serial NOR configuration based on FlexSPI interface

The ROM SW supports Serial NOR based on FlexSPI module, using a 448-bytes
common FlexSPI configuration block and several specified parameters for Serial NOR
respectively. See below sections for more details.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 797
System Boot

6.1.5.2.1 FlexSPI Configuration Block

FlexSPI Configuration block consists of parameters regarding specific Flash devices
including read command sequence, quad mode enablement sequence (optional), etc.
Table 6-11. FlexSPI Configuration block
Name Offset Size(bytes) Description
Tag 0x000 4 0x42464346, ascii:” FCFB”
Version 0x004 4 0x56010000
[07:00] bugfix = 0
[15:08] minor = 0
[23:16] major = 1
[31:24] ascii ‘V’
- 0x008 4 Reserved
readSampleClkSrc 0x00C 1 0 – internal loopback
1 – loopback from DQS pad
3 – Flash provided DQS
dataHoldTime 0x00D 1 Serial Flash CS Hold Time
Recommend default value is
0x03
dataSetupTime 0x00E 1 Serial Flash CS setup time
Recommended default value
is 0x03
columnAdressWidth 0x00F 1 3 – For HyperFlash
12/13 – For Serial NAND, see
datasheet to find correct value
0 – Other devices
deviceModeCfgEnable 0x010 1 Device Mode Configuration
Enable feature
0 – Disabled
1 – Enabled
- 0x011 3 Reserved
deviceModeSeq 0x014 4 Sequence parameter for
device mode configuration
deviceModeArg 0x018 4 Device Mode argument,
effective only when
deviceModeCfgEnable = 1
configCmdEnable 0x01C 1 Config Command Enable
feature
0 – Disabled
1 – Enabled
- 0x01D 3 Reserved
configCmdSeqs 0x020 16 Sequences for Config
Command, allow 4 separate
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

798 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-11. FlexSPI Configuration block (continued)

Name Offset Size(bytes) Description
configuration command
sequences.
cfgCmdArgs 0x030 16 Arguments for each separate
configuration command
sequence.
controllerMiscOption 0x040 4 Bit0 – differential clock enable
Bit1 – CK2 enable, must set
to 0 in this silicon
Bit2 – ParallelModeEnable,
must set to 0 for this silicon
Bit3 –
wordAddressableEnable
Bit4 – Safe Configuration
Frequency enable set to 1 for
the devices that support DDR
Read instructions
Bit5 – Pad Setting Override
Enable
Bit6 – DDR Mode Enable, set
to 1 for device supports DDR
read command
deviceType 0x044 1 1 – Serial NOR
2 – Serial NAND
sflashPadType 0x045 1 1 – Single pad
2 – Dual pads
4 – Quad pads
8 – Octal pads
serialClkFreq 0x046 1 Chip specific value, for this
silicon
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
4 – 75 MHz
5 – 80 MHz
6 – 100 MHz
7 – 133 MHz
8 – 166 MHz
Other value: 30 MHz
lutCustomSeqEnable 0x047 1 0 – Use pre-defined LUT
sequence index and number
1 - Use LUT sequence
parameters provided in this
block

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 799
System Boot

Table 6-11. FlexSPI Configuration block (continued)

Name Offset Size(bytes) Description
- 0x048 8 Reserved
sflashA1Size 0x050 4 For SPI NOR, need to fill with
actual size
For SPI NAND, need to fill
with actual size * 2
sflashA2Size 0x054 4 The same as above
sflashB1Size 0x058 4 The same as above
sflashB2Size 0x05C 4 The same as above
csPadSettingOverride 0x060 4 Set to 0 if it is not supported
sclkPadSettingOverride 0x064 4 Set to 0 if it is not supported
dataPadSettingOverride 0x068 4 Set to 0 if it is not supported
dqsPadSettingOverride 0x06C 4 Set to 0 if it is not supported
timeoutInMs 0x070 0 Maximum wait time during
read busy status
0 – Disabled timeout checking
feature Other value – Timeout
if the wait time exceeds this
value.
commandInterval 0x074 4 Unit: ns
Currently, it is used for SPI
NAND only at high frequency
dataValidTime 0x078 4 Time from clock edge to data
valid edge, unit ns. This field
is used when the FlexSPI
Root clock is less than 100
MHz and the read sample
clock source is device
provided DQS signal without
CK2 support.
[31:16] data valid time for
DLLB in terms of 0.1 ns
[15:0] data valid time for DLLA
in terms of 0.1 ns
busyOffset 0x07C 2 busy bit offset, valid range :
0-31
busyBitPolarity 0x07E 2 0 – busy bit is 1 if device is
busy
1 – busy bit is 0 if device is
busy
lookupTable 0x080 256 Lookup table
lutCustomSeq 0x180 48 Customized LUT sequence,
see below table for details.
0x1B0 16 Reserved for future use

Note:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

800 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

1. To customize the LUT sequence for some specific device, users need to enable
“lutCustomSeqEnable” and fill in corresponding “lutCustomSeq” field specified by
command index below.
2. For Serial (SPI) NOR, the pre-defined LUT index is as follows:
Table 6-12. LUT sequence definition for Serial
NOR
Command Index Name Index in lookup table Description
0 Read 0 Read command
Sequence
1 ReadStatus 1 Read Status
command
2 WriteEnable 3 Write Enable
command sequence
3 EraseSector 5 Erase Sector
Command
4 PageProgram 9 Page Program
Command
5 ChipErase 11 Full Chip Erase
6 Dummy 15 Dummy Command as
needed
Reserved 2,4,6,7,8,10,12,13,14 All reserved indexes
can be freely used for
other purpose

6.1.5.2.2 Serial NOR configuration block (512 bytes)

Table 6-13. Serial NOR configuration block
Name Offset Size (Bytes) Description
memCfg 0 448 The common memory
configuration block, see
FlexSPI configuration block
for more details
pageSize 0x1C0 4 Page size in terms of bytes,
not used by ROM
sectorSize 0x1C4 4 Sector size in terms of bytes,
not used by ROM
ipCmdSerialClkFreq 0x1C8 4 Chip specific value, not used
by ROM For Ultra
0 – No change, keep current
serial clock unchanged
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
4 – 75 MHz
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 801
System Boot

Table 6-13. Serial NOR configuration block (continued)

Name Offset Size (Bytes) Description
5 – 80 MHz
6 – 100 MHz
7 – 133 MHz
8 – 166 MHz
Reserved 0x1CC 52 Reserved for future use

6.1.5.3 NAND flash

The boot ROM supports a number of MLC/SLC NAND flash devices from different
vendors and LBA NAND flash devices. The Error Correction and Control (ECC)
subblock (BCH) is used to detect the errors.

6.1.5.3.1 NAND eFUSE configuration

The boot ROM determines the configuration of the external NAND flash by parameters,
either provided by the eFUSE, or sampled on the GPIO pins during boot. See Table 6-14
for parameters details.
NOTE
BOOT_CFGx sampled on the GPIO pins depends on the
BT_FUSE_SEL setting. See Boot Fusemap for details.
Table 6-14. NAND boot eFUSE descriptions
Fuse Config Definition GPIO1 Shipped Settings
value
BOOT_CFG[15:12] OEM Boot device selection Yes 0 0011—boot from the NAND
interface
BOOT_CFG[7] OEM BT_TOGGLEMODE Yes 0 0—raw NAND
1—toggle mode NAND
BOOT_CFG[11:10] OEM Pages in block Yes 0 00—128
01—64
10—32
11—256
BOOT_CFG[9:8] OEM Row address cycles Yes 00 00—3
01—2
10—4
11—5

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

802 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-14. NAND boot eFUSE descriptions (continued)

Fuse Config Definition GPIO1 Shipped Settings
value
BOOT_CFG[4:1] OEM Toggle mode 33 MHz Yes 000 0000—16 GPMICLK cycles
preamble delay, read latency
0001—1 GPMICLK cycles
0010—2 GPMICLK cycles
0011—3 GPMICLK cycles
0100—4 GPMICLK cycles
0101—5 GPMICLK cycles
0110—6 GPMICLK cycles
0111—7 GPMICLK cycles
1000—8 GPMICLK cycles
1001—9 GPMICLK cycles
1010—10 GPMICLK cycles
1011—11 GPMICLK cycles
1100—12 GPMICLK cycles
1101—13 GPMICLK cycles
1110—14 GPMICLK cycles
1111—15 GPMICLK cycles
BOOT_CFG[6:5] OEM Boot search count Yes 00 00—2
01—2
10—4
11—8
0x4B0[7] OEM Override pad settings No 0 Override the NAND pad settings
0—use the default values
1—use the PAD_SETTINGS
value
0x4A0[31:24] OEM PAD_SETTINGS[7:0] No 0 NAND pad settings value
0x4B0[15:12] OEM READ_RETRY_SEQ_ID[3:0] No 0000 0000—don't use the ROM
embedded read-retry sequence
0001—use Micron 20 nm read-
retry sequence
0010—use Toshiba A19nm
read-retry sequence
0011—use Toshiba 19nm read-
retry sequence
0100—use SanDisk 19nm read-
retry sequence
0101—use SanDisk 1ynm read-
retry sequence
0110 to 1111—reserved

1. The setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See Table 1 for the
corresponding GPIO pin.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 803
System Boot

6.1.5.3.2 NAND flash boot flow and Boot Control Blocks (BCB)
There are two BCB data structures:
• FCB
• DBBT
As a part of the NAND media initialization, the ROM driver uses safe NAND timings to
search for the Firmware Configuration Block (FCB) that contains the optimum NAND
timings, the page address of the Discovered Bad Block Table (DBBT) Search Area, and
the start page address of the primary and secondary firmware.
The hardware ECC level to use is embedded inside the FCB block. The FCB data
structure is also protected using the ECC. The driver reads raw 2112 bytes of the first
sector and runs through the software ECC engine that determines whether the FCB data is
valid or not.
If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC
fails, or the fingerprints do not match, the Block Search state machine increments the
page number to the Search Stride number of pages to read for the next BCB until the
SearchCount pages have been read.
If the search fails to find a valid FCB, the NAND driver responds with an error and the
boot ROM enters the serial download mode.
The FCB contains the page address of the DBBT Search Area, and the page address for
primary and secondary boot images. The DBBT is searched in the DBBT Search Area,
just like the FCB is searched. After the FCB is read, the DBBT is loaded, and the primary
or secondary boot image is loaded using the starting page address from the FCB.
This figure shows the state diagram of the FCB search:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

804 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

START

Current Page = 0,
Search Stride = Stride Size Fuse Value,
Search Count = Boot Search Count Fuse Value

Read 4K, ReadCount++

Current Page += Search

Stride

YES

Read Count <

Is Valid FCB? NO
Search Count

YES NO

Recovery Device/
NCB Found
Serial Loader

Figure 6-5. FCB search flow

When the FCB is found, the boot ROM searches for the Discovered Bad Blocks Table
(DBBT). If the DBBT Search Area is 0 in the FCB, the ROM assumes that there are no
bad blocks on the NAND device boot area. See this figure for the DBBT search flow:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 805
System Boot

START

Current Page = DBBT Start Page,

Search Stride = Stride Size Fuse Value,
Search Count = 4

Read 4K, ReadCount++

Current Page += Search

Stride

YES

Read Count <

Is Valid DBBT? NO
Search Count

YES

NO
DBBT Found, Copy to IRAM

DBBT Not Found

DBBT Found

Figure 6-6. DBBT search flow

The BCB search and load function also monitors the ECC correction threshold and sets
the PERSIST_BLOCK_REWRITE persistent bit if the threshold exceeds the maximum
ECC correction ability.
If there is a page with a number of errors higher than ECC can correct during the primary
image read, the boot ROM turns on the PERSIST_SECONDARY_BOOT bit and
performs the software reset (After the software reset, the secondary image is used).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

806 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

If there is a page with number of errors higher than ECC can correct during secondary
image read, the boot ROM goes to the serial loader.

6.1.5.3.3 Firmware configuration block

The FCB is the first sector in the first good block. The FCB must be present at each
search stride of the search area.
The search area contains copies of the FCB at each stride distance, so, in case the first
NAND block becomes corrupted, the ROM finds its copy in the next NAND block. The
search area must span over at least two NAND blocks. The location information for the
DBBT search area, FW1, and FW2 are all specified in the FCB. This table shows the
flash control block structure:
Table 6-15. Flash control block structure
Name Start byte Size in bytes Description
Reserved 0 4 Reserved for Fingerprint #1(Checksum)
FingerPrint 4 4 32-bit word with a value of 0x20424346, in ascii
"FCB"
Version 8 4 32-bit version number; this version of FCB is
0x00000001
m_NANDTiming 12 8 8 B of data for eight NAND timing parameters
from the NAND datasheet. The eight
parameters are:
m_NandTiming[0]=data_setup,
m_NandTiming[1]=data_hold,
m_NandTiming[2]=address_setup,
m_NandTiming[3]=dsample_time,
m_NandTiming[4]=nand_timing_state,
m_NandTiming[5]=REA,
m_NandTiming[6]=RLOH,
m_NandTiming[7]=RHOH.
The ROM only uses the first four parameters,
but the FCB provides space for other four
parameters to be used by the bootloader or
other applications.
PageDataSize 20 4 The number of bytes of data in a page.
Typically, this is 2048 bytes for 2112 bytes
page size or 4096 bytes for 4314/4224 bytes
page size or 8192 for 8568 bytes page size.
TotalPageSize 24 4 The total number of bytes in a page. Typically,
2112 for 2-KB page or 4224 or 4314 for 4-KB
page or 8568 for 8-KB page.
SectorsPerBlock 28 4 The number of pages per block. Typically 64 or
128 or depending on the NAND device type.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 807
System Boot

Table 6-15. Flash control block structure (continued)

Name Start byte Size in bytes Description
NumberOfNANDs 32 4 Not used by ROM
TotalInternalDie 36 4 Not used by ROM
CellType 40 4 Not used by ROM
EccBlockNEccType 44 4 Value from 0 to is used to set the BCH Error
Corrrection level 0, 2, 4, .. or 62 for Block BN of
ECC page, used in configuring the BCH62
page layout registers.
EccBlock0Size 48 4 Size of block B0 used in configuring the BCH62
page-layout registers.
EccBlockNSize 52 4 Size of block BN used in configuring the
BCH62 page-layout registers.
EccBlock0EccType 56 4 Value from 0 to used to set the BCH Error
Corrrection level 0, 2, 4, .. or 62 for Block BN of
ECC page, used in configuring the BCH62
page layout registers.
MetadataBytes 60 4 Size of metadata bytes used in configuring the
BCH62 page-layout registers.
NumEccBlocksPerPage 64 4 Number of the ECC blocks BN not including
B0. This value is used in configuring the
BCH62 page-layout registers.
EccBlockNEccLevelSDK 68 4 Not used by ROM
EccBlock0SizeSDK 72 4 Not used by ROM
EccBlockNSizeSDK 76 4 Not used by ROM
EccBlock0EccLevelSDK 80 4 Not used by ROM
NumEccBlocksPerPageSDK 84 4 Not used by ROM
MetadataBytesSDK 88 4 Not used by ROM
EraseThreshold 92 4 Not used by ROM
Firmware1_startingPage 104 4 Page number address where the first copy of
bootable firmware is located.
Firmware2_startingPage 108 4 Page number address where the second copy
of bootable firmware is located.
PagesInFirmware1 112 4 Size of the first copy of firmware in pages.
PagesInFirmware2 116 4 Size of the second copy of firmware in pages.
DBBTSearchAreaStartAddress 120 4 Page address for the bad block table search
area.
BadBlockMarkerByte 124 4 This is an input offset in the BCH page for the
ROM to swap with the first byte of metadata
after reading a page using the BCH62. The
ROM supports the restoration of manufacturer-
marked bad block markers in the page and this
offset is the bad block marker offset location.
BadBlockMarkerStartBit 128 4 This is an input bit offset in the
BadBlockMarkerByte for the ROM to use when
swapping eight bits with the first byte of
metadata.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

808 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-15. Flash control block structure (continued)

Name Start byte Size in bytes Description
BBMarkerPhysicalOffset 132 4 This is the offset where the manufacturer
leaves the bad block marker on a page.
BCHType 136 4 0 for BCH20 and 1 for BCH62. The chip is
backwards compatible to BCH20 and this field
tells the ROM to use the BCH20 or BCH62
block.
TMTiming2_ReadLatency 140 4 Toggle mode NAND timing parameter read
latency, the ROM uses this value to configure
the timing2 register of the GPMI.
TMTiming2_PreambleDelay 144 4 Toggle mode NAND timing parameter
Preamble Delay. The ROM uses this value to
configure the timing2 register of the GPMI.
TMTiming2_CEDelay 148 4 Toggle mode NAND timing parameter CE
Delay. The ROM uses this value to configure
the timing2 register of the GPMI.
TMTiming2_PostambleDelay 152 4 Toggle mode NAND timing parameter
Postamble Delay. The ROM uses this value to
configure the timing2 register of the GPMI.
TMTiming2_CmdAddPause 156 4 Toggle mode NAND timing parameter Cmd
Add Pause. The ROM uses this value to
configure the timing2 register of the GPMI.
TMTiming2_DataPause 160 4 Toggle mode NAND timing parameter Data
Pause. The ROM uses this value to configure
the timing2 register of the GPMI.
TMSpeed 164 4 This is the toggle mode speed for the ROM to
configure the gpmi clock. 0 for 33 MHz, 1 for 40
MHz, and 2 for 66 MHz.
TMTiming1_BusyTimeout 168 4 Toggle mode NAND timing parameter Busy
Timeout. The ROM uses this value to configure
the timing1 register of the GPMI.
DISBBM 172 4 If 0, the ROM swaps the BadBlockMarkerByte
with metadata[0] after reading a page using the
BCH62. If the value is 1, the ROM does not
swap.
BBMark_spare_offset 176 4 The offset in the metadata place which stores
the data in the bad block marker place.
Onfi_sync_enable 180 4 Enable the Onfi nand sync mode support.
Onfi_sync_speed 184 4 Speed for the Onfi nand sync mode:
0 - 24 MHz, 1 - 33 MHz, 2 - 40 MHz, 3 - 50
MHz, 4 - 66 MHz, 5 - 80 MHz, 6 - 100 MHz, 7 -
133 MHz, 8 - 160 MHz, 9 - 200 MHz
Onfi_syncNANDData 188 28 The parameters for the Onfi nand sync mode
timing. They are read latency, ce_delay,
preamble_delay, postamble_delay,
cmdadd_pause, data_pause, and
busy_timeout.
DISBB_Search 216 4 Disable the bad block search function when
reading the firmware, only using DBBT.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 809
System Boot

The FCB data structure is protected using a 62-bit ECC. The layout of the FCB page is
illustrated in this figure:

Meta D0 D1 D2 D3

parity

parity

parity

parity
32B 128B 128B 128B 128B

D4 D5 D6 D7

parity

parity

parity

parity
128B 128B 128B 128B

Figure 6-7. Layout of the FCB page

The detailed parameters of the FCB pages are listed in this table:
Table 6-16. Parameters setting for FCB page
Parameter Value
TotalPageSize 2048+64=2112
MetadataBytes 32
EccBlock0Size 128
EccBlock0EccType 31
BCHType 0
EccBlockNSize 128
EccBlockNEccType 31
NumEccBlocksPerPage 7

To reduce the disturbances caused by a neighboring cell in the FCB page in the NAND
chip, a randomizer is enabled when reading the FCB page. BCH ECC has a Randomizer
module that is interfaced through the GPMI APBHDMA chain. The Randomizer can
generate random data based on BCH ECC encoded/decoded data. It can be employed to
reduce the disturbances caused by a neighboring cell in the NAND chip, thus reducing bit
errors. The randomizer is used to reduce the bit errors in the FCB. Ensure that the
randomizer is enabled when burning the FCB pages in the NAND flash. To control the
randomizer for the pages (except for FCB), a new field called Randomizer_Enable is
added into the FCB structure. If the Randomizer_Enable field is set to 0, the randomizer
is disabled. Reading the pages (except for FCB) being set to a non-zero value enables the
randomizer. For detailed randomizer information, see Randomizer.

6.1.5.3.4 Discovered Bad Block Table (DBBT)

See this table for the DBBT format:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

810 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-17. DBBT structure

Name Start byte Size in bytes Description
reserved 0 4 -
FingerPrint 4 4 32-bit word with a value of 0x44424254,in
ascii "DBBT"
Version 8 4 32-bit version number; this version of
DBBT is 0x00000001
reserved 12 4 -
DBBT_NUM_OF_PAGES 16 4 Size of the DBBT in pages
reserved 20 4*PageSize-20 -
reserved 4*PageSize 4 -
Number of Entries 4*PageSize + 4 4 Number of bad blocks
Bad Block Number 4*PageSize + 8 4 First bad block number
Bad Block Number 4*PageSize + 12 4 Second bad block number
- - - Next bad block number
- - - -
Last bad block number - - Last bad block number

6.1.5.3.5 Bad block handling in ROM

During the firmware boot, at the block boundary, the Bad Block table is searched for a
match to the next block.
If no match is found, the next block can be loaded. If a match is found, the block must be
skipped and the next block checked.
If the Bad Block table start page is null, check the manufactory made Bad Block marker.
The location of the Bad Block maker is at the first three or last three pages in every block
of the NAND flash. The NAND manufacturers normally use one byte in the spare area of
certain pages within a block to mark that a block is bad or not. A value of 0xFF means
good block, non-FF means bad block.
To preserve the BI (bad block information), the flash updater or gang programmer
applications must swap the Bad Block Information (BI) data to byte 0 of the metadata
area for every page before programming the NAND flash. When the ROM loads the
firmware, it copies back the value at metadata[0] to the BI offset in the page data. This
figure shows how the factory bad block marker is preserved:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 811
System Boot

Bad block information at

column address 2048

64 B
2 KB Main area spare

512 main parity 512 main parity 512 main parity 512 main parity

meta
data Bad block information at
fourth block of data area
Swap byte

Figure 6-8. Factory bad block marker preservation

In the FCB structure, there are two elements (m_u32BadBlockMarkerByte and

m_u32BadBlockMarkerStartBit) to indicate the byte and bit place in the page data that
the manufacturer marked the bad block marker.

6.1.5.3.6 Toggle mode DDR NAND boot

If the BT_TOGGLEMODE efuse is blown, the ROM does the following to boot from the
Samsung's toggle mode DDR NAND.

6.1.5.3.6.1 GPMI and BCH clocks configuration

The ROM sets the clock source and the dividers in the CCM registers.
If the is set (toggle mode), the GPMI/BCH CLK source is PLL2PFD4, and running at 66
MHz, otherwise the GPMI/ BCH CLK souce is PLL3, running at 24 MHz. The ROM sets
the default values to timing0, timing1, and timing2 gpmi registers for 24 MHz clock
speed. It uses the fuse to configure the GPMI timing2 register parameters preamble delay
and read latency. The default value for these parameters is 2 when the fuses are not
blown.
The default timing parameter values used by the ROM for the toggle-mode device are:
• Timing0.ADDRESS_SETUP = 5
• Timing0.DATA_SETUP = 10
• Timing0.DATA_HOLD = 10
• Timing1.DEVICE_BUSY_TIMEOUT = 0 x 500

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

812 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

• Timing2.READ_LATENCY = if blown, otherwise 2

• Timing2.CE_DELAY = 2
• Timing2.PREAMBLE_DELAY = if blown, otherwise 2
• Timing2.POSTAMBLE_DELAY = 3
• Timing2.CMDADD_PAUSE = 4
• Timing2.DATA_PAUSE = 6
The default timing parameters can be overriden by the TMTiming2_ReadLatency,
TMTiming2_PreambleDelay, TMTiming2_CEDelay, TMTiming2_PostambleDelay,
TMTiming2_CmdAddPause, and TMTiming2_DataPause parameters of the FCB.

6.1.5.3.6.2 Setup DMA for DDR transfers

In the DMA descriptors, the GPMI is configured to read the page data at a double data
rate, the word length is set to 16, and the transfer count to a half of the page size.

6.1.5.3.6.3 Reconfigure timing and speed using values in FCB

After reading the FCB page with the GPMI set to default timings and a speed of 33 MHz,
the ROM reconfigures the CCM dividers to run the gpmi/bch clks to a desired speed
specified in the FCB for the rest of the boot process. The GPMI timing registers are also
reconfigured to the values specified in the FCB.
The GPMI speed can be configured using the FCB parameter TMSpeed:
• 0—25 MHz
• 1—33 MHz
• 2—40 MHz
• 3—50 MHz
• 4—66 MHz
• 5—80 MHz
• 6—100 MHz
• 7—133 MHz
• 8—133 MHz
• 9—200 MHz
The GPMI timing0 register fields data_setup, data_hold, and address_setup are set to the
values specified for the data_setup and data_hold and address_setup in the FCB member
m_NANDTiming.
The GPMI timing1.DEVICE_BUSY_TIMEOUT is set to the value specified in the FCB
member TMTiming1_BusyTimeout.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 813
System Boot

The GPMI timing2 register values are set using the FCB members
TMTiming2.READ_LATENCY, CE_DELAY, PREAMBLE_DELAY,
POSTAMBLE_DELAY, CMDADD_PAUSE, and DATA_PAUSE.

6.1.5.3.7 Typical NAND page organization

6.1.5.3.7.1 BCH ECC page organization

The first data block is called block 0 and the rest of the blocks are called block N. A
separate ECC level scan is used for block 0 and block N.
The metadata bytes must be located at the beginning of a page, starting at byte 0,
followed by the data block 0, the ECC bytes for data block 0, the block 1 and its ECC
bytes, and so on, up until the N data blocks. The ECC level for the block 0 can be
different from the ECC level for the rest of the blocks.
For the NAND boot with page-size restrictions and the data block size restricted to 512
B, only few combinations of the ECC for block 0 and block N are possible.
This figure shows the valid layout for 2112-byte sized page.

Block0 Block1 Block2 Block3

M 512 bytes EccB0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN

Figure 6-9. Valid layout for 2112-byte sized page

The example below is for 13 bits of parity (GF13). The number of ECC bits required for
a data block is calculated using the (ECC_Correction_Level * 13) bits.
In the above layout, the ECC size for EccB0 and EccBN must be selected to not exceed a
total page size of 2112 bytes. The EccB0 and EccBN can be one of the 2, 4, 6, 8, 10, 12,
14, 16, 18, and 20 bits on the ECC correction level. The total bytes are:
[M + (data_block_size x 4) + ([EccB0 + (EccBN x 3)] x 13) / 8] <= 2112;
M = metadata bytes and data_block_size is 512.
There are four data blocks of 512 bytes each in a page of 2-KB page sized NAND. The
values of EccB0 and EccBN must be such that the above calculation does not result in a
value greater than 2112 bytes.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

814 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Block0 Block1 Block2 Block3

M 512 bytes EccB0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN

Block4 Block5 Block6 Block7

512 bytes EccBN 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN

Figure 6-10. Valid layout for 4-KB sized page

Different NAND manufacturers have different sizes for a 4-KB page; 4314 bytes is
typical.
[M + (data_block_size x 8) + ([EccB0 + (EccBN x 7)] x 13) / 8] <= 4314;
M= metadata bytes and data_block_size is 512.
There are eight data blocks of 512 bytes each in a page of a 4-KB page sized NAND. The
values of the EccB0 and EccBN must be such that the above calculation does not result in
a value greater than the size of a page in a 4-KB page NAND.

6.1.5.3.7.2 Metadata
The number of bytes used for the metadata is specified in the FCB. The metadata for the
BCH encoded pages is placed at the beginning of a page. The ROM only cares about the
first byte of metadata to swap it with a bad block marker byte in the page data after each
page read; it is important to have at least one byte for the metadata bytes field in the FCB
data structure.

6.1.5.3.8 IOMUX configuration for NAND

The following table shows the RawNAND IOMUX pin configuration.
Table 6-18. NAND IOMUX pin configuration
Signal Pad name
NAND_CLE SD3_CLK.alt1
NAND_ALE SD3_CMD.alt1
NAND_WP_B SAI1_MCLK.alt1
NAND_RE_B SD3_STROBE.alt1
NAND_WE_B SD3_RESET_B.alt1
NAND_READY_B SAI1_TXD.alt1
NAND_DQS SAI1_TXFS.alt1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 815
System Boot

Table 6-18. NAND IOMUX pin configuration (continued)

NAND_CE0_B SAI1_TXC.alt1
NAND_DATA00 SD3_DATA0.alt1
NAND_DATA01 SD3_DATA1.alt1
NAND_DATA02 SD3_DATA2.alt2
NAND_DATA03 SD3_DATA3.alt3
NAND_DATA04 SD3_DATA4.alt4
NAND_DATA05 SD3_DATA5.alt5
NAND_DATA06 SD3_DATA6.alt6
NAND_DATA07 SD3_DATA7.alt7

6.1.5.4 Expansion device

The ROM supports booting from the MMC/eMMC and SD/eSD compliant devices.

6.1.5.4.1 Expansion device eFUSE configuration

The SD/MMC/eSD/eMMC/SDXC boot can be performed using either USDHC ports,
based on the setting of the BOOT_CFG[11:10] (Port Select) fuse or it is associated to the
GPIO input value at the boot.
All USDHC ports support the fast boot. See this table for details:
Table 6-19. USDHC boot eFUSE descriptions
Fuse Config Definition GPIO1 Shippe Settings
d value
BOOT_CFG[7] OEM Fast boot support Yes 000 0 - Normal boot
1 - Fast boot
BOOT_CFG[6:4] OEM Bus width Yes 000 0 - SD/eSD/SDXC
1 - MMC/eMMC
BOOT_CFG[3:1] OEM SD/MMC speed mode/ Yes 000 MMC speed selection
USDHC1 IO voltage
00 - Normal
selection
01 - High
else - Reserved

SD speed selection speed

000 - Normal/SDR12
001 - High/SDR25
010 - SDR50
011 - SDR104
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

816 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-19. USDHC boot eFUSE descriptions

(continued)
Fuse Config Definition GPIO1 Shippe Settings
d value
else - Reserved

USDHC1 IO VOLTAGE
SELECTION (only for MMC/eMMC
boot)
0 - 3.3 V
1 - 1.8 V
MMC Speed Mode Yes 00 MMC speed
(CFG[3:2]) selection
00 - Normal
01 - High
else - Reserved
USDHC1 IO Voltage Yes 0 USDHC1 IO
Selection (CFG[1]) VOLTAGE
SELECTION (only
for MMC/eMMC
boot)
0 - 3.3 V
1 - 1.8 V
BOOT_CFG[0] OEM USDHC2 IO VOLTAGE Yes 0 USDHC2 IO VOLTAGE
SELECTION (only for MMC/eMMC
boot)
0 - 3.3 V
1 - 1.8 V
BOOT_CFG[15:12] OEM Boot device selection Yes 0000 0001 - Boot from SD/eSD
0010 - Boot from MMC/eMMC
BOOT_CFG[11:10] OEM USDHC port selection Yes 00 00 - USDHC-1
01 - USDHC-2
10 - USDHC-3
else - reserved
BOOT_CFG[9] OEM SD power cycle enable/ Yes 0 SD power cycle/eMMC reset
eMMC reset enable
0 - Disabled
1 - Enabled
BOOT_CFG[8] OEM USDHC loopback clock Yes 0 USDHC loopback clock source
selection selection
0 - Through SD pad
1 - Direct
0x490[14:8] OEM SD/MMC DLL DLY No 0 Delay target for USDHC DLL, it is
config applied to the slave mode target
delay or overrides the mode target
delay, depending on the DLL
override fuse bit value.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 817
System Boot

Table 6-19. USDHC boot eFUSE descriptions

(continued)
Fuse Config Definition GPIO1 Shippe Settings
d value
0x490[15] OEM USDHC DLL override No 0 0 - No override
enabled
1 - Override
0x490[16] OEM USDHC DLL enabled No 0 0 - Disable the DLL for SD/eMMC
1 - Enable the DLL for SD/eMMC
0x490[17] OEM USDHC override pad 0 - Use default pad settings
settings selection
1 - Override the USDHC pad
settings by using the
PAD_SETTINGS value
0x490[18] OEM USDHC_IOMUX_SION_ No 0 0 - Disable
BIT_ENABLE
1 - Enable
0x490[19] OEM ENABLE_EMMC_5K_P No 0 0 - 47 K pullup
ULLUP
1 - 5 K pullup
0x490[20] OEM USDHC_PAD_PULL_D No 0 0 - No action
OWN
1 - Pull down
0x490[21] OEM Issue pre-idle command No 0 0 - Enable
enabled (for eMMC4.4)
1 - Disable
0x490[23] OEM Disable SDMMC No 0 0 - Enable
manufacture mode
1 - Disable
0X490[31:24] OEM USDHC pad setting No 0 Override pad settings default if
override 0X490[17] is set
0x4A0[0] OEM Fast boot acknowledge No 0 0 - Boot Ack disabled
enable
1 - Boot Ack enabled
0x4A0[1] OEM USDHC3 IO voltage No 0 0 - 3.3 V
selection
1 - 1.8 V
0x4A0[2] OEM uSDHC power-off No 0 0 - Low
polarity selection
1 - High
0x4A0[3] OEM uSDHC power cycle No 0 0 - 5 ms
delay selection
1 - 2.5 ms
0x4A0[5:4] OEM uSDHC power cycle No 0 00 - 20 ms
interval
01 - 10 ms
10 - 5 ms
11 - 2.5 ms

1. The setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See GPIO boot overrides for
the corresponding GPIO pin.

The boot code supports these standards:

• MMCv4.4 or less
• eMMCv5.0 or less

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

818 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

• SDv2.0 or less
• eSDv2.10 rev-0.9, with or without FAST_BOOT
• SDXCv3.0
The MMC/SD/eSD/SDXC/eMMC can be connected to any of the USDHC blocks and
can be booted by copying 4 KB of data from the MMC/SD/eSD/eMMC device to the
internal RAM. After checking the Image Vector Table header value (0xD1) from
program image, the ROM code performs a DCD check. After a successful DCD
extraction, the ROM code extracts from the Boot Data Structure the destination pointer
and length of image to be copied to the RAM device from where the code execution
occurs.
The maximum image size to load into the SD/MMC boot is 32 MB. This is due to a
limited number of uSDHC ADMA Buffer Descriptors allocated by the ROM.
NOTE
The initial 4 KB of the program image must contain the IVT,
DCD, and the Boot Data structures.
Table 6-20. SD/MMC frequencies
SD MMC MMC (DDR mode)
Identification (KHz) 347.22
Normal-speed mode (MHz) 25 20 25
High-speed mode (MHz) 50 40 50
UHSI SDR50 (MHz) 100
UHSI SDR104 (MHz) 200

NOTE
The boot ROM code reads the application image length and the
application destination pointer from the image.

6.1.5.4.2 MMC and eMMC boot

This table provides the MMC and eMMC boot details.
Table 6-21. MMC and eMMC boot details
Normal boot mode During the initialization (normal boot mode), the MMC
frequency is set to 347.22 KHz. When the MMC card enters
the identification portion of the initialization, the voltage
validation is performed, and the ROM boot code checks the
high-voltage settings and the card capacity. The ROM boot
code supports both the high-capacity and low-capacity MMC/
eMMC cards. After the initialization phase is complete, the
ROM boot code switches to a higher frequency (20 MHz in
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 819
System Boot

Table 6-21. MMC and eMMC boot details (continued)

the normal boot mode or 40 MHz in the high-speed mode).
The eMMC is also interfaced via the USDHC and follows the
same flow as the MMC.
The boot partition can be selected for an MMC4.x card after
the card initialization is complete. The ROM code reads the
BOOT_PARTITION_ENABLE field in the Ext_CSD[179] to get
the boot partition to be set. If there is no boot partition
mentioned in the BOOT_PARTITION_ENABLE field or the
user partition was mentioned, the ROM boots from the user
partition.
eMMC4.3 or eMMC4.4 device supporting special boot mode If using an eMMC4.3 or eMMC4.4 device that supports the
special boot mode, it can be initiated by pulling the CMD line
low. If the BOOT ACK is enabled, the eMMC4.3/eMMC4.4
device sends the BOOT ACK via the DATA lines and the
ROM can read the BOOT ACK [S010E] to identify the
eMMC4.3/eMMC4.4 device. If the BOOT ACK is enabled, the
ROM waits 50 ms to get the BOOT ACK. If BOOT ACK is
disabled ROM waits 1 second for data. If the BOOT ACK or
data was received, the eMMC4.3/eMMC4.4 is booted in the
"boot mode", otherwise the eMMC4.3/eMMC4.4 boots as a
normal MMC card from the selected boot partition. This boot
mode can be selected by the (fast boot) fuse. The BOOT ACK
is selected by the fuse.
eMMC4.4 device If using the eMMC4.4 device, the Double Data Rate (DDR)
mode can be used. This mode can be selected by the
BOOT_CFG2[7:5] (bus width) fuse.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

820 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Start

Check data bus width fuse.

. Accordingly
do the IOMUX config

eSDHC Software Reset, Set RSTA

Set Identification Frequency

(Approx 400 KHz)

Check MMC and Fast Boot Yes

6
Selection Fuse
No

Set INITA to send 80 SDCLK to card

Card SW Reset (CMD0)

No
Command Successful? 5

Yes

SD MMC
1 Check SD/MMC Selection fuse 2

Figure 6-11. Expansion device boot flow (1 of 6)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 821
System Boot

Set Strong pull-up

For CMD line

Start GPT with 1s delay MMC Boot Set MMC card CSD Set operating frequency MMC Boot
Voltage Validation (Issue CMD9) to 20 MHz Device Init
for CMD1
Set Weak pull-up Put card data Transfer
For CMD line Mode (Issue CMD7)
Issue CMD1 with HV Increment loop counter
Yes Yes
No No
Command Successful? Command Successful?
No Yes
Command Successful? 5
No Send CMD13 to read
Yes Set RCA (Issue CMD3) status
Yes Loop Cntr < 3000 and Yes
Busy Bit == 1 Yes
looping period < 1s Card State ==
No 5
Command Successful? TRANS?
No
Is Response OCR for Yes Yes
Card Is HC MMC
HC Get CID from card(Issue No
Spec ver >= 4.0?
CMD2)
No Yes
Card Is LC MMC
Send CMD8 to get
Ext_CSD

No Bus width No High Speed mode Extract the boot partition

fuse <> 1? fuse == 0? to set
Yes Yes No
Send switch command Got valid partition?
Send switch command
to change bus width and
to set high frequency
DDR mode Yes
Yes Yes
No No Send switch command
4 Switch Successful? Switch Successful? to select partition
Yes Yes
Change ESDHC bus Set operating frequency
width to 40 MHz

Start MMC Boot

Switch Command

Send CMD6 with switch

argument

No
Command Successful?

Yes
Set CMD13 poll timeout
to 100ms

Send CMD13 to read

status

Command Successful?

No Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes Yes

Switch failed Switch succeeded Switch failed

End

Figure 6-12. Expansion device (MMC) boot flow (2 of 6)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

822 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Issue CMD8 with HV

(3.3V) SD Boot
Voltage Validation
No Issue CMD8 with LV No
Command Successful? Command Successful?
(1.8V)
Yes Yes
Card is HC/LC HV SD
ver 2.x
Set ACMD41 ARG to LV Card is LC SD Card is LC SD
and HC ver 2.x ver 1.x
Set ACMD41 ARG to HV No
UHSI mode Set ACMD41 ARG bit 29
and HC selected? for FAST BOOT
Yes
Start GPT delay of1s for Set ACMD41 ARG to HV
Set ACMD41 ARG bit 24
ACMD41 and LC
for 1.8v switch

Issue CMD55
Set ACMD41 ARG bit 28
for SDXC power control
No
Command Successful?

Yes Yes
FAST_BOOT Yes
selected? No Loop Cntr < 3000 and
Issue ACMD41 2
looping period < 1s
No
No
Command Successful?

UHSI mode No Yes

Busy Bit == 1 Issue ACMD41
selected?
Yes

Bit 24 of response No
2
0 set?

Yes

No Is Response OCR for Yes

Card is LC SD Card is HC SD
HC

Figure 6-13. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 823
System Boot

8 SD Boot
Switch Voltage

Send CMD11 to switch

voltage

No
Command Successful?

Yes
No
DATA lines driven low?

Yes
switch supply voltage
to 1.8v

delay for 5ms

set DATA line voltage

high poll timeout to
1ms

No
Voltage high No DATA lines
poll timeout? driven high?

Yes Yes

Switch failed Switch succeeded

2 7

Figure 6-14. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 2

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

824 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Get CID from card(Issue

CMD2)
SD Boot
Device Initialization

Yes Yes Set operating frequency

Command Successful? Get RCA (Issue CMD3) Command Successful?
to 20 MHz

No No
Put card data Transfer
5 Mode (Issue CMD7)

No
No
Card State == Send CMD13 to read Yes
TRANS? Command Successful?
status
Yes

Yes
UHSI mode selected? 9

No

Yes Yes Send ACMD6 with bus Command Successful?

Bus width Send CMD55 Command Successful?
fuse <> 1? width argument Yes
No No
No

Change USDHC bus Yes Set CMD13 poll timeout

Success? Check Status
width to 100ms
No
High Speed mode
fuse == 0? Yes
Send CMD6 with high Yes Set operating frequency
No Command Successful?
speed argument to 40 MHz
No
Send CMD43 to select
10
partition 1

No
Command Successful? 4

Yes Set CMD13 poll timeout

to 15ms
FAST_BOOT Yes
Card is eSD
selected? Set CMD13 poll timeout Check Status
No to 1s

9 SD Boot
UHSI init

Check response of
CMD7

Yes No
Card is locked?

No
No Send ACMD6 with Yes
Command Successful? Command Successful? Send CMD55
argument of 4 bit width

Yes
Set CMD13 poll timeout Yes Change USDHC bus
Check Status Success?
to 100ms width
No

No Send CMD6 with clock Get clock speed from

Command Successful?
speed argument fuse

Yes

Change USDHC clock Loopback clock Yes Set loopback clock bit in
speed fuse set? USDHC register

No

Init failed
11

Figure 6-15. Expansion device (MMCSD/eSD/SDXC) boot flow (4 of 6)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 825
System Boot

SD Boot USB Boot

Check Status
Serial Boot
Start 5

Send CMD13 to read

status USB Flow
(Serial Boot)

No
Command Successful?

Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes
Failure Success Failure

End

4 SD/MMC Boot
Data Read

No Set block length 512

DDR Mode Selected?
bytes (Issue CMD16)

Yes

Init ADMA buffer Yes

Command Successful?
descriptors

No
Send CMD18 (multiple
block read)

Set CMD18 poll timeout

to 1s

Wait for command

completion or timeout

No
Command Successful? 5

Yes

End

Figure 6-16. Expansion device (SD/eSD) boot flow (5 of 6)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

826 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6
eMMC 4.x Boot
Fast Boot

High Speed mode Set operating frequency

fuse == 0? to 40 MHz

Set operating frequency

to 20 MHz

Change ESDHC bus

width and configure DLL

Setup ADMA BD[0]

length to 2K and BD[1]
to 32 bytes

Wait for block gap or Wait for block gap or

Set CMD line low Reached block gap? timeout
timeout

Set ESDHC poll counter Analyze IVT and setup

to 50ms ADMA buffer descriptors
to final destination
Wait for acknowledge
token or timeout Continue data trasmition

Acknowledge token Set GPT poll counter to Wait for block gap or
accepted? 1s timeout

End
2

SD Boot
11 sample point tuning

Set bottom boundary to

current value
Get start point and
ramping step from fuse

Increase current value

Set the USDHC into with ramping step
tuning mode

Yes
Set the USDHC into Exceed limit?
tuning mode
No
Configure the block
Set delay cell number to
length and block number
current value

Configure the block Send CMD19 to request

length and block number the tuning block

Send CMD19 to request

the tuning block Check the tuning status

Check the tuning status Yes

Tuning passed?
No
No
Exceed limit? No
Tuning passed?
Set upper boundary to
Yes last value
Yes

Increase current value

Tuning failed with ramping step Set delay cell number to
Tuning passed average of bottom and
upper boundary value

4 10

Figure 6-17. Expansion device boot flow (6 of 6)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 827
System Boot

6.1.5.4.3 SD, eSD, and SDXC

After the normal boot mode initialization begins, the SD/eSD/SDXC frequency is set to
347.22 kHz. During the identification phase, the SD/eSD/SDXC card voltage validation
is performed. During the voltage validation, the boot code first checks with the high-
voltage settings; if that fails, it checks with the low-voltage settings.
The capacity of the card is also checked. The boot code supports the high-capacity and
low-capacity SD/eSD/SDXC cards after the voltage validation card initialization is done.
During the card initialization, the ROM boot code attempts to set the boot partition for all
SD, eSD, and SDXC devices. If this fails, the boot code assumes that the card is a normal
SD or SDXC card. If it does not fail, the boot code assumes it is an eSD card. After the
initialization phase is over, the boot code switches to a higher frequency (25 MHz in the
normal-speed mode or 50 MHz in the high-speed mode).
For the UHSI cards, the clock speed fuses can be set to SDR50 or SDR104 on ports. This
enables the voltage switch process to set the signaling voltage to 1.8 V during the voltage
validation. The bus width is fixed at a 4-bit width and a sampling point tuning process is
needed to calibrate the number of the delay cells. If the SD Loopback Clock eFuse is set,
the feedback clock comes directly from the loopback SD clock, instead of the card clock
(by default). The SD clock speed can be selected by the BOOT_CFG[3:2], and the SD
Loopback Clock is selected by the BOOT_CFG[0].
The UHSI calibration start value (MMC_DLL_DLY[6:0]) and the step value can be set
to optimize the sample point tuning process.
If the SD Power Cycle Enable eFuse is 1, the ROM sets the SD_RST pad low, waits for 5
ms, and then sets the SD_RST pad high. If the SD_RST pad is connected to the SD
power supply enable logic on board, it enables the power cycle of the SD card. This may
be crucial in case the SD logic is in the 1.8 V states and must be reset to the 3.3 V states.

6.1.5.4.4 IOMUX configuration for SD/MMC

Table 6-22. SD/MMC IOMUX pin configuration
Signal USDHC1 USDHC2 USDHC3
CLK SD1_CLK.alt0 SD2_CLK.alt0 SD3_CLK.alt0
CMD SD1_CMD.alt0 SD2_CMD.alt0 SD3_CMD.alt0
DATA0 SD1_DATA0.alt0 SD2_DATA0.alt0 SD3_DATA0.alt0
DATA1 SD1_DATA1.alt0 SD2_DATA1.alt0 SD3_DATA1.alt0
DATA2 SD1_DATA2.alt0 SD2_DATA2.alt0 SD3_DATA2.alt0
DATA3 SD1_DATA3.alt0 SD2_DATA3.alt0 SD3_DATA3.alt0
DATA4 ECSPI2_SCLK.alt2 ECSPI1_SCLK.alt2 SD3_DATA4.alt0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

828 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-22. SD/MMC IOMUX pin configuration (continued)

Signal USDHC1 USDHC2 USDHC3
DATA5 ECSPI2_MOSI.alt2 ECSPI1_MOSI.alt2 SD3_DATA5.alt0
DATA6 ECSPI2_MISO.alt2 ECSPI1_MISO.alt2 SD3_DATA6.alt0
DATA7 ECSPI2_SS0.alt2 ECSPI1_SS0.alt2 SD3_DATA7.alt0
VSELECT GPIO1_IO08.alt1 GPIO1_IO12.alt1 GPIO1_IO13.alt1
RESET_B SD1_RESET_B.alt5 SD2_RESET_B.alt5 SD3_RESET_B.alt5
CD_B SD1_CD_B.alt0 - -

6.1.5.4.5 Redundant boot support for expansion device

The ROM supports the redundant boot for an expansion device. The primary or
secondary image is selected, depending on the PERSIST_SECONDARY_BOOT setting.
(see Table 6-8).
If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address 0x8400 for the
primary image.
If the PERSIST_SECONDARY_BOOT is 1, the boot ROM reads the secondary image
table from address 0x8200 on the boot media and uses the address specified in the table
for the secondary image.
Table 6-23. Secondary image table format
Reserved (chipNum)
Reserved (driveType)
tag
firstSectorNumber
Reserved (sectorCount)

Where:
• The tag is used as an indication of the valid secondary image table. It must be
0x00112233.
• The firstSectorNumber is the first 512-byte sector number of the secondary image.
For the secondary image support, the primary image must reserve the space for the
secondary image table. See this figure for the typical structures layout on an expansion
device.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 829
System Boot

0x00000000
Reserved for Guid
- 0x00007FFF
Partition Table (GPT)

0x00008000
Reserved for MBR
(
(optional))

0x00008200
Reserved for Secondary
Image Table (optional)

0x00008400

Program Image
(starting from IVT)

Media Partitions

Figure 6-18. Expansion device structures layout

For the Closed mode, if there are failures during primary image authentication, the boot
ROM turns on the PERSIST_SECONDARY_BOOT bit (see Table 6-8) and performs the
software reset. (After the software reset, the secondary image is used.)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

830 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.1.5.5 Serial NOR through SPI

The chip supports booting from serial memory devices, such as EEPROM and serial
flash, using the SPI.
These ports are available for serial boot: eCSPI (eCSPI1, eCSPI2, eCSPI3) interfaces.

6.1.5.5.1 Serial(SPI) NOR eFUSE configuration

The boot ROM code determines the type of device using the following parameters, either
provided by the eFUSE settings or sampled on the I/O pins, during boot.
See this table for details:
Table 6-24. Serial(SPI) NOR boot eFUSE descriptions
Fuse Config Definition GPIO1 Shipped Settings
value
BOOT_CFG[14:12] OEM Boot device selection Yes 0000 110 - Boot from the serial(SPI) NOR
BOOT_CFG[11:9] OEM ECSPI port selection Yes 000 000 - eCSPI1
001 - eCSPI2
010 - eCSPI3
BOOT_CFG[8] OEM SPI addressing Yes 0 0 - 3 B (24-bit)
1 - 2 B (16-bit)
0x480[25] OEM Recovery boot enable No 0 0 – Disabled
1 – Enabled
BOOT_CFG[7:6] OEM CS selection (SPI only) Yes 00 00 – CS#0
0x480[31:29] OEM Recovery port selection No 000 000 - eCSPI1
001 - eCSPI2
010 - eCSPI3
0x480[28] OEM Recovery SPI No 0 0 - 3 B (24-bit)
addressing
1 - 2 B (16-bit)
0x480[27:26] OEM Recovery CS selection No 00 00 - CS#0
(SPI only)

1. The setting can be overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See Table 1 for the
corresponding GPIO pin.

The ECPSI-1/ECPSI-2/ECPSI-3 block can be used as a boot device using the ECSPI
interface for the serial(SPI) NOR boot. The SPI interface is configured to operate at 12.5
MHz for 3-byte addressing devices and at 3.125 MHz for 2-byte addressing devices.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 831
System Boot

The boot ROM copies 4 KB of data from the serial ROM device to the internal RAM.
After checking the Image Vector Table header value (0xD1) from the program image, the
ROM code performs a DCD check. After a successful DCD extraction, the ROM code
extracts the destination pointer and length of image from the Boot Data Structure to be
copied to the RAM device from where the code execution occurs.
NOTE
The Initial 4 KB of program image must contain the IVT, DCD,
and the Boot Data Structures.

6.1.6 Program image

This section describes the data structures that are required to be included in the user's
program image. The program image consists of:
• Image vector table—a list of pointers located at a fixed address that the ROM
examines to determine where the other components of the program image are
located.
• Boot data—a table that indicates the program image location, program image size in
bytes, and the plugin flag.
• Device configuration data—IC configuration data.
• User code and data.

6.1.6.1 Image Vector Table and Boot Data

The Image Vector Table (IVT) is the data structure that the ROM reads from the boot
device supplying the program image containing the required data components to perform
a successful boot.
The IVT includes the program image entry point, a pointer to Device Configuration Data
(DCD) and other pointers used by the ROM during the boot process.The ROM locates
the IVT at a fixed address that is determined by the boot device connected to the Chip.
The IVT offset from the base address and initial load region size for each boot device
type is defined in the table below. The location of the IVT is the only fixed requirement
by the ROM. The remainder or the image memory map is flexible and is determined by
the contents of the IVT.
Table 6-25. Image Vector Table Offset and Initial Load Region Size
Boot Device Type Image Vector Table Offset Initial Load Region Size
NAND 1 Kbyte = 0x4000 bytes 8 Kbyte

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

832 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-25. Image Vector Table Offset and Initial Load Region Size (continued)
Boot Device Type Image Vector Table Offset Initial Load Region Size
SD/eSD/MMC/eMMC normal boot 33 Kbyte = 0x8400 bytes 8 Kbyte
eMMC Fast boot 1 Kbyte = 0x400 bytes 8 Kbyte
FlexSPI 4 Kbyte = 0x1000 bytes 8 Kbyte
ECSPI 1 Kbyte = 0x400 bytes 8 Kbyte

Initial
Load Region

Figure 6-19. Image Vector Table

6.1.6.1.1 Image vector table structure

The IVT has the following format where each entry is a 32-bit word:
Table 6-26. IVT format
header
entry: Absolute address of the first instruction to execute from the image
reserved1: Reserved and should be zero
dcd: Absolute address of the image DCD. The DCD is optional so this field may be set to NULL if no DCD is required. See
Device Configuration Data (DCD) for further details on the DCD.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 833
System Boot

Table 6-26. IVT format (continued)

boot data: Absolute address of the boot data
self: Absolute address of the IVT. Used internally by the ROM.
csf: Absolute address of the Command Sequence File (CSF) used by the HAB library. See High-Assurance Boot (HAB) for
details on the secure boot using HAB. This field must be set to NULL when not performing a secure boot
reserved2: Reserved and should be zero

Figure 6-20 shows the IVT header format:

Tag Length Version

Figure 6-20. IVT header format

where:
Tag: A single byte field set to 0xD1
Length: a two byte field in big endian format containing the overall length of the IVT,
in bytes, including the header. (the length is fixed and must have a value of
32 bytes)
Version: A single byte field set to 0x40 or 0x41

6.1.6.1.2 Boot data structure

The boot data must follow the format defined in the table found here, each entry is a 32-
bit word.
Table 6-27. Boot data format
start Absolute address of the image
length Size of the program image
plugin Plugin flag (see Plugin image)

6.1.6.2 Device Configuration Data (DCD)

Upon reset, the chip uses the default register values for all peripherals in the system.
However, these settings typically are not ideal for achieving the optimal system
performance and there are even some peripherals that must be configured before they can
be used.
The DCD is a configuration information contained in the program image (external to the
ROM) that the ROM interprets to configure various peripherals on the chip.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

834 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

For example, the EIM default settings allow the core to interface to a NOR flash device
immediately after the reset. This allows the chip to interface with any NOR flash device,
but has the disadvantage of slow performance. Additionally, some components (such as
DDR) require some sequence of register programming as a part of the configuration
before it is ready to be used. The DCD feature can be used to program the EIM registers
and the DDR Controller registers to the optimal settings.
The ROM determines the location of the DCD table based on the information located in
the Image Vector Table (IVT). See Image Vector Table and Boot Data for more details.
The DCD table shown below is a big-endian byte array of the allowable DCD commands.
The maximum size of the DCD is limited to 1768 B.

Header

[CMD]

[CMD]

...

Figure 6-21. DCD data format

The DCD header is 4 B with the following format:

Tag Length Version

Figure 6-22. DCD header format

where:
Tag: A single-byte field set to 0xD2
Length: a two-byte field in the big-endian format containing the overall length of the DCD
(in bytes) including the header
Version: A single-byte field set to 0x41

6.1.6.2.1 Write data command

The write data command is used to write a list of given 1-, 2- or 4-byte values (or
bitmasks) to a corresponding list of target addresses.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 835
System Boot

The format of the write data command (in a big-endian byte array) is shown in this table:
Table 6-28. Write data command format
Tag Length Parameter
Address
Value/Mask
[Address]
[Value/Mask]
...
[Address]
[Value/Mask]

where:
Tag: a single-byte field set to 0xCC
Length: a two-byte field in a big-endian format, containing the length of the Write Data
Command (in bytes) including the header
Address: the target address to which the data must be written
Value/Mask: the data value (or bitmask) to be written to the preceding address

The parameter field is a single byte divided into the bitfields, as follows:
Table 6-29. Write data command parameter field
7 6 5 4 3 2 1 0
flags bytes

where
bytes: the width of the target locations in bytes (either 1, 2, or 4)
flags: control flags for the command behavior
Data Mask = bit 3: if set, only specific bits may be overwritten at the target address
(otherwise all bits may be overwritten)
Data Set = bit 4: if set, the bits at the target address are overwritten with this flag
(otherwise it is ignored)

One or more target address and value/bitmask pairs can be specified. The same bytes' and
flags' parameters apply to all locations in the command.
When successful, this command writes to each target address in accordance with the flags
as follows:
Table 6-30. Interpretation of write data command flags
"Mask" "Set" Action Interpretation
0 0 *address = val_msk Write value
0 1 *address = val_msk Write value
1 0 *address &= ~val_msk Clear bitmask
1 1 *address |= val_msk Set bitmask

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

836 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

NOTE
If any of the target addresses does not have the same alignment
as the data width indicated in the parameter field, none of the
values are written.
If any of the values are larger or any of the bitmasks are wider
than permitted by the data width indicated in the parameter
field, none of the values are written.
If any of the target addresses do not lie within the allowed
region, none of the values are written. The list of allowable
blocks and target addresses for the chip are provided below.

6.1.6.2.2 Check data command

The check data command is used to test for a given 1-, 2-, or 4-byte bitmasks from a
source address.
The check data command is a big-endian byte array with the format shown in this table:
Table 6-31. Check data command format
Tag Length Parameter
Address
Mask
[Count]

where:
Tag: a single-byte field set to 0xCF
Length: a two-byte field in the big-endian format containing the length of the check data
command (in bytes) including the header
Address: the source address to test
Mask: the bit mask to test
Count: an optional poll count; If the count is not specified, this command polls
indefinitely
until the exit condition is met. If count = 0, this command behaves as for the NOP.

The parameter field is a single byte divided into bitfields, as follows:

Table 6-32. Check data command parameter field
7 6 5 4 3 2 1 0
flags bytes

where
bytes: the width of target locations in bytes (either 1, 2, or 4)
flags: control flags for the command behavior
Data Mask = bit 3: if set, only the specific bits may be overwritten at a target address

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 837
System Boot
(otherwise all bits may be overwritten)
Data Set = bit 4: if set, the bits at the target address are overwritten with this flag
(otherwise it is ignored)

This command polls the source address until either the exit condition is satisfied, or the
poll count is reached. The exit condition is determined by the flags as follows:
Table 6-33. Interpretation of check data command flags
"Mask" "Set" Action Interpretation
0 0 (*address & mask) == 0 All bits clear
0 1 (*address & mask) == mask All bits set
1 0 (*address & mask)!= mask Any bit clear
1 1 (*address & mask)!= 0 Any bit set

NOTE
If the source address does not have the same alignment as the
data width indicated in the parameter field, the value is not
read.
If the bitmask is wider than permitted by the data width
indicated in the parameter field, the value is not read.

6.1.6.2.3 NOP command

This command has no effect.
The format of the NOP command is a big-endian four-byte array, as shown in this table:
Table 6-34. NOP command format
Tag Length Undefined

where:
Tag: a single-byte field set to 0xC0
Length: a two-byte field in big endian containing the length of the NOP command in bytes
(fixed to a
value of 4)
Undefined: this byte is ignored and can be set to any value.

6.1.6.2.4 Unlock command

The unlock command is used to prevent specific engine features from being locked when
exiting the ROM.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

838 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

The format of the unlock command (in a big-endian byte array) is shown in this table:
Table 6-35. Unlock command format
Tag Length Eng
Value
Value
...
Value

where:
NOTE
This command may not be used in the DCD structure if the
SEC_CONFIG is configured as closed.

6.1.7 Plugin image

The ROM supports a limited number of boot devices. When using other devices as a boot
source (for example, Ethernet, CDROM, or USB), the supported boot device must be
used (typically serial(SPI) NOR) as a firmware to provide the missing boot drivers.
Additionally, the plugin can be customized to support boot drivers, which is more
flexible when performing the device initialization, such as condition judging, delay
assertion, or to apply custom settings to the boot device and memory system.
In addition to the standard images, the chip also supports plugin images. The plugin
images return the execution to the ROM whereas the standard image does not.
The boot ROM detects the image type using the plugin flag of the boot data structure (see
Boot data structure). If the plugin flag is 1, then the ROM uses the image as a plugin
function. The function must initialize the boot device and copy the program image to the
final location. At the end, the plugin function must return with the program image
parameters. (See High-level boot sequence for details about the boot flow).
The boot ROM authenticates the plugin image before running the plugin function and
then authenticates the program image.
The plugin function must follow the API described below:
typedef BOOLEAN (*plugin_download_f)(void **start, size_t *bytes, UINT32
*ivt_offset);
ARGUMENTS PASSED:
• start - the image load address on exit.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 839
System Boot

• bytes - the image size on exit.

• ivt_offset - the offset (in bytes) of the IVT from the image start address on exit.
RETURN VALUE:
• 1 - success
• 0 - failure

6.1.8 Serial Downloader

The Serial Downloader provides a means to download a program image to the chip over
the USB serial connection.
In this mode, the ROM programs the WDOG1 for a time-out specified by the fuse
WDOG Time-out Select (See fusemap for details) if the WDOG_ENABLE eFuse is 1
and continuously polls for the USB connection. If no activity is found on the USB OTG1
and the watchdog timer expires, the Arm core is reset.
NOTE
After the downloaded image is loaded, it is responsible for
managing the watchdog resets properly.
This figure shows the USB boot flow:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

840 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

START

Configure USBOTG1,
, program WDOG for 32 sec timer

Poll USBOTG1 No

WDOG_ENABLE
Activity
No == 1 &&
Detected WDOG timeout

Yes

Yes

Complete USB HID enumeration

Ready for Serial

Reset
Download

Figure 6-23. Serial Downloader boot flow

NOTE
Before going into USB serial mode, Boot ROM detect
SD/MMC card on USDHC2 port. If a card is inserted, ROM
will try to boot from it. This is the so-called Manufacture
SD/MMC boot. This feature can be disabled by blowing fuse
“Disable SD/MMC Manufacture Mode”. See SD/MMC
manufacture mode for details.

6.1.8.1 USB
The USB support is composed of the USB (core controller, compliant with the USB 2.0
specification) and the USBPHY (HS USB transceiver).
The ROM supports the USB OTG port for boot purposes. The other USB ports on the
chip are not supported for boot purposes.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 841
System Boot

The USB Driver is implemented as a USB HID class. A collection of four HID reports
are used to implement the SDP protocol for data transfers, as described in Table 6-36.
Table 6-36. USB HID reports
Report ID (first byte) Transfer endpoint Direction Length Description
1 control OUT Host to device 17 B SDP command from the
host to the device.
2 control OUT Host to device Up to 1025 B Data associated with
the report 1 SDP
command.
3 interrupt Device to host 5B HAB security
configuration. The
device sends
0x12343412 in the
closed mode and
0x56787856 in the
open mode.
4 interrupt Device to host Up to 65 B Data in response to the
SDP command in report
1.

6.1.8.1.1 USB configuration details

The USB OTG function device driver supports a high speed (HS for UTMI) non-stream
mode with a maximal packet size of 512 B and a low-level USB OTG function.
The VID/PID and strings for the are listed in the following table.
Table 6-37. VID/PID and strings for USB device driver
Descriptor Value
VID 0x1FC9
(NXP vendor ID)
PID1 0x012B
String Descriptor1 (manufacturer) NXP Semiconductors
String Descriptor2 (product)
SE Blank

SP Blank
NS Blank

FR Blank
String Descriptor4 NXP Flash
String Descriptor5 NXP Flash

1. Allocation based on the BPN (Before Part Number)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

842 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.1.8.1.2 IOMUX configuration for USB

The interface signals of the UTMI PHY are not configured in the IOMUX,, except for the
USB_OTGn_ID pins. The USB ID pin function is configured using the
USBNC_n_CTRL2[ID_DIG_SEL] and the
IOMUXC_USB_OTGn_ID_SELECT_INPUT register. The remaining pins of the UTMI
PHY interface use the dedicated contacts on the IC. See the chip data sheet for details.

6.1.8.2 Serial Download Protocol (SDP)

The 16-byte SDP command from the host to device is sent using the HID report 1.
This table describes the 16-byte SDP command data structure:
Table 6-38. 16-byte SDP command data structure
BYTE offset Size Name Description
0 2 COMMAND TYPE These commands are supported for the ROM:
• 0x0101 READ_REGISTER
• 0x0202 WRITE_REGISTER
• 0x0404 WRITE_FILE
• 0x0505 ERROR_STATUS
• 0x0A0A DCD_WRITE
• 0x0B0B JUMP_ADDRESS
2 4 ADDRESS Only relevant for these commands:
READ_REGISTER, WRITE_REGISTER, WRITE_FILE,
DCD_WRITE, and JUMP_ADDRESS.
For the READ_REGISTER and WRITE_REGISTER
commands, this field is the address to a register. For the
WRITE_FILE and JUMP_ADDRESS commands, this
field is an address to the internal or external memory
address.
6 1 FORMAT Format of access, 0x8 for an 8-bit access, 0x10 for a 16-
bit access, and 0x20 for a 32-bit access. Only relevant
for the READ_REGISTER and WRITE_REGISTER
commands.
7 4 DATA COUNT Size of the data to read or write. Only relevant for the
WRITE_FILE, READ_REGISTER, WRITE_REGISTER,
and DCD_WRITE commands. For the WRITE_FILE and
DCD_WRITE commands, the DATA COUNT is in the
byte units.
11 4 DATA The value to write. Only relevant for the
WRITE_REGISTER command.
15 1 RESERVED Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 843
System Boot

6.1.8.2.1 SDP commands

The SDP commands are described in the following sections.

6.1.8.2.1.1 READ_REGISTER
The transaction for the READ_REGISTER command consists of these reports: Report1
for the command, Report3 for the security configuration, and Report4 for the response or
the register value.
The register to read is specified in the ADDRESS field of the SDP command. The first
device sends Report3 with the security configuration followed by the Report4 with the
bytes read at a given address. If the count is greater than 64, multiple reports with the
report id 4 are sent until the entire data requested by the host is sent. The STATUS is
either 0x12343412 for the closed parts and 0x56787856 for the open or field return parts.
Report1, Command, Host to Device:
1 Valid values for the READ_REGISTER COMMAND, ADDRESS, FORMAT, DATA_COUNT

ID 16-byte SDP command

Report3, Response, Device to Host:
3 Four bytes indicating the security configuration

ID 4 bytes status
Report4, Response, Device to Host: first response report
4 Register value

ID 4 bytes of data containing the register value. If the number of bytes requested is less
than 4, the remaining bytes must be ignored by the host.
Multiple reports of the report id 4 are sent until the entire requested data is sent.
Report4, Response, Device to Host: last response report
4 Register value

ID 64 bytes of data containing the register value. If the number of bytes requested is less
than 64, the remaining bytes must be ignored by the host.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

844 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.1.8.2.1.2 WRITE_REGISTER
The transaction for the WRITE_REGISTER command consists of these reports: Report1
for the command, Report3 for the security configuration and Report4 for the write status.
The host sends Report1 with the WRITE_REGISTER command. The register to write is
specified in the ADDRESS field of the SDP command of Report1, with the FORMAT
field set to the data type (number of bits to write, either 8, 16, or 32) and the value to
write in the DATA field of the SDP command. The device writes the DATA to the
register address and returns the WRITE_COMPLETE code using Report4 and the
security configuration using Report3 to complete the transaction.
Report1, Command, Host to Device:
1 Valid values for WRITE_REGISTER COMMAND, ADDRESS, FORMAT, DATA_COUNT and DATA

ID 16-byte SDP command

Report3, Response, Device to Host:
3 4 bytes indicating the security configuration

ID 4 bytes status
Report4, Response, Device to Host:
4 WRITE_COMPLETE (0x128A8A12) status

ID 64 bytes data with the first 4 bytes to indicate that the write is completed with code
0x128A8A12. On failure, the device reports the HAB error status.

6.1.8.2.1.3 WRITE_FILE
The transaction for the WRITE_FILE command consists of these reports: Report1 for the
command phase, Report2 for the data phase, Report3 for the HAB mode, and Report4 to
indicate that the data are received in full.
The size of each Report2 is limited to 1024 bytes (limitation of the USB HID protocol).
Hence, multiple Report2 packets are sent by the host in the data phase until the entire
data is transferred to the device. When the entire data (DATA_COUNT bytes) is
received, the device sends Report3 with the HAB mode and Report4 with 0x88888888,
indicating that the file download completed.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 845
System Boot

Report1, Host to Device:

1 Valid values for WRITE_FILE COMMAND, ADDRESS, DATA_COUNT

ID 16-byte SDP command

========================Optional Begin=================
Host sends the ERROR_STATUS command to query if the HAB rejected the address
======================== Optional End==================
Report2, Host to Device:
2 File data

ID Max 1024 bytes data per report

Report2, Host to Device:

2 File data

ID Max 1024 bytes data per report

Report3, Device to Host:

3 4 bytes indicating security configuration

ID 4 bytes status

Report4, Response, Device to Host:

4 COMPLETE (0x88888888) status

ID 64 bytes data with the first four bytes to indicate that the file download completed
with code 0x88888888. On failure, the device reports the HAB error status.

6.1.8.2.1.4 ERROR_STATUS
The transaction for the SDP command ERROR_STATUS consists of three reports.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

846 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Report1 is used by the host to send the command; the device sends global error status in
four bytes of Report4 after returning the security configuration in Report3. When the
device receives the ERROR_STATUS command, it returns the global error status that is
updated for each command. This command is useful to find out whether the last
command resulted in a device error or succeeded.
Report1, Command, Host to Device:
1 ERROR_STATUS COMMAND

ID 16-byte SDP Command

Report3, Response, Device to Host:
3 Four bytes indicating the security configuration

ID 4 bytes status
Report4, Response, Device to Host:
4 Four bytes Error status

ID first 4 bytes status in 64 bytes Report4

6.1.8.2.1.5 DCD_WRITE
The SDP command DCD_WRITE is used by the host to send multiple register writes in
one shot. This command is provided to speed up the process of programming the register
writes (such as to configure an external RAM device).
The command goes with Report1 from the host with COMMAND TYPE set to
DCD_WRITE, ADDRESS which is used as a temporary location of the DCD data, and
DATA_COUNT to the number of bytes sent in the data out phase. In the data phase, the
host sends the data for a number of registers using Report2. The device completes the
transaction with Report3 indicating the security configuration and Report4 with the
WRITE_COMPLETE code 0x12828212.
Report1, Command, Host to Device:
1 DCD_WRITE COMMAND, ADDRESS, DATA_COUNT

ID 16-byte SDP Command

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 847
System Boot

Report2, Data, Host to Device:

2 DCD binary data

ID Max 1024 bytes per report

Report3, Response, Device to Host:
3 Four bytes indicating the security configuration

ID 4 bytes status
Report4, Response, Device to Host:
4 WRITE_COMPLETE (0x128A8A12) status

ID 64 bytes report with the first four bytes to indicate that the write completed with the
code 0x128A8A12. On failure, the device reports the HAB error status.
See Device Configuration Data (DCD) for the DCD format description.

6.1.8.2.1.6 SKIP_DCD_HEADER
The SDP command SKIP_DCD_HEADER is used by the host to inform the device to
skip the DCD configuration within the download image.
If the download image must be run on the DDR, the DCD configuration data must be
built into the image. In case the host issued DCD_WRITE to push the DCD configuration
data to the device for the DDR initialization, the image with the DCD information causes
the ROM to initialize the DDR twice, and may cause the initialization processing to hang.
The SKIP_DCD_HEADER command informs the device to skip the DCD configuration
within the download image and avoid this issue.
This command is typically sent after JUMP_ADDRESS. This command is sent by the
host in the command-phase of the transaction using Report1, there is no data phase for
this command. The device completes the transaction with Report3 indicating the security
configuration and Report4 with the OK_ACK code 0x900DD009.
Report1, Command, Host to Device:
1 SKIP_DCD_HEADER

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

848 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

ID 16-byte SDP Command

Report3, Response, Device to Host:
3 Four bytes indicating the security configuration

ID 4 bytes status
Report4, Response, Device to Host:
4 OK_ACK (0x900DD009)

6.1.8.2.1.7 JUMP_ADDRESS
The SDP command JUMP_ADDRESS is the last command that the host can send to the
device. After this command, the device jumps to the address specified in the ADDRESS
field of the SDP command and starts to execute.
This command usually follows after the WRITE_FILE command. The command is sent
by the host in the command-phase of the transaction using Report1. There is no data
phase for this command, but the device sends the status Report3 to complete the
transaction. If the authentication fails, it also sends Report4 with the HAB error status.
Report1, Command, Host to Device:
1 JUMP_ADDRESS COMMAND, ADDRESS

ID 16-byte SDP Command

Report3, Response, Device to Host:
3 Four bytes indicating the security configuration

ID 4 bytes status
This report is sent by the device only in case of an error jumping to the given address, or
if the device reports error in Report4, Response, Device to Host:
4 Four bytes HAB error status

ID 4 bytes status, 64 bytes report length

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 849
System Boot

6.1.9 Recovery devices

The chip supports recovery devices. If the primary boot device fails, the boot ROM tries
to boot from the recovery device using the USDHC2 port.

6.1.10 Low-power boot

The ROM supports the low-power boot. If the LPB_BOOT fuses are blown, the chip
checks if there is a low-power condition via the pad. If there is a low-power boot
condition, the ROM applies division factors on the ARM, DDR, AXI, and AHB root
clocks based on the LPB_BOOT fuses value (see the table below). The polarity of the
low-power boot condition on the pad is set by the BT_LPB_POLARITY fuse (see the
following figure).
Table 6-39. Low-power boot frequencies
LPB_BOOT Boot Frequencies=0 Boot Frequencies=1
00 ARM_A53_CLK_ROOT= 1000 MHz ARM_A53_CLK_ROOT= 500 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 333 MHz MAIN_AXI_CLK_ROOT= 166 MHz
01 ARM_A53_CLK_ROOT= 1000 MHz ARM_A53_CLK_ROOT= 500 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 333 MHz MAIN_AXI_CLK_ROOT= 166 MHz
10 ARM_A53_CLK_ROOT= 500 MHz ARM_A53_CLK_ROOT= 250 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 166 MHz MAIN_AXI_CLK_ROOT= 83.3 MHz
11 ARM_A53_CLK_ROOT= 250 MHz ARM_A53_CLK_ROOT= 250 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 83.3 MHz MAIN_AXI_CLK_ROOT= 41.67 MHz

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

850 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Start

LPB_BOOT fuses equal Yes

00?

No
No
GPIO1_9 pad equals
LPB_POLARITY fuse?

Yes

Setup post dividers and root

Setup post dividers and root
clock selectors according to
clock selectors according to
Boot Freqiencies and
Boot Freqiencies fuse
LPB_BOOT fuses

Enable PLLs

End

Figure 6-24. Low-power boot flow

6.1.11 SD/MMC manufacture mode

When the internal boot and recover boot (if enabled) failed, the boot goes to the
SD/MMC manufacture mode before the serial download mode. In the manufacture mode,
one bit bus width is used despite of the fuse setting.
By default, the SD/MMC manufacture mode is enabled. Blow the fuse of the
DISABLE_SDMMC_MFG to disable it.
NOTE
A secondary boot is not supported in the SD/MMC manufacture
mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 851
System Boot

BOOT_MODE==0 and
BOOT_MODE==1 BOOT_MODE==2
BT_FUSE_SEL==0

Y internal primary boot

SDMMC MFG
mode disabled?

N
N EEPROM recovery N
success?
enabled?
SDMMC MFG mode boot
Y Y

EEPROM recovery
Y
success?

N
N
success?
USB download mode

application entry

Figure 6-25. SD/MMC manufacture boot flow

6.1.11.1 Using manufacture mode / serial download mode with eMMC

Manufacture mode is intended to allow a system to boot from a SD/MMC card on a
board with unprogrammed boot media or to upgrade the image on a boot device. For
manufacture mode, the boot ROM assumes if there is a SD/MMC card present indicated
by the uSDHC card detect (CD) signal pulled low, then there is a valid image on the card.
If an unprogrammed eMMC device is connected to the uSDHC port(s) on which
manufacture mode is supported and the CD signal is low, the ROM will attempt
manufacturing mode with the eMMC device, which does not contain a valid image. The
ROM loads the invalid image, and this will cause the ROM code to fail to enter serial
download mode, resulting in a reset of the system by the ROM. To enter serial download
mode in this case, the CD pin should be pulled up so the ROM does not detect a eMMC
device present and will bypass the manufacture mode to enter serial download mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

852 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.1.12 High-Assurance Boot (HAB)

The High Assurance Boot (HAB) component of the ROM protects against the potential
threat of attackers modifying the areas of code or data in the programmable memory to
make it behave in an incorrect manner. The HAB also prevents the attempts to gain
access to features which must not be available.
The integration of the HAB feature with the ROM code ensures that the chip does not
enter an operational state if the existing hardware security blocks detected a condition
that may be a security threat or if the areas of memory deemed to be important were
modified. The HAB uses the RSA digital signatures to enforce these policies.

CAAM
Flash

ROM
HAB

Core Processor
SNVS

RAM

Figure 6-26. Secure boot components

The figure above illustrates the components used during a secure boot using HAB. The
HAB interfaces with the SNVS to make sure that the system security state is as expected.
The HAB also uses the CAAM hardware block to accelerate the SHA-256 message
digest operations performed during the signature verifications and AES-128 operations
for the encrypted boot operations. The HAB also includes a software implementation of
SHA-256 for cases where a hardware accelerator can't be used. The RSA key sizes
supported are 1024, 2048, 3072, and 4096 bits. The RSA signature verification operations
are performed by a software implementation contained in the HAB library. The main
features supported by the HAB are:
• X.509 public key certificate support

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 853
System Boot

• CMS signature format support

• Proprietary encrypted boot support. Note that the encrypted boot depends on the
CAAM hardware module. When the CAAM is disabled (when the
EXPORT_CONTROL fuse is blown), the encrypted boot is not available.
NOTE
NXP provides the reference Code Signing Tool (CST) for key
generation, certificate generation, and code signing for use with
the HAB library. The CST can be found by searching for
"IMX_CST_TOOL" at http://www.nxp.com.
NOTE
For further details on using the secure boot feature using HAB,
refer to Secure Boot on i.MX Series (AN4581).

6.1.12.1 HAB API vector table addresses

For devices that perform a secure boot, the HAB library may be called by the boot stages
that execute after the ROM code.
NOTE
For additional information on the secure boot including the
HAB API, refer to HABv4 RVT Guidelines and
Recommendations (AN12263).

6.1.13 Boot information for software

To address the requirement that the boot image may need to get the basic boot
information when getting out of the boot process, the boot software information
(Boot_SW_Info) is provisioned by the ROM.
The software must read the ROM address 0x9e8 to get the base address of the
Boot_SW_Info data structure, and parse the Boot_SW_Info content to get the boot
information.
Table 6-40. Boot_SW_Info structure
Offset Byte3 Byte2 Byte1 Byte0
0x0 Reserved Boot Device Type Boot Device Instance Reserved
0x4 Arm core frequency (in Hz)
0x8 AXI bus frequency (in Hz)
0xC DDR frequency (in Hz)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

854 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-40. Boot_SW_Info structure

(continued)
Offset Byte3 Byte2 Byte1 Byte0
0x10 GPT1 input clock frequency (in Hz)
0x14 Reserved
0x18
0x1C

NOTE
The boot ROM sets the GPT1 in a free-running mode with a
32-kHz input clock.
Boot device type mapping:
• 0x1 - SD card or eSD chip
• 0x2 - MMC card or eMMC chip
• 0x3 - NAND chip
Boot device instance: The instance index of the boot device, starting from 0.

6.2 Fusemap

6.2.1 Boot Fusemap

The following section details the various modes and selection of the required boot
devices. A separate map is given for each and every boot device. The device select is
specified by BOOT_CFG[14:12] fuses listed below.
Table 6-41. Boot Device Select
Boot Device BOOT_CFG[14] BOOT_CFG[13] BOOT_CFG[12]
SD/eSD 0 0 1
MMC/eMMC 0 1 0
NAND 0 1 1
FlexSPI 1 0 0
SPI/NOR 1 1 0

NOTE
Fuses marked as “Reserved” are reserved for NXP internal (and
future) use only. Customers should not attempt to burn these, as

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 855
Fusemap

the IC behavior may be unpredictable. The reserved fuses can

be read as either 0 or 1.
Table 6-42. SD/eSD Boot Fusemap
Addr 7 6 5 4 3 2 1 0
0x470[15:8] Reserved Boot Device Select Port Select: Power SD
Cycle Loopback
00 - SD1
Enable Clock
01 - SD2 Source SEL
0 - Disable
(SDR50 and
10 - SD3
1 - Enable SDR104
Only)
0 - Through
SD pad
1 - Direct
0x470[7:0] Fast Boot: Reserved Bus Width: Speed Reserved
0 - Regular 0 - 1-bit 000 - Normal/SDR12
1 - Fast 1 - 4-bit 001 - High/SDR25
Boot
010 - SDR50
011 - SDR104
101 - Reserved for DDR50
Others - Reserved

Table 6-43. MMC/eMMC Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x470[15:8] Reserved Boot Device Select Port Select: Power SD
Cycle Loopback
00 - SD1
Enable Clock
01 - SD2 Source SEL
0 - Disable
(SDR50 and
10 - SD3
1 - Enable SDR104
Only)
0 - Through
SD pad
1 - Direct
0x470[7:0] Fast Boot: Bus Width: Speed USDHC IO USDHC IO
VOLTAGE VOLTAGE
0 - Regular 000 - 1-bit 00 - Normal
SELECTIO SELECTIO
1 - Fast 001 - 4-bit 01 - High N N
Boot
010 - 8-bit 10 - Reserved for HS200 For Normal For
Boot Mode Manufactur
101 - 4-bit DDR (MMC 4.4) 11 - Reserved
e Mode
0 - 3.3V
110 - 8-bit DDR (MMC 4.4)
0 - 3.3V
1 - 1.8V
Else - Reserved
1 - 1.8V

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

856 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-44. NAND Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x470[15:8] Reserved Boot Device Select Pages in Block: NAND Row Address
Bytes:
00 - 128
00 - 3
01 - 64
01 - 2
10 - 32
10 - 4
11 - 256
11 - 5
0x470[7:0] BT_TOGGL BOOT_SEARCH_COUN Toggle Mode 33MHz Preamble Delay, Read Latency LBA Reset
EMODE T
000 - 16 GPMICLK cycles
0 - Raw 00 - 2
001 - 1 GPMICLK cycles
NAND
01 - 2
010 - 2 GPMICLK cycles
1 - Toggle
10 - 4
mode 011 - 3 GPMICLK cycles
11 - 8
100 - 4 GPMICLK cycles
101 - 5 GPMICLK cycles
110 - 6 GPMICLK cycles
111 - 7 GPMICLK cycles
1111- 15 GPMICLK cycles

Table 6-45. FlexSPI Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x470[15:8] Reserved Boot Device Select Flash Auto FLASH TYPE:
Probe
000 - Device supports 3B read by
default
001 - Device supports 4B read by
default
010 - HyperFlash 1V8
011 - HyperFlash 3V3
100 - MXIC Octal DDR
0x470[7:0] HOLD TIME: FLASH Auto Probe Type FlexSPI FLASH Dummy Cycle
00 - 500us
01 - 1ms
10 - 3ms
11 - 10ms

Table 6-46. SPI/NOR Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x470[15:8] Reserved Boot Device Select Port Select: SPI
Addressing:
000 - eCSPI1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 857
Fusemap

Table 6-46. SPI/NOR Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
001 - eCSPI2 0 - 3 bytes
(24-bit)
010 - eCSPI3
1 - 2 bytes
(16-bit)
0x470[7:0] CS select (SPI only) Reserved
00 - CS#0 (default)
01 - CS#1
10 - CS#2
11 - CS#3

Table 6-47. Boot Fusemap

Addr 7 6 5 4 3 2 1 0
0x480[7:0] Reserved Reserved FlexSPI FLASH Frequency
000 - 100 MHz
001 - 133 MHz
010 - 166 MHz
011 - 200 MHz
100 - 80 MHz
101 - 20 MHz
Other - Reserved
0x480[15:8] LPB_BOOT (Core/DDR/ BT_LPB_P L1 I-Cache TZASC_EN WDOG_EN Boot L1 D-Cache
Bus) OLARITY DISABLE ABLE ABLE Frequencies DISABLE
(GPIO (ARM/DDR)
00/01 - LPB Disable TZASC 0 - Disabled
polarity)
enable fuse. 0 - 800 /
10 - Div by 2 1 - Enabled
800 MHz
0 - TZASC
11 - Div by 4
module left 1 - 400 /
in disable 400 MHz
and bypass
state.
1 - TZASC
modules
and
associated
clocks and
muxing are
enabled by
Boot ROM
code.
0x480[23:16] NOC_ID_R SDP_READ SDP_DISA FORCE_IN Reserved WDOG Timeout Select
EMAP_BYP _DISABLE BLE TERNAL_B
000 - 64s
ASS OOT
001 - 32s
010 - 16s
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

858 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-47. Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
011 - 8s
100 - 4s
Others - Reserved
0x480[31:24] Recovery Port Select Recovery Recovery CS select (SPI Recovery Reserved
SPI only) Boot Enable
000 - eCSPI1
Addressing
00 - CS#0 (default) 0 - Disabled
001 - eCSPI2
0 - 3-bytes
1 - Enabled
010 - eCSPI3 (24-bit)
1 - 2-bytes
(16-bit)
0x490[7:0] Reserved
0x490[15:8] USDHC MMC_DLL_DLY[6:0]
DLL Select
Delay target for USDHC DLL, it is applied to slave mode target delay or override mode target
0 - DLL delay depends on DLL Override fuse bit value.
Slave Mode
for
1 - DLL
Override
Mode
0x490[23:16] Disable USDHC_C eMMC 4.4 - USDHC_PA ENABLE_E USDHC_IO USDHC USDHC
SDMMC MD_OE_PR RESET TO D_PULL_D MMC_22K_ MUX_SION Override DLL_ENAB
Manufactur E_EN PRE-IDLE OWN PULLUP _BIT_ENAB Pad LE
e mode (SD/MMC STATE LE Settings
0 - no 0 - 47K 0 - Disable
debug) (using
0 - Enable 0 - Enable action pullup 0 - Disable DLL for SD/
PAD_SETTI
eMMC
1 - Disable 1 - Disable 1 - pull 1 - 22K 1 - Enable NGS value)
down pullup 1 - Enable
DLL for SD/
eMMC
0x490[31:24] USDHCPAD_SETTINGS[7:0]
0x4A0[7:0] SD Calibration Step uSDHC Power Cycle uSDHC uSDHC USDHC_PA Fast Boot
Interval Power Power On D_SETTIN Acknowledg
00 - 1
Cycle Delay Polarity GS[8] e Disable
00 - 20ms
0 - 5ms 0 - Low 0 - Boot Ack
01 - 10ms
Disabled
1 - 2.5ms 1 - High
10 - 5ms
1 - Boot Ack
11 - 2.5ms Enabled
0x4A0[15:8] NAND_READ_CMD_CODE1[7:0]
0x4A0[23:16] NAND_READ_CMD_CODE2[7:0]
0x4A0[31:24] NAND_PAD_SETTINGS[7:0]
0x4B0[7:0] Override GPMI Read DDR DLL Target Value NAND 0x4B0[1:0]
NAND Pad Reset time
0000 - 7 NAND Number of
Settings 1.5ms
Devices:
(using 0001 - 1
PAD_SETTI 00 - 1
0111 - 0
NGS value)
01 - 2
1111 - 15
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 859
Fusemap

Table 6-47. Boot Fusemap (continued)

Addr 7 6 5 4 3 2 1 0
10 - 4
11 - Reserved
0x4B0[15:8] READ_RETRY_SEQ_ID[3:0] Reserved
0000 - do not use read retry (RR) sequence
embedded in ROM
0001 - Micron 20nm RR sequence
0010 - Toshiba A19nm RR sequence
0011 - Toshiba 19nm RR sequence
0100 - SanDisk 19nm RR sequence
0101 - SanDisk 1ynmRR sequence
0110 - Hynix 20nm A Die RR sequence
0111 - Hynix 26nm RR sequence
1000 - Hynix 20nm B Die RR sequence
1001 - Hynix 20nm C Die RR sequence
Others - Reserved
0x4B0[23:16] Reserved
0x4B0[31:24] RNG_TRIM[7:0]

6.2.2 Lock Fusemap

Table 6-48 describes the functions of various lock fuses.
Table 6-48. Lock Fuses
Addr 7 6 5 4 3 2 1 0
0x400[7:0] Reserved Reserved BOOT_CFG_LOCK TESTER_LOCK
1x - OP 1x - OP
x1 - WP x1 - WP
0x400[15:8] MAC_ADDR_LOCK USB_ID_LOCK Reserved SJC_RESP Reserved Reserved
_LOCK
1x - OP 1x - WP + OP
WRP,OP,R
x1 - WP 01 - WP
DP
0x400[23:16] GP2_LOCK GP1_LOCK Reserved Reserved Reserved
1x - OP 1x - OP
x1 - WP x1 - WP
0x400[31:24] Reserved GP5_LOCK
1x – OP
x1 – WP

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

860 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

NOTE
TESTER_LOCK programmed by NXP / set at factory

6.2.3 Fusemap Descriptions Table

NOTE
Definitions for fuse settings are as follows:
• Unlock - The controlled field can be read, sensed, burned,
or overridden in the corresponding OCOTP shadow
register.
• Lock - The controlled field cannot be read, burned, or
overridden.
• Override Protect (OP) - The controlled field can be read,
sensed, or burned in the corresponding OCOTP shadow
register.
• Write Protect (WP) - The controlled field can be read,
sensed, or overridden in the corresponding OCOTP shadow
register.
• OP + WP - The controlled field can only be read or sensed
in the corresponding OCOTP shadow register. It cannot be
burned or overridden in the corresponding OCOTP shadow
register.
Table 6-49. Fusemap Descriptions
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x400[1:0] TESTER_LOCK 2 Lock for tester related fuses 00 - Unlock OCOTP
at 0x400-0x460.
10 - OP
01 - WP
11 - OP + WP
0x400[3:2] BOOT_CFG_LOCK 2 Lock for BOOT related fuses 00 - Unlock OCOTP
at 0x470-4B0.
10 - OP
01 - WP
11 - OP + WP
0x400[8:4] Reserved 5 Reserved Reserved Reserved
0x400[9] Reserved 1 Reserved Reserved Reserved
0x400[10] SJC_RESP_LOCK 1 Lock for SJC_RESP[55:0] 0 - Unlock OCOTP
fuses.
1 - Lock
0x400[11] Reserved 1 Reserved Reserved Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 861
Fusemap

Table 6-49. Fusemap Descriptions (continued)

Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x400[13:12] USB_ID_LOCK 2 Lock for USB_PID and 00 - Unlock OCOTP
USB_VID fuses.
01 - WP
11 - OP + WP
0x400[15:14] MAC_ADDR_LOCK 2 Lock for MAC_ADDR fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x400[19:16] Reserved 4 Reserved Reserved Reserved
0x400[21:20] GP1_LOCK 2 Lock for GP1[63:0] fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x400[23:22] GP2_LOCK 2 Lock for GP2 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x400[25:24] GP5_LOCK 2 Lock for GP5 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x400[31:26] Reserved 6 Reserved Reserved Reserved
0x410-0x420 SJC_CHALL[63:0] / 32 The SJC CHALLENGE / - SJC, SW
UNIQUE_ID[63:0] Unique ID
0x430 Reserved 32 Reserved Reserved Reserved
0x440[3:0] Reserved 4 Reserved Reserved Reserved
0x440[7:4] Reserved 4 Reserved Reserved Reserved
0x440[13:8] SPEED_GRADING 6 Burned by tester program, FC FH FR MH P/N PROD / SW
for indicating IC core speed. A[5 A[3 AL[ z
(Hot burn may not be used). :4] :2] 1:0
]
xx xx 00 800 08
xx xx 01 120 12
0
xx xx 10 160 16
0
xx xx 11 180 18
0

0x440[31:14] Reserved 18 Reserved Reserved Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

862 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-49. Fusemap Descriptions (continued)

Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x450[1:0] NUM_A53_CORES 2 Number of A53 CPU cores 00 - 4 cores SRC, SJC, SW
available.
01 - Reserved
10 - 2 cores
11 - 1 core
0x450[7:2] Reserved 6 Reserved Reserved Reserved
0x450[8] M4_DISABLE 1 Disable M4 Core. 0 - enabled M4
1 - disabled
0x450[9] M4_MPU_DISABLE 1 Disable M4 MPU IP. 0 - enabled M4
1 - disabled
0x450[10] M4_FPU_DISABLE 1 Disable M4 FPU IP. 0 - enabled M4
1 - disabled
0x450[11] USB_OTG1_DISAB 1 Disable USB OTG1 IP. 0 - enabled USB OTG1
LE
1 - disabled
0x450[12] USB_OTG2_DISAB 1 Disable USB OTG2 IP. 0 - enabled USB OTG2
LE
1 - disabled
0x450[15:13] Reserved 3 Reserved Reserved Reserved
0x450[18] VPU_G1_DISABLE 1 Disable G1 Decoder in VPU 0 - enabled VPU
1 - disabled
0x450[19] VPU_G2_DISABLE 1 Disable G2 Decoder in VPU 0 - enabled VPU
1 - disabled
0x450[20] VPU_H1_DISABLE 1 Disable H1 Encoder in VPU 0 - enabled VPU
1 - disabled
0x450[21] GPU2D_DISABLE 1 Disable GPU 2D IP. 0 - enabled GPU
1 - disabled
0x450[22] PCIE1_DISABLE 1 Disable PCIe-1 IP. 0 - enabled PCIE
1 - disabled
0x450[23] Reserved 1 Reserved. Reserved Reserved
0x450[24] GPU3D_DISABLE 1 Disable GPU 3D IP. 0 - enabled GPU
1 - disabled
0x450[27:25] Reserved 3 Reserved Reserved Reserved
0x450[28] MIPI_DSI_DISABL 1 Disable MIPI DSI IP. 0 - enabled MIPI DSI
E
1 - disabled
0x450[29] ENET_DISABLE 1 Disable ENET IP. 0 - enabled ENET
1 - disabled
0x450[30] MIPI_CSI_DISABL 1 Disable MIPI CSI IP. 0 - enabled MIPI CSI
E
1 - disabled
0x450[31] Reserved 1 Reserved Reserved Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 863
Fusemap

Table 6-49. Fusemap Descriptions (continued)

Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x460[31:0] Reserved 32 Reserved Reserved Reserved
0x470[15:0] BOOT_CFG 16 BOOT configuration register, See boot fusemap for SRC SW(ROM)
Usage varies, depending on details.
selected boot device.
0x470[24:16] Reserved 9 Reserved Reserved Reserved
0x470[26:16] Reserved 10 Reserved Reserved Reserved
0x470[27] Reserved 1 Reserved Reserved Reserved
0x470[28] BT_FUSE_SEL 1 Determines, whether using If boot_mode="00" SRC SW(ROM)
fuses for boot configuration, (Development)
or GPIO /Serial loader.
0=Boot mode configuration
is taken from GPIOs.
1=Boot mode configuration
is taken from fuses.
If boot_mode="10"
(Production)
0 - Boot using Serial Loader
(USB)
1- Boot mode configuration
is taken from fuses.
0x470[29] FORCE_COLD_BO 1 Force cold boot when A7 Fuse Function: SRC SW(ROM)
OT(SBMR) core come out of reset.
0 – Default behavior allowing
Reflected in SBMR reg of
a fast recovery from low
SRC
power modes. That is, the
ROM is allowed to jump to
the address previously
programmed in the SRC
persistent register.
1 – Fast recovery path in the
ROM is not allowed and a
cold boot is always
performed. Customers
wanting a higher level of
security should burn this
fuse.
0x470[31:30] Reserved 2 Reserved Reserved Reserved
0x480[31:0] BOOT_CFG_PARA 32 BOOT configuration See boot fusemap for SW (ROM)
METER parameters, Usage varies, details.
depending on selected boot
device.
0x490[31:0] BOOT_CFG_PARA 32 BOOT configuration See boot fusemap for SW (ROM)
METER parameters, Usage varies, details.
depending on selected boot
device.
0x4A0[31:0] BOOT_CFG_PARA 32 BOOT configuration See boot fusemap for SW (ROM)
METER parameters, Usage varies, details.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

864 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-49. Fusemap Descriptions (continued)

Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
depending on selected boot
device.
0x4B0[31:0] BOOT_CFG_PARA 32 BOOT configuration See boot fusemap for SW (ROM)
METER parameters, Usage varies, details.
depending on selected boot
device.
0x4C0-0x500 Reserved 384 Reserved Reserved Reserved
0x580[31:0] Reserved 256 Reserved Reserved Reserved
0x600[23:0] SJC_RESP[55:0] 56 Response reference value - SJC
for the secure JTAG
controller
0x610[31:24] Reserved 8 Reserved Reserved Reserved
0x620[15:0] USB_VID[31:0] 16 USB VID - SW
0x620[31:16] USB_PID[31:0] 16 USB PID - SW
0x630[31:0] Reserved 32 Reserved Reserved Reserved
0x640[15:0] MAC_ADDR[47:0] 48 Reserved for customers/SW - SW
0x650[31:16] Reserved 48 Reserved Reserved Reserved
0x670-0x6F0 Reserved 288 Reserved Reserved Reserved
0x700[31:0] Reserved 256 Reserved Reserved Reserved
0x780[31:0] GP1[63:0] 64 General Purpose fuse - SW
register #1
0x7A0[31:0] GP2[63:0] 64 General Purpose fuse - SW
register #2
0x7C0-0x7F0 Reserved 128 Reserved Reserved Reserved
0x800[31:0] GP5[383:0] 384 General Purpose fuse - SW
register #5
0x8C0[31:0] Reserved 128 Reserved Reserved Reserved
0x900-0x13F Reserved 5632 Reserved Reserved Reserved
0

6.3 On-Chip OTP Controller (OCOTP_CTRL)

6.3.1 Overview
This section contains information describing the requirements for the on-chip eFuse OTP
controller along with details about the block functionality and implementation.
In this document, the words "eFuse" and "OTP" are interchangeable. OCOTP refers to
the hardware block itself.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 865
On-Chip OTP Controller (OCOTP_CTRL)

6.3.1.1 Features
The OCOTP provides the following features:
• Loading and housing of fuse content into shadow registers.
• Generation of HWV_FUSE (hardware visible fuse bus) and the HWV_REG bus
which is made up of volatile PIO register based "fuses". The HWV_REG bits come
from the SCS (Software Controllable Signals) register.
• Generation of STICKY_REG which is consist of sticky register bits.
• Provide program-protect and read-protect eFuse.
• Provide override and read protection of shadow register.

6.3.2 Top-Level Symbol and Functional Overview

The figure found here shows the OCOTP system level diagram.

OCOTP_CTRL

APB Interface

IP bus
OCOTP control register 5 ip2apb

HW Capability Bus Other

Blocks
Shadow Regs To SJC
HWV_REG Bus
Blocks
STICKY_REG Bus Other
Blocks

OCOTP Controller/State Machine

OTP
FUSE

Figure 6-27. OCOTP System Level Diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

866 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.2.1 Operation
The IP bus interface of the OCOTP provides two functions.
• Configure control registers for programming and reading fuse .
• Override and read shadow registers.

6.3.2.1.1 Shadow Register Reload

All fuse words in are shadowed. Therefore, fuse information is available through memory
mapped shadow registers. If fuses are subsequently programmed, the shadow registers
should be reloaded to keep them coherent with the fuse bank arrays.
The "reload shadows" feature allows the user to force a reload of the shadow registers
(including HW_OCOTP_LOCK) without having to reset the device. To force a reload,
complete the following steps:
1. Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are
clear. Overlapped accesses are not supported by the controller. Any pending write ,
read or reload must be completed before a new access can be requested.
2. Set the HW_OCOTP_CTRL[RELOAD_SHADOWS] bit. OCOTP will read all the
fuse one by one and put it into corresponding shadow register.
3. Wait for HW_OCOTP_CTRL[BUSY] and
HW_OCOTP_CTRL[RELOAD_SHADOWS] to be cleared by the controller.
The controller will automatically clear the HW_OCOTP_CTRL[RELOAD_SHADOWS]
bit after the successful completion of the operation.

6.3.2.1.2 Fuse and Shadow Register Read

All shadow registers are always readable through the APB bus except some secret keys
regions. When their corresponding fuse lock bits are set, the shadow registers also
become read locked. After read locking, reading from these registers will return
0xBADABADA.
In addition OCOTP_CTRL[ERROR] will be set. It must be cleared by software before
any new write , read or reload access can be issued. Subsequent reads to unlocked
shadow locations will still work successfully however.
To read fuse words directly from correctly complete the following steps:
1. Check that OCOTP_CTRL[BUSY] and OCOTP_CTRL[ERROR] are clear.
Overlapped accesses are not supported by the controller. Any pending write, read or
reload must be completed before a read access can be requested.
2. Write the requested to OCOTP_CTRL[ADDR].

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 867
On-Chip OTP Controller (OCOTP_CTRL)

6.3.2.1.3 Fuse and Shadow Register Writes

Shadow register bits can be overridden by software until the corresponding fuse lock bit
for the region is set. When the lock shadow bit is set, the shadow registers for that lock
region become write locked. The LOCK shadow register also has no shadow or fuse lock
bits but it is always read only.
In order to avoid "rogue" code performing erroneous writes to OTP, a special unlocking
sequence is required for writes to the fuse banks. To program fuse bank correctly
complete the following steps:
1. Program HW_OCOTP_TIMING[STROBE_PROG] and fields with timing values to
match the current frequency of the ipg_clk. OTP writes will work at maximum bus
frequencies as long as the parameters are set correctly.
2. Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are
clear. Overlapped accesses are not supported by the controller. Any pending write or
reload must be completed before a write access can be requested.
3. Write the requested to HW_OCOTP_CTRL[ADDR] and program the unlock code
into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed for each write
access. The lock code is documented in the register description. Both the unlock code
and address can be written in the same operation.
It should be noted that write latencies to OTP are numbers of 10 micro-seconds. Write
latencies is based on amount of bit filed which is 1. For example : program half fuse bits
in one word need 10 us x 16.
For further details of OTP read/write operations see [eFUSE].
HW_OCOTP_CTRL[ERROR] will be set under the following conditions:
• A write is performed to a shadow register during a shadow reload (essentially, while
HW_OCOTP_CTRL[RELOAD_SHADOWS] is set. In addition, the contents of the
shadow register shall not be updated.
• A write is performed to a shadow register which has been locked.
• A read is performed to from a shadow register which has been read locked.
• A program is performed to a fuse which has been .
• A read is performed to from a fuse which has been read locked.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

868 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.2.1.4 Write Postamble

Due to internal electrical characteristics of the OTP during writes, all OTP operations
following a write must be separated by 2 us after the clearing of
HW_OCOTP_CTRL_BUSY following the write. This guarantees programming voltages
on-chip to reach a steady state when exiting a write sequence. This includes reads,
shadow reloads, or other writes.
A recommended software sequence to meet the postamble requirements is as follows:
• Issue the write and poll for BUSY (as per Fuse Shadow Memory Footprint).
• After BUSY is clear, wait an additional 2 us.
• Perform the next OTP operation.

6.3.2.2 Fuse Shadow Memory Footprint

The OTP memory footprint shows in the following figure. The registers are grouped by
lock region. Their names correspond to the PIO register and fusemap names.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 869
On-Chip OTP Controller (OCOTP_CTRL)

RESERVED RESERVED RESERVED

0x17 0x2F 0xFF
RESERVED RESERVED RESERVED
0x16 0x2E 0xFE
RESERVED RESERVED
0x15 0x2D
RESERVED RESERVED
0x14 0x2C
RESERVED RESERVED
0x13 0x2B
RESERVED RESERVED
0x12 0x2A
RESERVED RESERVED
0x11 0x29
RESERVED RESERVED
0x10 0x28

RESERVED RESERVED RESERVED

0x0F 0x27 0x3F
RESERVED MAC RESERVED
0x0E 0x26 0x3E
RESERVED MAC RESERVED
0x0D 0x25 0x3D
RESERVED MAC RESERVED
0x0C 0x24 0x3C
Shadow
Regs BOOT_CFG FIELD_RETURN GP2
0x0B 0x23 0x3B
BOOT_CFG USB_ID GP2
0x0A 0x22 0x3A
BOOT_CFG SJC GP1
0x09 0x21 0x39
BOOT_CFG SJC GP1
0x08 0x20 0x38

BOOT_CFG RESERVED RESERVED

0x07 0x1F 0x37
TESTER RESERVED RESERVED
0x06 0x1E 0x36
TESTER RESERVED RESERVED
0x05 0x1D 0x35
TESTER RESERVED RESERVED
0x04 0x1C 0x34
TESTER RESERVED RESERVED
0x03 0x1B 0x33
TESTER RESERVED RESERVED
0x02 0x1A 0x32
TESTER RESERVED RESERVED
0x01 0x19 0x31
LOCK RESERVED RESERVED
0x00 0x18 0x30

Figure 6-28. OTP Memory Footprint

6.3.2.3 OTP Read/Write Timing Parameters

There are timing fields contained in the HW_OCOTP_TIMING register that specify
counter limit values, which are used to specify the signal timing.
Both two timing parameters are specified in ipg_clk cycles. Since the ipg_clk frequency
can be set to a range of values, these parameters must be adjusted with the clock to yield
the appropriate delay.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

870 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.2.4 Hardware Visible Fuses

The hwv_fuse bus emanates from the OCOTP block and goes to various other blocks
inside the chip. This bus is made up of the shadow register bits for .
Only a subset of these fuse bits are currently used by the hardware. The fuse bits are
initially copied from the banks after reset is deasserted. When all fuse bits are loaded into
their shadow registers, the OCOTP asserts the fuse_latched output signal.
The hwv_reg bus also comes from the OCOTP. Its source is the HW_OCOTP_SCS
register. This register has 1 defined bit, the HAB_JDE bit, that is connected to the SJC
block. The SCS bits are intended to be used as volatile fuse bits under software control.
Additional bits will be defined as needed in future implementations.
The system-wide reset sequence must be coordinated by the system reset controller, so
that the hwv_fuse and hwv_reg buses are stable and reflect the values of the fuses before
they are used by the rest of the system.

6.3.2.5 Behavior During Reset

The OCOTP is always active. The shadow registers automatically load the appropriate
OTP contents after reset is deasserted. During this load-time
HW_OCOTP_CTRL_BUSY is set. The load time is similar to that of a "reload shadow"
operation.

6.3.3 Fuse Map

See the Fusemap chapter of this reference manual for more information.

6.3.4 OCOTP Memory Map/Register Definition

NOTE
When write/read unimplemented register address in ocotp_ctrl,
ocotp_ctrl will not send error and read data will be 0.

OCOTP Hardware Register Format Summary

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 871
On-Chip OTP Controller (OCOTP_CTRL)

OCOTP memory map

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
OTP Controller Control Register 6.3.4.1/
3035_0000 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_CTRL) 874
OTP Controller Control Register 6.3.4.1/
3035_0004 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_CTRL_SET) 874
OTP Controller Control Register 6.3.4.1/
3035_0008 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_CTRL_CLR) 874
OTP Controller Control Register 6.3.4.1/
3035_000C 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_CTRL_TOG) 874
OTP Controller Timing Register 6.3.4.2/
3035_0010 32 R/W 0400_0000h
(OCOTP_HW_OCOTP_TIMING) 875
OTP Controller Write Data Register 6.3.4.3/
3035_0020 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_DATA) 876
OTP Controller Write Data Register 6.3.4.4/
3035_0030 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_READ_CTRL) 877
OTP Controller Read Data Register 6.3.4.5/
3035_0040 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_READ_FUSE_DATA) 878
6.3.4.6/
3035_0050 Sticky bit Register (OCOTP_HW_OCOTP_SW_STICKY) 32 R/W 0000_0000h
879
Software Controllable Signals Register 6.3.4.7/
3035_0060 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_SCS) 880
Software Controllable Signals Register 6.3.4.7/
3035_0064 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_SCS_SET) 880
Software Controllable Signals Register 6.3.4.7/
3035_0068 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_SCS_CLR) 880
Software Controllable Signals Register 6.3.4.7/
3035_006C 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_SCS_TOG) 880
OTP Controller Version Register 6.3.4.8/
3035_0090 32 R/W 0148_1299h
(OCOTP_HW_OCOTP_VERSION) 881
Value of OTP Bank0 Word0 (Lock controls) 6.3.4.9/
3035_0400 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_LOCK) 882
Value of OTP Bank0 Word1 (Tester Info.) 6.3.4.10/
3035_0410 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_TESTER0) 884
Value of OTP Bank0 Word2 (tester Info.) 6.3.4.11/
3035_0420 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_TESTER1) 884
Value of OTP Bank0 Word3 (Tester Info.) 6.3.4.12/
3035_0430 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_TESTER2) 885
Value of OTP Bank1 Word0 (Tester Info.) 6.3.4.13/
3035_0440 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_TESTER3) 885
Value of OTP Bank1 Word1 (Tester Info.) 6.3.4.14/
3035_0450 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_TESTER4) 886
Value of OTP Bank1 Word2 (Tester Info.) 6.3.4.15/
3035_0460 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_TESTER5) 886
Value of OTP Bank1 Word3 (Boot Configuration Info.) 6.3.4.16/
3035_0470 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_BOOT_CFG0) 887
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

872 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

OCOTP memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Value of OTP Bank2 Word0 (Boot Configuration Info.) 6.3.4.17/
3035_0480 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_BOOT_CFG1) 887
Value of OTP Bank2 Word1 (Boot Configuration Info.) 6.3.4.18/
3035_0490 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_BOOT_CFG2) 888
Value of OTP Bank2 Word2 (Boot Configuration Info.) 6.3.4.19/
3035_04A0 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_BOOT_CFG3) 888
Value of OTP Bank2 Word3 (BOOT Configuration Info.) 6.3.4.20/
3035_04B0 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_BOOT_CFG4) 889
Value of OTP Bank8 Word0 (Secure JTAG Response Field) 6.3.4.21/
3035_0600 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_SJC_RESP0) 889
Value of OTP Bank8 Word1 (Secure JTAG Response Field) 6.3.4.22/
3035_0610 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_SJC_RESP1) 890
Value of OTP Bank8 Word2 (USB ID info) 6.3.4.23/
3035_0620 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_USB_ID) 890
Value of OTP Bank9 Word0 (MAC Address) 6.3.4.24/
3035_0640 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_MAC_ADDR0) 891
Value of OTP Bank9 Word1 (MAC Address) 6.3.4.25/
3035_0650 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_MAC_ADDR1) 891
Value of OTP Bank9 Word2 (MAC Address) 6.3.4.26/
3035_0660 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_MAC_ADDR2) 892
Value of OTP Bank14 Word0 () 6.3.4.27/
3035_0780 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_GP10) 892
Value of OTP Bank14 Word1 () 6.3.4.28/
3035_0790 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_GP11) 893
Value of OTP Bank14 Word2 () 6.3.4.29/
3035_07A0 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_GP20) 893
Value of OTP Bank14 Word3 () 6.3.4.30/
3035_07B0 32 R/W 0000_0000h
(OCOTP_HW_OCOTP_GP21) 893

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 873
On-Chip OTP Controller (OCOTP_CTRL)

6.3.4.1 OTP Controller Control Register

(OCOTP_HW_OCOTP_CTRLn)

The OCOTP Control and Status Register provides the necessary software interface for
performing read and write operations to the On-Chip OTP (One-Time Programmable
ROM). The control fields such as WR_UNLOCK, ADDR and BUSY/ERROR may be
used in conjuction with the HW_OCOTP_DATA register to perform write operations.
Read operations to the On-Chip OTP are involving ADDR, BUSY/ERROR bit field and
HW_OCOTP_READ_CTRL register. Read value is saved in
HW_OCOTP_READ_FUSE_DATA register.
Address: 3035_0000h base + 0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WR_UNLOCK

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
RELOAD_SHADOWS

R
ERROR

Reserved ADDR

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

874 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

OCOTP_HW_OCOTP_CTRLn field descriptions

Field Description
31–16 Write 0x3E77 to enable OTP write accesses. NOTE: This register must be unlocked on a write-by-write
WR_UNLOCK basis (a write is initiated when HW_OCOTP_DATA is written), so the UNLOCK bitfield must contain the
correct key value during all writes to HW_OCOTP_DATA, otherwise a write shall not be initiated. This field
is automatically cleared after a successful write completion (clearing of BUSY).
15–11 This field is reserved.
- Reserved
10 Set to force re-loading the shadow registers (HW/SW capability and LOCK). This operation will
RELOAD_ automatically set BUSY. Once the shadow registers have been re-loaded, BUSY and
SHADOWS RELOAD_SHADOWS are automatically cleared by the controller.
9 Set by the controller when an access to a locked region(OTP or shadow register) is requested. Must be
ERROR cleared before any further access can be performed. This bit can only be set by the controller. This bit is
also set if the Pin interface is active and software requests an access to the OTP. In this instance, the
ERROR bit cannot be cleared until the Pin interface access has completed. Reset this bit by writing a one
to the SCT clear address space and not by a general write.
8 OTP controller status bit. When active, no new write access or read access to OTP(including
BUSY RELOAD_SHADOWS) can be performed. Cleared by controller when access complete. After reset (or
after setting RELOAD_SHADOWS), this bit is set by the controller until the HW/SW and LOCK registers
are successfully copied, after which time it is automatically cleared by the controller.
ADDR OTP write and read access address register. Specifies one of 128 word address locations (0x00 - 0x7f). If
a valid access is accepted by the controller, the controller makes an internal copy of this value. This
internal copy will not update until the access is complete.

6.3.4.2 OTP Controller Timing Register

(OCOTP_HW_OCOTP_TIMING)

This register specifies timing parameters for programming and reading the OCOTP fuse
array.
Address: 3035_0000h base + 10h offset = 3035_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R RSRVD0
WAIT STROBE_READ RELAX STROBE_PROG
W

Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_TIMING field descriptions

Field Description
31–28 These bits always read back zero.
RSRVD0
27–22 This count value specifies time interval between auto read and write access in one time program. It is
WAIT given in number of ipg_clk periods.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 875
On-Chip OTP Controller (OCOTP_CTRL)

OCOTP_HW_OCOTP_TIMING field descriptions (continued)

Field Description
21–16 This count value specifies the strobe period in one time read OTP. Trd = ((STROBE_READ+1)- 2*(RELAX
STROBE_READ +1)) /ipg_clk_freq. It is given in number of ipg_clk periods.
15–12 This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd. It
RELAX is given in number of ipg_clk periods.
STROBE_PROG This count value specifies the strobe period in one time write OTP. Tpgm = ((STROBE_PROG+1)-
2*(RELAX+1)) /ipg_clk_freq. It is given in number of ipg_clk periods.

6.3.4.3 OTP Controller Write Data Register

(OCOTP_HW_OCOTP_DATA)

This register is used in conjuction with HW_OCOTP_CTRL to perform one-time writes

to the OTP.
Address: 3035_0000h base + 20h offset = 3035_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_DATA field descriptions

Field Description
DATA Used to initiate a write to OTP.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

876 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.4.4 OTP Controller Write Data Register

(OCOTP_HW_OCOTP_READ_CTRL)

This register is used in conjuction with HW_OCOTP_CTRL to perform one time read to
the OTP.
Address: 3035_0000h base + 30h offset = 3035_0030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R RSVD0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R RSVD0

READ_FUSE
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_READ_CTRL field descriptions

Field Description
31–1 Reserved
RSVD0
0 Used to initiate a read to OTP.
READ_FUSE

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 877
On-Chip OTP Controller (OCOTP_CTRL)

6.3.4.5 OTP Controller Read Data Register

(OCOTP_HW_OCOTP_READ_FUSE_DATA)

The data read from OTP

Address: 3035_0000h base + 40h offset = 3035_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_READ_FUSE_DATA field descriptions

Field Description
DATA The data read from OTP

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

878 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.4.6 Sticky bit Register (OCOTP_HW_OCOTP_SW_STICKY)

Some sticky bits are used by SW to lock some fuse area , shadow registers and other
features.
Address: 3035_0000h base + 50h offset = 3035_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R RSVD2

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISABLE_READ_GROUP_MASK

RSVD1
JTAG_BLOCK_RELEASE

R RSVD2 RSVD0
FIELD_RETURN_LOCK

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 879
On-Chip OTP Controller (OCOTP_CTRL)

OCOTP_HW_OCOTP_SW_STICKY field descriptions

Field Description
31–6 Reserved
RSVD2
5 Shadow register write and OTP write lock for GROUP_MASK region. When set, the writing of this region's
DISABLE_ shadow register and OTP fuse word are blocked. Once this bit is set, it is always high unless a POR is
READ_GROUP_ issued.
MASK
4 Set by Arm during Boot after DTCP is initialized and before test mode entry. * 0 (Default) - JTAG is
JTAG_BLOCK_ blocked (subject to other conditions).* 1 - JTAG block is released (subject to other controls). Once this bit
RELEASE is set, it is always high unless a POR is issued.
3 Reserved
RSVD1
2 Shadow register write and OTP write lock for FIELD_RETURN region. When set, the writing of this
FIELD_ region's shadow register and OTP fuse word are blocked.Once this bit is set, it is always high unless a
RETURN_LOCK POR is issued.
RSVD0 Reserved

6.3.4.7 Software Controllable Signals Register

(OCOTP_HW_OCOTP_SCSn)

This register holds volatile configuration values that can be set and locked by trusted
software. All values are returned to their defualt values after POR.
Address: 3035_0000h base + 60h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
LOCK

SPARE
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
HAB_JDE

SPARE
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_SCSn field descriptions

Field Description
31 When set, all of the bits in this register are locked and can not be changed through SW programming. This
LOCK bit is only reset after a POR is issued.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

880 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

OCOTP_HW_OCOTP_SCSn field descriptions (continued)

Field Description
30–1 Unallocated read/write bits for implementation specific software use.
SPARE
0 HAB JTAG Debug Enable. This bit is used by the HAB to enable JTAG debugging, assuming that a
HAB_JDE properlay signed command to do so is found and validated by the HAB. The HAB must lock the register
before passing control to the OS whether or not JTAG debugging has been enabled. Once JTAG is
enabled by this bit, it can not be disabled unless the system is reset by POR. 0: JTAG debugging is not
enabled by the HAB (it may still be enabled by other mechanisms). 1: JTAG debugging is enabled by the
HAB (though this signal may be gated off).

6.3.4.8 OTP Controller Version Register

(OCOTP_HW_OCOTP_VERSION)

This register indicates the RTL version in use.

Address: 3035_0000h base + 90h offset = 3035_0090h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MAJOR MINOR STEP

W

Reset 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 1

OCOTP_HW_OCOTP_VERSION field descriptions

Field Description
31–24 Fixed read-only value reflecting the MAJOR field of the RTL version.
MAJOR
23–16 Fixed read-only value reflecting the MINOR field of the RTL version.
MINOR
STEP Fixed read-only value reflecting the stepping of the RTL version.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 881
On-Chip OTP Controller (OCOTP_CTRL)

6.3.4.9 Value of OTP Bank0 Word0 (Lock controls)

(OCOTP_HW_OCOTP_LOCK)

Shadowed memory mapped access to OTP Bank 0, word 0.

Address: 3035_0000h base + 400h offset = 3035_0400h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R GP2 GP1

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

882 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAC_ADDR

SJC_RESP
R USB_ID BOOT_CFG TESTER

Reserved

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_LOCK field descriptions

Field Description
31–24 This field is reserved.
- Reserved
23–22 Status of shadow register and OTP write lock for gp2 region. When bit 1 is set, the writing of this region's
GP2 shadow register is blocked. When bit 0 is set, the writing of this region's OTP fuse word is blocked.
21–20 Status of shadow register and OTP write lock for gp1 region. When bit 1 is set, the writing of this region's
GP1 shadow register is blocked. When bit 0 is set, the writing of this region's OTP fuse word is blocked.
19–16 This field is reserved.
- Reserved
15–14 Status of shadow register and OTP write lock for mac_addr region. When bit 1 is set, the writing of this
MAC_ADDR region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP fuse word is
blocked.
13–12 Status of shadow register and OTP write lock for usb_id region. When bit 1 is set, the writing of this
USB_ID region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP fuse word is
blocked.
11 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 883
On-Chip OTP Controller (OCOTP_CTRL)

OCOTP_HW_OCOTP_LOCK field descriptions (continued)

Field Description
10 Status of shadow register read and write, OTP read and write lock for sjc_resp region. When set, the
SJC_RESP writing of this region's shadow register and OTP fuse word are blocked. The read of this region's shadow
register and OTP fuse word are also blocked.
9 This field is reserved.
- Reserved
8–4 This field is reserved.
- Reserved
3–2 Status of shadow register and OTP write lock for boot_cfg region. When bit 1 is set, the writing of this
BOOT_CFG region's shadow register is blocked. When bit 0 is set, the writing of this region's OTP fuse word is
blocked.
TESTER Status of shadow register and OTP write lock for tester region. When bit 1 is set, the writing of this region's
shadow register is blocked. When bit 0 is set, the writing of this region's OTP fuse word is blocked.

6.3.4.10 Value of OTP Bank0 Word1 (Tester Info.)

(OCOTP_HW_OCOTP_TESTER0)

Shadowed memory mapped access to OTP Bank 0, word 1.

Address: 3035_0000h base + 410h offset = 3035_0410h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_TESTER0 field descriptions

Field Description
BITS Reflects value of OTP Bank 0, word 1. These bits become read-only after the
HW_OCOTP_LOCK_TESTER[1] bit is set.

6.3.4.11 Value of OTP Bank0 Word2 (tester Info.)

(OCOTP_HW_OCOTP_TESTER1)

shadowed memory mapped access to OTP Bank 0, word 2.

Address: 3035_0000h base + 420h offset = 3035_0420h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

884 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

OCOTP_HW_OCOTP_TESTER1 field descriptions

Field Description
BITS Reflects value of OTP Bank 0, word 2. These bits become read-only after the
HW_OCOTP_LOCK_TESTER[1] bit is set.

6.3.4.12 Value of OTP Bank0 Word3 (Tester Info.)

(OCOTP_HW_OCOTP_TESTER2)

Shadowed memory mapped access to OTP Bank 0, word 3.

Address: 3035_0000h base + 430h offset = 3035_0430h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_TESTER2 field descriptions

Field Description
BITS Reflects value of OTP Bank 0, word 3. These bits become read-only after the
HW_OCOTP_LOCK_TESTER[1] bit is set.

6.3.4.13 Value of OTP Bank1 Word0 (Tester Info.)

(OCOTP_HW_OCOTP_TESTER3)

Non-shadowed memory mapped access to OTP Bank 1, word 0.

Address: 3035_0000h base + 440h offset = 3035_0440h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_TESTER3 field descriptions

Field Description
BITS Reflects value of OTP Bank 1, word 0. These bits become read-only after the
HW_OCOTP_LOCK_TESTER[1] bit is set.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 885
On-Chip OTP Controller (OCOTP_CTRL)

6.3.4.14 Value of OTP Bank1 Word1 (Tester Info.)

(OCOTP_HW_OCOTP_TESTER4)

Shadowed memory mapped access to OTP Bank 1, word 1.

Address: 3035_0000h base + 450h offset = 3035_0450h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_TESTER4 field descriptions

Field Description
BITS Reflects value of OTP Bank 1, word 1. These bits become read-only after the
HW_OCOTP_LOCK_TESTER[1] bit is set.

6.3.4.15 Value of OTP Bank1 Word2 (Tester Info.)

(OCOTP_HW_OCOTP_TESTER5)

Shadowed memory mapped access to OTP Bank 1, word 2.

Address: 3035_0000h base + 460h offset = 3035_0460h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_TESTER5 field descriptions

Field Description
BITS Reflects value of OTP Bank 1, word 2. These bits become read-only after the
HW_OCOTP_LOCK_TESTER[1] bit is set.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

886 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.4.16 Value of OTP Bank1 Word3 (Boot Configuration Info.)

(OCOTP_HW_OCOTP_BOOT_CFG0)

Shadowed memory mapped access to OTP Bank 1, word 3.

Address: 3035_0000h base + 470h offset = 3035_0470h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_BOOT_CFG0 field descriptions

Field Description
BITS Reflects value of OTP Bank 1, word 3. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.

6.3.4.17 Value of OTP Bank2 Word0 (Boot Configuration Info.)

(OCOTP_HW_OCOTP_BOOT_CFG1)

Shadowed memory mapped access to OTP bank 2, word 0.

Address: 3035_0000h base + 480h offset = 3035_0480h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_BOOT_CFG1 field descriptions

Field Description
BITS Reflects value of OTP bank 2, word 0. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 887
On-Chip OTP Controller (OCOTP_CTRL)

6.3.4.18 Value of OTP Bank2 Word1 (Boot Configuration Info.)

(OCOTP_HW_OCOTP_BOOT_CFG2)

Shadowed memory mapped access to OTP bank 2, word 1.

Address: 3035_0000h base + 490h offset = 3035_0490h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_BOOT_CFG2 field descriptions

Field Description
BITS Reflects value of OTP bank 2, word 1. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.

6.3.4.19 Value of OTP Bank2 Word2 (Boot Configuration Info.)

(OCOTP_HW_OCOTP_BOOT_CFG3)

Shadowed memory mapped access to OTP bank 2, word 2.

Address: 3035_0000h base + 4A0h offset = 3035_04A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_BOOT_CFG3 field descriptions

Field Description
BITS Reflects value of OTP bank 2, word 2. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

888 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.4.20 Value of OTP Bank2 Word3 (BOOT Configuration Info.)

(OCOTP_HW_OCOTP_BOOT_CFG4)

Shadowed memory mapped access to OTP bank 2, word 3.

Address: 3035_0000h base + 4B0h offset = 3035_04B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_BOOT_CFG4 field descriptions

Field Description
BITS Reflects value of OTP bank 2, word 3. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.

6.3.4.21 Value of OTP Bank8 Word0 (Secure JTAG Response Field)

(OCOTP_HW_OCOTP_SJC_RESP0)

Shadowed memory mapped access to OTP Bank 8, word 0.

Address: 3035_0000h base + 600h offset = 3035_0600h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_SJC_RESP0 field descriptions

Field Description
BITS Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 8, word 0). These bits can be not read
and wrotten after the HW_OCOTP_LOCK_SJC_RESP bit is set. If read, returns 0xBADA_BADA and sets
HW_OCOTP_CTRL[ERROR].

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 889
On-Chip OTP Controller (OCOTP_CTRL)

6.3.4.22 Value of OTP Bank8 Word1 (Secure JTAG Response Field)

(OCOTP_HW_OCOTP_SJC_RESP1)

Shadowed memory mapped access to OTP Bank 8, word 1.

Address: 3035_0000h base + 610h offset = 3035_0610h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_SJC_RESP1 field descriptions

Field Description
BITS Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 8, word 1). These bits can be not read
and wrotten after the HW_OCOTP_LOCK_SJC_RESP bit is set. If read, returns 0xBADA_BADA and sets
HW_OCOTP_CTRL[ERROR].

6.3.4.23 Value of OTP Bank8 Word2 (USB ID info)

(OCOTP_HW_OCOTP_USB_ID)

Shadowed memory mapped access to OTP Bank 8, word 2.

Address: 3035_0000h base + 620h offset = 3035_0620h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_USB_ID field descriptions

Field Description
BITS Reflects value of OTP Bank 8, word 2.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

890 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.4.24 Value of OTP Bank9 Word0 (MAC Address)

(OCOTP_HW_OCOTP_MAC_ADDR0)

Shadowed memory mapped access to OTP Bank 9, word 0.

Address: 3035_0000h base + 640h offset = 3035_0640h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_MAC_ADDR0 field descriptions

Field Description
BITS Reflects value of OTP Bank 9, word 0.

6.3.4.25 Value of OTP Bank9 Word1 (MAC Address)

(OCOTP_HW_OCOTP_MAC_ADDR1)

Shadowed memory mapped access to OTP Bank 9, word 1.

Address: 3035_0000h base + 650h offset = 3035_0650h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_MAC_ADDR1 field descriptions

Field Description
BITS Reflects value of OTP Bank 9, word 1.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 891
On-Chip OTP Controller (OCOTP_CTRL)

6.3.4.26 Value of OTP Bank9 Word2 (MAC Address)

(OCOTP_HW_OCOTP_MAC_ADDR2)

Shadowed memory mapped access to OTP Bank 9, word 2.

Address: 3035_0000h base + 660h offset = 3035_0660h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_MAC_ADDR2 field descriptions

Field Description
BITS Reflects value of OTP Bank 9, word 2.

6.3.4.27 Value of OTP Bank14 Word0 () (OCOTP_HW_OCOTP_GP10)

Shadowed memory mapped access to OTP Bank 14, word 0.

Address: 3035_0000h base + 780h offset = 3035_0780h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_GP10 field descriptions

Field Description
BITS Reflects value of OTP Bank 14, word 0.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

892 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.3.4.28 Value of OTP Bank14 Word1 () (OCOTP_HW_OCOTP_GP11)

Shadowed memory mapped access to OTP Bank 14, word 1.

Address: 3035_0000h base + 790h offset = 3035_0790h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_GP11 field descriptions

Field Description
BITS Reflects value of OTP Bank 14, word 1.

6.3.4.29 Value of OTP Bank14 Word2 () (OCOTP_HW_OCOTP_GP20)

Shadowed memory mapped access to OTP Bank 14, word 2.

Address: 3035_0000h base + 7A0h offset = 3035_07A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCOTP_HW_OCOTP_GP20 field descriptions

Field Description
BITS Reflects value of OTP Bank 14, word 2.

6.3.4.30 Value of OTP Bank14 Word3 () (OCOTP_HW_OCOTP_GP21)

Shadowed memory mapped access to OTP Bank 14, word 3.

Address: 3035_0000h base + 7B0h offset = 3035_07B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 893
Secure Non-Volatile Storage (SNVS)

OCOTP_HW_OCOTP_GP21 field descriptions

Field Description
BITS Reflects value of OTP Bank 14, word 3.

6.4 Secure Non-Volatile Storage (SNVS)

6.4.1 SNVS introduction

SNVS is a companion module to the CAAM module.
SNVS incorporates both security and non-security functionality. The SNVS non-security
functionality is described in this document, but the SNVS security functionality is
described only in the Security Reference Manual.
SNVS non-security functions:
• Realtime Counter (RTC) - a software accessible realtime counter
• RTC can be set to the value in the SRTC
• General Purpose Register - a set of registers used to hold 128 bits of data specified by
software
• If the SNVS_LP power input is connected to an uninterrupted power supply, the
GPR value is maintained when main SoC is powered off
• Chip power-on/power-off - If the SNVS_LP power input is connected to an
uninterrupted power supply and the Power On button input signal is connected to a
power button external to the chip, logic within SNVS_LP can be used to wake the
chip from a power down.

6.4.1.1 SNVS feature list

The following table summarizes the features of SNVS:
Table 6-50. SNVS feature list
Feature Description Links for Further
Information
Real time counter • The RTC is driven by a dedicated clock, which is off when the SNVS_HP Real Time
(RTC) system power is down. Counter
• Programmable time alarm interrupt
General-purpose • The general-purpose register is available to software to store 128 Using the General-
register bits of data. Purpose Register
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

894 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Table 6-50. SNVS feature list (continued)

Feature Description Links for Further
Information
• The general-purpose register is zeroized when a security violation is
detected.
• If the SNVS_LP power input is connected to an uninterrupted power
supply (see SNVS power domains), the general-purpose register
value is retained even if the main chip is powered down.
Register access • Some registers/values can be written only once per boot cycle. privileged and non-
restrictions privileged registers
Wakeup from power off • Input signal from off chip requests SNVS_LP to power on the main LP Wake-Up Interrupt
SoC (Assuming that the SNVS_LP power input is connected to an Enable
uninterrupted power supply (see SNVS power domains).
• Hardware debounces the input signal using software-specified signal
bounce characteristics

6.4.1.2 SNVS functional description

SNVS implements several non-security features that involve software interaction:
• reading or writing the Realtime Counter (RTC) (This is a non-privileged operation.) -
software can also instruct SNVS to load the current SRTC value into the RTC
• reading or writing the General Purpose Register (GPR) (Note that there may be a
significant delay when reading or writing registers in the LP section if the LP clock is
different from the HP clock.)
The following sections describe in more detail the operation of SNVS.

6.4.2 SNVS Structure

SNVS is organized as two major sub-modules:
• Low-Power Section of SNVS (SNVS_LP)
The SNVS_LP section provides hardware that enables secure storage and protection
of sensitive data. The SNVS module is designed to safely hold security-related data
such as cryptographic key, time counter, monotonic counter, and general purpose
security information.
The SNVS_LP block implements the following functional units:
• Control and Status Registers
• General Purpose Registers
When the LP section is powered by an uninterrupted power supply, like a backup
battery, the state of these registers is maintained even when the main chip power is
off. (see SNVS power domains)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 895
Secure Non-Volatile Storage (SNVS)

• High-Power Section of SNVS (SNVS_HP)

The SNVS_HP section contains all SNVS status and configuration registers. It
implements all features that enable system communication and provisioning of the
SNVS_LP section.
The SNVS_HP provides an interface between SNVS_LP and the rest of the system.
The SNVS_HP block implements the following functional units:
• IP Bus Interface
• SNVS_LP Interface
• Zeroizable Master Key Programming Mechanism
• Real Time Counter with Alarm Control and Status Registers
• Control and status registers
SNVS_HP is in the chip's power supply domain and thus receives power along with
the rest of the chip.
The following figure illustrates the structure of SNVS.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

896 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

IP Bus System Reset

32/ Interrupts
MC Era Bits
System Security Configuration
HP
Config. Inputs IP Bus Interface
Secure Scan Enable
System Secure Boot & Control Periodic Interrupt

Time Alarm
Security Violations
Software
Violation
Trusted State System Security
Real Time Counter
Secure State Monitor Software
Security State Fail State Fatal Violation
Hard Reset Req.

Scan Mode

Scan Enter
Scan Control Bus
Scan Exit

HP-LP Interface

256/ VCC
OTPMK
Master Key Chip Power Domain
256/ Control Internal
Master Key LP-HP Bus

Isolation Cells
LP Control

Chip Power Supply

General Purpose Reg

dumb_pmic_default VCC
PMIC
pmic_en_b LP Power Domain
Control
btn
Security Event

Set_pwr_off_irq
LP

LP Power Supply
LP Power-On-Reset

Chip Power Fail

LP POR HP Power
Module Fail Detector

Figure 6-29. SNVS Block Diagram

6.4.2.1 SNVS power domains

In some versions of SNVS (including this version), the LP (Low Power) section is
implemented in an independent power domain from the HP (High Power) section, and
most other logic on the chip. Throughout the SNVS documentation whenever mention is

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 897
Secure Non-Volatile Storage (SNVS)

made of "always-on" logic, this assumes a version of SNVS that implements an

independent power domain for the LP section, and that the power for this section is
supplied by an uninterrupted power supply. The purpose for the independent power
domain is so that data can be retained and certain logic can remain functional even when
the main chip logic is powered down. But this is possible only if the LP domain remains
powered via an uninterrupted power supply when the main chip power domain is
powered off. Usually this uninterrupted power supply would be a battery, with possibly
some power management logic to power the LP section from main power (and perhaps
recharge the battery) when main power is on, and switch to battery power when the main
power is off. In versions of SNVS with an independent LP power domain the LP section
can be electrically isolated from the rest of the chip logic to ensure that its logic does not
get corrupted when the main chip is powered down. If the battery runs down or is
removed, an LP POR will occur when the LP section next powers up. Note that some
OEMs may choose to connect LP power to HP/main chip power and dispense with a
battery. In that case the SNVS will operate the same as an SNVS without an independent
LP power domain. No state will be retained in the LP section when the chip is powered
down, and an LP POR will occur whenever there is an HP POR.

6.4.2.2 Digital Low-Voltage Detector (LVD)

SNVS_LP incorporates a mechanism to detect interruptions of the SNVS_LP power
supply that might cause the LP control, status, and secure counter values to change. The
mechanism works as follows:
1. The LVD register (LPLVDR) is loaded with the known specific value 4173_6166h
as part of the SNVS initialization process.
2. Subsequently, this register's value is continuously compared to the hardwired value
4173_6166h.
3. If the comparison indicates that any bit has changed, a low-voltage violation is
asserted.
Digital low-voltage detection is always enabled and cannot be disabled. At LP POR this
register is reset to all 0's, so the hardwired comparison fails and a low-voltage violation is
reported. Therefore, before programming any feature in the SNVS the low-voltage
violation should be cleared. The initialization software should write the proper value
(4173_6166h) into LPLVDR (see SNVS_LP Digital Low-Voltage Detector Register
(LPLVDR)) and should then clear the low-voltage event record in the LP status register
(see SNVS_LP Status Register (LPSR)).
The following figure shows the LVD mechanism.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

898 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

32/
Low-Voltage Detector Register
Digital Low-Voltage Violation
Compare
32/

41736166h
(Hardwired value is in hexadecimal format)

Figure 6-30. Digital low-voltage detector

6.4.2.3 SNVS clock sources

The SNVS has the following clock sources:
• System peripheral clock input. This clock is used by the SNVS's internal logic, for
example, the Security State Machine. This clock can be gated outside of the module
when the SNVS indicates that it is not in use.
• HP RTC clock. This clock is used by SNVS_HP real-time counter. This clock does
not need to be synchronous with other clocks.

6.4.3 Runtime Procedures

SNVS implements a number of features that are intended to be accessed by software at
runtime (as opposed to accessed at boot time). These features include:
• Real Time Clock (see SNVS_HP Real Time Counter)
• General Purpose Register (see Using the General-Purpose Register)
Procedures for using these features are described in the following sections.

6.4.3.1 Using SNVS Timer Facilities

SNVS incorporates timer facilities that can optionally generate an interrupt at a specified
time. As described in the following sections, SNVS_HP incorporates a Real Time
Counter that is available for general use, and SNVS_LP incorporates a Secure Real Time
Counter intended for security applications.

6.4.3.1.1 SNVS_HP Real Time Counter

SNVS_HP implements a real time counter that can be read or written by any application;
it has no privileged software access restrictions. When the chip is powered down the RTC
is not active and it is reset at chip POR. The RTC can be used to generate a functional
interrupt request either at a specific time, or at a specific frequency, or both. To generate
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 899
Secure Non-Volatile Storage (SNVS)

an interrupt request at a specific time HPTA_EN is set to 0, the desired time is written to
HPTA_MS and HPTA_LS and then HPTA_EN is set to 1. HPTA_EN, HPTA_MS and
HPTA_LS can be written by any software that has access to SNVS registers; there are no
privileged access restrictions. The counter can be synchronized to the SNVS_LP SRTC
by writing to the HP_TS bit of SNVS_HP Control Register. This is particularly useful if
the SNVS_LP is powered from an uninterrupted power source because the RTC can then
be set from a chip-internal time source.

6.4.3.1.2 RTC/SRTC control bits setting

All SNVS registers are programmed from the register bus, consequently any software-
initiated changes are synchronized with the IP clock. Several registers can also change
synchronously with the RTC/SRTC clock after they are programmed. To avoid IP clock
and RTC/SRTC clock synchronization issues, the following values can be changed only
when the corresponding function is disabled.
Table 6-51. RTC/SRTC synchronized values list
Function Value/register Control bit setting
HP section
HP Real Time Counter HPRTCMR and HPRTCLR Registers RTC_EN = 0 : HPRTCMR/HPRTCLR
can be programmed
RTC_EN = 1 : HPRTCMR/HPRTCLR
cannot be programmed
HP Time Alarm HPTAMR and HPTALR Registers HPTA_EN = 0 : HPTAMR/HPTALR can
be programmed
HPTA_EN = 1 : HPTAMR/HPTALR
cannot be programmed
LP section
LP Secure Real Time Counter LPRTCMR and LPRTCLR Registers SRTC_ENV = 0 : LPRTCMR/LPRTCLR
can be programmed
SRTC_ENV = 1 : LPRTCMR/LPRTCLR
cannot be programmed
LP Time Alarm LPTAR Register LPTA_EN = 0 : LPTAR can be
programmed
LPTA_EN = 1 : LPTAR cannot be
programmed

Use the following steps to program synchronized values:

1. Check the enable bit value. If set, clear it.
2. Verify that the enable bit is cleared. There are two reasons to verify the enable bit's
setting:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

900 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

• Enable bit clearing does not happen immediately; it takes three IP clock cycles and
two RTC/SRTC clock cycles to change the enable bit's value.
• If the enable bit is locked for programming, it cannot be cleared.
3. Program the desired value.
4. Set the enable bit; it takes three IP clock cycles and two RTC/SRTC clock cycles for
the bit to set.
NOTE
Incrementing the value programmed into RTC/SRTC registers
by two compensates for the two RTC/SRTC clock cycle delay
that is required to enable the counter.

6.4.3.1.3 Reading RTC and SRTC values

Software should follow the following procedure to ensure that it has read correct data
from the RTC (HPRTCMR and HPRTCLR) and SRTC (LPSRTCMR and LPSRTCLR)
registers:
• Read the most-significant half and the least-significant half of the RTC/SRTC and
then read both halves again. If the values read are the same both times, the value is
correct.
• If the two consecutive pairs of reads yield different results, perform two more reads.
The worst case scenario may require three sessions of two consecutive pairs of reads.
There are several reasons that the values may be incorrectly read initially:
• Synchronization issues between the RTC/SRTC clock and the system clock
• Since the counter continues to increment, there may be a carry from the least-
significant 32-bits to the most-significant bits in between reading the two halves of
the counter

6.4.3.2 Using Other SNVS Registers

The sections below describe how to use the General Purpose Register.Monotonic
Counter.The sections below describe how to use the General Purpose Register and the
Monotonic Counter.

6.4.3.2.1 Using the General-Purpose Register

SNVS implements a 128-bit general-purpose register allows software to store a small
amount of data. To maintain backward compatibility with versions of SNVS that
implement only a 32-bit general purpose register, the most-significant word of the

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 901
Secure Non-Volatile Storage (SNVS)

general purpose register is aliased to the original legacy address, and to maintain
backward compatibility with versions of snvs_module_name that implement a 128-bit
general purpose register, the most-significant half of the general purpose register is
aliased to the previous legacy address address. The data in the GPR will be retained
during system power-down mode as long as the SNVS_LP remains powered by an
uninterrupted power source.

6.4.4 Reset and Initialization of SNVS

SNVS is implemented in two sections (HP and LP) that both must be initialized by
software. If the SNVS_LP is powered by an uninterrupted power source that is separate
from main SoC power, then SNVS can operate in either of two modes, depending upon
whether the main SoC power is on or off. During main SoC power-down SNVS_HP is
powered-down, but SNVS_LP is powered from the backup power supply and is
electrically isolated from the rest of the chip. In this mode SNVS_LP keeps its registers'
values but the LP registers cannot be read or written. During main SoC power-up the
isolation of SNVS_LP is disabled and both SNVS_HP and SNVS_LP are powered from
the main SoC power. Both LP and HP registers can be read and written (locks and
privilege modes permitting). Signals between the SNVS_HP and SNVS_LP sections are
enabled and all SNVS functions are operational.
Since the HP and LP sections reside in different power domains, the POR for the two
sections can occur at different times. If the SNVS_LP section remains powered by an
uninterrupted power source when the main SoC power is off, SNVS_LP is initialized
rarely, typically once when the device is first powered on and again whenever the battery
is replaced. During main SoC power-up the isolation of SNVS_LP is disabled and both
SNVS_HP and SNVS_LP are powered from the main SoC power. Signals between the
SNVS_HP and SNVS_LP sections are enabled and all SNVS functions are operational.
The SNVS_HP section is powered from the main SoC power, so it must be initialized
after the device is powered on. If the SNVS_LP section is powered from the main SoC
power rather than from an uninterrupted power source, the SNVS_LP section must also
be initialized at SoC POR.
• Initializing the LP section
• The following steps should be completed to properly initialize the SNVS LP
section (required only on LP POR, i.e. when the battery is replaced):
• Software should write the proper initialization value (41736166h) into the
LP Digital Low-Voltage Detector Register and clear the low-voltage event
record in the LP status register. See Digital Low-Voltage Detector (LVD)
for more details.
• Initializing the HP section

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

902 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

• The following steps should be completed to properly initialize the SNVS HP

section (required on HP POR, i.e. SoC POR):
• Perform normal boot to put the SNVS into a functional state (Non-secure,
Trusted, Secure) (see HP Command Register, SSM_ST bitfield).
• Program SNVS general functions/configurations (see HP Control Register).
• Set lock bits. The ms bit of the HP Lock Register should be set before
starting any functional operation.
Lock_HAC_EN only

HP_Lock
register HP_COM
register

Lock Lock
If HAC_Enable
CAAM is set, setting
HAC_CLEAR is
SFP a security
Security
Security violation which
SDC violation
violation IRQ to causes an
interrupt
TMP_DETECT control MPIC instant hard fail.
control
register
register
LP_Section

Enable

Clear
Load
Stop
HA Counter
initial value
Each Sec_Vio configured as fatal starts
the HAC in addition to initiating an IRQ. Soft fail 0010000
HA counter

0007321

Memory zeroization
Hard fail
state
RESET_REQ
27

Figure 6-31. Relationship Between the Registers

6.4.5 SNVS register descriptions

This section contains detailed register descriptions for the SNVS registers. Each
description includes a standard register diagram and register table. The register table
provides detailed descriptions of the register bit and field functions, in bit order.
SNVS registers consist of two types:
• Privileged read/write accessible
• Non-privileged read/write accessible

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 903
Secure Non-Volatile Storage (SNVS)

Privileged read/write accessible registers can only be accessed for read/write by

privileged software. Unauthorized write accesses are ignored, and unauthorized read
accesses return zero. Non-privileged software can access privileged access registers when
the non-privileged software access enable bit is set in the SNVS_HP Command Register.
• Non-Secure
• Trusted
• Secure
Non-privileged read/write accessible registers are read/write accessible by any software.
The LP register values are set only on LP POR and are unaffected by System (HP) POR.
The HP registers are set only on System POR and are unaffected by LP POR.
The following table shows the SNVS main memory map.
NOTE
For more information on security-related bitfields, see the
Security Reference Manual.

6.4.5.1 SNVS memory map

SNVS base address: 3037_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4 SNVS_HP Command Register (HPCOMR) 32 RW 0000_0000
8 SNVS_HP Control Register (HPCR) 32 RW 0000_0000
14 SNVS_HP Status Register (HPSR) 32 RW 8000_0000
24 SNVS_HP Real Time Counter MSB Register (HPRTCMR) 32 RW 0000_0000
28 SNVS_HP Real Time Counter LSB Register (HPRTCLR) 32 RW 0000_0000
2C SNVS_HP Time Alarm MSB Register (HPTAMR) 32 RW 0000_0000
30 SNVS_HP Time Alarm LSB Register (HPTALR) 32 RW 0000_0000
34 SNVS_LP Lock Register (LPLR) 32 RW 0000_0000
38 SNVS_LP Control Register (LPCR) 32 RW 0000_0020
4C SNVS_LP Status Register (LPSR) 32 RW 0000_0008
5C SNVS_LP Secure Monotonic Counter MSB Register (LPSMCMR) 32 RW 0000_0000
60 SNVS_LP Secure Monotonic Counter LSB Register (LPSMCLR) 32 RW 0000_0000
64 SNVS_LP Digital Low-Voltage Detector Register (LPLVDR) 32 RW 0000_0000
68 SNVS_LP General Purpose Register 0 (legacy alias) (LPGPR0_legac 32 RW 0000_0000
y_alias)
90 - 9C SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3) 32 RW 0000_0000
BF8 SNVS_HP Version ID Register 1 (HPVIDR1) 32 RO 003E_0103
BFC SNVS_HP Version ID Register 2 (HPVIDR2) 32 RO 0600_0300

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

904 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.2 SNVS_HP Command Register (HPCOMR)

The SNVS_HP Command Register contains the command, configuration, and control bits
for the SNVS block. This is a privileged write register.

6.4.5.2.1 Offset
Register Offset
HPCOMR 4h

6.4.5.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
NPSWA_EN

Reserved

Reserved

Reserved

Reserved

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
LP_SWR_DI
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
LP_SW

W
R
S

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.2.3 Fields
Field Description
31 Non-Privileged Software Access Enable
NPSWA_EN When set, allows non-privileged software to access all SNVS registers, including those that are privileged
software read/write access only.
0 Only privileged software can access privileged registers
1 Any software can access privileged registers
30-20 Reserved
—

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 905
Secure Non-Volatile Storage (SNVS)

Field Description
19 Reserved
—
18 Reserved
—
17 Reserved
—
16 Reserved
—
15-14 Reserved
—
13 Reserved
—
12-11 Reserved
—
10 Reserved
—
9 Reserved
—
8 Reserved
—
7-6 Reserved
—
5 LP Software Reset Disable
LP_SWR_DIS When set, disables the LP software reset. Once set, this bit can only be reset by the system reset.
0 - LP software reset is enabled
1 - LP software reset is disabled
4 LP Software Reset
LP_SWR When set to 1, the registers in the SNVS_LP section are reset.
0 - No Action
1 - Reset LP section
3 Reserved
—
2 Reserved
—
1 Reserved
—
0 Reserved
—

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

906 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.3 SNVS_HP Control Register (HPCR)

The SNVS_HP Control Register contains various control bits of the HP section of SNVS.
This is not a privileged write register.

6.4.5.3.1 Offset
Register Offset
HPCR 8h

6.4.5.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
BTN_CONFIG
BTN_MASK
Reserved

Reserved

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
HPCALB_VAL

HPCALB_EN

HPTA_EN

RTC_EN
Reserved

Reserved

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.3.3 Fields
Field Description
31-28 Reserved
—
27 Button interrupt mask.
BTN_MASK This bit is used to mask the button (BTN) interrupt request.
0: Interrupt disabled
1: Interrupt enabled

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 907
Secure Non-Volatile Storage (SNVS)

Field Description
26-24 Button Configuration.
BTN_CONFIG This field is used to configure which feature of the button (BTN) input signal constitutes "active".
000: Button signal is active high
001: Button signal is active low
010: Button signal is active on the falling edge
011: Button signal is active on the rising edge
100: Button signal is active on any edge
All other patterns are Reserved
23-17 Reserved
—
16 Reserved
—
15 Reserved
—
14-10 HP Calibration Value
HPCALB_VAL Defines signed calibration value for the HP Real Time Counter. This field can be programmed only when
RTC Calibration is disabled (HPCALB_EN is not set). This is a 5-bit 2's complement value, hence the
allowable calibration values are in the range from -16 to +15 counts per 32768 ticks of the counter.
00000 - +0 counts per each 32768 ticks of the counter
00001 - +1 counts per each 32768 ticks of the counter
00010 - +2 counts per each 32768 ticks of the counter
01111 - +15 counts per each 32768 ticks of the counter
10000 - -16 counts per each 32768 ticks of the counter
10001 - -15 counts per each 32768 ticks of the counter
11110 - -2 counts per each 32768 ticks of the counter
11111 - -1 counts per each 32768 ticks of the counter
9 Reserved
—
8 HP Real Time Counter Calibration Enabled
HPCALB_EN Indicates that the time calibration mechanism is enabled.
0 - HP Timer calibration disabled
1 - HP Timer calibration enabled
7-2 Reserved
—
1 HP Time Alarm Enable
HPTA_EN When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to
the value of the HP Real Time Counter.
0 - HP Time Alarm Interrupt is disabled
1 - HP Time Alarm Interrupt is enabled
0 HP Real Time Counter Enable. This bit syncs with the 32KHz clock. It won't update with the bus clock.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

908 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Field Description
RTC_EN 0 - RTC is disabled
1 - RTC is enabled

6.4.5.4 SNVS_HP Status Register (HPSR)

The HP Status Register reflects the internal state of the SNVS. This is not a privileged
write register.

6.4.5.4.1 Offset
Register Offset
HPSR 14h

6.4.5.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reserved

Reserved

Reserved

Reserved

W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W1C HPTA
BTN

LPDI

R
BI
Reserved

Reserved

Reserved

Reserved

Reserved
S
W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.4.3 Fields
Field Description
31 Reserved
—

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 909
Secure Non-Volatile Storage (SNVS)

Field Description
30-28 Reserved
—
27 Reserved
—
26-25 Reserved
—
24-16 Reserved
—
15-12 Reserved
—
11-8 Reserved
—
7 Button Interrupt
BI Signal ipi_snvs_btn_int_b was asserted.
6 Button
BTN Value of the BTN input. This is the external button used for PMIC control.
0: BTN not pressed
1: BTN pressed
5 Reserved
—
4 Low Power Disable
LPDIS If 1, the low power section has been disabled by means of an input signal to SNVS.
3-2 Reserved
—
1 Reserved
—
0 HP Time Alarm
HPTA Indicates that the HP Time Alarm has occurred since this bit was last cleared.
0 - No time alarm interrupt occurred.
1 - A time alarm interrupt occurred.

6.4.5.5 SNVS_HP Real Time Counter MSB Register (HPRTCMR)

The SNVS_HP Real Time Counter MSB register contains the 15 most-significant bits of
the HP Real Time Counter. This is not a privileged write register.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

910 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.5.1 Offset
Register Offset
HPRTCMR 24h

6.4.5.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

RTC

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.5.3 Fields
Field Description
31-15 Reserved
—
14-0 HP Real Time Counter
RTC The most-significant 15 bits of the RTC. This register can be programmed only when RTC is not active
(RTC_EN bit is not set).

6.4.5.6 SNVS_HP Real Time Counter LSB Register (HPRTCLR)

The SNVS_HP Real Time Counter LSB register contains the 32 least-significant bits of
the HP real time counter. This is not a privileged write register.

6.4.5.6.1 Offset
Register Offset
HPRTCLR 28h

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 911
Secure Non-Volatile Storage (SNVS)

6.4.5.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
RTC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
RTC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.6.3 Fields
Field Description
31-0 HP Real Time Counter
RTC least-significant 32 bits. This register can be programmed only when RTC is not active (RTC_EN bit is not
set).

6.4.5.7 SNVS_HP Time Alarm MSB Register (HPTAMR)

The SNVS_HP Time Alarm MSB register contains the most-significant bits of the
SNVS_HP Time Alarm value. This is not a privileged write register.

6.4.5.7.1 Offset
Register Offset
HPTAMR 2Ch

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

912 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
HPTA_MS
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.7.3 Fields
Field Description
31-15 Reserved
—
14-0 HP Time Alarm, most-significant 15 bits.
HPTA_MS This register can be programmed only when HP time alarm is disabled (HPTA_EN bit is not set).

6.4.5.8 SNVS_HP Time Alarm LSB Register (HPTALR)

The SNVS_HP Time Alarm LSB register contains the 32 least-significant bits of the
SNVS_HP Time Alarm value. This is not a privileged write register.

6.4.5.8.1 Offset
Register Offset
HPTALR 30h

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 913
Secure Non-Volatile Storage (SNVS)

6.4.5.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
HPTA_LS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
HPTA_LS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.8.3 Fields
Field Description
31-0 HP Time Alarm, 32 least-significant bits.
HPTA_LS This register can be programmed only when HP time alarm is disabled (HPTA_EN bit is not set).

6.4.5.9 SNVS_LP Lock Register (LPLR)

The SNVS_LP Lock Register contains lock bits for the SNVS_LP registers. This is a
privileged write register.

6.4.5.9.1 Offset
Register Offset
LPLR 34h

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

914 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
MC_HL
GPR_H
W

L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.9.3 Fields
Field Description
31-29 Reserved
—
28 Reserved
—
27 Reserved
—
26 Reserved
—
25 Reserved
—
24 Reserved
—
23-10 Reserved
—
9 Reserved
—
8 Reserved
—
7 Reserved
—
6 Reserved
—
5 General Purpose Register Hard Lock
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 915
Secure Non-Volatile Storage (SNVS)

Field Description
GPR_HL When set, prevents any writes to the GPR. Once set, this bit can only be reset by the LP POR.
0 - Write access is allowed.
1 - Write access is not allowed.
4 Monotonic Counter Hard Lock
MC_HL When set, prevents any writes (increments) to the MC Registers and MC_ENV bit. Once set, this bit can
only be reset by the LP POR.
0 - Write access (increment) is allowed.
1 - Write access (increment) is not allowed.
3 Reserved
—
2 Reserved
—
1 Reserved
—
0 Reserved
—

6.4.5.10 SNVS_LP Control Register (LPCR)

The SNVS_LP Control Register contains various control bits of the LP section of SNVS.
This is a privileged write register.

6.4.5.10.1 Offset
Register Offset
LPCR 38h

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

916 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BTN_PRESS_TIM
PK_OVERRIDE

DEBOUNCE
ON_TIME
Reserved

Reserved

PK_EN
W

E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPWUI_EN

MC_ENV
LVD_EN
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
TOP

DP_E
W

N
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

6.4.5.10.3 Fields
Field Description
31-25 Reserved
—
24 Reserved
—
23 PMIC On Request Override
PK_OVERRIDE The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override. That signal is
used to override the IOMUX control for the PMIC I/O pad.
22 PMIC On Request Enable
PK_EN The value written to PK_EN will be asserted on output signal snvs_lp_pk_en. That signal is used to turn
off the pullup/pulldown circuitry in the PMIC I/O pad.
21-20 The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is
asserted to turn on the SoC power.
ON_TIME
00: 500msec off->on transition time
01: 50msec off->on transition time
10: 100msec off->on transition time
11: 0msec off->on transition time
19-18 This field configures the amount of debounce time for the BTN input signal.
DEBOUNCE 00: 50msec debounce
01: 100msec debounce
10: 500msec debounce
11: 0msec debounce

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 917
Secure Non-Volatile Storage (SNVS)

Field Description
17-16 This field configures the button press time out values for the PMIC Logic.
BTN_PRESS_TI 00 : 5 secs
ME
01 : 10 secs
10 : 15 secs
11 : long press disabled (pmic_en_b will not be asserted regardlessof how long BTN is asserted)
15 Reserved
—
14-10 Reserved
—
9 Reserved
—
8 Reserved
—
7 Digital Low-Voltage Event Enable
LVD_EN By default the detection of a low-voltage event does not cause the pmic_en_b signal to be asserted.
Setting the Digital Low-Voltage Event Enable bit to 1 enables the low-voltage event for the PMIC.
0 - disabled
1 - enabled
6 Turn off System Power
TOP Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power.
This bit will clear once power is off. This bit is only valid when the Dumb PMIC is enabled.
0 - Leave system power on.
1 - Turn off system power.
5 Dumb PMIC Enabled
DP_EN When set, software can control the system power. When cleared, the system requires a Smart PMIC to
automatically turn power off.
0 - Smart PMIC enabled.
1 - Dumb PMIC enabled.
4 Reserved
—
3 LP Wake-Up Interrupt Enable
LPWUI_EN This interrupt line should be connected to the external pin and is intended to inform the external chip
about an SNVS_LP event (MC rollover, SRTC rollover, or time alarm ). This wake-up signal can be
asserted only when the chip (HP section) is powered down, and the LP section is isolated.
0 LP wake-up interrupt is disabled.
1 LP wake-up interrupt is enabled.
2 Monotonic Counter Enabled and Valid
MC_ENV When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR). Once
MC_SL or MC_HL bit is set this bit can be changed only by LP software reset or LP POR.
0 - MC is disabled or invalid.
1 - MC is enabled and valid.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

918 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Field Description
1 Reserved
—
0 Reserved
—

6.4.5.11 SNVS_LP Status Register (LPSR)

The SNVS_LP Status Register reflects the internal state and behavior of the SNVS_LP.
This is a privileged write register.

6.4.5.11.1 Offset
Register Offset
LPSR 4Ch

6.4.5.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

W1C SPO
R
Reserved

Reserved

Reserved

Reserved

Reserved
O
E
F

W1C
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C Reserved

W1C Reserved
MCR

R
Reserved

Reserved

Reserved

Reserved

Reserved

W1C

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 919
Secure Non-Volatile Storage (SNVS)

6.4.5.11.3 Fields
Field Description
31 Reserved
—
30 Reserved
—
29-20 Reserved
—
19 Reserved
—
18 Set Power Off
SPOF The SPO bit is set when the power button is pressed longer than the configured debounce time. Writing
to the SPO bit will clear the set_pwr_off_irq interrupt.
0 - Set Power Off was not detected.
1 - Set Power Off was detected.
17 Emergency Off
EO This bit is set when a power off is requested.
0 - Emergency off was not detected.
1 - Emergency off was detected.
16 Reserved
—
15-11 Reserved
—
10 Reserved
—
9 Reserved
—
8-7 Reserved
—
6-4 Reserved
—
3 Reserved
—
2 Monotonic Counter Rollover
MCR 0 - MC has not reached its maximum value.
1 - MC has reached its maximum value.
1-0 Reserved
—

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

920 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.12 SNVS_LP Secure Monotonic Counter MSB Register (LPSM

CMR)

The SNVS_LP Secure Monotonic Counter MSB Register contains the monotonic counter
era bits and the most-significant 16 bits of the monotonic counter. The monotonic counter
is incremented by one if there is a write command to the LPSMCMR or LPSMCLR
register. This is a non-privileged read-only register.

6.4.5.12.1 Offset
Register Offset
LPSMCMR 5Ch

6.4.5.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R MC_ERA_BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
MON_COUNTER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.12.3 Fields
Field Description
31-16 Monotonic Counter Era Bits
MC_ERA_BITS These bits are inputs to the module and typically connect to fuses. When the Monotonic Counter is in use
(i.e. enabled and valid and powered by an uninterrupted power source), and the boot software detects
that the Monotonic Counter most-significant 16 Bits and Monotonic Counter LSB Register have been
reset (MC_ENV=0), the boot software can take action to ensure that the value in the monotonic counter
remains monotonic (i.e. never decreasing). The action is to blow an additional MC_ERA_BITS fuse.
Since the MC_ERA_BITS field forms the most-significant field of the monotonic counter, blowing an
additional fuse guarantees that the new monotonic counter value is higher than any previous value. Since
the Monotonic Counter is reset on an LP Software Reset, an excessive number of MC_ERA_BITS fusez
may be consumed if LP Software Reset is used repeatedly.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 921
Secure Non-Volatile Storage (SNVS)

Field Description
15-0 Monotonic Counter most-significant 16 Bits
MON_COUNTE Note that writing to this register does not change the value of this field to the value that was
R written.
The 48-bit monotonic counter value (consisting of LPSMCMR[MON_COUNTER] prepended to
LPSMCLR[MON_COUNTER]) is incremented by one when:
• A write transaction to the LPSMCMR or LPSMCLR register is detected.
• The MC_ENV bit is set.
• MC_SL and MC_HL bits are not set.

This value can be reset only by LP software reset or LP POR.

6.4.5.13 SNVS_LP Secure Monotonic Counter LSB Register (LPSM

CLR)

The SNVS_LP Secure Monotonic Counter LSB Register contains the 32 least-significant
bits of the monotonic counter. The MC is incremented by one if there is a write command
to the LPSMCMR or LPSMCLR register. This is a non-privileged read-only register.

6.4.5.13.1 Offset
Register Offset
LPSMCLR 60h

6.4.5.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
MON_COUNTER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
MON_COUNTER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

922 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.13.3 Fields
Field Description
31-0 Monotonic Counter bits
MON_COUNTE Note that writing to this register does not change the value of this field to the value that was
R written.
The 48-bit monotonic counter value (consisting of LPSMCMR[MON_COUNTER] prepended to
LPSMCLR[MON_COUNTER]) is incremented by one when:
• A write transaction to the LPSMCMR or LPSMCLR register is detected.
• The MC_ENV bit is set.
• MC_SL and MC_HL bits are not set.

This value can be reset only by LP software reset or LP POR.

6.4.5.14 SNVS_LP Digital Low-Voltage Detector Register (LPLVDR)

The SNVS_LP Digital Low-Voltage Detector Register is a 32-bit read/write register that
is used for storing the low-voltage detector value, as described in Digital Low-Voltage
Detector (LVD). This is a privileged write register.

6.4.5.14.1 Offset
Register Offset
LPLVDR 64h

6.4.5.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
LVD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
LVD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 923
Secure Non-Volatile Storage (SNVS)

6.4.5.14.3 Fields
Field Description
31-0 Low-Voltage Detector Value
LVD

6.4.5.15 SNVS_LP General Purpose Register 0 (legacy alias) (LPGP

R0_legacy_alias)

See register SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3).

6.4.5.15.1 Offset
Register Offset
LPGPR0_legacy_alias 68h

6.4.5.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.15.3 Fields
Field Description
31-0 General Purpose Register
GPR When GPR_SL or GPR_HL bit is set, the register cannot be programmed.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

924 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.16 SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGP

R3)

The SNVS_LP General Purpose Register is a 128-bit read/write register located in

SNVS_LP, which can be used by any application for retaining data during an SoC power-
down mode. This is a privileged read/write register. The full GPR register is accessed as
4 32-bit registers located in successive word addresses starting at offset 90h. For
backward compatibility with earlier versions of SNVS, LPGPR0 is also aliased at its
original offset of 68h. New software should access the GPR register at the preferred
offset of 90h.

6.4.5.16.1 Offset
Register Offset
LPGPR0 90h
LPGPR1 94h
LPGPR2 98h
LPGPR3 9Ch

6.4.5.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6.4.5.16.3 Fields
Field Description
31-0 General Purpose Register
GPR When GPR_SL or GPR_HL bit is set, the register cannot be programmed.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 925
Secure Non-Volatile Storage (SNVS)

6.4.5.17 SNVS_HP Version ID Register 1 (HPVIDR1)

The SNVS_HP Version ID Register 1 is a non-privileged read-only register that contains

the current version of the SNVS. The version consists of a module ID, a major version
number, and a minor version number.

6.4.5.17.1 Offset
Register Offset
HPVIDR1 BF8h

6.4.5.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R IP_ID
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MAJOR_REV MINOR_REV
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1

6.4.5.17.3 Fields
Field Description
31-16 SNVS block ID
IP_ID
15-8 SNVS block major version number
MAJOR_REV
7-0 SNVS block minor version number
MINOR_REV

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

926 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.4.5.18 SNVS_HP Version ID Register 2 (HPVIDR2)

The SNVS_HP Version ID Register 2 is a non-privileged read-only register that indicates

the current version of the SNVS. Version ID register 2 consists of the following fields:
integration options, ECO revision, and configuration options.

6.4.5.18.1 Offset
Register Offset
HPVIDR2 BFCh

6.4.5.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R IP_ERA INTG_OPT
W
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R ECO_REV CONFIG_OPT
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0

6.4.5.18.3 Fields
Field Description
31-24 IP Era
IP_ERA 00h - Era 1 or 2
03h - Era 3
04h - Era 4
05h - Era 5
06h - Era 6
23-16 SNVS Integration Options
INTG_OPT
15-8 SNVS ECO Revision
ECO_REV
7-0 SNVS Configuration Options
CONFIG_OPT

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 927
System Reset Controller (SRC)

6.5 System Reset Controller (SRC)

6.5.1 SRC Overview

The System Reset Controller (SRC) controls the reset and boot operation of the SoC.
It is responsible for the generation of all reset signals and boot decoding.
The reset controller determines the source and the type of reset, such as POR, COLD, and
performs the necessary reset qualification and stretching sequences. Based on the type of
reset, the reset logic generates the reset sequence for the entire IC. Whenever the chip is
powered on, the reset is issued through SRC_ONOFF signal and the entire chip is reset.

6.5.1.1 Features
The SRC includes the following features.
• Receives and handles the resets from all the reset sources
• Resets the appropriate domains based upon the resets sources and the nature of the
reset
• Latches the SRC_BOOT_MODE pins and common configuration signals from the
internal fuse

6.5.2 Top-level resets, power-up sequence and external supply

integration
Information found here defines chip resets, power-up sequence, and external supply
integration.

6.5.2.1 Reset and Power-up Flow

The chip presumes the following reset and power-up flow:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

928 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

analog
External
PMIC

(button) POR_B

SRC_POR_B
PMIC_STBY_REQ CCM

PMIC_ON_REQ SoC resets

SNVS ipp_reset_b
wake-up
alarm
FSM irq
SRC
ONOFF
(No Connect)
ipp_user_reset_b
TEST_MODE

PMIC_ON_REQ acts as power-on alarm:

0->1 = power-on by alarm

PMIC_STBY_REQ enters and exits PMIC standby

0->1 = enter standby
1-> 0 = wake-up from standby

Figure 6-32. Chip reset scheme under external PMIC control

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 929
System Reset Controller (SRC)

Reset

Button press longer

than the max timeout or
Software enabled shutdown
ON

Wakeup or button press longer OFF

than Off to On configuration

Figure 6-33. Chip on/off state flow diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

930 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.5.2.2 Finite-State Machine (FSM)

ON
alarm positive edge

button pressed < 5s. button pressed > 5s.

emgergency off
generate irq
log emgergency off

alarm negative edge

OFF

button pressed (any duration)

Figure 6-34. FSM

6.5.2.3 Power mode transitions

Table 6-52. Power mode transitions
Power mode Configuration with external PMIC Configuration with internal PMIC
ON, first time 1. SoC power supply is connected to SNVS. 1. SoC power supply is connected to SNVS.
2. When button is pressed, PMIC powers 2. When button is pressed, 'state' goes ON,
on. PMIC_ON_REQ goes '1'.
3. External regulator is enabled.
Normal ON to OFF, 1. Button is pressed for a short duration on 1. SoC button is pressed for a short duration.
by button the external PMIC. 2. Interrupt request (irq) is sent to SoC from FSM.
2. Interrupt request (irq) is sent to SoC from 3. Alarm timer is set up by software routine and
external PMIC. started.
3. SoC is programming PMIC for power off 4. Upon alarm_in assertion to '1',
when standby is asserted. PMIC_ON_REQ goes '0'.
5. External regulator goes OFF.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 931
System Reset Controller (SRC)

Table 6-52. Power mode transitions (continued)

Power mode Configuration with external PMIC Configuration with internal PMIC
4. In CCM STOP mode, Standby is
asserted, PMIC gates SoC supplies.
Emergency ON to 1. Button is pressed for an extended time on 1. Button is pressed for longer than 5 seconds on
OFF, by button the external PMIC. the SoC.
2. PMIC is powering off. 2. FSM validates button pressed for 5 seconds.
3. Emergency power off is logged,
PMIC_ON_REQ goes '0', alarm_mask goes '1'.
4. External regulator goes OFF.
OFF to ON, by 1. Button is pressed on the external PMIC. 1. Button is pressed on the SoC.
button 2. PMIC powers ON. 2. PMIC_ON_REQ goes '1', alarm_mask goes '0'.
3. External regulator powers ON.
OFF to ON, by timer 1. Timer alarm in SNVS is programmed by 1. Timer alarm in SNVS is programmed by
alarm software before SoC goes OFF. software before SoC goes OFF.
2. SoC enters OFF mode. 2. SoC enters OFF mode.
3. Upon timer limit, wake up alarm goes '0'. 3. Upon timer limit, wake up alarm goes '0'.
PMIC_ON_REQ goes '1'. PMIC_ON_REQ goes '1'.
4. PMIC receives assertion of 4. External regulator is enabled by
PMIC_ON_REQ and wakes up. PMIC_ON_REQ = 1.

6.5.3 Power-On Reset and power sequencing

This SRC module generates an internal POR_B signal that is logically AND'ed with any
externally applied SRC_POR_B signal. The internal POR_B signal will be held low until
all of the following conditions are met:
• 4ms after the external power supply VDDHIGH_IN is valid
• 1ms after the VDD_SOC_CAP supply is valid
The 4ms and 1ms delays are derived from counting the 32 kHz RTC clock cycles; the
accuracy depends on the accuracy of the RTC.

6.5.3.1 External POR using SRC_POR_B

If the external SRC_POR_B signal is used to control the processor POR, SRC_POR_B
must remain low (asserted) until the VDD_ARM_CAP and VDD_SOC_CAP supplies
are stable.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

932 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.5.3.2 Internal POR

If the external SRC_POR_B signal is not used (always held high or left unconnected), the
processor defaults to the internal POR function (PMU controls generation of the POR
based on the power supplies).
If the internal POR function is used, the following power supply requirements must be
met:
• VDD_ARM_IN and VDD_SOC_IN may be supplied from the same source, or
• VDD_SOC_IN can be supplied before VDD_ARM_IN with a maximum delay of 1
ms.

6.5.4 Functional Description

6.5.4.1 Reset Control

This section details the reset control of this device.

6.5.4.1.1 Reset inputs and outputs

The reset control logic receives reset requests from all potential reset sources. All the
immediate sources of reset are directly passed to the reset stretching block, whereas the
resets requiring qualification are passed on to the reset qualification logic before they are
sent to the reset stretching block.
All reset inputs and outputs are described in the following figure:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 933
 System Reset Controller (SRC)

SRC

COLD System module reset (system_early_rst_b)

CSU Reset (csu_reset_b)
COLD
Functional module reset (system_rst_b)
SRC_ONOFF (ipp_user_reset_b)

COLD
WDOG_RST_B_DEB (wdog_rst_b) Arm Reset (arm_rst_b)

COLD
SJC S/W Reset (jtag_sw_rst) M4 Reset (m4c_rst_b, m4p_rst_b)

POR (no SJC)

SJC_TRST_B (jtag_rst_b) EIM Reset (eim_rst_b)
POR
SRC_POR_B (ipp_reset_b)

Arm POR (arm_por_rst_b)

SJC Reset (sjc_por_rst_b)

Figure 6-35. SRC inputs and outputs

The reset types and modules they affect are shown in Table 6-53. As there is no chip
POR, the POR_B is used to reset the entire chip including test logic and JTAG modules.
NOTE
All resets are expected to be active low except jtag_sw_rst.
Table 6-53. SRC reset functionality
SoC Modules POR COLD
System modules (PLLs, fuses, etc) yes yes
Functional modules yes yes
Arm yes yes
Arm SoC yes yes
M4 Core yes yes
M4 Platform yes yes
Arm POR yes no
Arm debug yes no
SJC yes no
SRTC yes no

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

934 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

The reset priorities are POR (strongest) and COLD (weakest). If a stronger reset is
asserted during the sequence of a weaker reset, then the weaker sequence will be
overridden, and the stronger reset sequence will commence. There is no priority within a
reset type (POR, etc). If a reset is asserted during the reset sequence of the same type, the
reset sequence will be interrupted and restarted.
The following lists the functionality of each of these reset outputs:
• system_early_rst_b - Resets the system modules that need to start first as CCM,
OCOTP_CTRL, FUSEBOX, etc.
• system_rst_b - Resets functional modules
• arm_rst_b - Resets Arm module (on regular system reset)
• arm_por_rst_b - Resets Arm POR input
• arm_soc_rst_b - Reset for Arm SOC
• m4c_rst_b - Reset for M4 core
• m4p_rst_b - Reset for M4 platform
• arm_dbg_rst_b - Reset debug logic of Arm
• test_logic_rst_b - Reset test logic (IOMUXC, DAP)
• sjc_por_rst_b - Reset to SJC
• srtc_rst_b - Resets SRTC
NOTE
It is assumed that each reset source will deassert after its
assertion, either due to reset generated to the system from SRC,
or by negation of the reset source (if it came from an external
source to the chip). In the latter case, the reset source is
assumed to be held for at least 2 XTALI clocks so it can be
sampled by SRC.

6.5.4.1.2 Reset Handling

6.5.4.1.2.1 POR (SRC_POR_B)

SRC_POR_B is an external reset signal. When the chip is powered up, the reset signal is
passed through the POR_B pin indicating power-up sequence. The SRC resets the entire
chip including the JTAG (SJC) module. All SRC registers will be reset during the POR
sequence.
As soon as SRC_POR_B occurs, all resets are asserted and the entire chip is reset by
SRC. The SRC_POR_B is stretched for 2 XTALI cycles and the stretching sequence
takes place after 2 XTALI clocks of POR_B pin deassertion.
The srtc_rst_b signal is deasserted together with SRC_POR_B signal. The output are also
deasserted after the stretching of SRC_POR_B has deasserted.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 935
System Reset Controller (SRC)

The sjc_por_rst_b signal is deasserted together with SRC_POR_B signal. The output is
also deasserted after the stretching of SRC_POR_B has deasserted.
After the above resets deassert, system_early_rst_b reset is deasserted after 2 XTALI
clocks. The system_early_rst_b is used for the CCM and PLL-IPs to start generating PLL
clock ouputs and the system root clocks.
When the system root clocks are ready, the CCM will assert system_clk_ready signal.
This signal is generated during the start sequence in the CCM and it involves the
preparation of the PLLs to generate clock roots for functional operation.
SRC then enables OCOTP_CTRL and fusebox clocks, so that fuses can be loaded to
OCOTP_CTRL.
• SRC will prepare the boot information
• After 8 ipg cycles, resets to all modules will be de-asserted
• After 8 ipg cycles, system clocks will be enabled (en_system_clk).

6.5.4.1.2.2 COLD RESET

The sequence is similar to SRC_POR_B except the memory repair operation is not
performed.
After the reset source deasserts, system_early_rst_b reset is deasserted after at least 2
XTALI clocks. The system_early_rst_b is used for the CCM and PLL-IPs to start
generating PLL clock outputs and the system root clocks.
After the system root clocks are ready, the CCM will assert system_clk_ready signal.
This signal is generated during the start sequence in the CCM and it involves the
preparation of the PLLs to generate clock roots for functional operation. See CCM for
more information.
After system_clk_ready arrives at the SRC, it will enable OCOTP_CTRL and fusebox
clocks, so that fuses can be loaded to OCOTP_CTRL. OCOTP_CTRL will notify with
iim_ready_flag when the fusebox loading finishes.
• SRC will prepare the boot information
• After 8 ipg cycles resets to all modules will be deasserted
• After 8 ipg cycles, system clocks will be enabled (en_system_clk).

6.5.4.2 Parallel Reset Requests

SRC will follow the following rules in the case of parallel reset requests:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

936 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

1. The order of strength of resets is POR - strongest, COLD - weakest

2. If a stronger reset is asserted during weaker reset sequence, then the stronger reset
will take over and the stronger reset process will commence. The following cases fall
into this category:
• POR reset request in the middle of cold reset process - the cold will be stopped
and the POR sequence will start.
3. If a weaker reset is asserted during stronger reset sequence, then the stronger reset
sequence will continue without interference. If at the end of the stronger reset process
the weaker request is still asserted then the weaker sequence will commence. The
following cases fall into this category:
• COLD reset requests in the middle of POR reset process - the POR process will
continue without interference.
4. If a similar reset request is asserted during the process of reset handling, then the
process of reset handling will start over (with the same process). The following cases
fall into this category:
• POR reset request in the middle of POR reset process - the POR process will
start over.
• COLD reset request in the middle of COLD reset process - the COLD process
will start over.

6.5.4.3 Boot Mode Control

6.5.4.3.1 BOOT_MODE Pin Latching

The exact boot sequence is controlled by the values of the BOOT_MODE pins on this
device.
The value of the BOOT_MODE pins will be latched after the OCOTP_CTRL asserts the
fuse read completion flag. After latching, the values of the BOOT_MODE pins are used
to determine the booting options of the core as described in the SRC_SBMRx registers.
The boot mode general purpose bits can be provided to the SRC from either e-fuses or
GPIO signals. The gpio_bt_sel e-fuse defines the source to be used to derive the boot
information. When gpio_bt_sel is set, e-fuses are used. When cleared, GPIO signals are
used.
The boot information is provided in SRC_SBMR1 register. The figure below shows the
selection of boot mode information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 937
System Reset Controller (SRC)

BOOT_MODE1

BOOT_MODE0
BOOT_MODE0
BOOT_MODE1

GPIO_BT_SEL_FUSE
BOOT_MODE0
BOOT_MODE1
BOOT_CFG[19:16]

BOOT_CFG[15:8]
0

BOOT_CFG[7:0]

SRC_SBMR1
Register
chip
fuses BOOT_CFG[19:16]

e-fuse signals

BOOT_CFG[15:8] 1

BOOT_CFG[7:0]

Figure 6-36. Boot mode information

6.5.5 SRC Memory Map/Register Definition

SRC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
6.5.5.1/
3039_0000 SRC Reset Control Register (SRC_SCR) 32 R/W 0000_00A0h
940
6.5.5.2/
3039_0004 A53 Reset Control Register (SRC_A53RCR0) 32 R/W 000A_0000h
941
6.5.5.3/
3039_0008 A53 Reset Control Register (SRC_A53RCR1) 32 R/W 0000_0001h
946
6.5.5.4/
3039_000C M4 Reset Control Register (SRC_M4RCR) 32 R/W 0000_00A8h
948
USB OTG PHY1 Reset Control Register 6.5.5.5/
3039_0020 32 R/W 0000_0000h
(SRC_USBOPHY1_RCR) 951
USB OTG PHY2 Reset Control Register 6.5.5.6/
3039_0024 32 R/W 0000_0000h
(SRC_USBOPHY2_RCR) 953
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

938 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
6.5.5.7/
3039_0028 MIPI PHY Reset Control Register (SRC_MIPIPHY_RCR) 32 R/W 0000_0000h
954
6.5.5.8/
3039_002C PCIE PHY Reset Control Register (SRC_PCIEPHY_RCR) 32 R/W 0000_000Ah
956
6.5.5.9/
3039_0034 DISPLAY Reset Control Register (SRC_DISP_RCR) 32 R/W 0000_0000h
958
6.5.5.10/
3039_0040 GPU Reset Control Register (SRC_GPU_RCR) 32 R/W 0000_0000h
960
6.5.5.11/
3039_0044 VPU Reset Control Register (SRC_VPU_RCR) 32 R/W 0000_0000h
961
6.5.5.12/
3039_0058 SRC Boot Mode Register 1 (SRC_SBMR1) 32 R 0000_0000h
963
6.5.5.13/
3039_005C SRC Reset Status Register (SRC_SRSR) 32 R/W 0000_0001h
963
6.5.5.14/
3039_0068 SRC Interrupt Status Register (SRC_SISR) 32 R/W 0000_0000h
966
6.5.5.15/
3039_006C SRC Interrupt Mask Register (SRC_SIMR) 32 R/W 0000_03FFh
968
6.5.5.16/
3039_0070 SRC Boot Mode Register 2 (SRC_SBMR2) 32 R 0000_0000h
970
6.5.5.17/
3039_0074 SRC General Purpose Register 1 (SRC_GPR1) 32 R/W 0000_0000h
972
6.5.5.18/
3039_0078 SRC General Purpose Register 2 (SRC_GPR2) 32 R/W 0000_0000h
972
6.5.5.19/
3039_007C SRC General Purpose Register 3 (SRC_GPR3) 32 R/W 0000_0000h
972
6.5.5.20/
3039_0080 SRC General Purpose Register 4 (SRC_GPR4) 32 R/W 0000_0000h
973
6.5.5.21/
3039_0084 SRC General Purpose Register 5 (SRC_GPR5) 32 R/W 0000_0000h
973
6.5.5.22/
3039_0088 SRC General Purpose Register 6 (SRC_GPR6) 32 R/W 0000_0000h
974
6.5.5.23/
3039_008C SRC General Purpose Register 7 (SRC_GPR7) 32 R/W 0000_0000h
974
6.5.5.24/
3039_0090 SRC General Purpose Register 8 (SRC_GPR8) 32 R/W 0000_0000h
974
6.5.5.25/
3039_0094 SRC General Purpose Register 9 (SRC_GPR9) 32 R/W 0000_0000h
975
6.5.5.26/
3039_0098 SRC General Purpose Register 10 (SRC_GPR10) 32 R/W 0000_0000h
975
SRC DDR Controller Reset Control Register 6.5.5.27/
3039_1000 32 R/W 0000_000Fh
(SRC_DDRC_RCR) 976

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 939
System Reset Controller (SRC)

6.5.5.1 SRC Reset Control Register (SRC_SCR)

The reset control register (SCR), contains bits that control operation of the reset
controller.
Address: 3039_0000h base + 0h offset = 3039_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
R
DOM_EN

LOCK

Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
MASK_TEMPSENSE_
Reserved Reserved
RESET
W

Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

SRC_SCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

940 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_SCR field descriptions (continued)

Field Description
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–8 This field is reserved.
- Reserved
7–4 Mask tempsense_reset source. If these 4 bits are coded from A to 5 then, the tempsense_reset input to
MASK_ SRC will be masked and the tempsense_reset will not create a reset to the chip.
TEMPSENSE_
RESET 0101 tempsense_reset is masked
1010 tempsense_reset is not masked
- This field is reserved.
Reserved

6.5.5.2 A53 Reset Control Register (SRC_A53RCR0)

The A53 Reset Control Register (A53RCR), contains bits that control the A53 reset
generation.
Address: 3039_0000h base + 4h offset = 3039_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A53_SOC_DBG_
A53_L2RESET

R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

RESET
LOCK

Reserved Reserved MASK_WDOG1_RST

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A53_DBG_RESET3

A53_DBG_RESET2

A53_DBG_RESET1

A53_DBG_RESET0
A53_ETM_RESET3

A53_ETM_RESET2

A53_ETM_RESET1

A53_ETM_RESET0

A53_CORE_POR_

A53_CORE_POR_

A53_CORE_POR_

A53_CORE_POR_

R
A53_CORE_

A53_CORE_

A53_CORE_

A53_CORE_
RESET3

RESET2

RESET1

RESET0

RESET3

RESET2

RESET1

RESET0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 941
System Reset Controller (SRC)

SRC_A53RCR0 field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–22 This field is reserved.
- Reserved
21
A53_L2RESET Software reset for A53 Snoop Control Unit (SCU).

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert SCU reset

1 assert SCU reset
20
A53_SOC_DBG_ Software reset for system level debug reset. It initializes the shared Debug APB, the CTI, and the CTM. It
RESET also causes:
• A53_dbgreset[3:0] and A53_etmreset[3:0] to be asserted
• debug logic in the processor power domain and in the debug power domain to be reset
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

942 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_A53RCR0 field descriptions (continued)

Field Description
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert system level debug reset

1 assert system level debug reset
19–16
MASK_WDOG1_ Mask wdog1_rst_b source. If these 4 bits are coded from A to 5 then, the wdog1_rst_b input to SRC will
RST be masked and the wdog1_rst_b will not create a reset to the chip.

NOTE: During the time the WDOG event is masked using SRC logic, it is likely that the WDOG Reset
Status Register (WRSR) bit 1 (which indicates a WDOG timeout event) will get asserted.
software / OS developer must prepare for this case. Re-enabling the WDOG is possible, by un-
masking it in SRC, though it must be preceded by servicing the WDOG. However, for the case
that the event has been asserted, the status bit (WRSR bit-1) will remain asserted, regardless of
servicing the WDOG module.
(Hardware reset is the only way to cause the de-assertion of that bit). Any other code will be coded to
1010 i.e. wdog1_rst_b is not masked

0101 wdog1_rst_b is masked

1010 wdog1_rst_b is not masked
15 Software reset for core3 ETM only.
A53_ETM_
RESET3 NOTE: This is a self clearing bit. Once it is set to 1, the rest process will begin, and once it finished, this
bit will be self-cleared.

0 do not assert core3 ETM reset

1 assert core3 ETM reset
14 Software reset for core2 ETM only.
A53_ETM_
RESET2 NOTE: This is a self clearing bit. Once it is set to 1, the rest process will begin, and once it finished, this
bit will be self-cleared.

0 do not assert core2 ETM reset

1 assert core2 ETM reset
13
A53_ETM_ Software reset for core1 ETM only.
RESET1
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core1 ETM reset

1 assert core1 ETM reset
12
A53_ETM_ Software reset for core0 ETM only.
RESET0
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core0 ETM reset

1 assert core0 ETM reset
11
A53_DBG_ Software reset for core3 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET3 core3 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 943
System Reset Controller (SRC)

SRC_A53RCR0 field descriptions (continued)

Field Description
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core3 debug reset

1 assert core3 debug reset
10
A53_DBG_ Software reset for core2 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET2 core2 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core2 debug reset

1 assert core2 debug reset
9
A53_DBG_ Software reset for core1 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET1 core1 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core1 debug reset

1 assert core1 debug reset
8
A53_DBG_ Software reset for core0 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET0 core1 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core0 debug reset

1 assert core0 debug reset
7
A53_CORE_ Software reset for core3 only. It initializes the processor logic in the core1 processor power domains, not
RESET3 including the debug, breakpoint and watchpoint logic.

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core3 reset

1 assert core3 reset
6
A53_CORE_ Software reset for core2 only. It initializes the processor logic in the core1 processor power domains, not
RESET2 including the debug, breakpoint and watchpoint logic.

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core2 reset

1 assert core2 reset

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

944 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_A53RCR0 field descriptions (continued)

Field Description
5
A53_CORE_ Software reset for core1 only. It initializes the processor logic in the core1 processor power domains, not
RESET1 including the debug, breakpoint and watchpoint logic.

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core1 reset

1 assert core1 reset
4
A53_CORE_ Software reset for core0 only. It initializes the processor logic in the core0 processor power domains, not
RESET0 including the debug, breakpoint and watchpoint logic.

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core0 reset

1 assert core0 reset
3
A53_CORE_ POR reset for A53 core3 only. It initializes all the core1 processor logic, including CPU Debug, and
POR_RESET3 breakpoint and watchpoint logic in the core3 processor power domains

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core3 reset

1 assert core3 reset
2
A53_CORE_ POR reset for A53 core2 only. It initializes all the core1 processor logic, including CPU Debug, and
POR_RESET2 breakpoint and watchpoint logic in the core2 processor power domains

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core2 reset

1 assert core2 reset
1
A53_CORE_ POR reset for A53 core1 only. It initializes all the core1 processor logic, including CPU Debug, and
POR_RESET1 breakpoint and watchpoint logic in the core1 processor power domains

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core1 reset

1 assert core1 reset
0
A53_CORE_ POR reset for A53 core0 only. It initializes all the core0 processor logic, including CPU Debug, and
POR_RESET0 breakpoint and watchpoint logic in the core0 processor power domains

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.

0 do not assert core0 reset

1 assert core0 reset

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 945
System Reset Controller (SRC)

6.5.5.3 A53 Reset Control Register (SRC_A53RCR1)

The A53 Reset Control Register (A53RCR), contains bits that control the A53 reset
generation.
Address: 3039_0000h base + 8h offset = 3039_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A53_CORE0_ENABLE
R
A53_CORE3_ENABLE

A53_CORE2_ENABLE

A53_CORE1_ENABLE

Reserved A53_RST_SLOW

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

946 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_A53RCR1 field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–7 This field is reserved.
- Reserved
6–4 A53_RST_SLOW
A53_RST_SLOW
3 core 3 enable
A53_CORE3_
ENABLE 0 core3 is disabled
1 core3 is enabled
2 core 2 enable
A53_CORE2_
ENABLE 0 core2 is disabled
1 core2 is enabled
1 core 1 enable
A53_CORE1_
ENABLE
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 947
System Reset Controller (SRC)

SRC_A53RCR1 field descriptions (continued)

Field Description
0 core1 is disabled
1 core1 is enabled
0 Always 1, can't be changed.
A53_CORE0_
ENABLE

6.5.5.4 M4 Reset Control Register (SRC_M4RCR)

The M4 Reset Control Register (M4RCR), contains bits that control the M4 reset
generation.
Address: 3039_0000h base + Ch offset = 3039_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SW_M4C_NON_
WDOG3_RST_

WDOG3_RST_

SW_M4C_RST
SW_M4P_RST
R

ENABLE_M4
OPTION_M4

SCLR_RST
OPTION

Reserved MASK_WDOG3_RST

Reset 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0

SRC_M4RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

948 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_M4RCR field descriptions (continued)

Field Description
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–10 This field is reserved.
- Reserved
9 Wdog3_rst_b option
WDOG3_RST_
OPTION 0 Wdog3_rst_b asserts M4 reset
1 Wdog3_rst_b asserts global reset
8 Wdog3_rst_b option for M4. This bit is only effective when wdog3_rst_option is set to 1.
WDOG3_RST_
OPTION_M4 0 wdgo3_rst_b Reset M4 core only
1 Reset both M4 core and platform
7–4
MASK_WDOG3_ Mask wdog3_rst_b source. If these 4 bits are coded from A to 5 then, the wdog3_rst_b input to SRC will
RST be masked and the wdog3_rst_b will not create a reset to the chip.

NOTE: During the time the WDOG3 event is masked using SRC logic, it is likely that the WDOG3 Reset
Status Register (WRSR) bit 1 (which indicates a WDOG3 timeout event) will get asserted.
Software / OS developer must prepare for this case. Re-enabling the WDOG3 is possible, by un-
masking it in SRC, though it must be preceded by servicing the WDOG3. However, for the case
that the event has been asserted, the status bit (WRSR bit-1) will remain asserted, regardless of
servicing the WDOG3 module.
(Hardware reset is the only way to cause the de-assertion of that bit). Any other code will be coded to
1010 i.e. wdog3_rst_b is not masked

0101 wdog3_rst_b is masked

1010 wdog3_rst_b is not masked
3 Enable M4
ENABLE_M4
0 M4 is disabled
1 M4 is enabled

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 949
System Reset Controller (SRC)

SRC_M4RCR field descriptions (continued)

Field Description
2
SW_M4P_RST Self-clearing SW reset for M4 platform

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared. Software can determine that the reset has finished once this bit is cleared.
Software can also configure SRC to generate interrupt once the software has finished. Please
refer to SRC_SISR register for details.

0 do not assert M4 platform reset

1 assert M4 platform reset
1
SW_M4C_RST Self-clearing SW reset for M4 core

NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared. Software can determine that the reset has finished once this bit is cleared.
Software can also configure SRC to generate interrupt once the software has finished. Please
refer to SRC_SISR register for details.

0 do not assert M4 core reset

1 assert M4 core reset
0 Non-self-clearing SW reset for M4 core
SW_M4C_NON_
SCLR_RST 0 do not assert M4 core reset
1 assert M4 core reset

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

950 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.5.5.5 USB OTG PHY1 Reset Control Register

(SRC_USBOPHY1_RCR)

The USB OTG PHY1 Reset Control Register (SRC_IP_RCR2), contains bits that control
the USB OTG PHY1 reset generation.
Address: 3039_0000h base + 20h offset = 3039_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OTG1_PHY_RES
R

Reserved

ET
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_USBOPHY1_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 951
System Reset Controller (SRC)

SRC_USBOPHY1_RCR field descriptions (continued)

Field Description
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 0 Don't reset USB OTG1 PHY
OTG1_PHY_RE 1 Reset USB OTG1 PHY
SET

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

952 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.5.5.6 USB OTG PHY2 Reset Control Register

(SRC_USBOPHY2_RCR)

The USB OTG PHY2 Reset Control Register (SRC_IP_RCR2), contains bits that control
the USB OTG PHY2 reset generation.
Address: 3039_0000h base + 24h offset = 3039_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OTG2_PHY_RES
R

Reserved

ET
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_USBOPHY2_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 953
System Reset Controller (SRC)

SRC_USBOPHY2_RCR field descriptions (continued)

Field Description
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 0 Don't reset USB OTG2 PHY
OTG2_PHY_RE 1 Reset USB OTG2 PHY
SET

6.5.5.7 MIPI PHY Reset Control Register (SRC_MIPIPHY_RCR)

The MIPI PHY Reset Control Register (SRC_MIPIPHY_RCR), contains bits that control
the MIPI PHYreset generation.
Address: 3039_0000h base + 28h offset = 3039_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0

R
DOM_EN

LOCK

Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

954 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_MIPIPHY_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 955
System Reset Controller (SRC)

6.5.5.8 PCIE PHY Reset Control Register (SRC_PCIEPHY_RCR)

The PCIE PHY Control Register (SRC_PCIEPHY_RCR), contains bits that control the
PCIE PHY reset generation.
Address: 3039_0000h base + 2Ch offset = 3039_002Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCIE_CTRL_APP_XFER_
R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0

PENDING
DOM_EN

LOCK

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCIE_PHY_POWER_ON_
PCIE_CTRL_APPS_CLK_
PCIE_CTRL_APPS_EXIT
PCIE_CTRL_APPS_PME

PCIE_CTRL_APPS_RST
PCIE_CTRL_APPS_EN
PCIE_CTRL_CFG_L1_
PCIE_CTRL_SYS_INT

PCIE_CTRL_APPS_

PCIE_CTRL_APPS_

PCIE_CTRL_APPS_

PCIEPHY_BTNRST
PCIE_CTRL_APP_

PCIEPHY_PERST
R
UNLOCK_MSG

TURNOFF
Reserved

Reserved
READY
ENTER

RESET
REQ
AUX

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

SRC_PCIEPHY_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

956 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_PCIEPHY_RCR field descriptions (continued)

Field Description
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–17 This field is reserved.
- Reserved
16 PCIE_CTRL_APP_XFER_PENDING
PCIE_CTRL_
APP_XFER_
PENDING
15 PCIE_CTRL_APP_UNLOCK_MSG
PCIE_CTRL_
APP_UNLOCK_
MSG
14 PCIE_CTRL_SYS_INT
PCIE_CTRL_
SYS_INT
13 This field is reserved.
-
12 Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en
PCIE_CTRL_
CFG_L1_AUX
11 Pcie_ctrl_apps_pm_xmt_turnoff
PCIE_CTRL_
APPS_
TURNOFF
10 Pcie_ctrl_apps_pm_xmt_pme
PCIE_CTRL_
APPS_PME
9 Pcie_ctrl_app_req_exit_l1
PCIE_CTRL_
APPS_EXIT
8 Pcie_ctrl_app_req_entr_l1
PCIE_CTRL_
APPS_ENTER

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 957
System Reset Controller (SRC)

SRC_PCIEPHY_RCR field descriptions (continued)

Field Description
7 Pcie_ctrl_app_ready_entr_l23
PCIE_CTRL_
APPS_READY
6 Pcie_ctrl_app_ltssm_enable
PCIE_CTRL_
APPS_EN
5 Pcie_ctrl_app_init_rst
PCIE_CTRL_
APPS_RST
4 Pcie_ctrl_app_clk_req_n
PCIE_CTRL_
APPS_CLK_REQ
3 Pciephy_perst
PCIEPHY_
PERST
2 PCIE PHY button
PCIEPHY_BTNR
ST
1 This field is reserved.
- Reserved
0 PCIE_PHY_POWER_ON_RESET
PCIE_PHY_
POWER_ON_
RESET

6.5.5.9 DISPLAY Reset Control Register (SRC_DISP_RCR)

The DISPLAY Control Register contains bits that control the DISPLAY reset generation.
Address: 3039_0000h base + 34h offset = 3039_0034h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISP_RESET

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

958 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_DISP_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 0 Don't reset dispmix
DISP_RESET 1 Reset dispmix

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 959
System Reset Controller (SRC)

6.5.5.10 GPU Reset Control Register (SRC_GPU_RCR)

The GPU Control Register contains bits that control the GPU reset generation.
Address: 3039_0000h base + 40h offset = 3039_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPU_RESET
R

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPU_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

960 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_GPU_RCR field descriptions (continued)

Field Description
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 GPU_RESET
GPU_RESET

6.5.5.11 VPU Reset Control Register (SRC_VPU_RCR)

The VPU Control Register contains bits that control the VPU reset generation.
Address: 3039_0000h base + 44h offset = 3039_0044h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VPU_RESET
R

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_VPU_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 961
System Reset Controller (SRC)

SRC_VPU_RCR field descriptions (continued)

Field Description
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 VPU_RESET
VPU_RESET

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

962 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.5.5.12 SRC Boot Mode Register 1 (SRC_SBMR1)

The Boot Mode register (SBMR) contains bits that reflect the status of Boot Mode Pins
of the chip. The reset value is configuration dependent (depending on boot/fuses/IO
pads).
Address: 3039_0000h base + 58h offset = 3039_0058h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R BOOT_CFG
Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_SBMR1 field descriptions

Field Description
31–20 This field is reserved.
- Reserved
BOOT_CFG Refer to fusemap.

6.5.5.13 SRC Reset Status Register (SRC_SRSR)

The SRSR is a write to one clear register which records the source of the reset events for
the chip. The SRC reset status register will capture all the reset sources that have
occurred. This register is reset on ipp_reset_b. This is a read-write register.
For bit[9-0] - writing zero does not have any effect. Writing one will clear the
corresponding bit. The individual bits can be cleared by writing one to that bit. When the
system comes out of reset, this register will have bits set corresponding to all the reset
sources that occurred during system reset. Software has to take care to clear this register
by writing one after every reset that occurs so that the register will contain the
information of recently occurred reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 963
System Reset Controller (SRC)

Address: 3039_0000h base + 5Ch offset = 3039_005Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ipp_user_reset_b
wdog2_rst_b

wdog3_rst_b

wdog1_rst_b

csu_reset_b

ipp_reset_b
jtag_sw_rst

jtag_rst_b
R 0 0
tempsense_rst_b

W w1c w1c w1c w1c w1c w1c w1c w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

SRC_SRSR field descriptions

Field Description
31–10 This read-only field is reserved and always has the value 0.
Reserved
9 Temper Sensor software reset. Indicates whether the reset was the result of software reset from on-chip
tempsense_rst_b Temperature Sensor.

0 Reset is not a result of software reset from Temperature Sensor.

1 Reset is a result of software reset from Temperature Sensor.
8 IC Watchdog2 Time-out reset. Indicates whether the reset was the result of the watchdog2 time-out event.
wdog2_rst_b
0 Reset is not a result of the watchdog4 time-out event.
1 Reset is a result of the watchdog4 time-out event.
7 IC Watchdog3 Time-out reset. Indicates whether the reset was the result of the watchdog3 time-out event.
wdog3_rst_b
0 Reset is not a result of the watchdog3 time-out event.
1 Reset is a result of the watchdog3 time-out event.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

964 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_SRSR field descriptions (continued)

Field Description
6 JTAG software reset. Indicates whether the reset was the result of software reset from JTAG.
jtag_sw_rst
0 Reset is not a result of software reset from JTAG.
1 Reset is a result of software reset from JTAG.
5 HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG.
jtag_rst_b
0 Reset is not a result of HIGH-Z reset from JTAG.
1 Reset is a result of HIGH-Z reset from JTAG.
4 IC Watchdog1 Time-out reset. Indicates whether the reset was the result of the watchdog time-out event.
wdog1_rst_b
0 Reset is not a result of the watchdog1 time-out event.
1 Reset is a result of the watchdog1 time-out event.
3 Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.
ipp_user_reset_b
0 Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
1 Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
2 Indicates whether the reset was the result of the csu_reset_b input.
csu_reset_b
NOTE: If case the csu_reset_b occurred during a WARM reset process, during the phase that ipg_clk is
not available yet, then the occurrence of CSU reset will not be reflected in this bit.

0 Reset is not a result of the csu_reset_b event.

1 Reset is a result of the csu_reset_b event.
1 This read-only field is reserved and always has the value 0.
Reserved
0 Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)
ipp_reset_b
0 Reset is not a result of ipp_reset_b pin.
1 Reset is a result of ipp_reset_b pin.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 965
System Reset Controller (SRC)

6.5.5.14 SRC Interrupt Status Register (SRC_SISR)

Address: 3039_0000h base + 68h offset = 3039_0068h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISPLAY_PASSED_RESET

OTGPHY2_PASSED_RESE

OTGPHY1_PASSED_RESE
GPU_PASSED_RESET

PCIE1_PHY_PASSED_
M4C_PASSED_RESET
VPU_PASSED_RESET

M4P_PASSED_RESET

RESET

R
T

T
Reserved

Reserved

Reserved

Reserved
Reserved

W w1c w1c w1c w1c w1c w1c w1c w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

966 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_SISR field descriptions

Field Description
31–12 This field is reserved.
- Reserved
11 Interrupt generated to indicate that VPU passed software reset and is ready to be used
VPU_PASSED_
RESET 0 interrupt generated not due to VPU reset
1 interrupt generated due to VPU reset
10 Interrupt generated to indicate that GPU passed software reset and is ready to be used
GPU_PASSED_
RESET 0 interrupt generated not due to GPU reset
1 interrupt generated due to GPU reset
9 Interrupt generated to indicate that m4 platform passed software reset and is ready to be used
M4P_PASSED_
RESET 0 interrupt generated not due to m4 platform reset
1 interrupt generated due to m4 platform reset
8 Interrupt generated to indicate that m4 core passed software reset and is ready to be used
M4C_PASSED_
RESET 0 interrupt generated not due to m4 core reset
1 interrupt generated due to m4 core reset
7 Interrupt generated to indicate that DISPLAY passed software reset and is ready to be used
DISPLAY_
PASSED_ 0 Interrupt generated not due to DISPLAY passed reset
RESET 1 Interrupt generated due to DISPLAY passed reset
6 This field is reserved.
- Reserved
5 Interrupt generated to indicate that PCIE1 PHY passed software reset and is ready to be used
PCIE1_PHY_
PASSED_ 0 Interrupt generated not due to PCIE1 PHY passed reset
RESET 1 Interrupt generated due to PCIE1 PHY passed reset
4 This field is reserved.
- Reserved
3 Interrupt generated to indicate that OTG PHY2 passed software reset and is ready to be used
OTGPHY2_PAS
SED_RESET 0 Interrupt generated not due to OTG PHY2 passed reset
1 Interrupt generated due to OTG PHY2 passed reset
2 Interrupt generated to indicate that OTG PHY1 passed software reset and is ready to be used
OTGPHY1_PAS
SED_RESET 0 Interrupt generated not due to OTG PHY1 passed reset
1 Interrupt generated due to OTG PHY1 passed reset
1 This field is reserved.
- Reserved
0 This field is reserved.
- Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 967
System Reset Controller (SRC)

6.5.5.15 SRC Interrupt Mask Register (SRC_SIMR)

Address: 3039_0000h base + 6Ch offset = 3039_006Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MASK_OTGPHY2_PASS

MASK_OTGPHY1_PASS
MASK_M4P_PASSED_R
MASK_GPU_PASSED_

MASK_M4C_PASSED_
MASK_VPU_PASSED_

MASK_PCIE_PHY_
MASK_DISPLAY_
PASSED_RESET

PASSED_RESET
R

ED_RESET

ED_RESET
Reserved

Reserved
RESET

RESET

RESET
ESET

Reserved Reserved

Reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

SRC_SIMR field descriptions

Field Description
31–12 This field is reserved.
- Reserved
11 Mask interrupt generation due to VPU passed reset
MASK_VPU_
PASSED_ 0 do not mask interrupt due to VPU passed reset - interrupt will be created
RESET 1 mask interrupt due to VPU passed reset
10 Mask interrupt generation due to GPU passed reset
MASK_GPU_
PASSED_ 0 do not mask interrupt due to GPU passed reset - interrupt will be created
RESET 1 mask interrupt due to GPU passed reset
9 mask interrupt generation due to m4 platform passed reset
MASK_M4P_PA
SSED_RESET 0 do not mask interrupt due to m4 platform passed reset - interrupt will be created
1 mask interrupt due to m4 platform passed reset
8 mask interrupt generation due to m4 core passed reset
MASK_M4C_
PASSED_ 0 do not mask interrupt due to m4 core passed reset - interrupt will be created
RESET 1 mask interrupt due to m4 core passed reset

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

968 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_SIMR field descriptions (continued)

Field Description
7 Mask interrupt generation due to display passed reset
MASK_
DISPLAY_ 0 do not mask interrupt due to display passed reset - interrupt will be created
PASSED_ 1 mask interrupt due to display passed reset
RESET
6 This field is reserved.
- Reserved
5 Mask interrupt generation due to PCIE PHY passed reset
MASK_PCIE_
PHY_PASSED_ 0 do not mask interrupt due to PCIE PHY passed reset - interrupt will be created
RESET 1 mask interrupt due to PCIE PHY passed reset
4 This field is reserved.
- Reserved
3 mask interrupt generation due to OTG PHY2 passed reset
MASK_OTGPHY
2_PASSED_RES 0 do not mask interrupt due to OTG PHY2 passed reset - interrupt will be created
ET 1 mask interrupt due to OTG PHY2 passed reset
2 mask interrupt generation due to OTG PHY1 passed reset
MASK_OTGPHY
1_PASSED_RES 0 do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created
ET 1 mask interrupt due to OTG PHY1 passed reset
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 969
System Reset Controller (SRC)

6.5.5.16 SRC Boot Mode Register 2 (SRC_SBMR2)

The Boot Mode register (SBMR), contains bits that reflect the status of Boot Mode Pins
of the chip. The default values for those bits depends on the values of pins/fuses during
reset sequence.
Address: 3039_0000h base + 70h offset = 3039_0070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IPP_BOOT_
R 0 0
MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

970 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEC_CONFIG[1:0]
BT_FUSE_SEL
FORCE_COLD_
R 0 0
BOOT

Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_SBMR2 field descriptions

Field Description
31–26 This read-only field is reserved and always has the value 0.
Reserved
25–24 IPP_BOOT_MODE shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the
IPP_BOOT_ rising edge of POR_B. See the Boot mode pin settings section of System Boot.
MODE
23–8 This read-only field is reserved and always has the value 0.
Reserved
7–5 See Fusemap for additional information.
FORCE_COLD_
BOOT
4 BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse. See
BT_FUSE_SEL Fusemap for additional information on this fuse.
3 This field is reserved.
- Reserved
2 This read-only field is reserved and always has the value 0.
Reserved
SEC_ SEC_CONFIG[1] shows the state of the SEC_CONFIG[1] fuse and SEC_CONFIG[0] shows the state of
CONFIG[1:0] the SEC_CONFIG[0] fuse. See Fusemap for additional information on this fuse.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 971
System Reset Controller (SRC)

6.5.5.17 SRC General Purpose Register 1 (SRC_GPR1)

Address: 3039_0000h base + 74h offset = 3039_0074h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C0_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR1 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
C0_START_ Core0 start reset address:
ADDRH
RVBARADDR0 = {SRC_GPR1[15:0], SRC_GPR2[21:2]}

6.5.5.18 SRC General Purpose Register 2 (SRC_GPR2)

Address: 3039_0000h base + 78h offset = 3039_0078h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C0_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR2 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
C0_START_ Core0 start reset address:
ADDRL
RVBARADDR0 = {SRC_GPR1[15:0], SRC_GPR2[21:2]}

6.5.5.19 SRC General Purpose Register 3 (SRC_GPR3)

Address: 3039_0000h base + 7Ch offset = 3039_007Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C1_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

972 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_GPR3 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
C1_START_ Core1 start reset address:
ADDRH
RVBARADDR1 = {SRC_GPR3[15:0], SRC_GPR4[21:2]}

6.5.5.20 SRC General Purpose Register 4 (SRC_GPR4)

Address: 3039_0000h base + 80h offset = 3039_0080h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C1_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR4 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
C1_START_ Core1 start reset address:
ADDRL
RVBARADDR1 = {SRC_GPR3[15:0], SRC_GPR4[21:2]}

6.5.5.21 SRC General Purpose Register 5 (SRC_GPR5)

Address: 3039_0000h base + 84h offset = 3039_0084h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C2_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR5 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
C2_START_ Core2 start reset address:
ADDRH
RVBARADDR2 = {SRC_GPR5[15:0], SRC_GPR6[21:2]}

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 973
System Reset Controller (SRC)

6.5.5.22 SRC General Purpose Register 6 (SRC_GPR6)

Address: 3039_0000h base + 88h offset = 3039_0088h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C2_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR6 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
C2_START_ Core2 start reset address:
ADDRL
RVBARADDR2 = {SRC_GPR5[15:0], SRC_GPR6[21:2]}

6.5.5.23 SRC General Purpose Register 7 (SRC_GPR7)

Address: 3039_0000h base + 8Ch offset = 3039_008Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C3_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR7 field descriptions

Field Description
31–16 This field is reserved.
- Reserved
C3_START_ Core3 start reset address:
ADDRH
RVBARADDR3 = {SRC_GPR7[15:0], SRC_GPR8[21:2]}

6.5.5.24 SRC General Purpose Register 8 (SRC_GPR8)

Address: 3039_0000h base + 90h offset = 3039_0090h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C3_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

974 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_GPR8 field descriptions

Field Description
31–22 This field is reserved.
- Reserved
C3_START_ Core3 start reset address:
ADDRL
RVBARADDR3 = {SRC_GPR7[15:0], SRC_GPR8[21:2]}

6.5.5.25 SRC General Purpose Register 9 (SRC_GPR9)

Reserved for Internal Use.

Address: 3039_0000h base + 94h offset = 3039_0094h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR9 field descriptions

Field Description
- This field is reserved.
Reserved.

6.5.5.26 SRC General Purpose Register 10 (SRC_GPR10)

Address: 3039_0000h base + 98h offset = 3039_0098h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SRC_GPR10 field descriptions

Field Description
- This field is reserved.
Reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 975
System Reset Controller (SRC)

6.5.5.27 SRC DDR Controller Reset Control Register

(SRC_DDRC_RCR)
DDR Controller Reset Control Register
Address: 3039_0000h base + 1000h offset = 3039_1000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DOMAIN3

DOMAIN2

DOMAIN1

DOMAIN0
DOM_EN

LOCK

Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DDRC1_SYS_RST

DDRC1_CORE_

DDRC1_PRST
DDRC1_PHY_

DDRC1_PHY_

DDRC1_PHY_
R

PWROKIN

RESET
WRST

RST
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

SRC_DDRC_RCR field descriptions

Field Description
31
DOM_EN Domain Control enable for this register.

NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.

0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock

NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0

0 [31] and [27:24] bits can be modified

1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

976 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

SRC_DDRC_RCR field descriptions (continued)

Field Description
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain0 cannot write to this register.
1 This register is assigned to domain0. The master from domain0 can write to this register
23–6 This field is reserved.
- Reserved
5 Active 1
DDRC1_PHY_
WRST
4 Active 1
DDRC1_SYS_
RST
3 0 De-assert DDR controller
DDRC1_PHY_ 1 Assert DDR Controller
PWROKIN
2 0 De-assert DDR controller
DDRC1_PHY_ 1 Assert DDR Controller
RESET
1 DDR Controller core_ddrc_rstn and aresetn.
DDRC1_CORE_
RST 0 De-assert DDR controller aresetn and core_ddrc_rstn
1 Assert DDR Controller preset and DDR PHY reset
0
DDRC1_PRST DDR Controller preset and DDR PHY reset.

NOTE: This reset can only be released when DDR Controller clock inputs are active and stable for 30
cycles

0 De-assert DDR Controller preset and DDR PHY reset reset

1 Assert DDR Controller preset and DDR PHY reset

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 977
Watchdog Timer (WDOG)

6.6 Watchdog Timer (WDOG)

6.6.1 Overview
The Watchdog Timer (WDOG) protects against system failures by providing a method by
which to escape from unexpected events or programming errors.
Once the WDOG is activated, it must be serviced by the software on a periodic basis. If
servicing does not take place, the timer times out. Upon timeout, the WDOG asserts the
internal system reset signal, WDOG_RESET_B_DEB to the System Reset Controller
(SRC).
There is also a provision for WDOG signal assertion by timeout counter expiration. There
is an option of programmable interrupt generation before the counter actually times out.
The time at which the interrupt needs to be generated prior to counter timeout is
programmable. There is a power down counter which is enabled out of any reset (POR,
Warm/Cold). This counter has a fixed timeout period of 16 seconds, upon which it asserts
the WDOG signal.
Flow diagrams for the timeout counter, power down counter and interrupt operations are
are shown in Flow Diagrams.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

978 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

LOW POWER
WAIT Mode
LOW POWER
STOP/ DOZE Low Power
Mode Control
Time-Out Counter
DEBUG Mode

Low Frequency
Reference Clock

WDOG-1 Reset Reset

wdog_rst
Generation Logic

Pre Time-Out Interrupt Interrupt

Peripheral Bus
Control Logic

TIMEOUT

Low Frequency
WDOG-1 Generation WDOG-1
Reference Clock Power Down Counter
Logic

Figure 6-37. WDOG Diagram

6.6.1.1 Features
The WDOG features are listed below:
• Configurable timeout counter with timeout periods from 0.5 to 128 seconds which,
after timeout expiration, result in the assertion of WDOG_RESET_B_DEB reset
signal .
• Time resolution of 0.5 seconds
• Configurable timeout counter that can be programmed to run or stop during low-
power modes
• Configurable timeout counter that can be programmed to run or stop during DEBUG
mode
• Programmable interrupt generation prior to timeout
• The duration between interrupt and timeout events can be programmed from 0 to
127.5 seconds in steps of 0.5 seconds.
• Power down counter with fixed timeout period of 16 seconds, which if not disabled
after reset will assert WDOG_B signal low

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 979
Watchdog Timer (WDOG)

• Power down counter will be enabled out of any reset (POR, Warm / Cold reset)
by default.

6.6.2 Functional description

This section provides a complete functional description of the block.

6.6.2.1 Timeout event

The WDOG provides timeout periods from 0.5 to 128 seconds with a time resolution of
0.5 seconds.
The user can determine the timeout period by writing to the WDOG timeout field
(WT[7:0]) in the Watchdog Control Register (WDOG_WCR). The WDOG must be
enabled by setting the WDE bit of Watchdog Control Register (WDOG_WCR) for the
timeout counter to start running. After the WDOG is enabled, the counter is activated,
loads the timeout value and begins to count down from this programmed value. The timer
will time out when the counter reaches zero and the WDOG outputs a system reset signal,
WDOG_RESET_B_DEB and asserts WDOG_B (WDT bit should be set in Watchdog
Control Register (WDOG_WCR)).
However, the timeout condition can be prevented by reloading the counter with the new
timeout value (WT[7:0] of WDOG_WCR) if a service routine (see Servicing WDOG to
reload the counter) is performed before the counter reaches zero. If any system errors
occur which prevent the software from servicing the Watchdog Service Register
(WDOG_WSR), the timeout condition occurs. By performing the service routine, the
WDOG reloads its counter to the timeout value indicated by bits WT[7:0] of the
Watchdog Control Register (WDOG_WCR) and it restarts the countdown.
A system reset will reset the counter and place it in the idle state at any time during the
countdown. The counter flow diagram is shown in Flow Diagrams.
NOTE
The timeout value is reloaded to the counter either at the time
WDOG is enabled or after the service routine has been
performed.

6.6.2.1.1 Servicing WDOG to reload the counter

To reload a timeout value to the counter the proper service sequence begins by writing
0x_5555 followed by 0x_AAAA to the Watchdog Service Register (WDOG_WSR). Any
number of instructions can be executed between the two writes. If the WDOG_WSR is
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
980 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

not loaded with 0x_5555 prior to writing 0x_AAAA to the WDOG_WSR, the counter is
not reloaded. If any value other than 0x_AAAA is written to the WDOG_WSR after
0x_5555, the counter is not reloaded. This service sequence will reload the counter with
the timeout value WT[7:0] of Watchdog Control Register (WDOG_WCR). The timeout
value can be changed at any point; it is reloaded when WDOG is serviced by the core.

6.6.2.2 Interrupt event

Prior to timeout, the WDOG can generate an interrupt which can be considered a warning
that timeout will occur shortly.
The duration between interrupt event and timeout event can be controlled by writing to
the WICT field of Watchdog Interrupt Control Register (WDOG_WICR). It can vary
between 0 and 127.5 seconds. If the WDOG is serviced (Servicing WDOG to reload the
counter)before the interrupt generation, the counter will be reloaded with the timeout
value WT[7:0] of Watchdog Control Register (WDOG_WCR) and the interrupt will not
be triggered.

6.6.2.3 Power-down counter event

The power-down counter inside WDOG will be enabled out of reset. This counter has a
fixed timeout value of 16 seconds, after which it will drive the WDOG_B signal low.
To prevent this, the software must disable this counter by clearing the PDE bit of
Watchdog Miscellaneous Control Register (WDOG_WMCR) within 16 seconds of reset
deassertion. Once disabled, this counter can't be enabled again until the next system reset
occurs. This feature is intended to prevent the hanging up of cores after reset, as WDOG
is not enabled out of reset.

6.6.2.4 Low power modes

6.6.2.4.1 STOP and DOZE mode

If the WDOG timer disable bit for low power STOP and DOZE mode (WDZST) bit in
the Watchdog Control Register (WDOG_WCR), is cleared, the WDOG timer continues
to operate using the low frequency reference clock. If the low power enable (WDZST) bit
is set, the WDOG timer operation will be suspended in low power STOP or DOZE mode.
Upon exiting low power STOP or DOZE mode, the WDOG operation returns to what it
was prior to entering the STOP or DOZE mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 981
Watchdog Timer (WDOG)

6.6.2.4.2 WAIT mode

If the WDOG timer disable bit for low power WAIT mode (WDW) bit in the Watchdog
Control Register (WDOG_WCR), is cleared, the WDOG timer continues to operate using
the low frequency reference clock . If the low power WAIT enable (WDW) bit is set, the
WDOG timer operation will be suspended. Upon exiting low power WAIT mode, the
WDOG operation returns to what it was prior to entering the WAIT mode.
NOTE
The WDOG timer won't be able to detect events that happen for
periods shorter than one low frequency reference clock cycle.
For example, in repeated WAIT mode entry or exit, if the RUN
mode time is less than one low frequency reference clock cycle
and if the WDW bit is set, the WDOG timer may never time
out, even though the system is in RUN mode for a finite
duration; WDOG may not see a low frequency reference clock
edge during its wake time.

6.6.2.5 Debug mode

The WDOG timer can be configured for continual operation, or for suspension during
debug mode. If the WDOG debug enable (WDBG) bit is set in the Watchdog Control
Register (WDOG_WCR), the WDOG timer operation is suspended in debug mode. If the
WDBG bit is set and the debug mode is entered, WDOG timer operation is suspended
after two low frequency reference clocks. Similarly, WDOG timer operation continues
after two low frequency reference clocks of debug mode exit. Register read and write
accesses in debug mode continue to function normally. Also, while in debug mode, the
WDE bit of Watchdog Control Register (WDOG_WCR) can be enabled/disabled
directly. If the WDOG debug enable (WDBG) bit is cleared then WDOG timer operation
is not suspended. The power-down counter is not affected by debug mode entry/exit.
NOTE
If the WDE bit of Watchdog Control Register (WDOG_WCR)
is set/cleared while in debug mode, it remains set/cleared even
after exiting debug mode.

6.6.2.6 Operations

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

982 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

6.6.2.6.1 Watchdog reset generation

The WDOG generated reset signal WDOG_RESET_B_DEB is asserted by the following
operations:
• A software write to the Software Reset Signal (SRS) bit of the Watchdog Control
Register (WDOG_WCR).
• WDOG timeout. See Timeout event.
The wdog_rst will be asserted for one clock cycle of low frequency reference clock for
both a timeout condition and a software write occurrence. It remains asserted for 1 clock
cycle of low frequency reference clock even if a system reset is asserted in between.
Figure 6-39 shows the timing diagram of this signal due to a timeout condition.

6.6.2.6.2 WDOG_B generation

The WDOG asserts WDOG_B in the following scenarios:
• Software write to WDA bit of Watchdog Control Register (WDOG_WCR).
WDOG_B signal remains asserted as long as the WDA bit is "0".
• WDOG timeout condition, WDT bit of Watchdog Control Register (WDOG_WCR)
must be set for this scenario. A description of the timeout condition can be found in
the Timeout event. WDOG_B signal remains asserted until a power-on reset (POR)
occurs. It gets cleared after the POR occurs (not due to any other system reset).
Figure 6-40 shows the timing diagram of WDOG_B due to timeout condition.
• WDOG power-down counter timeout, PDE bit of Watchdog Miscellaneous Control
Register (WDOG_WMCR) should not be cleared for this scenario. A description of
this counter can be found in the Power-down counter event. WDOG_B signal
remains asserted for one clock cycle of low frequency reference clock.

Figure 6-38 shows the scenarios under which WDOG_B gets asserted.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 983
Watchdog Timer (WDOG)

Watchdog Misc. Control Register (WDOG_WMCR)

Watchdog Control Register (WDOG_WCR)

WDOG_WCR[WDT]
WDOG_WCR[WDA]
WDOG_WMCR[PDE]
Low Frequency Power Down Counter Logic
Reference Clock

WDOG-1 Time Out Counter WDOG-1

Figure 6-38. WDOG_B generation

Low frequency
reference clock

Time-out
Counter 01 00

wdog_rst

System reset

WDOG-1

Figure 6-39. WDOG timeout condition/WDT bit is not set

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

984 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Low frequency
reference clock

Time-out
Counter 01 00

wdog_rst

System reset

Power on reset

WDOG-1

Figure 6-40. WDOG timeout condition/WDT bit is set

6.6.2.7 Reset
The block is reset by a system reset and the WDOG counter will be disabled. The power-
down counter is enabled and starts counting.

6.6.2.8 Interrupt
The WDOG has the feature of Interrupt generation before timeout.
The interrupt will be generated only if the WIE bit in Watchdog Interrupt Control
Register (WDOG_WICR) is set. The exact time at which the interrupt should occur (prior
to timeout) depends on the value of WICT field of Watchdog Interrupt Control Register
(WDOG_WICR). For example, if the WICT field has a value 0x04, then the interrupt
will be generated two seconds prior to timeout. Once the interrupt is triggered the WTIS
bit in Watchdog Interrupt Control Register (WDOG_WICR) will be set. The software
needs to clear this bit to deassert the interrupt. If the WDOG is serviced before the
interrupt generation then the counter will be reloaded with the timeout value WT[7:0] of
Watchdog Control Register (WDOG_WCR) and interrupt would not be triggered.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 985
Watchdog Timer (WDOG)

6.6.2.9 Flow Diagrams

A flow diagram of WDOG operation is shown below.

Reset no
(Cold/Warm)
negated?

yes
Counter in
IDLE State
start counter

Decrement counter

yes
PDE bit
cleared?

no

Is no
count=0?

yes

Assert WDOG

Figure 6-41. Power-Down Counter Flow Diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

986 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

Reset no
Negated?

yes

Enable interrupt
& WDOG timer

Decrement counter

yes Interrupt
count=0?

no

Is
WDOG yes
serviced? Reload counter

no

yes Interrupt
Assert interrupt Count=0?

Figure 6-42. Interrupt Generation Flow Diagram

6.6.3 Initialization
The following sequence should be performed for WDOG initialization.
• PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR) should be
cleared to disable the power down counter.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 987
Watchdog Timer (WDOG)

• WT field of Watchdog Control Register (WDOG_WCR) should be programmed for

sufficient timeout value.
• WDOG should be enabled by setting WDE bit of Watchdog Control Register
(WDOG_WCR) so that the timeout counter loads the WT field value of Watchdog
Control Register (WDOG_WCR) and starts counting.

6.6.4 WDOG Memory Map/Register Definition

The WDOG Memory Map/Register Definition can be found here.

The WDOG has user-accessible, 16-bit registers used to configure, operate, and monitor
the state of the Watchdog Timer. Byte operations can be performed on these registers. If
a 32-bit access is performed,the WDOG will not generate a peripheral bus error but will
behave normally, like a 16-Bit access, making read/write possible. A 32-Bit access
should be avoided, as the system may go to an unknown state.
WDOG memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
6.6.4.1/
3028_0000 Watchdog Control Register (WDOG1_WCR) 16 R/W 0030h
989
6.6.4.2/
3028_0002 Watchdog Service Register (WDOG1_WSR) 16 R/W 0000h
991
6.6.4.3/
3028_0004 Watchdog Reset Status Register (WDOG1_WRSR) 16 R 0000h
991
6.6.4.4/
3028_0006 Watchdog Interrupt Control Register (WDOG1_WICR) 16 R/W 0004h
992
Watchdog Miscellaneous Control Register 6.6.4.5/
3028_0008 16 R/W 0001h
(WDOG1_WMCR) 993
6.6.4.1/
3029_0000 Watchdog Control Register (WDOG2_WCR) 16 R/W 0030h
989
6.6.4.2/
3029_0002 Watchdog Service Register (WDOG2_WSR) 16 R/W 0000h
991
6.6.4.3/
3029_0004 Watchdog Reset Status Register (WDOG2_WRSR) 16 R 0000h
991
6.6.4.4/
3029_0006 Watchdog Interrupt Control Register (WDOG2_WICR) 16 R/W 0004h
992
Watchdog Miscellaneous Control Register 6.6.4.5/
3029_0008 16 R/W 0001h
(WDOG2_WMCR) 993
6.6.4.1/
302A_0000 Watchdog Control Register (WDOG3_WCR) 16 R/W 0030h
989
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

988 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

WDOG memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
6.6.4.2/
302A_0002 Watchdog Service Register (WDOG3_WSR) 16 R/W 0000h
991
6.6.4.3/
302A_0004 Watchdog Reset Status Register (WDOG3_WRSR) 16 R 0000h
991
6.6.4.4/
302A_0006 Watchdog Interrupt Control Register (WDOG3_WICR) 16 R/W 0004h
992
Watchdog Miscellaneous Control Register 6.6.4.5/
302A_0008 16 R/W 0001h
(WDOG3_WMCR) 993

6.6.4.1 Watchdog Control Register (WDOGx_WCR)

The Watchdog Control Register (WDOG_WCR) controls the WDOG operation.

• WDZST, WDBG and WDW are write-once only bits. Once the software does a write
access to these bits, they will be locked and cannot be reprogrammed until the next
system reset assertion.
• WDE is a write one once only bit. Once software performs a write "1" operation to
this bit it cannot be reset/cleared until the next system reset.
• WDT is also a write one once only bit. Once software performs a write "1" operation
to this bit it cannot be reset/cleared until the next POR. This bit does not get reset/
cleared due to any system reset.
Address: Base address + 0h offset
Bit 15 14 13 12 11 10 9 8
Read WT
Write
Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0
Read WDW SRE WDA SRS WDT WDE WDBG WDZST
Write
Reset 0 0 1 1 0 0 0 0

WDOGx_WCR field descriptions

Field Description
15–8 Watchdog Time-out Field. This 8-bit field contains the time-out value that is loaded into the Watchdog
WT counter after the service routine has been performed or after the Watchdog is enabled. After reset,
WT[7:0] must have a value written to it before enabling the Watchdog otherwise count value of zero which
is 0.5 seconds is loaded into the counter.

NOTE: The time-out value can be written at any point of time but it is loaded to the counter at the time
when WDOG is enabled or after the service routine has been performed. For more information
see Timeout event .
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 989
Watchdog Timer (WDOG)

WDOGx_WCR field descriptions (continued)

Field Description
0x00 - 0.5 Seconds (Default).
0x01 - 1.0 Seconds.
0x02 - 1.5 Seconds.
0x03 - 2.0 Seconds.
0xff - 128 Seconds.
7 Watchdog Disable for Wait. This bit determines the operation of WDOG during Low Power WAIT mode.
WDW This is a write once only bit.

0 Continue WDOG timer operation (Default).

1 Suspend WDOG timer operation.
6 Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset
SRE Signal (SRS).

0 Reserved
1 This bit must be set to 1.
5 WDOG_B assertion. Controls the software assertion of the WDOG_B signal.
WDA
0 Assert WDOG_B output.
1 No effect on system (Default).
4 Software Reset Signal. Controls the software assertion of the WDOG-generated reset signal
SRS WDOG_RESET_B_DEB. This bit automatically resets to 1 after it has been asserted to 0. For proper
operation of this function, the SRE bit in this register must be set to 1.

NOTE: This bit does not generate the software reset to the block.

0 Assert system reset signal.

1 No effect on the system (Default).
3 WDOG_B Time-out assertion. Determines if the WDOG_B gets asserted upon a Watchdog Time-out
WDT Event. This is a write-one once only bit.

NOTE: There is no effect on WDOG_RESET_B_DEB (WDOG Reset) upon writing on this bit. WDOG_B
gets asserted along with WDOG_RESET_B_DEB if this bit is set.

0 No effect on WDOG_B (Default).

1 Assert WDOG_B upon a Watchdog Time-out event.
2 Watchdog Enable. Enables or disables the WDOG block. This is a write one once only bit. It is not
WDE possible to clear this bit by a software write, once the bit is set.

NOTE: This bit can be set/reset in debug mode (exception).

0 Disable the Watchdog (Default).

1 Enable the Watchdog.
1 Watchdog DEBUG Enable. Determines the operation of the WDOG during DEBUG mode. This bit is write
WDBG once only.

0 Continue WDOG timer operation (Default).

1 Suspend the watchdog timer.
0 Watchdog Low Power. Determines the operation of the WDOG during low-power modes. This bit is write
WDZST once-only.

NOTE: The WDOG can continue/suspend the timer operation in the low-power modes (STOP and DOZE
mode).
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

990 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

WDOGx_WCR field descriptions (continued)

Field Description
0 Continue timer operation (Default).
1 Suspend the watchdog timer.

6.6.4.2 Watchdog Service Register (WDOGx_WSR)

When enabled, the WDOG requires that a service sequence be written to the Watchdog
Service Register (WSR) to prevent the timeout condition.
NOTE
Executing the service sequence will reload the WDOG timeout
counter.
Address: Base address + 2h offset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read WSR
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDOGx_WSR field descriptions

Field Description
WSR Watchdog Service Register. This 16-bit field contains the Watchdog service sequence. Both writes must
occur in the order listed prior to the time-out, but any number of instructions can be executed between the
two writes. The service sequence must be performed as follows:

0x5555 Write to the Watchdog Service Register (WDOG_WSR).

0xAAAA Write to the Watchdog Service Register (WDOG_WSR).

6.6.4.3 Watchdog Reset Status Register (WDOGx_WRSR)

The WRSR is a read-only register that records the source of the output reset assertion. It
is not cleared by a hard reset. Therefore, only one bit in the WRSR will always be
asserted high. The register will always indicate the source of the last reset generated due
to WDOG. Read access to this register is with one wait state. Any write performed on
this register will generate a Peripheral Bus Error .
A reset can be generated by the following sources, as listed in priority from highest to
lowest:
• Watchdog Time-out
• Software Reset

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 991
Watchdog Timer (WDOG)

Address: Base address + 4h offset

Bit 15 14 13 12 11 10 9 8

Read 0

Write
Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

Read 0 POR 0 TOUT SFTW

Write
Reset 0 0 0 0 0 0 0 0

WDOGx_WRSR field descriptions

Field Description
15–5 This read-only field is reserved and always has the value 0.
Reserved
4 Power On Reset. Indicates whether the reset is the result of a power on reset.
POR
0 Reset is not the result of a power on reset.
1 Reset is the result of a power on reset.
3–2 This read-only field is reserved and always has the value 0.
Reserved
1 Timeout. Indicates whether the reset is the result of a WDOG timeout.
TOUT
0 Reset is not the result of a WDOG timeout.
1 Reset is the result of a WDOG timeout.
0 Software Reset. Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit
SFTW
0 Reset is not the result of a software reset.
1 Reset is the result of a software reset.

6.6.4.4 Watchdog Interrupt Control Register (WDOGx_WICR)

The WDOG_WICR controls the WDOG interrupt generation.

Address: Base address + 6h offset

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read WTIS 0
WIE WICT
Write w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

WDOGx_WICR field descriptions

Field Description
15 Watchdog Timer Interrupt enable bit. Reset value is 0.
WIE
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

992 NXP Semiconductors
 Chapter 6 SNVS, Reset, Fuse, and Boot

WDOGx_WICR field descriptions (continued)

Field Description
NOTE: This bit is a write once only bit. Once the software does a write access to this bit, it will get locked
and cannot be reprogrammed until the next system reset assertion

0 Disable Interrupt (Default).

1 Enable Interrupt.
14 Watchdog Timer Interrupt Status bit will reflect the timer interrupt status, whether interrupt has occurred or
WTIS not. Once the interrupt has been triggered software must clear this bit by writing 1 to it.

0 No interrupt has occurred (Default).

1 Interrupt has occurred
13–8 This read-only field is reserved and always has the value 0.
Reserved
WICT Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must
the interrupt occur. The reset value is 0x04 implies interrupt will occur 2 seconds before time-out. The
maximum value that can be programmed to WICT field is 127.5 seconds with a resolution of 0.5 seconds.

NOTE: This field is write once only. Once the software does a write access to this field, it will get locked
and cannot be reprogrammed until the next system reset assertion.

0x00 WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.

0x01 WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
0x04 WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
0xff WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.

6.6.4.5 Watchdog Miscellaneous Control Register (WDOGx_WMCR)

WDOG_WMCR Controls the Power Down counter operation.

Address: Base address + 8h offset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read 0 PDE
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

WDOGx_WMCR field descriptions

Field Description
15–1 This read-only field is reserved and always has the value 0.
Reserved
0 Power Down Enable bit. Reset value of this bit is 1, which means the power down counter inside the
PDE WDOG is enabled after reset. The software must write 0 to this bit to disable the counter within 16
seconds of reset de-assertion. Once disabled this counter cannot be enabled again. See Power-down
counter event for operation of this counter.

NOTE: This bit is write-one once only bit. Once software sets this bit it cannot be reset until the next
system reset.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 993
Watchdog Timer (WDOG)

WDOGx_WMCR field descriptions (continued)

Field Description
0 Power Down Counter of WDOG is disabled.
1 Power Down Counter of WDOG is enabled (Default).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

994 NXP Semiconductors
Chapter 7
Interrupts and DMA

7.1 Interrupts and DMA Events

7.1.1 Overview
This chapter provides the interrupt assignments of the ARM domain in A53 Interrupts,
CM4 Interrupts, and the DMA events in SDMA event mapping

7.1.2 A53 Interrupts

The Global Interrupt Controller (GIC) collects up to 128 interrupt requests from all the
chip sources and provides an interface to the Cortex A53 CPU.
Each interrupt can be configured as a normal or a secure interrupt. Software force
registers and software priority masking are also supported. The following table describes
the A53 interrupt sources.
Table 7-1. ARM Domain Interrupt Summary
IRQ Module Logic Interrupt Description
0 boot - Used to notify cores on exception condition while
boot
1 dap - DAP Interrupt
2 sdma1 - AND of all 48 SDMA1 interrupts (events) from all
the channels
3 gpu3d - GPU3D Interrupt
4 snvs_lp_wrapper OR ON-OFF button press shorter than 5 secs (pulse
event)
4 snvs_hp_wrapper OR ON-OFF button press shorter than 5 secs (pulse
event)
5 lcdif - LCDIF Interrupt
6 spdif1 OR SPDIF Rx interrupt

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 995
Interrupts and DMA Events

Table 7-1. ARM Domain Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
6 spdif1 OR SPDIF Tx interrupt
7 vpu - VPU G1 Decoder Interrupt
8 vpu - VPU G2 Decoder Interrupt
9 qos - QOS Interrupt
10 wdog3 - Watchdog Timer reset
11 hs - HS Interrupt Request
12 apbhdma OR4 GPMI operation channel 0 description complete
interrupt
12 apbhdma OR4 GPMI operation channel 1 description complete
interrupt
12 apbhdma OR4 GPMI operation channel 2 description complete
interrupt
12 apbhdma OR4 GPMI operation channel 3 description complete
interrupt
13 - OR -
13 - OR -
14 rawnand - BCH operation complete interrupt
15 rawnand - GPMI operation TIMEOUT ERROR interrupt
16 csi1 - CSI Interrupt
17 mipi_csi1 - MIPI CSI Interrupt
18 mipi_dsi - MIPI DSI Interrupt
19 snvs_hp_wrapper - SRTC Consolidated Interrupt. Non TZ.
20 snvs_hp_wrapper - SRTC Security Interrupt. TZ.
21 csu - CSU Interrupt Request. Indicates to the
processor that one or more alarm inputs were
asserted
22 usdhc1 - uSDHC1 Enhanced SDHC Interrupt Request
23 usdhc2 - uSDHC2 Enhanced SDHC Interrupt Request
24 usdhc3 - uSDHC3 Enhanced SDHC Interrupt Request
25 gpu2d - GPU3D interrupt
26 uart1 - UART-1 ORed interrupt
27 uart2 - UART-2 ORed interrupt
28 uart3 - UART-3 ORed interrupt
29 uart4 - UART-4 ORed interrupt
30 vpu - VPU H1 Encoder Interrupt
31 ecspi1 - eCSPI1 interrupt request line to the core.
32 ecspi2 - eCSPI2 interrupt request line to the core.
33 ecspi3 - eCSPI3 interrupt request line to the core.
34 sdma3 - AND of all 48 SDMA3 interrupts (events) from all
the channels
35 i2c1 - I2C-1 Interrupt

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

996 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-1. ARM Domain Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
36 i2c2 - I2C-2 Interrupt
37 i2c3 - I2C-3 Interrupt
38 i2c4 - I2C-4 Interrupt
39 rdc - RDC interrupt
40 usb1 - USB-1 Interrupt
41 usb2 - USB-2 Interrupt
42 - - -
43 - - -
44 micfil - Digital Microphone interface voice activity
detector event interrupt
45 micfil - Digital Microphone interface voice activity
detector error interrupt
46 gpt6 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
47 sctr - System Counter Interrupt [0]
48 sctr - System Counter Interrupt [1]
49 anamix OR TempSensor (Temperature alarm).
49 anamix OR TempSensor (Temperature critical alarm).
49 - - -
50 sai3 OR4 SAI3 Receive Interrupt
50 sai3 OR4 SAI3 Receive Async Interrupt
50 sai3 OR4 SAI3 Transmit Interrupt
50 sai3 OR4 SAI3 Transmit Async Interrupt
51 gpt5 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
52 gpt4 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
53 gpt3 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
54 gpt2 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
55 gpt1 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
56 gpio1 - Active HIGH Interrupt from INT7 from GPIO
57 gpio1 - Active HIGH Interrupt from INT6 from GPIO
58 gpio1 - Active HIGH Interrupt from INT5 from GPIO
59 gpio1 - Active HIGH Interrupt from INT4 from GPIO

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 997
Interrupts and DMA Events

Table 7-1. ARM Domain Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
60 gpio1 - Active HIGH Interrupt from INT3 from GPIO
61 gpio1 - Active HIGH Interrupt from INT2 from GPIO
62 gpio1 - Active HIGH Interrupt from INT1 from GPIO
63 gpio1 - Active HIGH Interrupt from INT0 from GPIO
64 gpio1 - Combined interrupt indication for GPIO1 signal 0
throughout 15
65 gpio1 - Combined interrupt indication for GPIO1 signal
16 throughout 31
66 gpio2 - Combined interrupt indication for GPIO2 signal 0
throughout 15
67 gpio2 - Combined interrupt indication for GPIO2 signal
16 throughout 31
68 gpio3 - Combined interrupt indication for GPIO3 signal 0
throughout 15
69 gpio3 - Combined interrupt indication for GPIO3 signal
16 throughout 31
70 gpio4 - Combined interrupt indication for GPIO4 signal 0
throughout 15
71 gpio4 - Combined interrupt indication for GPIO4 signal
16 throughout 31
72 gpio5 - Combined interrupt indication for GPIO5 signal 0
throughout 15
73 gpio5 - Combined interrupt indication for GPIO5 signal
16 throughout 31
74 - - -
75 - - -
76 - - -
77 - - -
78 wdog1 - Watchdog 1 Timer reset
79 wdog2 - Watchdog 2 Timer reset
80 - - -
81 pwm1 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
82 pwm2 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
83 pwm3 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
84 pwm4 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
85 ccmsrcgpcmix - CCM, Interrupt Request 1
86 ccmsrcgpcmix - CCM, Interrupt Request 2

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

998 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-1. ARM Domain Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
87 ccmsrcgpcmix - GPC, Interrupt Request 1
88 mu - Interrupt to A53
89 ccmsrcgpcmix - SRC interrupt request
90 sai5 OR4 SAI5 Receive Interrupt
90 sai5 OR4 SAI5 Receive Async Interrupt
90 sai5 OR4 SAI5 Transmit Interrupt
90 sai5 OR4 SAI5 Transmit Async Interrupt
90 sai6 OR4 SAI6 Receive Interrupt
90 sai6 OR4 SAI6 Receive Async Interrupt
90 sai6 OR4 SAI6 Transmit Interrupt
90 sai6 OR4 SAI6 Transmit Async Interrupt
91 rtic - RTIC Interrupt
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[0])
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[1])
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[2])
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[3])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[0])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[1])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[2])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[3])
94 ccmsrcgpcmix - Combined CPU wdog interrupts (4x) out of SRC.
95 sai1 OR4 SAI1 Receive Interrupt
95 sai1 OR4 SAI1 Receive Async Interrupt
95 sai1 OR4 SAI1 Transmit Interrupt
95 sai1 OR4 SAI1 Transmit Async Interrupt
96 sai2 OR4 SAI2 Receive Interrupt
96 sai2 OR4 SAI2 Receive Async Interrupt
96 sai2 OR4 SAI2 Transmit Interrupt
96 sai2 OR4 SAI2 Transmit Async Interrupt
97 mu - Interrupt to M4
98 ddr - Interrupt for performance monitor in DRAM
controller
99 ddr - -
100 - OR4 -

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 999
Interrupts and DMA Events

Table 7-1. ARM Domain Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
100 - OR4 -
100 - OR4 -
100 - OR4 -
101 cpu - Error indicator for AXI transaction with a write
response error condition.
102 cpu - Error indicator for L2 RAM double-bit ECC error.
103 sdma2 - AND of all 48 SDMA2 interrupts (events) from all
the channels
104 sjc - Interrupt triggered by SJC register
105 caam_wrapper - CAAM interrupt queue for JQ
106 caam_wrapper - CAAM interrupt queue for JQ
107 qspi - QSPI Interrupt
108 tzasc - TZASC (PL380) interrupt
109 micfil - Digital Microphone interface interrupt
110 micfil - Digital Microphone interface error interrupt
111 - - -
112 perfmon1 - General interrupt
113 perfmon2 - General interrupt
114 caam_wrapper - CAAM interrupt queue for JQ
115 caam_wrapper - Recoverable error interrupt
116 hs - HS Interrupt Request
117 - - -
118 enet1 OR4 MAC 0 Receive Buffer Done
118 enet1 OR4 MAC 0 Receive Frame Done
118 enet1 OR4 MAC 0 Transmit Buffer Done
118 enet1 OR4 MAC 0 Transmit Frame Done
119 enet1 OR4 MAC 0 Receive Buffer Done
119 enet1 OR4 MAC 0 Receive Frame Done
119 enet1 OR4 MAC 0 Transmit Buffer Done
119 enet1 OR4 MAC 0 Transmit Frame Done
120 enet1 OR MAC 0 Periodic Timer Overflow
120 enet1 OR MAC 0 Time Stamp Available
120 enet1 OR MAC 0 Payload Receive Error
120 enet1 OR MAC 0 Transmit FIFO Underrun
120 enet1 OR MAC 0 Collision Retry Limit
120 enet1 OR MAC 0 Late Collision
120 enet1 OR MAC 0 Ethernet Bus Error
120 enet1 OR MAC 0 MII Data Transfer Done
120 enet1 OR MAC 0 Receive Buffer Done
120 enet1 OR MAC 0 Receive Frame Done

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1000 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-1. ARM Domain Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
120 enet1 OR MAC 0 Transmit Buffer Done
120 enet1 OR MAC 0 Transmit Frame Done
120 enet1 OR MAC 0 Graceful Stop
120 enet1 OR MAC 0 Babbling Transmit Error
120 enet1 OR MAC 0 Babbling Receive Error
120 enet1 OR MAC 0 Receive Flush Frame0
120 enet1 OR MAC 0 Receive Flush Frame1
120 enet1 OR MAC 0 Receive Flush Frame2
120 enet1 OR MAC 0 Wakeup Request (sync)
120 enet1 OR MAC 0 Babbling Receive Error
120 enet1 OR MAC 0 Wakeup Request (sync)
121 enet1 - MAC 0 1588 Timer Interrupt – synchronous
122 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
123 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
124 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
125 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
126 - - -
127 pcie_ctrl1 - Channels [63:32] interrupts requests

7.1.3 CM4 Interrupts

The Nested Vectored Interrupt Controller (NVIC) collects up to 128 interrupt requests
from all chip sources and provides an interface to the Cortex M4 Core.
The following table describes the M4 interrupt sources.
Table 7-2. CM4 Interrupt Summary
IRQ Module Logic Interrupt Description
0 GPR_IRQ_IRQn - Used to notify cores on exception condition while
boot.
1 dap - DAP Interrupt
2 sdma1 - AND of all 48 SDMA1 interrupts (events) from all
the channels
3 gpu3d - GPU3D Interrupt
4 snvs_lp_wrapper OR ON-OFF button press shorter than 5 secs (pulse
event)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1001
Interrupts and DMA Events

Table 7-2. CM4 Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
4 snvs_hp_wrapper OR ON-OFF button press shorter than 5 secs (pulse
event)
5 lcdif - LCDIF Interrupt
6 spdif1 OR SPDIF Rx interrupt
6 spdif1 OR SPDIF Tx interrupt
7 vpu - VPU G1 Decoder Interrupt
8 vpu - VPU G2 Decoder Interrupt
9 qos - QOS Interrupt
10 wdog3 - Watchdog Timer reset
11 hs - HS Interrupt Request
12 apbhdma OR4 GPMI operation channel 0 description complete
interrupt
12 apbhdma OR4 GPMI operation channel 1 description complete
interrupt
12 apbhdma OR4 GPMI operation channel 2 description complete
interrupt
12 apbhdma OR4 GPMI operation channel 3 description complete
interrupt
13 - OR -
13 - OR -
14 rawnand - BCH operation complete interrupt
15 rawnand - GPMI operation TIMEOUT ERROR interrupt
16 csi1 - CSI Interrupt
17 mipi_csi1 - MIPI CSI Interrupt
18 mipi_dsi - MIPI DSI Interrupt
19 snvs_hp_wrapper - SRTC Consolidated Interrupt. Non TZ.
20 snvs_hp_wrapper - SRTC Security Interrupt. TZ.
21 csu - CSU Interrupt Request. Indicates to the
processor that one or more alarm inputs were
asserted
22 usdhc1 - uSDHC1 Enhanced SDHC Interrupt Request
23 usdhc2 - uSDHC2 Enhanced SDHC Interrupt Request
24 usdhc3 - uSDHC3 Enhanced SDHC Interrupt Request
25 gpu2d - GPU3D interrupt
26 uart1 - UART-1 ORed interrupt
27 uart2 - UART-2 ORed interrupt
28 uart3 - UART-3 ORed interrupt
29 uart4 - UART-4 ORed interrupt
30 vpu - VPU H1 Encoder Interrupt
31 ecspi1 - eCSPI1 interrupt request line to the core.
32 ecspi2 - eCSPI2 interrupt request line to the core.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1002 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-2. CM4 Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
33 ecspi3 - eCSPI3 interrupt request line to the core.
34 sdma3 - AND of all 48 SDMA3 interrupts (events) from all
the channels
35 i2c1 - I2C-1 Interrupt
36 i2c2 - I2C-2 Interrupt
37 i2c3 - I2C-3 Interrupt
38 i2c4 - I2C-4 Interrupt
39 rdc - RDC interrupt
40 usb1 - USB-1 Interrupt
41 usb2 - USB-2 Interrupt
42 - - -
43 - - -
44 micfil - Digital Microphone interface voice activity
detector event interrupt
45 micfil - Digital Microphone interface voice activity
detector error interrupt
46 gpt6 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
47 sctr - System Counter Interrupt [0]
48 sctr - System Counter Interrupt [1]
49 anamix OR TempSensor (Temperature alarm).
49 anamix OR TempSensor (Temperature critical alarm).
49 - - -
50 sai3 OR4 SAI3 Receive Interrupt
50 sai3 OR4 SAI3 Receive Async Interrupt
50 sai3 OR4 SAI3 Transmit Interrupt
50 sai3 OR4 SAI3 Transmit Async Interrupt
51 gpt5 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
52 gpt4 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
53 gpt3 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
54 gpt2 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
55 gpt1 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1,2 &3 Interrupt
lines
56 gpio1 - Active HIGH Interrupt from INT7 from GPIO

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1003
Interrupts and DMA Events

Table 7-2. CM4 Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
57 gpio1 - Active HIGH Interrupt from INT6 from GPIO
58 gpio1 - Active HIGH Interrupt from INT5 from GPIO
59 gpio1 - Active HIGH Interrupt from INT4 from GPIO
60 gpio1 - Active HIGH Interrupt from INT3 from GPIO
61 gpio1 - Active HIGH Interrupt from INT2 from GPIO
62 gpio1 - Active HIGH Interrupt from INT1 from GPIO
63 gpio1 - Active HIGH Interrupt from INT0 from GPIO
64 gpio1 - Combined interrupt indication for GPIO1 signal 0
throughout 15
65 gpio1 - Combined interrupt indication for GPIO1 signal
16 throughout 31
66 gpio2 - Combined interrupt indication for GPIO2 signal 0
throughout 15
67 gpio2 - Combined interrupt indication for GPIO2 signal
16 throughout 31
68 gpio3 - Combined interrupt indication for GPIO3 signal 0
throughout 15
69 gpio3 - Combined interrupt indication for GPIO3 signal
16 throughout 31
70 gpio4 - Combined interrupt indication for GPIO4 signal 0
throughout 15
71 gpio4 - Combined interrupt indication for GPIO4 signal
16 throughout 31
72 gpio5 - Combined interrupt indication for GPIO5 signal 0
throughout 15
73 gpio5 - Combined interrupt indication for GPIO5 signal
16 throughout 31
74 - - -
75 - - -
76 - - -
77 - - -
78 wdog1 - Watchdog 1 Timer reset
79 wdog2 - Watchdog 2 Timer reset
80 - - -
81 pwm1 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
82 pwm2 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
83 pwm3 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1004 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-2. CM4 Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
84 pwm4 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
85 ccmsrcgpcmix - CCM, Interrupt Request 1
86 ccmsrcgpcmix - CCM, Interrupt Request 2
87 ccmsrcgpcmix - GPC, Interrupt Request 1
88 mu - Interrupt to A53
89 ccmsrcgpcmix - SRC interrupt request
90 sai5 OR4 SAI5 Receive Interrupt
90 sai5 OR4 SAI5 Receive Async Interrupt
90 sai5 OR4 SAI5 Transmit Interrupt
90 sai5 OR4 SAI5 Transmit Async Interrupt
90 sai6 OR4 SAI6 Receive Interrupt
90 sai6 OR4 SAI6 Receive Async Interrupt
90 sai6 OR4 SAI6 Transmit Interrupt
90 sai6 OR4 SAI6 Transmit Async Interrupt
91 rtic - RTIC Interrupt
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[0])
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[1])
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[2])
92 cpu OR Performance Unit Interrupts from Quad-A53
platform (interrnally: PMUIRQ[3])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[0])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[1])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[2])
93 cpu OR CTI trigger outputs from Quad-A53 platform
(internal: nCTIIRQ[3])
94 ccmsrcgpcmix - Combined CPU wdog interrupts (4x) out of SRC.
95 sai1 OR4 SAI1 Receive Interrupt
95 sai1 OR4 SAI1 Receive Async Interrupt
95 sai1 OR4 SAI1 Transmit Interrupt
95 sai1 OR4 SAI1 Transmit Async Interrupt
96 sai2 OR4 SAI2 Receive Interrupt
96 sai2 OR4 SAI2 Receive Async Interrupt
96 sai2 OR4 SAI2 Transmit Interrupt
96 sai2 OR4 SAI2 Transmit Async Interrupt

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1005
Interrupts and DMA Events

Table 7-2. CM4 Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
97 mu - Interrupt to M4
98 ddr - Interrupt for performance monitor in DRAM
controller
99 ddr - -
100 - OR4 -
100 - OR4 -
100 - OR4 -
100 - OR4 -
101 cpu - Error indicator for AXI transaction with a write
response error condition.
102 cpu - Error indicator for L2 RAM double-bit ECC error.
103 sdma2 - AND of all 48 SDMA2 interrupts (events) from all
the channels
104 sjc - Interrupt triggered by SJC register
105 caam_wrapper - CAAM interrupt queue for JQ
106 caam_wrapper - CAAM interrupt queue for JQ
107 qspi - QSPI Interrupt
108 tzasc - TZASC (PL380) interrupt
109 micfil - Digital Microphone interface interrupt
110 micfil - Digital Microphone interface error interrupt
111 - - -
112 perfmon1 - General interrupt
113 perfmon2 - General interrupt
114 caam_wrapper - CAAM interrupt queue for JQ
115 caam_wrapper - Recoverable error interrupt
116 hs - HS Interrupt Request
117 - - -
118 enet1 OR4 MAC 0 Receive Buffer Done
118 enet1 OR4 MAC 0 Receive Frame Done
118 enet1 OR4 MAC 0 Transmit Buffer Done
118 enet1 OR4 MAC 0 Transmit Frame Done
119 enet1 OR4 MAC 0 Receive Buffer Done
119 enet1 OR4 MAC 0 Receive Frame Done
119 enet1 OR4 MAC 0 Transmit Buffer Done
119 enet1 OR4 MAC 0 Transmit Frame Done
120 enet1 OR MAC 0 Periodic Timer Overflow
120 enet1 OR MAC 0 Time Stamp Available
120 enet1 OR MAC 0 Payload Receive Error
120 enet1 OR MAC 0 Transmit FIFO Underrun
120 enet1 OR MAC 0 Collision Retry Limit

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1006 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-2. CM4 Interrupt Summary (continued)

IRQ Module Logic Interrupt Description
120 enet1 OR MAC 0 Late Collision
120 enet1 OR MAC 0 Ethernet Bus Error
120 enet1 OR MAC 0 MII Data Transfer Done
120 enet1 OR MAC 0 Receive Buffer Done
120 enet1 OR MAC 0 Receive Frame Done
120 enet1 OR MAC 0 Transmit Buffer Done
120 enet1 OR MAC 0 Transmit Frame Done
120 enet1 OR MAC 0 Graceful Stop
120 enet1 OR MAC 0 Babbling Transmit Error
120 enet1 OR MAC 0 Babbling Receive Error
120 enet1 OR MAC 0 Receive Flush Frame0
120 enet1 OR MAC 0 Receive Flush Frame1
120 enet1 OR MAC 0 Receive Flush Frame2
120 enet1 OR MAC 0 Wakeup Request (sync)
120 enet1 OR MAC 0 Babbling Receive Error
120 enet1 OR MAC 0 Wakeup Request (sync)
121 enet1 - MAC 0 1588 Timer Interrupt – synchronous
122 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
123 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
124 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
125 pcie_ctrl1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
126 - - -
127 pcie_ctrl1 - Channels [63:32] interrupts requests

7.1.4 SDMA event mapping

The following table shows the DMA request signals for peripherals in the chip.
Table 7-3. SDMA1 event mapping
SDMA Module Description
0 ecspi1 eCSPI1 Rx request
1 ecspi1 eCSPI1 Tx request
2 ecspi2 eCSPI2 Rx request
3 ecspi2 eCSPI2 Tx request

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1007
Interrupts and DMA Events

Table 7-3. SDMA1 event mapping (continued)

SDMA Module Description
4 ecspi3 eCSPI3 Rx request
5 ecspi3 eCSPI3 Tx request
6 - Reserved
7 - Reserved
8 SPDIF1 Rx DMA request
9 SPDIF1 Tx DMA request
10 SAI-2 receive DMA request
11 SAI-2 transmit DMA request
12 SAI-3 receive DMA request
13 SAI-3 transmit DMA request
14 iomux external DMA from pad through IOMUX #1
15 iomux external DMA from pad through IOMUX #2
16 SPDIF2 Rx DMA request
17 SPDIF2 Tx DMA request
18 i2c1 I2C1 DMA event
18 - Reserved
19 i2c2 I2C2 DMA event
19 - Reserved
20 i2c3 I2C3 DMA event
20 - Reserved
21 i2c4 I2C4 DMA event
21 - Reserved
22 uart1 Rx FIFO
23 uart1 Tx FIFO
24 uart2 Rx FIFO
25 uart2 Tx FIFO
26 uart3 Rx FIFO
27 uart3 Tx FIFO
28 uart4 Rx FIFO
29 uart4 Tx FIFO
30 - Reserved
31 - Reserved
32 - Reserved
33 - Reserved
34 - Reserved
35 - Reserved
36 qspi1 QSPI DMA TX request
37 qspi1 QSPI DMA RX request
38 gpt1 GPT1 counter event

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1008 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-3. SDMA1 event mapping (continued)

SDMA Module Description
39 gpt2 GPT2 counter event
40 gpt3 GPT3 counter event
41 PDM Digital Microphone Interface DMA request
42 - Reserved
43 - Reserved
44 enet1 ENET1 1588 Event 2
45 enet1 ENET1 1588 Event 0
46 enet1 ENET1 1588 Event 3
47 enet1 ENET1 1588 Event 1

Table 7-4. SDMA2/SDMA3 event mapping

SDMA Module Description
0 sai1 SAI-1 receive DMA request
1 sai1 SAI-1 transmit DMA request
2 sai2 SAI-2 receive DMA request
3 sai2 SAI-2 transmit DMA request
4 sai3 SAI-3 receive DMA request
5 sai3 SAI-3 transmit DMA request
6 - Reserved
7 - Reserved
8 sai5 SAI-5 receive DMA request
9 sai5 SAI-5 transmit DMA request
10 sai6 SAI-6 receive DMA request
11 sai6 SAI-6 transmit DMA request
12 - Reserved
13 - Reserved
14 iomux external DMA from pad through IOMUX #1
15 iomux external DMA from pad through IOMUX #2
16 - Reserved
17 - Reserved
18 - Reserved
18 - Reserved
19 - Reserved
19 - Reserved
20 - Reserved
20 - Reserved
21 - Reserved
21 - Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1009
Smart Direct Memory Access Controller (SDMA)

Table 7-4. SDMA2/SDMA3 event mapping (continued)

SDMA Module Description
22 - Reserved
23 - Reserved
24 micfil PDM Digital Microphone Interface DMA request
25 - Reserved
26 - Reserved
27 - Reserved
28 spdif1 SPDIF1 Rx DMA request
29 spdif1 SPDIF1 Tx DMA request
30 - Reserved
31 - Reserved
32 - Reserved
33 - Reserved
34 - Reserved
35 - Reserved
36 - Reserved
37 - Reserved
38 gpt4 GPT4 counter event
39 gpt5 GPT5 counter event
40 gpt6 GPT6 counter event
40 - Reserved
41 - Reserved
41 - Reserved
42 - Reserved
43 - Reserved
44 - Reserved
45 - Reserved
46 - Reserved
47 - Reserved
47 - Reserved

7.2 Smart Direct Memory Access Controller (SDMA)

7.2.1 Overview
The Smart Direct Memory Access (SDMA) controller offers highly-competitive DMA
features combined with software-based virtual-DMA flexibility. It enables data transfers
between peripheral I/O devices and internal/external memories.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1010 NXP Semiconductors
 Chapter 7 Interrupts and DMA

The SDMA controller helps maximize system performance by off-loading the Arm core
in dynamic data routing.

7.2.1.1 Block Diagram

The figure below shows a block diagram of the SDMA controller. It includes the custom
RISC core along with its RAM, ROM, DMA units, and the scheduler.

AP Peripherals AP Memory

32 32

Peripheral Burst
DMA DMA

32 32

Functional Units Bus

AP
AP
Peripheral
Control
Bus 32
Scheduler On CE JTAG
DMA SDMA Core
48 Interface
Requests

data instructions
32 16

System Bus

32 32 32 32

SDMA
SPBA RAM ROM
REGISTERS
32

External to SDMA
Per #1 Per #... Per #14

Figure 7-1. SDMA Block Diagram

The SDMA core executes short routines that perform DMA transfers; these routines are
called scripts. The SDMA core interfaces to its own memory via the SDMA system bus.
The SDMA system bus supports a 32-bit data path and a 16-bit address bus. The system
bus datapath is used for both 16-bit instruction (program) memory access and 32-bit data
access. DMA units interface to the core via the Functional Unit Bus and use dedicated
registers to perform DMA transfers.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1011
Smart Direct Memory Access Controller (SDMA)

The SDMA memory contains a ROM and a RAM. The ROM contains startup scripts (for
example, boot code) and other common utilities, which are referenced by the scripts that
reside in the RAM. The internal RAM is divided into a context area and a script area
(more details about this mapping are available in Instruction Memory Map and Data
Memory Map).
Every transfer channel requires one context area to keep the contents of all the core and
unit registers while inactive. Channel scripts are downloaded into the internal RAM by
the SDMA using a dedicated channel that is started during the boot sequence. Downloads
are invoked using commands and pointers provided by the Arm platform. Every channel
contains a corresponding channel script located in RAM and/or ROM that can be
reconfigured independently as-needed. Channel scripts can be stored in an external
memory and downloaded when needed. The SDMA can be configured with any mixture
of scripts to enable an endless combination of supported services.
The scheduler monitors and detects DMA requests, mapping them to channels, and
mapping individual channels to a pre-configured priority. At any given point, the
scheduler presents the highest priority channel that requires service to the SDMA core. A
special SDMA core instruction is used to "conditionally yield" the current channel being
executed to an eligible channel that requires service. If (and only if) there is an eligible
channel pending, will the current channel execution be preempted.
There are two yield instructions that differently determine the eligible channels: In the
first version, eligible channels are pending channels with a strictly higher priority than the
current channel priority. In the second version (yieldge), eligible channels are pending
channels with a priority that is greater or equal to the current channel priority. The
scheduler detects devices that need service through its 48 DMA request inputs. After a
request is detected, the scheduler determines the channel(s) that is (are) triggered by this
request and marks it (them) as pending in the "Channel Pending (EP)" register. The
priorities of all the pending channels are continuously evaluated in order to update the
highest pending priority. The channel pending flag is cleared by the channel script when
the transfer has completed.
The Arm platform control block contains the control registers used to configure the 32
individual channels. There are 48 Channel Enable registers, and every register maps one
DMA request to any desired combination of channels. The 32 Priority registers are used
to assign a programmable 1-of-7 level priority to every possible channel. This block also
contains all other control registers that the Arm platform can access.
The 48 DMA requests that are connected to the scheduler come from a variety of sources.
The "receive register full" and "transmit register empty" signals found in the UART and
USB ports are typical examples of DMA requests that can be connected to the SDMA.
These requests can be used to trigger a specific SDMA channel, or several channels.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1012 NXP Semiconductors
 Chapter 7 Interrupts and DMA

There is an OnCE compatible debug port for product development. The OnCE includes
support for setting breakpoints, single-step and trace, and register dump capability. In
addition, all memory locations are accessible from the debug port.

7.2.1.2 Features
The following are the SDMA features:
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels
• Hardware or software driven triggers for each channel
• 48 hardware driven triggers that can be mapped to any channel.
• Memory accesses including linear addressing, FIFO addressing and 2D addressing
• Fast context-switching with two-level, priority-based preemptive multi-tasking
• 16-bit instruction-set micro-RISC engine (the SDMA core)
• Two DMA units with some or all the following features:
• Auto-flush and prefetch capability
• Flexible address management (increment, decrement, and no address changes on
source and destination address)
• Misaligned data-transfer support
• Uni-directional and bi-directional flows (copy mode)
• Up to eight-word buffers for configurable burst transfers
• Support of byte-swapping
• An available API and library of scripts
• Little-Endian and Big-Endian modes
• Hardware handshakes for low-power entry sequence
• Security support to lock contents of the SDMA script RAM.
• 4-Kbyte ROM containing startup scripts (for example, boot code) and other common
utilities that can be referenced by RAM-located scripts
• 8-Kbyte RAM area is divided into a processor context area and a code space area
used to store channel scripts that are downloaded from the system memory
• Debug support, including a OnCE port, real-time monitors, and embedded cross-
trigger events
• Supported clock frequencies in process:
• Configurable clock options for the SDMA core and the Arm platform DMA
units
• 1:2 ratio with maximum of SDMA core running at Arm platform Peripheral
Bus speed and DMA running at max DMA frequency.
• 1:1 ratio when both SDMA core and Arm platform DMA clocks are set to
the Arm platform Peripheral Bus speed.
• Peripheral bus interface for configuration register programming by the Arm platform

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1013
Smart Direct Memory Access Controller (SDMA)

• The SDMA RISC engine (arithmetic and logic operations), which is referred to as the
"SDMA core."
• An internal peripheral bus connected to the Shared Peripherals Bus Interface (SPBA)
that enables access to up to 14 shared peripherals. SDMA supports 32-bit accesses to
word peripherals and 16-bit accesses to half-word peripherals.
• The peripheral DMA unit that is hooked-up to the Arm platform Crossbar Switch to
service Arm peripherals
• The burst DMA unit is able to perform burst accesses to the external memory
• All the DMA units are 32-bit AHB masters. They are connected to different buses,
thus allowing concurrent accesses.

7.2.2 Functional Description

The figure below shows the SDMA topology, and is composed of the following
components:
• SDMA Core (SDMA Core)
• SDMA Scheduler (Scheduler)
• Functional Units:
• Burst DMA (Burst DMA Unit)
• Peripheral DMA (Peripheral DMA Unit)
• Arm platform Control for Arm control register access.
• Internal RAM and ROM Memory (SDMA Programming Model)
• OnCE debug Port (The OnCE Controller)
The functional unit bus provides access by the SDMA core to the DMA units. The system
bus provides access to SDMA internal memory and also supports up to 14 peripherals.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1014 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Periph Periph Periph

Periph Periph Periph

AIPS MemCtrl RAM
External Memory

EMI
AIPS
Platform

Xbar
AP

Switch

StarCore
Platform
Per DMA Burst DMA BP DMA Xbar
Unit unit unit Switch

functional units bus

MemCtrl
AP Peripheral Bus AP Control ROM

SDMA

OnCE
DMA Requests Scheduler µRISC RAM
core M2/M1
BP Peripheral Bus BP Control Regs

peripheral bus

AP BP
Peripheral SPBA Peripheral
Bus Bus

Per# 1 ... Per# 14

Figure 7-2. SDMA Connections

7.2.2.1 SDMA Core

The SDMA core is a customized RISC-like processor that is specifically developed to
control DMA units and perform L1 tasks like byte-stuffing or framing.
The SDMA core incorporates on-chip debug capability using the OnCE.
The SDMA core is based on a 32-bit register architecture with 16-bit instructions. There
are eight general purpose 32-bit registers, four flags (T, LM, SF, and DF), and four PCU
registers (PC, RPC, SPC, and EPC) that can address 16,384 16-bit instructions.

7.2.2.1.1 SDMA Core Structure

The figure found here shows the structure of the SDMA core. It also shows the different
registers, calculation resources, and possible data movements.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1015
Smart Direct Memory Access Controller (SDMA)

DECR

GREG0
32

32
GREG1

GREG2
ALU
GREG3

32
GREG4
32

32 GREG5

GREG6
8
SF DF T LM
GREG7
Flags
General Registers

Instruction Decoder
5

16
Instruction
AGU

32 8 32 16
PC

RPC
14 14

SPC
(instruction)

EPC
address

address

address
data

data

data

PCU

FUBUS DMBUS IBUS

Figure 7-3. SDMA Core

• The Program Control Unit (PCU) is described in Program Control Unit (PCU). It
handles the state of the core and generates the instruction fetch addresses.
Instructions are retrieved from the Instruction Bus (IBUS) and stored in the SDMA

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1016 NXP Semiconductors
 Chapter 7 Interrupts and DMA

core instruction register prior to their decoding. The PCU contains the following
registers:
• The Program Counter (PC) contains the address of the current instruction.
• The Return Program Counter (RPC) contains the address of the instruction that
follows a jump to the subroutine.
• The Start Program Counter (SPC) contains the address of the first instruction of
the current hardware loop.
• End Program Counter (EPC) contains the address of the last instruction of the
current hardware loop.
• The other core registers are the general purpose registers (GREGn) and the flags.
• The general purpose registers can be used to hold data and addresses. They can
be loaded with immediate values (for example, 8-bit data that are encoded in the
instruction), results of calculations that were performed with the ALU, 32-bit
data that comes from the memory or peripherals via the Data Memory Bus
(DMBUS), 32-bit data that comes from the DMAs via the Functional Units Bus
(FUBUS) or another general purpose register. Their content can be the operands
of the ALU, the data to send on either bus (DMBUS or FUBUS), or a pointer to
memory (DMBUS address).
• The general register 0 (GREG0) is also the hardware loop counter. In hardware
loops, it cannot be used for any other purpose. This register uses a dedicated
decrement unit (DECR) shown in Figure 7-3.
• The flags reflect the status of operations:
• SF and DF are set when the last load or store on either bus (FUBUS or
DMBUS) received an error response.
• LM is set when the core is executing instructions inside a hardware loop.
• T is set when the ALU operation result was 0 or the loop counter reaches 0
(the latter is preponderant when an ALU operation is the last instruction of a
hardware loop).
• The ALU has two operands: any general register and either a second general register
or an immediate value. The result is always stored into the first general register. A
NOP function can be utilized by moving a register's contents into itself (For example,
the instruction: mov R0,R0).
• The 16-bit instructions are fetched via the instruction bus (IBUS) whose address is
driven by the PC. The SDMA RAM and ROM are visible to the core as 16-bit
devices through this interface.
• The memory (RAM and ROM), memory mapped registers, and external peripherals
are accessed via the DMBUS. The address is always taken from a general register
whose content is added to a 5-bit immediate value. This is the only available
addressing mode. The DMBUS is a 32-bit data bus. Except for the peripherals that

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1017
Smart Direct Memory Access Controller (SDMA)

are external to the SDMA, the address accuracy is the 32-bit word (for example,
adding 1 to an address points to the next word, not the next byte).
• The functional units are accessed via the FUBUS connection. The data is exchanged
with any general register, but the address (which in fact is the instruction and the
selector of the functional unit) comes from an 8-bit field of the corresponding load or
store.

7.2.2.1.2 Program Control Unit (PCU)

This part of the SDMA core is dedicated to the control of the RISC engine, as implied by
the instructions that are executed. Its behavior is determined by the instruction type and
the inputs of the SDMA.
It contains the PC, RPC, SPC, and EPC registers that are described in SDMA Core
Structure.

7.2.2.1.2.1 Instruction Types

The state sequence and the delay of execution vary according to the type of the
instruction. There are six possible categories of instructions, as follows:
1. Standard: Most of the instructions belong to this category, and always last 1 cycle.
2. ldf/stf: These are respectively the load and store instructions that access the
functional units. They last 1+n cycles where n is the number of wait-states of the
targeted functional unit.
3. ld/st: These are the load and store instructions that access the memory and
peripherals. They last 1+n cycles where n is the number of wait-states of the targeted
device (1 for the ROM, RAM, and memory mapped registers, 1 + the external
peripheral wait-states). These instructions always last at least two cycles, but the core
is able to handle them in one cycle. The first wait-state is inserted outside the core.
4. Branch: These are all the instructions that cause the Program Counter to point to
another instruction other than the following one (for example, one that breaks the
sequential flow). There are the absolute jumps, the conditional branches, the jump to
the sub-routines, and the return from the sub-routine.
5. Loop,Modified Load or Store: The hardware loop instruction modifies the potential
behavior of any load or store inside the loop (for example, when the LM flag is set).
A jump may be implied after any such load or store if it received an error. The error
causes an early exit of the loop, which means a jump to the instruction that follows
the one that is pointed to by EPC. An additional cycle is required by the PCU to
perform the jump (+1 to the ld/st/ldf/stf original execution delay). Although there is
usually an implicit jump after the last instruction of the loop when the PC goes back
to SPC, this is performed at no cycle cost.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
1018 NXP Semiconductors
 Chapter 7 Interrupts and DMA

6. Done: The done, yield, or yieldge instructions are used to control channel switching.
When no channel switching is performed, these instructions last a single cycle. When
there is a change of channel or context switch, the delay is variable and depends on
many factors (as detailed in Context Switching).

7.2.2.1.2.2 PCU States

The PCU state is visible through outputs of the SDMA (see Real-Time Debug Outputs)
or the OnCE status register(see OnCE Status Register (OSTAT)).
The PCU state is a four-bit field that can take the values shown in the following table.
Figure 7-4 shows the possible state transitions and the corresponding conditions.
Table 7-5. PCU States
Value State Description
0 Program This is the usual instruction cycle.
1 Data This state is inserted when there are wait-states during a load or a store on the
data bus (ld/st type).
2 Change of Flow This is the second cycle of any instruction that breaks the sequence of
instructions (branch and done types). This state lasts only a single cycle; it is
always followed by the Program state.
3 Error in Loop This state is used when an error causes a hardware loop exit (loop-modified load
or store type). This state only lasts a single cycle; it is always followed by the
Program state.
4 Debug The SDMA is stopped in debug mode.
5 Functional Unit This state is inserted when there are wait-states during a load or a store on the
functional units bus (ldf/stf type).
6 Sleep No script is running: The core is idle after saving the last channel context.
7 Save The context switch FSM is saving the current channel.
8 Program in Sleep Same as Program except there is no associated channel, this state is used when
instructions are executed after entering debug mode, whereas the core was in
either Sleep mode.
9 Data in Sleep This is the same as Data except there is no associated channel.
10 Change of Flow in Sleep This is the same as Change of Flow except there is no associated channel. This
state only lasts a single cycle, and is always followed by the Program in Sleep
state.
11 Error in Loop in Sleep This is the same as Error in Loop except there is no associated. channel. This
state only lasts a single cycle, and is always followed by the Program in Sleep
state.
12 Debug in Sleep This is the same as Debug except the core was put in debug mode when no
channel was active.
13 Functional Unit in Sleep This is the same as Functional Unit except there is no associated channel.
14 Sleep after Reset This shows that no script is running, and the core is idle after a reset. When a
channel becomes active, no context is restored but the core starts its boot
program located at address 0 (or the address available in register in Channel 0
Boot Address (SDMAARM_CHN0ADDR)).
15 Restore The context switch FSM is restoring the next channel context.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1019
Smart Direct Memory Access Controller (SDMA)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1020 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Id/st
loop-modified
Idf/stf
error in
loop-modified
error in
ack
Data load/store Error in Loop
loop-modified
error in
in Id/st
wait-states

Functional Unit Change of Flow

ack
branch
in Idf/stf
wait-states

Program
PC is
context Restored
switch
pending
(done) channel(s)

Save Restore
no more
channels
pending pending
channel(s) channel(s)

run_core run_core
when coming from when coming from
Sleep after Reset Sleep

Sleep Debug
Sleep
After Reset in Sleep
debug debug
request request

reset debug
exec_once or request or
exec_core exec_once
completed done

Program
in Sleep debug
debug request or
request wait-states exec_once
branch in Idf/stf completed

Change of Flow ack Functional Unit

in Sleep in Sleep
debug
debug request or
request wait-states exec_once
error in
in Id/st completed
loop-modified
Error in Loop load/store Data
in Sleep in Sleep
ack
error in
loop-modified error in
ldf/stf loop-modified
ld/st

Figure 7-4. PCU State Diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 1021
Smart Direct Memory Access Controller (SDMA)

7.2.2.1.3 SDMA Core Memory

The SDMA has two memory spaces: one for the instructions and one for the data. As
both spaces share the same resources (ROM and RAM devices), the system bus manages
possible conflicts when the core accesses the same resource for both an instruction read
and a data read or write.
Program and data memory is further described in Address Space.
Instructions of 16-bit width are stored in 32-bit wide devices and can be accessed as data.
The mapping is Big Endian: an even instruction address (terminated by 0) accesses the
most significant part of the 32-bit data (bits [31:16]), and an odd instruction address
(terminated by 1) accesses the least significant part of the 32-bit data (bits [15:0]).
Instructions can be fetched out of internal ROM or RAM.
Data can be read from ROM, RAM, memory mapped registers, and external peripherals,
and written to the same devices (except the ROM).
The ROM contains bootload scripts, channel scripts, and common subroutines which may
be referenced by channel scripts elsewhere in the ROM or RAM.
The RAM is divided into a context area and a code space area which may be used to store
channel scripts. The RAM contains undefined values after a hardware reset. Channel
scripts and initial context values are downloaded into RAM using channel 0 which is
reserved for bootload functions.

7.2.2.2 Scheduler
All channel scheduling hardware is included in the Scheduler.

7.2.2.2.1 Primary Functions

The scheduler is a hardware-based design used to coordinate the timely execution of 32
virtual DMA channels by the SDMA core on the basis of channel status and priority.
The scheduler performs the following functions:
• Monitors, detects, and registers the occurrence of any one of the 48 DMA requests
• Links a specific request to a channel or group of channels (channel mapping)
• Ignores requests that are not mapped to a previously configured channel
• Maintains a list of all the channels that are requesting service
• Assigns a pre-programmed priority level (1 of 7) to every channel requesting service
• Detects and flags overrun/underrun conditions

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1022 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.2.2 Channels and DMA Requests

7.2.2.2.2.1 Channels
A Virtual Channel (hereafter simply called a channel) manages a flow of data through the
SDMA. Flows are typically unidirectional.
The SDMA can have up to 32 simultaneously operating channels, numbered from 0 to
31. Channel 0 is usually dedicated to control the SDMA script downloading. All the
channels can be assigned by the Arm platform software.

7.2.2.2.2.2 DMA Requests

A DMA request is caused by externally (for example, external to the SDMA) controlled
conditions (for example, UART receive FIFO reaches a threshold). The SDMA currently
supports up to 48 DMA requests.

7.2.2.2.2.3 Mapping from DMA Requests to Channels and Priorities

A channel can stall waiting on a single DMA request. A single DMA request can awake
more than one channel (in fact, any request can awake any combination of channels).
The mapping between DMA requests and channels is program-controlled. There is a
storage element assigned for each of the 48 requests that contains a bitmap table of the
channels that are awakened by the event.
Every channel also has a three-bit register that indicates its priority.

7.2.2.2.3 Scheduler Functional Description

Scheduler Overview describes the behavior of the SDMA scheduler-from the channel
enabling conditions to the highest priority pending channel selection.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1023
 Smart Direct Memory Access Controller (SDMA)

7.2.2.2.3.1 Scheduler Overview

The scheduler algorithm is built in hardware. It is provided with possibilities for the Arm
platform to control its behavior.
The scheduler processes incoming DMA requests, maps detected requests to 0, one, or
several channels, maintains a list of channels that are requesting service (pending
channels), identifies the top priority and its associated channel, and selects the next active
channel when the current channel yields.
The following figure shows a functional overview.

Channel Enable for DMA request 0 CHNENBL_0

Channel Enable for DMA request 46 CHNENBL_46 Channel Error
Channel Enable for DMA request 47 CHNENBL_47 CHNERR

48
32

48 6 DMA request 32
DMA DMA requests Channel overflow
to pending channel
requests scanning detection
mapping

32

32
Channel Pending from External DMA Requests EP

32 5
External DMA request Override EO Runnable channels
32 Current Channel
Arm Platform Channel Enable HE evaluation
32
Arm Channel Enable Overide HO
32

Channel 31 Priority CHNPRI31 32

Next channel 5
Channel 30 Priority CHNPRI30 32 Current Channel
decision tree
Channel 0 Priority CHNPRI0 32

16 5

Decision Status PSW Next Channel

Figure 7-5. SDMA Hardware Scheduler

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1024 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.2.3.2 DMA Requests Scanning

The scheduler contains a 48-bit edge detection device that detects the rising edge of every
DMA request and transmits the request number to the next stage.
The DMA requests are assumed to be generated on the same reference clock as the
SDMA core clock; they are detected as soon as the signal goes from a 1-to-n-cycles low
state to a 1-to-m-cycles high state.
This system is able to detect single-cycle pulses as well as level-based DMA requests
such as a FIFO threshold crossing. In this case, the SDMA provides a memory mapped
register that can be used by the channel script to monitor the DMA requests lines, and
thus determines whether the data transfer is done or not done, and then continues with the
transfer or closes the channel.
When several DMA requests are detected at the same time, they are forwarded to the next
scheduler stage at the rate of one request per cycle. No request is lost.

SDMA clock

Long Pulse

Level

Short Pulse

Requests are detected here

Figure 7-6. Examples of Valid DMA Requests

The DMA request inputs are connected to various sources that depend on the SoC. The
exact list of DMA request inputs and their associated number is available in each
respective project-specific chapter.

7.2.2.2.3.3 Mapping DMA Requests to Pending Channels

Whenever a DMA request is detected by the first stage, its number is used in the second
stage to determine the channels that have to be activated.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1025
Smart Direct Memory Access Controller (SDMA)

This is performed with an array of 48 registers that are 32 bits wide: There are 48
Channel Enable Registers (CHNENBLn), one register per DMA request. The DMA
request number selects the Channel Enable Registers, and every bit of this 32-bit register
indicates that the corresponding channel must be activated when it is a 1.
This information is passed on the EP register. For every bit of the Channel Enable
Register that is set, the corresponding bit of the EP register is also set, and the remaining
bits of EP are left unchanged. The transformation of EP is summarized by the following
equation:
EP = EP or CHNENBLn
The EP register is used to know which channels require service because they received a
DMA request.
Typical contents of the CHNENBLn registers are all 0s, except for a single bit set. For
example, a DMA request triggers one channel, but all 0s or several 1s are possible. One
DMA request could activate several channels, and the channel execution sequence can be
controlled by the channel priorities and numbers, as explained in the next sections. The
following table illustrates an example configuration.
NOTE
From the table, the DMA request 0 is programmed to
simultaneously trigger channels 0, 1, and 31. Also, DMA
requests 30-47 are not used in this example. The remaining
channels 2 to 30, are configured to be triggered by DMA
requests 29 to 1, respectively.
Table 7-6. Channel Enable RAM Programming Example
Channel
3 0
DMA Request Number

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1026 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-6. Channel Enable RAM Programming Example (continued)

Channel
3 0
DMA Request Number

7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1027
Smart Direct Memory Access Controller (SDMA)

Table 7-6. Channel Enable RAM Programming Example (continued)

Channel
3 0
DMA Request Number

40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

7.2.2.2.3.4 Channel Overflow

A channel overflow occurs when a DMA request requires service from channel n by
setting bit n of the register EP, but this bit is already set, meaning channel n is already
pending. This can come from an overrun/underrun condition.
This detection is possible only when the DMA requests are pulses, because a level-based
DMA request stays high until it is serviced, even though an underrun or overrun
condition occurs, thus preventing another edge detection of the DMA request.
The channel overflow information is saved in the 32-bit CHNERR register (1 bit per
channel). You can configure the SDMA to trigger an interrupt to the Arm platform when
there are 1s in CHNERR. Every bit of CHNERR is masked with the corresponding bit of
INTRMASK and if it gives a 1, the corresponding bit of INTR is set, triggering the
interrupt.

7.2.2.2.3.5 Runnable Channels Evaluation

The EP register is used in conjunction with several other 32-bit registers to determine the
channels that are runnable.
Registers EO, DO, HO and HE, are controlled by the Arm platform. EP is controlled by
the DMA requests and their mapping to channels.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1028 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Several channels may be runnable at any given time. The ith channel is runnable if (and
only if) the condition below is true:
(HE[i] or HO[i]) and (DO[i]) and (EP[i] or EO[i])
After reset, the HE[i], HO[i], EP[i], and EO[i] bits are all cleared whereas the DO[i] bits
are all set. The functions associated with DO are not available for this device. When
DO[i] is set, the scheduler condition becomes:
(HE[i] or HO[i]) and (EP[i] or EO[i])
The registers in these equations are controlled as follows:
• Arm platform (host) channel enable flag HE[i] may be set or cleared by the Arm
platform with the HSTART and STOP_STAT registers. It can also be cleared by the
ith channel script.
Typical usage is for the Arm platform to set this flag to activate the channel. The flag
is cleared by the SDMA core when the transfer is done.
• Externally triggered channel pending flag EP[i] is set by the scheduler when the
channel was activated by a DMA request. It can be cleared by the ith channel script.
• The Arm platform channel override flag HO[i] may be set or cleared by the Arm
platform. When set, it enables the ith channel to run without the involvement of the
Arm platform.
Typical usage is for the Arm platform to set this flag for channels that do not need
Arm platform supervision such as channels that are controlled by DMA request
events (EP).
• DO should always be set to 1 so that the runnable channel evaluation considers only
HO, HE, EP, and EO.
• Externally triggered channel override flag EO[i] may be set or cleared by the Arm
platform. When set, it prevents the ith channel from stopping and stalling on
incoming peripheral DMA requests. This is the case when the channel is not handling
data transfers with peripherals (for example, a memory to memory transfer).
The SDMA can clear the HE[i], and EP[i] bits by means of a done or notify instruction.
The done instruction causes a reschedule; thus, enabling another channel to preempt the
current one, while the notify instruction does not. The done and notify instructions can
clear either HE[i] or EP[i] (never more than one at a time).
Table 7-7. Runnable Channel Selection Control
Register Set by Cleared By
HO Write to HOSTOVR register Write to HOSTOVR register

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1029
Smart Direct Memory Access Controller (SDMA)

Table 7-7. Runnable Channel Selection Control (continued)

Register Set by Cleared By
HE Write to HSTART register Write to STOP_STAT register or by the channel script
with the done or notify instructions.
DO Write to DSPOVR register Write to DSPOVR register
EO Write to EVTOVER register Write to EVTOVER register
EP Set by external DMA request event input. By the channel script with the done or notify instructions

7.2.2.2.3.6 Next Channel Decision Tree

The next channel number is computed from the runnable channels list, the current
channel number, and their respective priorities.
It is re-evaluated every cycle, but is only used when the current channel yields or
terminates by executing a yield, yieldge, or done instruction.
The decision tree is based on the selection of the runnable channel that has the highest
priority.
The highest priority channel is selected according to the following rules:
• Runnable channels are sorted by priority.
• If one of the channels with the highest priority had been preempted by a channel with
a higher priority, but did not want to yield to a channel of the same priority (for
example, it executed a yield, not a yieldge), it is elected as the next channel.
• The channels that belong to the highest priority group are sorted by their number and
the channel that has the highest number in this group becomes the next channel. For
example, if priorities are the same, channel 31 will be selected before channel 30.
When the current channel requires a reschedule with a yield(ge) or a done instruction, the
context switch decision is based on the instruction parameter, the current channel number
and priority, and the next channel number and priority. The possible cases are all listed in
the following table. The grayed cells correspond to unusual cases that should not occur
with a typical usage of the SDMA.
Table 7-8. Channel Switching Decision with a yield, yield(ge), or done
Instruction Current Next Channel Priorities New Running Channel/Comments
Channel Comparison
yield (done 0) Runnable Not runnable none Current
Runnable Runnable Current > Next Current
Current = Next Current
Current < Next Next, 1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1030 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-8. Channel Switching Decision with a yield, yield(ge), or done (continued)
Instruction Current Next Channel Priorities New Running Channel/Comments
Channel Comparison
Not runnable Not runnable none none, 2
(occurs when the channel was disabled by the
Arm platform)
Not runnable Runnable none Next1
(occurs when the channel was disabled by the
Arm platform)
yieldge (done 1) Runnable Not runnable none Current
Runnable Runnable Current > Next Current
Current = Next Next1
Current < Next Next1
Not runnable Not runnable none none2
(occurs when the channel was disabled by the
Arm platform)
Not runnable Runnable none Next1
(occurs when the channel was disabled by the
Arm platform)
done (done>1) Not runnable Not runnable none none2
Runnable Not runnable none Current3
(occurs when the done instruction does not
disable the channel runnable condition)
Not runnable Runnable none Next1
Runnable Runnable none Current3
(occurs when the done instruction does not
disable the channel runnable condition)

1. Current channel script execution is stopped, its context is saved; the next channel context is restored and its script
execution resumes
2. Current channel context is saved and SDMA enters IDLE mode
3. Current channel context is saved, then restored, and the current channel script resumes execution

Finally, when the SDMA is in IDLE mode and a runnable channel is elected as the next
channel, its context is immediately restored and the script execution resumes.
The combinatorial-decision tree supports dynamic modifications of the EP, EO, HE, HO,
and DO flags as well as dynamic modifications of the channel priorities. The propagation
times are detailed in Scheduler Pipeline Timing Diagram.
The decision tree status is available in the PSW register, which is continuously updated.
It contains the next channel priority, the next channel number, the current channel
priority, and the current channel number. When a priority is read as 0, it means the
channel is not runnable.
A few examples of decisions are presented below:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1031
Smart Direct Memory Access Controller (SDMA)

• Channel 31 is running with priority 5, channels 13 and 24 are pending with the same
priority 5; channel 24 is eligible as the next channel since 24 > 13.
• Channel 31 is running with priority 7, channels 13 and 24 are pending with priority
5; channel 31 is the next channel because its priority is greater than the other pending
channels.
• Channels 7, 23, and 29 are pending with the same priority. Channel 7 is active and
runs a yieldge; it is preempted by channel 29. After a period of time, channel 29 runs
a yieldge, it is then preempted by channel 23 that is the selected channel since
channel 29 is the current channel. Later, channel 23 runs a yieldge and is preempted
by channel 29. Channels 23 and 29 will go on switching after every yieldge until one
of them terminates. It is only at that point that channel 7 becomes eligible again.
• Channel 11 is running with priority 3, and channel 15 is pending with priority 4.
When the channel 31 script executes a yield instruction, it gets preempted by channel
15; then channels 6 and 18 with priority 3 become pending. Because channel 11 was
preempted after executing a yield and there is no pending channel with a strictly
greater priority, it is eligible as the next channel (although its number 11 < 18).

7.2.2.2.3.7 Scheduler State Diagram

The Figure 7-7 summarizes the behavior of the SDMA scheduler with details about the
exact mechanism of the priority decision tree. It is important to understand the scheduler
is a hardwired pipeline, which means all the stages are performed simultaneously every
cycle, but a change on any given stage is reflected on the next stage after the delays
presented in Scheduler Pipeline Timing Diagram.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1032 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMA AP
DMA Mapping to new ctrl regs ctrl regs
request pending channels update update
#n

done

Repeat 32 times
for every channel #i

is channel #i Yes Set error for

already channel #i
Sort channels pending?
per priority

No Evaluate channel #i
runnable condition
Sort highest priority
channels per number

No is channel #i
Next channel = Channel #i
priority(i) = 0 runnable?
highest number among
highest priority channels

Yes

Channel #i
priority(i) = CHNPRI(i)
yield AND
Yes INT (priority(current))>
INT(priority(next))

No is channel #i the Yes

current channel

yieldge AND
Yes priority (current)>
priority (next) No

Channel #i
No priority(i) = priority(i) + 0.5

Stop the current channel Yes

done
and save its context Channel #i
Channel #i Yes
was preempted
priority(i) = priority(i) + 0.25
after a yield?
No

No
is the
current channel active: Yes
priority (current)>0?

No

is the next
Yes channel active:
priority (current)>0?

No

Restore the next channel SDMA core

context and run it is in IDLE mode

END

Figure 7-7. Scheduler State Diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1033
Smart Direct Memory Access Controller (SDMA)

7.2.2.2.3.8 Scheduler Pipeline Timing Diagram

The SDMA scheduler process of DMA-request and control-register modifications is not
immediate.
The figure below shows the exact delays of all the tasks. The reference clock is the
SDMA core clock.

SDMA Clock
1 2 3 4 5 6 1 2 3

DMA Request

mapping to EP

control regs update

(EP, HE, DO, HO)

runnable channels
decision

next channel

Figure 7-8. Scheduler Timing Diagram

Two numbers can be inferred from this timing diagram. First, it takes six SDMA core
clock cycles to update the next channel from a DMA request. Second, it takes three
SDMA core clock cycles to update the next channel from a direct modification of the
condition registers (EP, DO, HE, or HO) by any processor. The processors that can
modify these bits include SDMA with a done instruction or the Arm platform with a
write access through the corresponding control port on their respective peripheral bus).

7.2.2.2.3.9 Channel-DMA Request Mapping

The 48 DMA request inputs to the SDMA scheduler are listed in project-specific
chapters. Refer to the respective chapters for this information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1034 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.2.3.10 Examples: How to Start a Channel

A channel can be started when the following equation is true for channel i:
(HE[i] or HO[i]) and (DO[i]) and (EP[i] or EO[i])
Once this equation is true, the scheduler can start this channel according to the priority of
all pending channels. Several examples of configuration are listed below:
1. To start a channel triggered by Arm platform software:
• Initially, configure HO[i]=0, DO[i]=1, and EO[i]=1 using registers indicated in
Table 7-7.
• Arm platform software triggers the channel by writing to the HSTART register
to set HE[i]=1, thereby setting the above equation true.
2. To start a channel triggered by DMA request event.
• Initially, configure HO[i]=1, DO[i]=1, and EO[i]=0 using registers indicated in
Table 7-7.
• The DMA request is asserted to trigger the channel by setting EP[i]=1, which
makes the above equation true.

7.2.2.2.4 Context Switching

On execution of a done or yield(ge) instruction, the current channel may be changed
either because it has finished (which necessarily happens when the done instruction is
executed), or it was preempted by a higher priority channel (which is possible but not
systematic when the yield(ge) is executed).
Upon a channel change the SDMA goes through a context switch procedure.
When the current channel yields or ends, the context for that channel is saved into the
context RAM locations for that channel. When the next channel starts running, its context
is first restored from RAM.
Since context RAM is not yet initialized by reset, there will be no context restore at the
beginning of the first channel (bootload channel) run after reset. It is expected that the
bootload channel will be used to initialize the context for all other channels. When the
bootload channel finishes running or yields, SDMA will enter its SAVE state and save
that channel's context into RAM. Then, if the bootload channel is called again later, the
context will be restored from RAM when the channel starts again.
The context structure for each channel is defined in Context Switching-Programming and
Table 7-13. There will be one context area reserved for each channel. When a channel
ends or yields, the SDMA core registers are automatically saved into the context RAM
and later restored from the context RAM when the channel is next run. The total RAM

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1035
Smart Direct Memory Access Controller (SDMA)

space reserved for 32-channel contexts is either 3K or 4K depending on whether the

SMSZ bit is set in the CHN0ADDR register, which enables an additional 8 words of
scratch RAM for each context.

7.2.2.2.4.1 Context Switch Modes

The exact procedure to save the context of the old channel, and to restore the context of
the new channel depends on the context switch mode selected by the Arm platform in the
CONFIG control register.
The following are the context switch modes:
• By default, the "dynamic" context switch is set. This mode provides the most
efficient context switch for an average of eight cycles to stop the current channel,
save its context, restore the next channel context, and resume its execution. It
consists of saving modified registers of the current channel in the background (for
example, during the channel execution)-which leaves very few registers to save when
the switch is decided-resuming execution of the next channel as soon as possible (for
example, when the minimal set of registers is restored), and continuing the restore
phase during this execution.
• In "dynamic with no loop" mode, the same principle is followed except the modified
registers are only saved in the background when the loop flag is not set. This mode
offers almost the same effectiveness as the previous one, but it prevents the system
from accessing the RAM during loops to save power. This is the recommended mode
for an efficient context-switch when the loop bodies are short.
• In "dynamic power" mode, no background saving is performed, which reduces power
consumption to the minimum. The modified registers are only saved when the
context switch starts. The restore phase is the same as before. This is the mode that
achieves the optimal power consumption at the cost of a slower context-switch.
• In a "static" context switch, all the registers are saved when a context switch is
decided, and all the registers are restored before starting the execution of the new
channel. This mode enables a predictable behavior of the context switch since all the
registers are restored prior to the channel start and all registers are saved after the
channel termination.
NOTE
Static context mode should be used for the first channel called
after reset to ensure that the all context RAM for that channel is
initialized during the context SAVE phase when the channel is
done or yields. Subsequent calls to the same channel or
different channels may use any of the dynamic context modes.
This will ensure that all context locations for the bootload

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1036 NXP Semiconductors
 Chapter 7 Interrupts and DMA

channel are initialized, and prevent undefined values in context

RAM from being loaded during the context restore if the
channel is re-started later.

7.2.2.2.4.2 Context Switch Procedure

The Program Control Unit goes into the save state, the current context is spilled into
memory, and the next channel context is restored according to the context-switch mode
that was selected by the Arm platform.
The context switch procedure is as follows:
1. Load the current context's spill base address.
2. Spill the modified registers of the current channel to memory according to the
selected context switch mode while the channel is running.
On a done or yield(ge) that causes the channel preemption, the PCU goes into the
save state. In static mode, all the registers are saved; whereas, in either dynamic
mode, the registers that were modified but not yet saved are then saved, and the PCU
registers and flags are finally saved.
3. Put the SDMA core into sleep and wait for new channels to be serviced. This step is
skipped if there are pending channels when the current channel is saved.
As soon as there is at least one pending channel, the PCU goes into its restore state to
restore the context of the channel that was elected by the scheduler.
Once a channel is elected, it remains the current channel until its script requests a
rescheduling operation with a done or yield(ge) instruction. That means the current
channel cannot be modified by the Arm platform, even if it is no more runnable or if
its priority is modified.
The Arm platform can however force a reschedule by writing the corresponding bit
in the CONFIG register, which has the same effect as if the script had executed a
done instruction. That feature should only be used to stop the SDMA in emergency
cases.
4. Load the context base-address of the new channel.
In "static" mode, all the registers are restored. In either "dynamic" modes, only the
PCU registers are restored.
The new channel is running. In "static" mode, no more activity regarding context
restoring or saving is performed. In either "dynamic" modes, the registers are
restored in the background every time an access to the context RAM is possible, and

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1037
Smart Direct Memory Access Controller (SDMA)

priority is given to restoring the registers that are required by the next instruction to
be executed. When a register has not been restored and the next instruction needs it,
this instruction gets stalled until the register was restored.
In "dynamic" and "dynamic with no loop" modes, background saving of dirty
registers is performed every time an access to the context RAM is possible and
allowed by the context switch mode.
NOTE
The contents of a channel context space in the context
RAM depends on the selected context switch mode. In
"dynamic" and "dynamic with no loop" modes, the contents
of the context RAM tend to match the contents of the
SDMA registers (except for the PCU registers and flags
that are never saved in the background). In "dynamic
power" and "static" modes, the contents of the context
RAM remain unchanged until the channel terminates with a
done or gets preempted.

7.2.2.2.4.3 Context Map in Memory

Refer to Context Switching-Programming.

7.2.2.3 Functional Units

The functional units are small systems that are used by the SDMA core to handle data
transfers between the core and a bus domain external to the SDMA.
The SDMA core is able to control and exchange data with these systems by sending
instructions and reading or writing data from/to the functional units' registers via the
FUBUS. This is done with the ldf and stf instructions.
The following sections provide introductions to the available functional units. Functional
Units Programming Model provides descriptions the functional units' behaviors.

7.2.2.3.1 Burst DMA Unit

The burst DMA unit enables the SDMA core to perform data transfers to and from the
Arm platform memory.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1038 NXP Semiconductors
 Chapter 7 Interrupts and DMA

It is optimized for accessing SDRAM-like devices. It does not provide control to assign a
privilege level to the DMA access. The burst DMA unit provides the SDMA with means
to do the following:
• Perform up to 8-beat read and write bursts to the Arm platform memory, which
optimizes throughput when accessing SDRAM-type devices because of an internal,
36-byte FIFO
• Access the Arm platform memory at once or twice the SDMA core frequency
• Copy data from one Arm platform memory location to another Arm platform
memory location at the Arm platform bus speed, which provides a very high
throughput
• Control the method for addressing the Arm platform memory (automatic increment
of addresses or frozen addresses-the former aimed at accessing RAM-like memory
and the latter aimed at accessing single-address FIFOs)
• Enable or disable automatic prefetch when reading data from the Arm platform
memory. When the prefetch mode is selected, the burst DMA automatically triggers
external bursts to fill its FIFO without waiting for the SDMA core to request the
corresponding data, greatly improving throughput.
• Rely on the DMA to automatically flush its FIFO content when there is enough data
to generate an 8-beat burst to the Arm platform memory. Or, it forces a flush when a
data transfer must terminate.
• In the former case, the SDMA core may only be stalled when it tries writing data and
there is not enough room left in the FIFO. In the latter case, the core is stalled until
the data is effectively written to the Arm platform memory.
In automatic flush mode, the core receives an acknowledge that does not reflect the
actual error status when the data is effectively written into the Arm platform
memory. This error status is retrieved by a later access to the burst DMA.
Terminating a write data transfer with a forced flush command guarantees that any
bus error to the Arm platform memory is caught.
• Handle address alignment issues between the Arm platform memory map and the
SDMA core data. This enables the core to read or write 32-bit data from the burst
DMA, whereas the corresponding Arm platform address is not 32-bit aligned. This
drastically improves the SDMA scripts' efficiency since the same loop that transfers
32 bits at a time can be used regardless of the start and end addresses in the Arm
platform memory space.
This unit structure and registers are described in Burst DMA Structure and Burst DMA
Registers.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1039
Smart Direct Memory Access Controller (SDMA)

7.2.2.3.1.1 Burst DMA Structure

The burst DMA is essentially made up of a 36-byte FIFO, address registers, and a
controlling state-machine. The 36-byte FIFO enables eight-word buffering with address
alignment, and the state-machine manages clock adaptation when required.
The burst DMA is depicted in the figure below.

DMA interface to AP memory

read and write address control

32 32
data

Setup and FSM State (MS)

36-byte
FIFO Source Address (MSA)
(MD) Burst DMA
Control
Destination Address (MDA)

32 32 32

FUBUS

Figure 7-9. Burst DMA Structure

7.2.2.3.1.2 Burst DMA Registers

There are four registers, as follows, that may be accessed from the SDMA core:
• MSA (Memory Source Address) - Holds the source byte address in the Arm platform
memory map for reading data from this location. This register is automatically
modified every time the core reads new data from the FIFO.
• MDA (Memory Destination Address) - Holds the destination byte address in the Arm
platform memory map for writing data to this location. This register is automatically
modified every time the core writes new data into the FIFO.
• MD (Memory Data) - Labels the 36-byte FIFO access point: Reading a byte,
halfword, or word from MD respectively retrieves the first 1, 2, or 4 bytes of the
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
1040 NXP Semiconductors
 Chapter 7 Interrupts and DMA

FIFO (for example, the bytes that were stored first by the DMA state-machine when
transferring data from the Arm platform memory).
• When the FIFO does not hold as many bytes as required by the SDMA core, the core
is stalled until the missing bytes are read from the Arm platform memory. In the case
of prefetch mode, the DMA controller decides when it should start a burst to Arm
platform memory in order to reduce the risk to not have the required data for the
future accesses of the core. When there is no prefetching, a burst is triggered when
the required data is not available in the FIFO.
Writing a byte, halfword, or word to MD stores 1, 2, or 4 bytes, respectively, at the
end of the FIFO (for example, these bytes are transmitted to the Arm platform
memory after all the other bytes that were previously stored in the FIFO). When the
FIFO does not have enough room left to hold the written data, the SDMA core is
stalled until a sufficient amount of FIFO contents are flushed out to the Arm platform
memory. Flushing is decided by the DMA controller when there are enough bytes in
the FIFO to perform the largest allowed burst to Arm platform memory (the exact
size depends on the burst start address and the AHB 1 Kbyte boundary rule).
However, the SDMA core has the ability to force the flushing operation at any time,
for example, when at the end of the data transfer, prior to channel closure.
• MS (Memory Setup) - Contains the state of the burst DMA control, the two flags that
define whether each address register is incremented after every access to the external
memory, and another flag that is set when a bus error occurred.

7.2.2.3.1.3 Burst DMA Data Transfers

Three typical usages have been identified that involve the burst DMA: the data transfer
startpoint, the endpoint, or both.
Every case requires a different procedure, as listed in the following sections:

7.2.2.3.1.3.1 Data Retrieval from the Arm platform Memory

The following steps retrieve data from Arm platform memory using the burst DMA unit:
• Set up the MS flags to reflect the mode for the source address (incremented or frozen
according to the type of accessed device: memory or peripheral FIFO), then initialize
the source address register itself (MSA).
• Read data from the FIFO using the ldf MD instruction as many times as needed. If an
error occurred during the fetch from Arm platform memory, the DMA control tags
the error status on the data and the SDMA core SF flag is set when reading this data
from the FIFO.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1041
Smart Direct Memory Access Controller (SDMA)

7.2.2.3.1.3.2 Storing Data Into the Arm platform Memory

The following steps store data from Arm platform memory using the burst DMA unit:
• Set up the MS flags to reflect the mode for the destination address (incremented or
frozen according to the type of accessed device: memory or peripheral FIFO), then
initialize the destination address register itself (MDA).
• Store data into the FIFO using the stf MD instruction as many times as needed.
• When the transfer is finished and if the DMA worked in automatic flush mode, force
the flush of the FIFO. This instruction is stalled until all the FIFO data is effectively
sent to the Arm platform memory and the error status of the transfer is available in
the DF flag.

7.2.2.3.1.3.3 Transferring Data Between Two Arm platform Memory Locations-Burst DMA
Unit
The following steps copy data between two Arm platform memory locations using the
burst DMA unit:
• Set up the MS flags to reflect the modes for the source and destination addresses (all
the combinations are possible), then initialize the source address register (MSA) and
the destination address register (MDA). Both addresses must be word-aligned.
• Use as many stf MD instructions with the COPY flag as needed. Every instruction
triggers a burst read of a given number of words from the source address (this
number is provided to the burst DMA via the SDMA core general purpose register,
which is referenced in the stf instruction). Once all the data is loaded into the FIFO,
the DMA empties it with a write burst of the same count to the destination address.
The DMA acknowledges prior to instruction completion, which frees the SDMA core
for other tasks at no delay cost.
• Once the transfer is done, there should be a final access to the burst DMA to check
the error status.

7.2.2.3.2 Peripheral DMA Unit

The peripheral DMA unit is the second functional unit that connects the SDMA to the
Arm platform memory.
Unlike the burst DMA, it does not support burst transfers and is optimized for accessing
peripherals. It does not provide control to assign a privilege level to the DMA access. Its
feature list comprises the following:
• Access to the Arm platform peripherals or memory at once or twice the SDMA core
frequency

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1042 NXP Semiconductors
 Chapter 7 Interrupts and DMA

• Data copy from one Arm platform memory location to another Arm platform
memory location at memory bus speed, improving throughput
• Control of the method for addressing the Arm platform memory (automatic
increment or decrement of addresses or frozen addresses, the first ones aimed at
accessing RAM-like memory and the last one aimed at accessing single-address
FIFOs)
• Selectable automatic prefetch when reading data from the Arm platform memory. In
prefetch mode, the peripheral DMA automatically fetches another data-without
waiting for the SDMA core to request it-when its data register is empty, which
improves the throughput
• Selectable automatic flush. In this mode, the SDMA core may only be stalled when it
tries writing data and the previous write operation is not finished yet; whereas, in
forced flush mode, the core is stalled until the data is effectively written to the Arm
platform memory.
• In automatic flush mode, the core receives an acknowledge that does not reflect the
actual error status when the data is effectively written into the Arm platform memory
or the peripheral. This error status is retrieved by a later access to the peripheral
DMA. Terminating a write data transfer with a forced flush command guarantees that
any bus error to the Arm platform memory has been caught.
This unit structure and registers are described in Peripheral DMA Structure and
Peripheral DMA Registers.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1043
Smart Direct Memory Access Controller (SDMA)

7.2.2.3.2.1 Peripheral DMA Structure

The peripheral DMA is made up of a 32-bit data register, two address registers, and a
controlling state-machine. The state-machine manages clock adaptation, when required.
It is shown in the following figure.

DMA interface to AP memory and peripherals

read and write address

control
data 32 32

Setup and FSM State (PS)

Source Address (PSA)

Peripheral DMA
Control
Destination Address (PDA)

Data Register (PD)

32 32 32

FUBUS

Figure 7-10. Peripheral DMA structure

7.2.2.3.2.2 Peripheral DMA Registers

According to Figure 7-10, the peripheral DMA has four registers that may be read or
written by the SDMA core:
• PD (Peripheral Data) is the DMA 32-bit data register.
• PSA (Peripheral Source Address) holds the source byte address in the Arm platform
memory map for reading data from this location. This register is automatically
modified every time the core reads a new data from PD.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1044 NXP Semiconductors
 Chapter 7 Interrupts and DMA

• PDA (Peripheral Destination Address) holds the destination byte address in the Arm
platform memory map for writing data to this location. This register is automatically
modified every time the core writes a new data into PD.
• PS (Peripheral Setup) contains the state of the peripheral DMA control, two
configuration fields that define the way address registers are modified after every
data access, two additional configuration fields that define the data size to access the
source and destination devices, and another field that contains the latest transfer error
status.

7.2.2.3.2.3 Peripheral DMA Data Transfers

There are three typical usages that involve the peripheral DMA, whether it is the data
transfer start-point, endpoint, or both.
Every case requires a different procedure, as described in Data Retrieval from the Arm
platform Memory or Peripheral, Storing Data into the Arm platform Memory or
Peripheral, and Transferring Data Between Two Arm platform Memory Locations-
Peripheral DMA Unit.

7.2.2.3.2.3.1 Data Retrieval from the Arm platform Memory or Peripheral

The following steps retrieve data from Arm platform memory using the peripheral DMA
unit:
• Set up the PS fields to reflect the mode and data size for the source (incremented,
decremented, or frozen address register; 8-bit, 16-bit, or 32-bit data transfers), then
initialize the source address register itself (PSA) with an address that is aligned to the
programmed data size.
• Read data from PD using the ldf PD instruction as many times as needed. If an error
occurs during the fetch from the Arm platform memory or peripheral, the DMA
control tags the error status on the data and the SDMA core SF flag is set when
reading this data from PD.

7.2.2.3.2.3.2 Storing Data into the Arm platform Memory or Peripheral

The following steps store data to Arm platform memory using the peripheral DMA unit:
• Set up the PS fields to reflect the mode and data size for the destination
(incremented, decremented, or frozen address register; 8-bit, 16-bit, or 32-bit data
transfers), then initialize the destination address register itself (PDA) with an address
that is aligned to the programmed data size.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1045
Smart Direct Memory Access Controller (SDMA)

• Store data into PD using the stf PD instruction as many times as needed.
• When the transfer is finished and if the peripheral DMA worked in automatic flush
mode, force the flush of PD. This instruction is stalled until PD contents are
effectively sent to the Arm platform memory or peripheral, and the error status of the
transfer is available in the DF flag.

7.2.2.3.2.3.3 Transferring Data Between Two Arm platform Memory Locations-Peripheral

DMA Unit
The following steps copy data between two Arm platform memory locations using the
peripheral DMA unit:
• Set up the PS fields to reflect the modes and data size for the source and destination
addresses (all the combinations of addressing modes are possible, but both data sizes
must be identical), then initialize the source address register (PSA) and the
destination address register (PDA). Both addresses must be aligned with the
programmed data size.
• Use as many stf PD instructions with the COPY flag as needed. Every instruction
triggers a single read from the source address; a single write of the received data
immediately follows. The DMA acknowledges prior to instruction completion, which
frees the SDMA core for other tasks at no delay cost.
• Once the transfer is done, there should be a final access to the peripheral DMA to
check the error status.

7.2.2.4 SDMA Security Support

The SDMA provides support to SDMA software to block unauthorized updates to the
scripts in RAM.
SDMA supports the following Security modes:
• Open Mode: has full control to load scripts and context into SDMA RAM. This is the
default mode.
• Locked Mode: The Arm platform loads scripts and channel contexts at startup when
it is still executing known safe software. When finished, it locks the SDMA to
prevent further updates to RAM and selected registers. More details described in
Locked Mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1046 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.4.1 Locked Mode

The LOCK bit in the SDMA_LOCK register provides support for SDMA scripts to
freeze RAM contents after the initial bootload routine to prevent future unauthorized
updates to SDMA RAM.
After initial RAM contents are uploaded, Arm platform software can set the LOCK bit to
secure the RAM contents to prevent future updates by an unauthorized. After the LOCK
bit is written with a '1', the SDMA is "locked" until reset.
The LOCK bit can be read in the SDMA's internal memory map in the LOCK register
(see Section SDMA LOCK (SDMAARM_SDMA_LOCK)). SDMA scripts which load
information into RAM can check the value of the LOCK bit to determine if an upload to
RAM is allowed. If not allowed, the script can refuse to allow the request to copy data
into the RAM to continue. The exact use of the LOCK bit in SDMA scripts for security
control will be described in SDMA software documentation (see SDMA Scripts).
While SDMA is locked, attempts to write to the SDMA_LOCK, CHN0ADR,
ILLINSTADDR, and ONCE_ENB registers will be ignored. All registers remain
readable. Writes to other registers are still allowed.
Once the SDMA is locked, the LOCK bit can only be cleared by a reset. A hardware reset
will always clear the LOCK bit. A software reset initiated by writing to the RESET
register will only clear the LOCK bit if the SRESET_LOCK_CLR bit in the
SDMA_LOCK register is set. Since SDMA_LOCK register cannot be updated if SDMA
is locked, the SRESET_LOCK_CLR bit must be configured before setting the LOCK bit.
The SREST_LOCK_CLR bit will also be cleared by resets that clear the LOCK bit.
The SDMA RISC core uses the ILLINST and CHN0ADDR registers as pointers to
determine where to jump to after an illegal instruction or upon boot after a reset. The
LOCK bit prevents updates to these registers to protect against unauthorized changes to
these pointers.
While SDMA is locked, the ONCE_ENB register cannot be written to prevent the OnCE
under Arm platform control from being used to gain access to SDMA internal memory. If
Arm platform control of the OnCE is enabled before setting the LOCK bit, the Arm
platform can use the ONCE for debug purpose after LOCK is set.

7.2.2.5 OnCE and PCU Debug States

The SDMA has two different debug modes in which the OnCE performs debug
instructions.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1047
Smart Direct Memory Access Controller (SDMA)

Refer to Figure 7-4 for an example of the PCU states in debug. The following are the two
debug states:
• When a channel is running (that is, when CCR and CCPRI are different from 0,
which can be read in the PSW register), SDMA can execute a SoftBkpt instruction
from the channel script or receive a debug request. When either happens, the SDMA
enters its "Classical" Debug state, which is described in OnCE and Real-Time
Debug.
• When a channel is not running, the SDMA can be in Sleep state or in Sleep after
Reset state. If a debug request is sent to the core, it enters its Debug in Sleep state.
This debug mode works similarly to the "Classical" Debug state, except it returns to
the original state (Sleep or Sleep after Reset) when the debug mode is left via the
exec_core instruction of the OnCE. From this Debug in Sleep state, the SDMA can
execute a program whereas no channel is running. If a new debug request is sent to
the core or if a SoftBkpt is executed, it comes back to this Debug in Sleep state.
The OnCE is provided with several instructions that can be executed when the core is in
either debug state. The following table summarizes the behavior of these OnCE debug
instructions. There exists other secondary OnCE instructions that are described in OnCE
and Real-Time Debug.
Table 7-9. SDMA in Debug Mode
Instruction Debug Debug in Sleep
exec_once exec_once <instruction> exec_once <instruction>
SDMA executes the <instruction> and returns to the SDMA executes the <instruction> and returns to the
Debug state. The Program Counter (PC) is not Debug in Sleep state. The Program Counter (PC) is
incremented. This command must not be used with an not incremented. This command must not be used
instruction that modifies the PC value. with an instruction that modifies the PC value.
run_core run_core <instruction> run_core <instruction>
SDMA executes the <instruction>, leaves the Debug SDMA executes the <instruction> and returns to its
state and continues executing the channel script from Sleep or Sleep after Reset initial state. This command
the position where it stopped. This command must not must not be used with an instruction that modifies the
be used with an instruction that modifies the PC PC value.
value.
exec_core exec_core <instruction> exec_core <instruction>
It is similar to run_core except it requires an If the previous state was Sleep after Reset, the SDMA
instruction that changes the PC value (jump, returns to this state, and Chn0Addr value overrides
branch...): the SDMA jumps to the new PC value, the PC value.
leaves the Debug state and starts executing
Otherwise, the SDMA jumps to the new PC value and
instructions from this new PC value.
starts executing instructions from this new PC.

NOTE
The feature exec_core in Debug in Sleep after Sleep after Reset
was added for the Channel boot (channel 0) to allow the
debugger to return to Sleep after Reset state with a new PC

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1048 NXP Semiconductors
 Chapter 7 Interrupts and DMA

value. The SDMA will be ready to boot at the Chn0Addr

address.

7.2.2.6 SDMA Clocks and Low Power Modes

The SDMA receives several root clocks from the SoC clock controller block and
performs adaptive clock gating to optimize its power consumption. From a user
standpoint, clock gating and power mode selection are fully automatized inside the
SDMA.
Root clock control is available from the SoC clock controller block.
There are numerous clock sources that are used in the SDMA. They belong to one of two
possible clock domains listed in the following table, and have frequency constraints
within each domain. Clocks are considered asynchronous between domains.
Within the Arm platform/SDMA clock domain, all clocks must come from the same
DPLL. The Arm platform DMA interfaces (peripheral DMA and burst DMA) receive
their clock from the Arm platform DMA clock source whose frequency can be once or
twice the frequency of the SDMA core clock. The DMA interfaces are designed to work
at the Arm platform DMA frequency, but the SDMA core is physically limited to a
maximum 104 MHz frequency. Since this is lower than the maximum Arm platform
DMA frequency, the SDMA core clock is tied to the Arm platform peripheral clock
frequency.
The Arm platform Peripheral Bus Clock source must be an exact sub-frequency of the
SDMA Core clock source (any integer value greater or equal to 1).
Table 7-10. Clocking Scheme
Clock Domain Source Clock Comments
Arm platform SDMA core Source clock for the core and all its operations; this clock is thus used by most
of the SDMA sub-blocks.
(SDMA main core)
Arm platform DMA DMA interface for the peripheral DMA and the burst DMA. It is balanced with
the main clock source, and its frequency is either once or twice the main clock
frequency.
Arm platform peripheral Connection to the Arm platform peripheral bus. It is a sub-frequency of the
main clock frequency.
JTAG TCK Clock for JTAG access, limited to maximum of 1/8 of the SDMA core clock
frequency.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1049
Smart Direct Memory Access Controller (SDMA)

The JTAG clock is sampled by the SDMA main clock to determine its rising edge. This
simplifies design and clock management, but it also adds a ratio constraint between those
two clocks. It is guaranteed the JTAG interface works properly when the frequency of
TCK is lower than 1/8th of the frequency of the SDMA main clock (which is about 8
MHz when the SDMA core clock frequency is 66 MHz).

7.2.2.6.1 Clock Gating and Low Power Modes

The SDMA automatically performs power saving without requiring user involvement. It
implements two levels of automatic clock gating.

7.2.2.6.1.1 Coarse Clock Gating

Every sub-block clock comes from one of the five available sources, and is gated with the
sub-block specific enabling condition.
The following table displays the sub-block clocks and their source. It also indicates the
relationships that may exist between different sub-blocks clock enables.
Table 7-11. Sub-blocks Clocks
Sub-block Source Clocks Enabling Condition and Comments Related Enabling
Conditions
Core SDMA Main The core sub-block clock is running when the core is not in one of None
Core its sleep states (Sleep or Sleep after Reset) or there is a pending
channel. Typically, the core sub-block clock is stopped once all the
channels are processed and the core enters its sleep state. A new
pending channel awakes the core sub-block clock.
Memories SDMA Main The clock activation only occurs during a core access. Disabled when
Core Core sub-block
clock is disabled or
no memory access
in progress
Scheduler SDMA Main Its clock only runs when scheduling is needed: for example, when None
Core there are pending channels, upon reception of a DMA request, and
anytime the Arm platform modifies the channel running conditions.
Arm platform SDMA Main The Arm platform peripheral clock is solely used to determine the None
Control Core frequency ratio with the SDMA main clock. The control registers'
clock is based on SDMA main clock; it is active when the Arm
&
platform or the SDMA modifies the contents of one of these
Arm platform registers.
peripheral
Burst DMA SDMA Main The burst DMA has two clocks: The first clock is derived from the Disabled when
Core SDMA main core clock and drives registers that are connected to Core sub-block
the FUBUS. The second clock is derived from the Arm platform clock is disabled
&
DMA clock and drives registers that are connected to the Arm
Arm platform platform DMA bus outside the SDMA. Both clocks are enabled
DMA
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1050 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-11. Sub-blocks Clocks (continued)

Sub-block Source Clocks Enabling Condition and Comments Related Enabling
Conditions
during active phases of data transfers (for example, these clocks
are turned off when the burst DMA is not used by the running
channel script).
Peripheral DMA SDMA Main The peripheral DMA has two clocks: The first clock is derived from Disabled when
Core SDMA main clock and drives registers that are connected to the Core sub-block
FUBUS. The second clock is derived from the Arm platform DMA clock is disabled
&
clock and drives registers that are connected to the Arm platform
Arm platform DMA bus outside the SDMA. Both clocks are enabled during active
DMA phases of data transfers (for example, these clocks are turned off
when the peripheral DMA is not used by the running channel
script).
OnCE SDMA Main The OnCE clock is derived from main source clock. It is disabled by When enabled, all
Core default. In order to use the OnCE, its clock must be explicitly turned other clocks are
on, either by enabling the OnCE access from the Arm platform systematically on
peripheral bus (register ONCE_ENB), or by driving the (clock gating is off)
clk_gating_off input pin high. This is a SDMA input whose driver
depends on the SoC implementation (typically a JTAG controller).
The OnCE also receives the TCK input, which is the JTAG clock. It
does not use it as a functional clock; the TCK input is sampled
instead. Refer to Synchronization Implementation.

7.2.2.6.1.2 Refined Clock Gating

The SDMA implements a second level of clock gating on a register-per-register basis.
Unlike the first level that covers all the SDMA flip-flops, except the synchronizers (only
five flip-flops are always running), the second level is only available for eligible
registers, which amounts to about 90% of the SDMA flip-flops.
These gated registers are only clocked when the hardware logic detects a new data
loading. This additional gating further reduces dynamic power consumption.

7.2.2.6.1.3 Low Power Modes and User Control

Power savings are automatically managed by the SDMA hardware without any user
involvement; however, one can distinguish three different power modes: SLEEP, RUN,
and DEBUG.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1051
Smart Direct Memory Access Controller (SDMA)

The following table describes these modes, and shows how to switch from one mode to
another.
Table 7-12. Power Modes
Power Sub-blocks Comments
Mode
Core Mem Sche Arm Burs Perip OnC
ories duler platf t heral E
orm DMA DMA
Cont
rol
SLEEP off1 off wait2 wait off off off Set when the PCU state is either Sleep or Sleep after Reset
and the SDMA is not in DEBUG mode. This is the default
mode after reset.
RUN on3 wait wait wait wait wait off Set for the other PCU states that are reachable out of debug:
Program, Data, Change of Flow, Error in Loop, Debug,
Functional Unit, Save, or Restore.
DEBUG on on on on on on on Set regardless of the PCU state when clock gating is turned
off to use the OnCE features (either clk_gating_off pin high
or ONCE_ENB[0] set).

1. off: no clock
2. wait: only clocked when accessed or stimulated
3. on: clock is always running

It is possible to control the SDMA power mode. The procedures to force the SDMA into
either mode are described in SLEEP Mode.

7.2.2.6.1.3.1 SLEEP Mode

This is the default mode after reset; therefore, resetting the SDMA forces this mode.
However, the common procedure is as follows:
• Ensure the clk_gating_off pin is low and ONCE_ENB[0] is cleared.
• Disable all channels (via the STOP_STAT control register, and the HO, DO, EO if
necessary).
• Wait for the active channels to complete or force a reschedule via the reschedule bit
in the RESET register.
• The SDMA is in SLEEP mode making it possible to completely shut off its clock
from the chip level clock controller using the procedure described in Stop Mode
Response.

7.2.2.6.1.3.2 RUN Mode

This is the default mode when a channel is running:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1052 NXP Semiconductors
 Chapter 7 Interrupts and DMA

• Ensure the clk_gating_off pin is low and ONCE_ENB[0] is cleared.

• Activate at least one channel (via the HSTART control registers, a DMA request,
and/or the HO, DO, EO register bits).

7.2.2.6.1.3.3 DEBUG Mode

The DEBUG mode must be set when one needs to use the debugging facilities of the
SDMA.
• Ensure the SDMA clocks are running from the CCM.
• Set the clk_gating_off pin high or use the SDMA to set ONCE_ENB[0].

7.2.2.6.1.4 Stop Mode Response

The SDMA receives a stop request from the chip level clock controller. This request may
be asserted when the chip enters the stop low power mode.
If the SDMA is running when the request is received, then the SDMA will complete all
pending channels before returning to the SLEEP state. The SDMA sends an
acknowledgement to the clock controller when the SLEEP state is entered indicating that
the SDMAs clocks can be turned off.

7.2.2.6.2 Reset
After reset (either received from the reset block or a software reset required by the Arm
platform), the SDMA is in IDLE mode. It will start its boot code located at address 0
once a channel is activated.
Activating a channel can be done by the Arm platform after programming a positive
priority and setting the channel bit in the EVTPEND register.
There will not be a context RESTORE for the first channel (bootload channel) called
after a reset because the context data in RAM has not been initialized. Static context
mode should be used for the first channel called after reset to ensure that the all context
RAM for that channel is initialized. Subsequent calls to the same channel or different
channels may use any of the dynamic context modes

7.2.2.7 Software Interface

Appendix A fully describes the SDMA Application Programming Interface (API).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1053
Smart Direct Memory Access Controller (SDMA)

7.2.2.8 Initialization Information

This section discusses the following:

• Hardware Reset
• Channel Script Execution
• Initialization and Script Execution Setup Sequence

7.2.2.8.1 Hardware Reset

After reset, the program RAM, context RAM, data RAM, and RAM containing the
channel enable registers (CHNENBLn) have unpredictable contents.
The active register set is assigned to channel 0 and the PC is initialized to all zeros.
However, since the channel enable register is all zeros, there are no active channels and
the SDMA is halted waiting for the boot channel to start.
The Arm platform will have to setup the SDMA in order to boot it. The CONFIG register
must be initialized to determine the DMA/core clock ratio (1 or 2). Channel Enable
Registers must also be initialized.
To start up the SDMA, the Arm platform first creates some channel control blocks (CCB)
and buffer descriptors (BD) in Arm platform memory for the boot channel (channel 0)
and then initializes the channel 0 pointer register (SDMA_MC0PTR) to the address of the
first control block. Data Structures for Boot Code and Channel Scripts provides an
overview of the data structure for the CCB and BD's. The SDMA_HSTART,
SDMA_HOSTOVR and SDMA_EVTOVR registers are then configured according to
Runnable Channels Evaluation to allow channel 0 to run.
Upon being enabled, the SDMA begins executing the script located at the address
indicated by the Channel 0 Boot Address register (SDMA_CHN0ADDR) in the program
memory. The reset value of SDMA_CHN0ADDR points to the default bootload script in
ROM. This ROM script will read the channel 0 pointer register (SDMA_MC0PTR) to
determine the location of the Channel Control Block (SDMA_CCB) in Arm platform
memory. The script will then begin fetching by DMA the first channel control block
which contains a pointer to the location channel 0 Buffer Descriptor chain which is also
fetched via DMA. If the buffer descriptor contains a valid command, the script interprets
the command in each buffer descriptor and proceeds to implement the command and
move on to the next buffer descriptor control block. The buffer descriptor commands for
channel zero are typically set up to load SDMA's program RAM, Data RAM, and initial
values for the channel contexts. Some channel scripts expect particular parameters to be
passed

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1054 NXP Semiconductors
 Chapter 7 Interrupts and DMA

There are two ways to make the SDMA boot on a user-defined script. The OnCE (either
via its JTAG interface or its Arm platform Control interface) can be used to download
any code in the SDMA RAM and force the SDMA to boot on that code. Also, the
SDMA_CHN0ADDR register in the Arm platform programming model can be modified
to point to user code in RAM which would need to either have been loaded via the ONCE
or default bootload routine (ex before a S/W reset).

7.2.2.8.2 Channel Script Execution

The execution of an SDMA script depends on both the instructions that make up the
script, the data context upon which it operates, and commands or parameters allowed to
the buffer. All these items must be initialized before the script is allowed to execute.
Each of the 32 channels has a separate context, but may share scripts and locations in
data RAM.
Channels are initialized by the Arm platform by using channel 0 to download any
required scripts and data values and the channels initial context. The context contains all
the initial values of the SDMA core registers. This includes the Program Counter (PC)
which is set to the start of the desired script in SDMA program memory.
The Arm platform selects which trigger conditions that must occur for the channel to start
by configuring the SDMA_CHNENBL, SDMA_HOSTOVR and SDMA_EVTOVR
registers. The trigger events include Arm platform setting HE (SDMA_HSTART) or a
hardware DMA request asserts an event input to SDMA. The channel can become active
according to its priority compared with other runnable channels when the selected
trigger(s) cause the condition described in Runnable Channels Evaluation to evaluate as
true.
The specific parameters to be passed to each script in the buffer descriptor or context are
documented in the software documentation for each script. Please refer to SDMA Scripts
for complete script documentation. Buffer Descriptor Format provides an overview of the
buffer descriptor format.

7.2.2.8.3 Initialization and Script Execution Setup Sequence

To summarize, the following steps are minimally required to setup SDMA and run
channel scripts.
• Perform Hardware Reset. The program RAM, context RAM, data RAM and
SDMA_CHNENBLn registers have unpredictable contents after this reset.
• Initialize SDMA_CHNENBLn registers to map DMA request events to desired
channels.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1055
Smart Direct Memory Access Controller (SDMA)

• Configure SDMA_CHNPRIn registers to select priority for runnable channels. A

non-zero priority is required for the channel to run.
• Configure the SDMA_CONFIG register to select DMA to SDMA core clock ratio .
• Set up channel control blocks and buffer descriptors in Arm platform to specify the
loading of SDMA program RAM and channel contexts for each SDMA channel to be
used. Reference Data Structures for Boot Code and Channel Scripts.
• Configure SDMA_MC0PTR register with base address of Arm platform Channel
Control Block base address.
• Initialize SDMA_CHNENBLn registers to map DMA request events to associated
channel. Reference Mapping DMA Requests to Pending Channels.
• Configure SDMA_CHNPRIn registers to set priority for each channel to be run.
• For each channel to be run, configure SDMA_HOSTOVR (HO) and
SDMA_EVTOVR (EO) registers to select which events (hardware and/or software
trigger events) must occur for the channel to be runnable. Reference Runnable
Channels Evaluation.
• Set bit 0 of the SDMA_HSTART register to set HE[0] and allow Channel 0 to run
(assumes EO[0] andDO[0] were both set in previous step). This will cause SDMA to
load the program RAM and channel contexts configured previously.
• Wait for Channel 0 to finish running. This is indicated by HI[0]=1 in the
SDMA_SDMA_INTR register, or by optional interrupt to the Arm platform.
• Set the LOCK bit in the SDMA_SDMA_LOCK register to prevent un-authorized
uploads of data to SDMA RAM.
• Additional channel scripts can now be run by enabling the selected software or
hardware trigger event according to Runnable Channels Evaluation.

7.2.2.9 SDMA Programming Model

This section describes the programming model for the SDMA RISC engine, including its
processor, memory, and internal control registers.
All addresses are related to the internal SDMA memory map, which is completely
different from the Arm platform memory maps. The Arm platform processor has no
access to any hardware resource described, except when those resources are described in
Arm Platform Memory Map and Control Register Summary. .

7.2.2.9.1 State and Registers Per Channel

The SDMA can be seen as a set of 32 identical devices that are able to perform one data
transfer channel each. Only one channel can work at a time, but every channel state is
available at any time.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1056 NXP Semiconductors
 Chapter 7 Interrupts and DMA

This chapter lists the components of every channel state.

7.2.2.9.2 General Purpose Registers

Each channel has eight general purpose registers of 32 bits for use by scripts. General
register 0 has a dedicated function for the loop instruction, but otherwise can be used for
any purpose.

7.2.2.9.3 Functional Unit State

Each channel context has some state that is part of the functional units.
The specific allocation of this state is part of the functional unit definition that is
described in Burst DMA Unit Programming, Peripheral DMA Unit Programming .
This state must be saved/restored on context switches.

7.2.2.9.3.1 Program Counter Register (PC)

The PC is 14 bits. Since instructions are 16 bits in width and all memory in the SDMA is
32 bits in width, the low order bit of the PC selects which half of the 32-bit word contains
the current instruction.
A low order bit of zero selects the most significant half of the word.1

7.2.2.9.3.2 Flags
Each channel has the following four flags:
• The T bit reflects the status of some arithmetic and test instructions. It is set when the
result of an addition or a subtraction is zero and cleared otherwise. It is also the copy
of the tested bits. Finally, it can also be set when the loop counter (GReg0) reaches
zero. When the last instruction of the hardware loop is an operation that can modify
the T flag, its effect on T is discarded and replaced by the GReg0 status.
• Two additional bits, SF and DF, are used to indicate error conditions resulting from
loading data sources and storing to destinations, respectively. Access errors set these
bits, and successful transactions clear them. They can also be cleared by specific
instructions (CLRF and loop). The source fault (SF) is updated by the loads LD and
LDF; the destination fault (DF) is updated by the stores ST and STF.

1. For example, big-Endian.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1057
Smart Direct Memory Access Controller (SDMA)

• Access errors are caused by several conditions including writing to the ROM, writing
to a read-only memory mapped register, accessing an unmapped address, or any
transfer error received by a peripheral when it is accessed.
The SF and DF flags have a major impact on the behavior of the hardware loop: If
SF or DF is set when starting a hardware loop and it is not masked by the loop
instruction, the loop body will not be executed. Inside the loop body, if a load or
store sets the corresponding SF or DF flag, the loop exits immediately. Testing the
status of the T flag at the end of the loop (as well as testing both SF and DF) tells if
the loop exited abnormally as any anticipated exit prevents GReg0 from reaching the
zero value and thus setting the T flag. This is also valid if the fault occurs at the last
instruction of the last loop.
• The last flag is the loop mode flag, LM, which is composed of two bits. The most
significant bit indicates when the processor is currently operating in loop mode. It is
set by the loop instruction and is cleared after execution of the last instruction of the
last loop. The least significant bit is set when the program counter points to the last
instruction of a loop on the last path. It is used for a channel that is restored with this
configuration to know that the next program counter is EPC. As with the dynamic
context switch Greg0, which indicates when the program must get out of the loop, it
can be restored only on the last instruction of the loop. This, however, is too late to
fetch the next instruction after the loop.

7.2.2.9.3.3 Return Program Counter (RPC)

The RPC is 14 bits. It is set by the jump to the subroutine instructions and used by the
return from the subroutine instructions.
Instructions are available to transfer its contents to and from a general register.

7.2.2.9.3.4 Loop Mode Start Program Counter (SPC)

The SPC is 14 bits. It is set by the loop instruction to the location immediately following
it.

7.2.2.9.3.5 Loop Mode End Program Counter (EPC)

The EPC is 14 bits. It is set by the loop instruction to the location of the next instruction
after the loop.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1058 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.9.4 Context Switching-Programming

Each channel has a separate context consisting of the eight general purpose registers and
additional registers representing the state of the functional units.
The active registers and functional units contain the context of the active channel. The
context of inactive channels is stored in SDMA RAM, which is part of the SDMA
address space.
In a function of the selected context switching mode (Context Switching), modified
registers by the program can be saved in the channel RAM space while the program is
going on. In every cycle, a write access to the RAM is possible.
On a done or yield(ge) instruction, SDMA goes into "real" context switching. In one of
the dynamic modes, modified registers not previously saved, as well as the PC-Loop
registers, are stored into the context area of the channel that will be closed. The new PC-
Loop registers are loaded from the context area of the new channel. All other registers are
restored while the program is executed, giving priority to registers used by the decoded
instruction. Therefore, in the best case, only the PC and Loop registers should be saved
and restored during this context-switching phase, which only requires five SDMA cycles.
In static mode, the context switch stores all registers in the old channel RAM space, and
restores all registers from the new channel RAM space. It requires 26 SDMA cycles.
The address of the context memory for channel i is CONTEXT_BASE + 24*i or
CONTEXT_BASE + 32*i where CONTEXT_BASE equals 0x0800. The table below
presents the layout of a channel context in memory:
Table 7-13. Layout of a Channel Context in Memory for SDMA
OFFSET 31 30 29-16 15 14 13-0
0 SF - RPC T - PC
1 LM EPC DF - SPC
2 GR0
3 GR1
4 GR2
5 GR3
6 GR4
7 GR5
8 GR6
9 GR7
10 MDA (burst DMA)
11 MSA (burst DMA)
12 MS (burst DMA)
13 MD (burst DMA)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1059
Smart Direct Memory Access Controller (SDMA)

Table 7-13. Layout of a Channel Context in Memory for SDMA (continued)

14 PDA (peripheral DMA)
15 PSA (peripheral DMA)
16 PS (peripheral DMA)
17 PD (peripheral DMA)
18
19
20 Reserved1
21 Reserved1
22 Reserved1
23 Reserved1
24 Scratch RAM (optional)
25 Scratch RAM (optional)
26 Scratch RAM (optional)
27 Scratch RAM (optional)
28 Scratch RAM (optional)
29 Scratch RAM (optional)
30 Scratch RAM (optional)
31 Scratch RAM (optional)

7.2.2.9.5 Address Space

The SDMA has four internal buses which are listed here.
• The Instruction bus reads instructions from the memory. Its address map is described
in Instruction Memory Map.
• The Data bus (DMBUS) accesses the same memories as those visible on the
Instruction bus, some memory-mapped registers (scheduler status and OnCE
registers), and up to 14 peripherals. Its address map is described in Data Memory
Map.
• The Functional Units bus (FUBUS) accesses the , Burst DMA, Peripheral DMA .
The addressing mechanism is further detailed in Functional Units Programming
Model.
• The Context Switch bus reads/writes registers into context-switch RAM space. It is a
64-bit bus dedicated for accessing this RAM space for updating the context of the
running channel. While the program is going on, this bus has the lowest priority
compared to the Instruction and Data buses, except for restoring a register needed for
the decoded instruction to be executed. On the save part of a context switch (when
the PCU is in its slave state), this is the only one used. On the restore part, the
Instruction bus has the priority to read the next instruction at the restored PC and

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1060 NXP Semiconductors
 Chapter 7 Interrupts and DMA

otherwise the Context Switch bus is used. It is not possible to control the actual data
transfers that occur on this bus.

7.2.2.9.5.1 Instruction Memory Map

The instruction memory map is based on a 14-bit address bus and a 16-bit data
(instruction) bus.
Instructions are fetched from either program ROM or program RAM. An SDMA script is
able to change the contents of the program RAM, which is also visible from the data bus.
The first two instruction locations (at 0 and 1) are special. Location 0 is where the PC is
set on reset. Location 1 is where the PC is set upon the execution of an illegal instruction.
It is expected that both of these locations will contain a jmp to handle routines.
Table 7-14. SDMA Instruction Memory Space
Device SDMA Base Address Label Block WS Description
Address (Hex) Name
ROM 0x0000 ↓ SDMA_IBUS_ROM_ADDR - 0 4 Kbyte internal ROM with
0x07FF boot code and standard
routines.
RAM 0x1000 ↓ SDMA_IBUS_RAM_ADDR - 0 8 Kbyte internal RAM with
0x1FFF channels context and user
data/routines.

7.2.2.9.5.2 Data Memory Map

All of the data accessible to SDMA scripts make up the data memory space of the
SDMA.
This address space has several components:
• ROM (also visible on the Instruction bus)
• RAM (also visible on the Instruction bus)
• Shared Peripherals Registers
• SDMA Internal Registers (scheduler, OnCE, and registers that are also accessible by
the Arm platform)
SDMA scripts can read and write to the context RAM, data RAM, shared peripheral
registers, and internal registers.
The address range is 16 bits and the data width is 32 bits. When accessing peripheral
registers (USB and so on), the data width may be different. The exact address map for the
peripherals depends on the project (as presented in each respective chapter).
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 1061
Smart Direct Memory Access Controller (SDMA)

Data access is performed with ld and st instructions that take the address from a general
purpose register in the core (GRegn). The mapping between the general purpose register
contents and the address bus is given in the following table:
Table 7-15. GRegn to DMBUS Address Mapping
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
address

Grayed bits are simply discarded but they must be cleared to ensure forward-script
compatibility.
• sz (bit 31) indicates the peripheral data width: 0 is used for a 32-bit peripheral and 1
is used for a 16-bit peripheral.
• address (bits 15 down to 0) is the address of the accessed resource (internal memory,
internal register, or shared peripheral).
Table 7-16. SDMA Data Memory Space
Device SDMA Address (Hex) Size Description
ROM 0x0000 → 0x03FF 4 Kbyte 4 Kbyte internal ROM with boot code and standard routines
Reserved 0x0400 → 0x07FF 4 Kbyte 4 Kbyte Reserved
RAM 0x0800 → 0x0FFF 8 Kbyte 8 Kbyte internal RAM with channels contexts and user data/routines
per1 0x1000 → 0x1FFF 16 Kbyte peripheral 1 memory space (4 Kbyte peripheral's address space)
per2 0x2000 → 0x2FFF 16 Kbyte peripheral 2 memory space (4 Kbyte peripheral's address space)
per3 0x3000 → 0x3FFF 16 Kbyte peripheral 3 memory space (4 Kbyte peripheral's address space)
per4 0x4000 → 0x4FFF 16 Kbyte peripheral 4 memory space (4 Kbyte peripheral's address space)
per5 0x5000 → 0x5FFF 16 Kbyte peripheral 5 memory space (4 Kbyte peripheral's address space)
per6 0x6000 → 0x6FFF 16 Kbyte peripheral 6 memory space (4 Kbyte peripheral's address space)
Registers 0x7000 → 0x7FFF 16 Kbyte Memory mapped registers
per7 0x8000 → 0x8FFF 16 Kbyte peripheral 7 memory space (4 Kbyte peripheral's address space)
per8 0x9000 → 0x9FFF 16 Kbyte peripheral 8 memory space (4 Kbyte peripheral's address space)
per9 0xA000 → 0xAFFF 16 Kbyte peripheral 9 memory space (4 Kbyte peripheral's address space)
per10 0xB000 → 0xBFFF 16 Kbyte peripheral 10 memory space (4 Kbyte peripheral's address space)
per11 0xC000 → 0xCFFF 16 Kbyte peripheral 11 memory space (4 Kbyte peripheral's address space)
per12 0xD000 → 0xDFFF 16 Kbyte peripheral 12 memory space (4 Kbyte peripheral's address space)
per13 0xE000 → 0xEFFF 16 Kbyte peripheral 13 memory space (4 Kbyte peripheral's address space)
per14 0xF000 → 0xFFFF 16 Kbyte peripheral 14 memory space (4 Kbyte peripheral's address space)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1062 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.10 SDMA Initialization

Appendix A describes the setup of the SDMA . This section provides a quick description
of several initialization procedures.
NOTE
There may be differences with the actual implementation in the
API.

7.2.2.10.1 Hardware Reset-SDMA

After reset, the RAM that holds contexts, data, scripts, and the DMA request-channels
matrix has unpredictable content.
The core registers are all reset to 0, including the PC; the PCU state is Sleep after Reset.
No channel can be activated because all of the priorities are also reset to 0.

7.2.2.10.2 Standard Boot Sequence

The following is the standard boot sequence:
1. Initialize the CONFIG register-detailed in Configuration Register
(SDMAARM_CONFIG)-to determine the Arm platform DMA/core clock ratio (1 or
2)
2. Initialize the DMA request-channels matrix (seeChannel Enable RAM
(SDMAARM_CHNENBLn) ).
3. Program the channel control registers-Channel Event Override
(SDMAARM_EVTOVR), Channel BP Override (SDMAARM_DSPOVR), Channel
BP Override (SDMA_HOSTOVR), and Channel Event Pending
(SDMAARM_EVTPEND)-according to the channel allocation.
4. Perform any necessary setup as required by the standard boot script in ROM (this is
described in Appendix A).
5. Trigger channel 0 with the Channel Start (SDMAARM_HSTART) register, which
starts the execution of the ROM script starting at address 0. This boot downloads
channel scripts and contexts in RAM.

7.2.2.10.3 User-Defined Boot Sequence

The following is a user-defined boot sequence:
1. Initialize the Configuration Register (SDMAARM_CONFIG)Channel Enable RAM
(SDMAARM_CHNENBLn), Channel Event Override (SDMAARM_EVTOVR),
Channel BP Override (SDMAARM_DSPOVR), Channel Arm platform Override
(SDMAARM_HOSTOVR), and Channel Event Pending (SDMAARM_EVTPEND).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1063
Smart Direct Memory Access Controller (SDMA)

2. Use the OnCE (either via its JTAG interface or its Arm platform control registers) to
download any code in the SDMA RAM. Accessing the Memory describes how to
write data to the RAM via the OnCE.
3. Use the OnCE instructions to make the PC default value point to the new boot script
start address, or rely on the ROM startup script, which first jumps to the address in
Channel 0 Boot Address (SDMAARM_CHN0ADDR). (This register default address
points to the standard boot script.)

7.2.2.10.4 Script Loading and Context Initialization

The execution of an SDMA script depends on both the instructions that make up the
script and the data context upon which it operates. Both must be initialized before the
script is allowed to execute.
Each of the 32 channels has a separate data context, but may share scripts and locations
in the data RAM.
The Arm platform manages the space in program RAM and data RAM. It also manages
the assignment of SDMA channels to the device drivers that need them. Channels are
initialized by the Arm platform via the channel 0 boot script. The boot channel
downloads any required scripts with their data and the channels' initial contexts. Every
context contains all the initial values of the registers, including the PC. Then the Arm
platform can enable any channel that becomes active and begins fetching and executing
instructions from its script.

7.2.2.11 Instruction Description

The following sections introduce the instruction of the SDMA.
Instruction set details are available in Instruction Set.

7.2.2.11.1 Scheduling Instructions

The following are scheduling instructions:
• done-The instruction causes certain scheduling or interrupt bits to be set or cleared,
which may cause a change in the schedule-ability of the running channel. Then the
instruction causes the SDMA to evaluate the current scheduling priorities and to
choose the highest priority ready channel. If this channel is not the current channel, a
context switch will take place. If there are no runnable channels, the SDMA will
enter the stopped mode. The done 5 has a special usage reserved for debug, as
explained in Debug Instructions.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1064 NXP Semiconductors
 Chapter 7 Interrupts and DMA

• yield-These instructions are special cases of the done instruction. They do not modify
the scheduling bits, but allow the highest pending channel (if it exists) to preempt the
current channel if the pending channel priority is strictly greater than the current
channel priority.
• yieldge-These instructions are special cases of the done instruction. They do not
modify the scheduling bits, but allow the highest pending channel (if it exists) to
preempt the current channel if the pending channel priority is strictly greater or equal
to the current channel priority.
• notify-The notify instruction affects the scheduling bits, but does not cause
rescheduling.

7.2.2.11.2 Conditional Branch Instructions

The conditional branch instructions of an 8-bit displacement, which is sign-extended and
added to the current PC (which points to the next instruction) if the condition is satisfied.
Otherwise, control passes to the next sequential instruction.
• BF-Branch if False. The branch is taken if the T bit in the processor status is zero
(false).
• BT-Branch if True. The branch is taken if the T bit in the processor status is one
(true).
• BSF-Branch if Source Fault. The branch is taken if the SF bit in the processor status
is one.
• BDF-Branch if Destination Fault. The branch is taken if the DF bit in the processor
status is one.

7.2.2.11.3 Unconditional Jump Instructions

There are two varieties of unconditional control transfers: an absolute transfer and a
through-register transfer.
Absolute transfers have a 14-bit address field that replaces the current PC.
• JMP-Jump. Causes the processor to jump to an absolute address encoded in the
instruction itself.
• JSR-Jump to Subroutine. Causes the processor to jump to a subroutine, the address of
which is encoded in the instruction itself.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1065
Smart Direct Memory Access Controller (SDMA)

• JMPR-Jump through Register. Causes the processor to jump to an absolute address

contained in a General register. This instruction is meant to be used when more than
one level of subroutines are required.
• JSRR-Jump to Subroutine through Register. Causes the processor to jump to a
subroutine, the address of which is contained in a General register. This instruction is
meant to be used when more than one level of subroutines are required.

7.2.2.11.4 Subroutine Return Instructions

The following are subroutine return instructions:
• RET-Return from Subroutine. The RET restores the contents of RPC to PC.
• LDRPC-Load from RPC to Register. THe LDRPC instruction is meant to be used
when more than one level of subroutines are required. It stores the contents of RPC
in any General register.

7.2.2.11.5 Loop Instruction

The following is a loop instruction:
LOOP-Enters Loop Mode. Before entering loop mode, the loop instruction can optionally
clear the fault flags (SF and/or DF) based on a 2-bit field in the instruction. This feature is
linked to the fact that setting SF or DF in loop mode will cause an immediate exit of the
loop.

7.2.2.11.6 Miscellaneous Instructions

The following are miscellaneous instructions:
• CLRF-Clear Fault Flags. This instruction clears any combination of SF and DF.
• MOV r,s-This moves data from GReg[s] to GReg[r].
• LDI r,immediate-This loads GReg[r] with a zero-extended immediate value.

7.2.2.11.7 Logic Instructions

The following are logic instructions:
• XORr,s-This performs an exclusive or between GReg[r] and GReg[s], and stores the
result in GReg[r].
• XORIr,immediate-This performs an exclusive or between GReg[r] and a zero-
extended immediate value, and stores the result in GReg[r].
• ORr,s-This performs an or between GReg[r] and GReg[s], and stores the result in
GReg[r].

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1066 NXP Semiconductors
 Chapter 7 Interrupts and DMA

• ORIr,immediate-This performs an or between GReg[r] and a zero-extended

immediate value and, stores the result in GReg[r].
• ANDNr,s-This performs an and between GReg[r] and the negated GReg[s], and
stores the result in GReg[r].
• ANDNIr,immediate-This performs an and between GReg[r] and the negated zero-
extended immediate value, and stores the result in GReg[r].
• ANDr,s-This performs an and between GReg[r] and GReg[s], and stores the result in
GReg[r].
• ANDIr,immediate-This performs an and between GReg[r] and a zero-extended
immediate value, and stores the result in GReg[r].

7.2.2.11.8 Arithmetic Instructions

Arithmetic instructions modify the T bit in the processor status according to the result of
the operation. The T bit is set if the result is zero, otherwise it is cleared.
• ADD r,s-This performs the addition of GReg[r] and GReg[s], and stores the result in
GReg[r].
• ADDI r,immediate-This performs the addition of GReg[r] and a zero-extended
immediate value, and stores the result in GReg[r].
• SUB r,s-This performs the subtraction of GReg[s] from GReg[r], and stores the result
in GReg[r].
• SUBIr,immediate-This performs the subtraction of a zero-extended immediate value
from GReg[r], and stores the result in GReg[r].

7.2.2.11.9 Compare Instructions

Compare instructions modify the T bit in the processor status according to the result of
the operation. The T bit is set if the comparison is true, otherwise it is cleared.
NOTE
Only one version of the immediate form is implemented. Non-
equality comparisons to immediate values will require two
instructions.
• CMPEQ r,s-This sets T when registers GReg[r] and GReg[s] are equal.
• CMPEQIr,immediate-This sets T when register GReg[r] and the zero-extended
immediate value are equal.
• CMPLTr,s-This sets T when register GReg[r] is less than and not equal to GReg[s].
The comparison is signed.
• CMPHS r,s-This sets T when register GReg[r] is greater than or equal to GReg[s].
The comparison is signed.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1067
Smart Direct Memory Access Controller (SDMA)

7.2.2.11.10 Test Instructions

Test instructions modify the T bit in the processor status according to the result of the
operation. The T bit is set if any bit in the result is one, otherwise it is cleared.
• TSTr,s-This performs an and between GReg[r] and GReg[s], and sets T if the result
is not zero.
• TSTIr,immediate-This performs an and between GReg[r] and a zero-extended
immediate value, and sets T if the result is not zero.

7.2.2.11.11 Byte Permutation Instructions

These instructions shuffle the bytes in a register. For the purpose of describing these
instructions, have the bytes in a register be numbered from the most significant as b3, b2,
b1, b0.
• RORBr-The rotate right byte. The result is b0, b3, b2, b1.
• REVBr-The reverse bytes in word. The result is b0, b1, b2, b3.
• REVBLOr-The reverse, two low-order bytes. The result is b3, b2, b0, b1.

7.2.2.11.12 Bit Shift Instructions

The following are bit shift instructions:
• ROR1r-The rotate right 1 bit. This instruction does a circular right shift of 1 bit.
• LSR1r-The logical shift right 1 bit. This instruction shifts all bits to the right by 1.
The high order bit is replaced by a 0.
• ASR1r-The arithmetic shift right 1 bit. This instruction shifts all bits to the right by 1.
The high order bit is replaced by itself.
• LSL1r-The logical shift left 1 bit. This instruction shifts all bits to the left by 1. The
low order bit is replaced by zero.

7.2.2.11.13 Bit Manipulation Instructions

• BCLRIr,n-The bit clear is immediate; clears bit number i in register r.
• BSETIr,n-The bit set is immediate; sets bit number i in register r.
• BTSTIr,n-The bit test is immediate; tests bit number i in register r (T becomes equal
to the selected register bit).

7.2.2.11.14 SDMA Memory Access Instructions

All memory accesses are 32 bits.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1068 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Any memory location that is implemented with less than 32 bits (for example, peripheral
registers) causes unimplemented bits to be read as 0s.
All memory accesses will cause either the SF or DF flags in the processor status to be set
if they cause a fault.
What constitutes a fault, especially when accessing peripheral registers, is a property of
the memory location.
• LDr,(b,d)-The load instruction creates an address by adding the displacement field
(d) to the contents of the base register (b). The SDMA location at the resulting
address is read and placed in the destination register (r).
• STr,(b,d)-The store instruction creates an address in the same manner as the load
instruction. The register (r) is stored in the SDMA location at the resulting address.

7.2.2.11.15 Functional Unit Instructions

The functional unit instructions have an 8-bit field that is placed on the functional unit
bus.
Some of these bits are used to select which functional unit should be involved in the
transfer. The remaining bits are decoded by the selected functional unit so their specific
use depends on the functional unit. See Functional Units Programming Model.
There are two functional unit instructions, as follows:
• LDFr,fub-The 8-bit field is placed on the functional unit bus and a read is issued to
the selected functional unit. As a result of this instruction, the SF may be set in the
processor status.
• STFr,fub-The 8-bit field is placed on the functional unit bus and a write is issued to
the selected functional unit. As a result of this instruction, the DF may be set in the
processor status.

7.2.2.11.16 Illegal Instructions

All instruction encodings that are illegal cause the following actions:
• The current PC (which points to one beyond the offending instruction) is put in the
EPC register.
• The loop mode bit is cleared.
• The PC is set to the value stored in the Illegal Instruction Trap Address
(SDMAARM_ILLINSTADDR) register (the default value is 0x0001).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1069
Smart Direct Memory Access Controller (SDMA)

ILLEGAL-Although any instruction other than those indicated in the SDMA

specification will trigger the illegal instruction mechanism, the ILLEGAL instruction
code is preferred as it will always be kept as illegal in the possible future versions of the
SDMA core.

7.2.2.11.17 Debug Instructions

The following are debug instructions:
• SOFTBKPT-The software breakpoint instruction causes the core to stop and enter
debug mode. The core can then be accessed and started by the OnCE debug block
only.
• done 5-This instruction is used for debugging, as it copies the contents of the PCU
registers and flags to the context memory. Information on this instruction is
described in Saving the Context.
• CpShReg-This instruction copies the context memory into the PCU registers and
flags. Modifying the corresponding memory location before executing this
instruction enables you to have the channel continue from a new instruction address.
This instruction is described in Restoring the Context.

7.2.2.12 Functional Units Programming Model

The functional unit instructions cause an 8-bit code, found in the low eight bits of the
instruction, to be asserted on the functional unit control bus.
Some of these bits are used to select one of several functional units. Functional units
which can be selected include SDMA registers such as MSA and MSD which are not
mapped in the SDMA memory map, and are accessible only through the functional unit
bus. These Functional Unit Registers are listed in the following table. In order to establish
a programming convention, assume the selection bits are some number of the most
significant bits of the 8-bit code. Furthermore, some number of the least significant bits is
decoded by a given functional unit to establish the type of operation to perform.
Table 7-17. Functional Unit Registers
Functional Unit Register Register Name Section/Page
Burst DMA Unit SDMSA Memory Source Address Register Memory Source Address
Programming Register (MSA)
MDA Memory Destination Address Register Memory Destination
Address Register (MDA)
MD Memory Data Buffer Register Memory Data Buffer
Register (MD)
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1070 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-17. Functional Unit Registers (continued)

Functional Unit Register Register Name Section/Page
(Write) Burst DMA Write
(stf)
(Read) Burst DMA Read
(ldf)
MS Memory State Register State Register (MS)
Peripheral DMA Unit PSA Peripheral Source Address Register Peripheral Source Address
Programming Register (PSA)
PDA Peripheral Destination Address Register Peripheral Destination
Address Register (PDA)
PD Peripheral Data Buffer Register Peripheral Data Register
(PD)
(Write) Peripheral DMA
Write (stf)-Write Mode
(Read) Peripheral DMA
Read (ldf)-Read Mode
PS Peripheral State Register Peripheral State Register
(PS)

More information regarding the functional units can be found in Peripheral DMA Unit,
and Burst DMA Unit.

7.2.2.12.1 Burst DMA Unit Programming

The DMA instructions control the DMA state machine and may cause a DMA cycle on
the associated memory bus.
There are four registers associated with the burst DMA unit: a Memory Source Address
register (MSA), a Memory Destination Address register (MDA), a Memory Data buffer
(MD), and a state register (MS). The burst DMA has two different uses:
• A data transfer between External Memory Interface and SDMA general register
• A data transfer in copy mode where blocks of data are transferred from the source
address to the destination address

7.2.2.12.1.1 Memory Source Address Register (MSA)

The source address register contains the pointer into EXTMC memory associated with
the next read data transfer. It has byte granularity.
Reading the register with the ldf instruction has no side effects, and gives the address
value in the EXTMC memory of the next data that is read by the SDMA during an ldf
MD instruction.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1071
Smart Direct Memory Access Controller (SDMA)

Writing the source address register has two side effects: If the prefetch bit is set, a DMA
read cycle (8-word read access) is issued with the new address. Any data still located in
the buffer is lost. If there is valid write data in the buffer, it is necessary to force the
DMA to completely flush it out before modifying MSA to guarantee all the data is
effectively written to memory.
The MSA register has two modes of programming:
• Frozen-In frozen mode, the MSA register is not modified after DMA accesses.
• Incremented (default mode)-In incremental mode, MSA is incremented by the
number of bytes transferred during read cycles.

7.2.2.12.1.2 Memory Destination Address Register (MDA)

The destination address register contains the pointer into EXTMC memory associated
with the next write data transfer. It has byte granularity.
Reading the MDA register with the ldf instruction has no side effects. It gives the address
value in the EXTMC memory where the next SDMA data (stf r,MD instruction) is stored
when MD FIFO is flushed.
Writing the destination address register has one side effect. Any data still located in the
buffer is lost. If there is valid write data in the buffer, it is necessary to force the DMA to
completely flush it out before modifying MDA to guarantee all the data is effectively
written to memory.
The MDA register has two modes of programming:
• Frozen-In frozen mode, the MDA register is not modified after DMA accesses.
• Incremented (default mode)-The MDA register is incremented by the number of
bytes transferred during write cycles.

7.2.2.12.1.3 Memory Data Buffer Register (MD)

The data buffer register consists of a bank of 36 bytes that behave like FIFO.
This FIFO stores the eight words received when a read burst is triggered by the DMA
(DMA is in read mode).
The MD register is in write mode after a writing in MDA or after an stf MD instruction.
In that case, a burst write access is automatically triggered when there are more than eight
words in MD. For bandwidth optimization, any transfers between DMA and the EXTMC
controller are based on burst accesses.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1072 NXP Semiconductors
 Chapter 7 Interrupts and DMA

An ldf r,MD|SIZE instruction that reads the data buffer may cause a DMA cycle, as
follows:
• If there are less bytes in the FIFO than the size parameter of the instruction. For
instance, if only two bytes are available in MD and a 4-byte read is requested, a burst
read access is executed to complete the two bytes.
• If the prefetch bit is set, and after reading there is enough space in the FIFO to store a
full burst, a burst read access is triggered.
An stf r,MD|SIZE instruction that writes to the data buffer may cause a DMA cycle if the
number of written bytes in MD is higher than 32 (eight words) or if the flush bit is set.
When DMA is used for data transfer between SDMA and EXTMC (reading or writing),
no immediate error is possible because the block manages a data misalignment issue;
therefore, it is allowed to read/write a word to/from a half-word address. However, the
addresses (source or destination) must belong to the EXTMC memory mapping. The only
potential error, in this mode, would be the error sent back by the EXTMC controller
when an access to a super-user page is detected. The whole transfer on the DMA
associated bus will be considered successful when there are no errors seen on the bus
during the transfer. In copy mode, an immediate error could be returned to SDMA as
described in Burst DMA Unit Error Management.

7.2.2.12.1.4 State Register (MS)

The state register contains the DMA state-machine value. It can be accessed in case of an
error received during a transfer. MS is also accessed to set-up the conditional yielding
feature.
The initialization value of this register is 0 and it consists of the following:
Table 7-18. SDMA_MS Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 spriv stype 0 0 dpriv dtype
W
R 0 0 0 0 y d e 0 0 n
W

Table 7-19. SDMA_MS Field Descriptions

Field Description
31-22 Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1073
Smart Direct Memory Access Controller (SDMA)

Table 7-19. SDMA_MS Field Descriptions

(continued)
Field Description
21 The spriv value is ignored for this device.
spriv 0 = valid value
1 = Reserved
20 Source Mode. Indicates if MSA has to be incremented (or not) during accesses.
stype 0 Frozen-MSA is not modified.
1 Incremented-MSA is incremented by the number of transferred bytes during read access.
19-18 Reserved
17 The dpriv value is ignored for this device.
dpriv 0 = valid value
1 = Reserved
16 Destination Mode. Indicates if MDA has to be incremented (or not) during accesses.
dtype 0 Frozen-MDA is not modified.
1 Incremented-MDA is incremented by the number of transferred bytes during write access.
15-12 Reserved
11 Conditional Yielding selector. When selected, theyield/yieldge instructions will not switch channels if
the Burst DMA is in Write Mode, and it has less than four bytes in its FIFO. This is aimed at
y
reducing the number of inefficient FIFO flushes due to context switches.
0 Always yields
1 Yields conditionally (when there are less than four bytes in the FIFO in write mode)
10 Access Direction or DMA Mode. DMA is in write mode when data was written into MD by stf MD
instructions, or if a previous DMA cycle on the external bus was a write access. Writing MDA or
d
MSA changes the DMA mode to the respective value. DMA is in read mode when a previous DMA
cycle was a read access, and DMA stays in read mode when data is read by SDMA with an ldf MD
instruction. Reading MDA or MSA does not change the DMA mode.
0 Read Mode
1 Write Mode
9-8 Error. Indicates if the previous access was acknowledged with a bus error.
e 00 No error was received.
01 reserved
10 Error mode
11 error read burst
7-6 Reserved
5-0 Number of bytes in the MD FIFO.
n

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1074 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.12.1.5 Burst DMA Write (stf)

When received from a stf instruction, the function code bits are interpreted as follows,
depending on the addressed register:
Table 7-20. STF Code Bits
Register 7 6 5 4 3 2 1 0
MSA s p freeze r spriv
MDA dpriv
MD f cpy sz
MS

Table 7-21. STF Code Bit Field Descriptions

Field Description
7-6 Functional Unit selector
s 00 for Burst DMA
5 Prefetch Flag
p (MSA) 0 No prefetch
1 Prefetch required from new MSA
5 Forced Flush Flag
f (MD) 0 Automatic flush
1 FIFO contents are flushed (including the new written data).
4 Address Freeze Mode
freeze (MSA/MDA) 0 Address is normally incremented.
1 Address is frozen.
4 Copy Mode selection
cpy (MD) 0 Write Mode
1 Copy Mode
3-2 Register selection
r 00 MSA
01 MDA
10 MD
11 MS
1-0 Transfer Size
sz (MD/MS) 00 size 0 (no data stored in the FIFO)
01 byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
0 The spriv value is ignored for this device.
spriv (MSA) 0 = valid value
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1075
Smart Direct Memory Access Controller (SDMA)

Table 7-21. STF Code Bit Field Descriptions (continued)

Field Description
1 = Reserved
0 The dpriv value is ignored for this device.
dpriv (MDA) 0 = valid value
1 = Reserved

The possible write instructions are listed in the table below (unused bits should always be
cleared).
Table 7-22. Burst DMA STF Instruction List
Binary Assembly Comments
00_0_0_00_00 stf r,MSA Writes content of the SDMA general register (r) to the source address
register. MSA is in incremented mode.
00_0_1_00_00 stf r,MSA|FR Writes content of the SDMA general register (r) to the source address
register. MSA is in frozen mode.
00_1_0_00_00 stf r,MSA|PF Writes content of the SDMA general register (r) to the source address
register, and starts a read burst access. MSA is in incremented mode.
00_1_1_00_00 stf r,MSA|PF|FR Writes content of the SDMA general register (r) to the source address
register, and starts a read burst access.
00_0_0_01_00 stf r,MDA Writes content of the SDMA general register (r) to the destination address
register. MDA is in incremented mode.
00_0_1_01_00 stf r,MDA|FR Writes content of the SDMA general register (r) to the destination address
register. MDA is in frozen mode.
00_1_0_10_00 stf r,MD|SZ0|FL No data transfers between the SDMA and MD, but all valid written data of
the MD is flushed to the memory. An acknowledge or error is sent back to
the SDMA core on transfer completion.
00_0_0_10_01 stf r,MD|SZ8 8-bit (byte) transfer to write buffer MD
00_1_0_10_01 stf r,MD|SZ8|FL 8-bit (byte) transfer to write buffer MD and flush after transfer. All valid
written data of the MD is flushed to memory.
00_0_0_10_10 stf r,MD|SZ16 16-bit (half-word) transfer to write buffer MD
00_1_0_10_10 stf r,MD|SZ16|FL 16-bit (half-word) transfer to write buffer MD and flush after transfer. All
valid written data of the MD is flushed to memory.
00_0_0_10_11 stf r,MD|SZ32 32-bit (word) transfer to write buffer MD
00_1_0_10_11 stf r,MD|SZ32|FL 32-bit (word) transfer to write buffer MD and flush after transfer. All valid
written data of MD is flushed to memory.
00_0_1_10_00 stf r,MD|CPY No data transfer between SDMA and MD but starts a copy transfer whose
length is given by the 4 LSB of r register. (Maximum burst length is eight
words.)
00_0_0_11_11 stf r,MS 32-bit (word) transfer to status register MS
00_0_0_11_00 stf r,MS|SZ0 Clears the error flag (if set). Other MS bits are unchanged; this instruction is
also known as clref MS.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1076 NXP Semiconductors
 Chapter 7 Interrupts and DMA

NOTE
When a flush bit is set, the SDMA flushes the FIFO including
the newly written data. An acknowledge is sent to the core
before the flush completes (except if size 0 is used). The goal of
this flush bit is to force a flush, but it is recommended to use it
only when needed (for example, when finishing a row of pixels
during 2D data transfers). Indeed, if this bit is omitted and if
there are more than 32 bytes in the FIFO, a burst write access is
automatically triggered.
Since all the stf r,MD instructions (including the copy mode)
acknowledge the SDMA core before the store is effective
(except if size 0 is used), it is recommended to perform an ldf
from MS before terminating a channel in order to check the
final error status. (The ldf from MS will stall the core until all
the data was flushed out and the transfer status is known.)
After every stf MD instruction, the MDA is incremented by the
number of bytes that are written in MD, except when it is
programmed in frozen mode.

7.2.2.12.1.6 Burst DMA Read (ldf)

When received from an ldf instruction, the function code bits are interpreted as follows,
depending on the addressed register:
Table 7-23. LDF Code Bits
Register 7 6 5 4 3 2 1 0
MSA s r
MDA
MD p sz
MS

Table 7-24. LDF Code Bit Field Descriptions

Field Description
7-6 Functional Unit selector
s 00 for Burst DMA
5 Prefetch Flag
p (MD) 0 no prefetch
1 automatic prefetch

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1077
Smart Direct Memory Access Controller (SDMA)

Table 7-24. LDF Code Bit Field Descriptions (continued)

Field Description
3-2 Register selection
r 00 MSA
01 MDA
10 MD
11 MS
1-0 Transfer Size
sz (MD) 00 reserved
01 byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)

The table below lists the possible write instructions (unused bits should always be
cleared).
Table 7-25. Burst DMA LDF Instruction List
Binary Assembly Comments
00_0_0_00_00 ldf r,MSA Copies the source address register value into an SDMA general register. It
gives the memory address of the next data that will be read with an ldf MD
instruction.
00_0_0_01_00 ldf r,MDA Copies the destination address register value into an SDMA general
register. It gives the memory address where the next incoming data will be
flushed.
00_0_0_10_01 ldf r,MD|SZ8 8-bit (byte) read
00_1_0_10_01 ldf r,MD|SZ8|PF 8-bit (byte) read. If after this reading and the MD FIFO is empty, a burst
read access at the MSA address is triggered.
00_0_0_10_10 ldf r,MD|SZ16 16-bit (half-word) read
00_1_0_10_10 ldf r,MD|SZ16|PF 16-bit (half-word) read. If after this reading, and the MD FIFO is empty, a
burst read access at the MSA address is triggered.
00_0_0_10_11 ldf r,MD|SZ32 32-bit (word) read
00_1_0_10_11 ldf r,MD|SZ32|PF 32-bit (word) read. If after this reading and the MD FIFO is empty, a burst
read access at the MSA address is triggered.
00_0_0_11_00 ldf r,MS Copy the status register value into an SDMA general register.

NOTE
Read data is 0-extended before writing in the SDMA general
registers. When reading the MD register, the DMA takes data
from the FIFO if it is available. If part or whole data is not in
the FIFO, an external burst read access is performed to provide
the missing data. The SDMA is stalled as long as the required
read data is not complete.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1078 NXP Semiconductors
 Chapter 7 Interrupts and DMA

After every reading, MSA is incremented by the number of read

bytes from MD FIFO, except when MSA is programmed in
frozen mode.

7.2.2.12.1.7 Prefetch/Flush and Auto-Flush Management-Burst DMA Unit

The prefetch and auto-flush management enables the SDMA RISC machine to go on
while a DMA access is performed.
When the RISC core requires a prefetch (p = 1) to the Burst DMA, it will receive an
immediate transfer acknowledge before the DMA has finished the external access. This
enables the RISC core to do other things like accessing another DMA machine.
The basic principle in prefetch mode is for the DMA to anticipate data reads from the
SDMA RISC engine by fetching external bursts of data as soon as there is enough space
in the DMA FIFO to store it. If ever the RISC engine required data that is not available in
the FIFO, the read acknowledge is delayed until the data is available, but it does not have
to wait until the burst completes.
The auto-flush basic principle is similar: An automatic flush is triggered every time there
are eight words to be written in the FIFO. If the FIFO is full and the RISC engine
requires another write, it is stalled until the burst has started and enough space was freed
in the FIFO to store that new data. This means the SDMA RISC engine does not have to
wait for the completion of a burst to receive its acknowledge and continue its processing.
In particular, an auto-flush is executed when DMA is in write mode and if the following
is true:
• If the FIFO is empty and the first write is to a word-aligned address of any size (ex:
the 2 LSB of MDA[1:0]= 0x0), the auto-flush is triggered immediately after the write
of the 32'nd byte.
• If the FIFO is empty, and if MDA is an odd byte address (1, 3, 5, 7,...) and an stf
MD|SZ8 is executed, the byte is flushed to memory. Once MDA increments to a
word aligned address, the auto-flush will be triggered every 32 bytes.
• If the FIFO is empty, and if MDA is a half-word address (2, 6, 0xA,...) and an stf
MD|SZ16 is executed, the two bytes of the incoming data are flushed to memory.
Once MDA increments to a word aligned address, the auto-flush will be triggered
every 32 bytes.
• If the FIFO is empty, and if MDA is not a word-aligned address (ex 1, 2, 3, 5, 6, 7,
9,...), and an stf MD|SZ32 is executed, the first 1 to 3 bytes will be flushed up to the
next word aligned address. Afterwards, an auto-flush will be triggered each time the
FIFO receives 32-bytes.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1079
Smart Direct Memory Access Controller (SDMA)

• Therefore, if an stf MD|SZ32 is executed with MDA equal to 0x1 and with an empty
MD FIFO, the bytes located at addresses 1, 2, and 3 are flushed, and the byte located
at address 4 remains in MD FIFO. This solves the misalignment issue. Additionally,
the next write instructions (stf) complete the FIFO until it contains eight words; then
a burst write is executed by the DMA to empty the FIFO. Protocol on the external
bus does not support bursts of different data types (byte, half-word, or word).
For example, consider the case where data is written using a byte access, stf MD|
SZ8. The value of MDA during the very first byte write determines when the auto-
flush will occur as follows:
• If MDA=0x0, the flush occurs following the write of byte 32
• If MDA=0x1, the flush occurs following the write of byte 1, byte 3 and byte 35.
• If MDA=0x2, the flush occurs following the write of byte 2 and byte 34.
• If MDA=0x3, the flush occurs following the write of byte 1 and byte 33.
• If MDA=0x4, the flush occurs following the write of byte 32
The flush command forces the DMA to flush all MD valid bytes to the EXTMC
controller. An acknowledge is sent immediately to the SDMA, and any potential error is
reported on a future access. It is thus essential to conclude a transfer with a last read from
MS, which will stall the core until all data was flushed out and returned to the transfer
status (acknowledge or error).
NOTE
During this kind of auto-flush (which occurs only at the
beginning of a misaligned write transfer) no acknowledge is
sent back to the SDMA, which is stalled until a flush is
completed.

7.2.2.12.1.8 Data Alignment and Endianness-Burst DMA Unit

7.2.2.12.1.8.1 Burst DMA in Read Mode

For every read access to MD, the data returned to the SDMA core and the new FIFO state
depends on the MSA status and the access size.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1080 NXP Semiconductors
 Chapter 7 Interrupts and DMA

The FIFO is considered as a stack of 36 bytes: Data is fetched externally on a 32-bit bus,
but the valid bytes only are stored in the FIFO and left-aligned (for a transfer of
consecutive words, it is only the first word that may be truncated). The following table
shows the FIFO byte alignment strategy and the corresponding MSA, the returned data,
and the new FIFO state for any access size of an internal read from MD.
Table 7-26. FIFO Read Configuration
Before read Internal read Read data After read
access size
MSA[1:0] FIFO state MSA[1:0] FIFO state
00 x0 x1 x2 x3 sz8 00 00 00 x0 01 x1 x2 x3 y0
y0 y1 y2 y3 y1 y2 y3 z0
z0 z1 z2 z3 sz16 00 00 x0 x1 10 x2 x3 y0 y1
and so on... y2 y3 z0 z1
sz32 x0 x1 x2 x3 00 y0 y1 y2 y3
z0 z1 z2 z3
01 x1 x2 x3 y0 sz8 00 00 00 x1 10 x2 x3 y0 y1
y1 y2 y3 z0 y2 y3 z0 z1
z1 z2 z3 t0 sz16 00 00 x1 x2 11 x3 y0 y1 y2
and so on... y3 z0 z1 z2
sz32 x1 x2 x3 y0 01 y1 y2 y3 z0
z1 z2 z3 t0
10 x2 x3 y0 y1 sz8 00 00 00 x2 11 x3 y0 y1 y2
y2 y3 z0 z1 y3 z0 z1 z2
z2 z3 t0 t1 sz16 00 00 x2 x3 00 y0 y1 y2 y3
and so on... z0 z1 z2 z3
sz32 x2 x3 y0 y1 10 y2 y3 z0 z1
z2 z3 t0 t1
11 x3 y0 y1 y2 sz8 00 00 00 x3 00 y0 y1 y2 y3
y3 z0 z1 z2 z0 z1 z2 z3
z3 t0 t1 t2 sz16 00 00 x3 y0 01 y1 y2 y3 z0
and so on... z1 z2 z3 t0
sz32 x3 y0 y1 y2 11 y3 z0 z1 z2
z3 t0 t1 t2

7.2.2.12.1.8.2 Burst DMA in Write Mode

For every write access to the MD, the new FIFO state depends on the MDA status and the
access size.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1081
Smart Direct Memory Access Controller (SDMA)

The FIFO is considered as a stack of 36 bytes: Data is stored in the FIFO according to the
internal access size and the former MDA value. The following table shows the FIFO byte
alignment strategy corresponding to MDA, as well as the new FIFO state for any access
size of an internal write to MD.
Table 7-27. FIFO Write Configuration
Before write Internal write Written data After write
access size
MDA[1:0] FIFO state MDA[1:0] FIFO state
00 tt uu vv ww sz8 ?? ?? ?? x0 01 tt uu vv ww
?? ?? ?? ?? x0 ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 10 tt uu vv ww
x0 x1 ?? ??
?? ?? ?? ??
sz32 x0 x1 x2 x3 00 tt uu vv ww
x0 x1 x2 x3
?? ?? ?? ??
01 tt uu vv ww sz8 ?? ?? ?? x0 10 tt uu vv ww
xx ?? ?? ?? xx x0 ?? ??
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 11 tt uu vv ww
xx x0 x1 ??
?? ?? ?? ??
sz32 x0 x1 x2 x3 01 tt uu vv ww
xx x0 x1 x2
x3 ?? ?? ??
10 tt uu vv ww sz8 ?? ?? ?? x0 11 tt uu vv ww
xx yy ?? ?? xx yy x0 ??
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 00 tt uu vv ww
xx yy x0 x1
?? ?? ?? ??
sz32 x0 x1 x2 x3 10 tt uu vv ww
xx yy x0 x1
x2 x3 ?? ??
11 tt uu vv ww sz8 ?? ?? ?? x0 00 tt uu vv ww
xx yy zz ?? xx yy zz x0
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 01 tt uu vv ww
xx yy zz x0
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1082 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-27. FIFO Write Configuration (continued)

Before write Internal write Written data After write
access size
MDA[1:0] FIFO state MDA[1:0] FIFO state
x1 ?? ?? ??
sz32 x0 x1 x2 x3 11 tt uu vv ww
xx yy zz x0
x1 x2 x3 ??

NOTE
If the FIFO mode changes from a write to a read mode, all
remaining written bytes in MD are lost but no error is returned.
Typically, this happens if an ldf MD is executed after stf MD
instructions. Before a mode change, it is recommended to force
the flush of a potential remaining byte by a stfMD|SZ0|FL
instruction. In the same way, if a FIFO mode changes from a
read to a write mode, all prefetched data present in the FIFO is
lost and no error is returned.

7.2.2.12.1.8.3 Endianness-Burst DMA Unit

Big and Little Endian are supported by the Burst DMA, but data is always stored in MD
in Big Endian.
Byte manipulation is performed when data is exchanged with an Burst controller (for
example, during read or write burst accesses).

7.2.2.12.1.9 Burst DMA Unit Copy Mode

A mechanism is available to perform fast Arm-to-Arm transfers.
Data does not flow through the SDMA core: It is kept in the DMA FIFO. This
mechanism is selected when writing MD with a special option in the instruction code
(copy flag).
It is possible to transfer up to eight words in one SDMA instruction (this does not mean
in one cycle). In this mode, every time an stf MD|CPY is executed, a read burst is
executed and directly followed by a write burst transfer. Burst transfers are limited to
eight words. The size of the transfer (in words)-given by the SDMA general register (4
LSB)-is also limited to eight. The following SDMA code shows how 100 bytes could be
copied from the MSA address to the MDA address. This is sample code only.
Burst DMA copy mode example

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1083
Smart Direct Memory Access Controller (SDMA)
ldi r0,@src

stf r0,MSA // Source address setup

ldi r1,@dst

stf r1,MSA // Destination address setup

ldi r0,0x64 // data transfer counter

ldi r1,0x8

MAIN_XFER:

cmphs r0,r1 // Is r0 >= 0x8

bf LAST_XFER // If not, jump to last transfer label

stf r1,MD|CPY // Copy 8 words from MSA to MDA address.

subi r0,0x8 // Decrement counter

jmp MAIN_XFER // return to main transfer loop

LAST_XFER:

stf r0,MD|CPY

The main transfer loop is executed 12 times; then r0 equals 4 and the last transfer loop is
run.
In this mode, an acknowledge is transmitted to the core as soon as the read burst can start;
thus, a first copy instruction returns an immediate acknowledge and subsequent copy
instructions will be acknowledged as soon as the previous copy has finished.

7.2.2.12.1.10 Burst DMA Unit Error Management

Another point to consider is the management of errors.
Because the DMA immediately sends an acknowledge to the RISC core (except for the
stf MS|SZ0|FLS instruction), it assumes no error will occur. If an error occurs, it is
flagged (transfer error acknowledge) for the following DMA access.
This should not be a problem if the DMA is used properly. The MD accesses are meant to
stall the SDMA as little as possible to optimize throughput and hide calculation time.
Therefore, final access to MS should be performed before closing a channel. This access
waits until any pending operation is finished in the burst DMA and gather any remaining
error.
In copy mode, an error could be immediately returned to the SDMA on execution of the
ldf copy or stf copy instruction. It happens when MSA or MDA are not word addresses
(for example, 0[4]). This is because copy mode must only be used for transferring a large
packet of aligned data.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1084 NXP Semiconductors
 Chapter 7 Interrupts and DMA

When an error is received during a read transfer to the external bus, which may occur
during the burst accesses, the MD FIFO contains the valid beats of the burst, and the error
flag of MS is set to 2'b11 (error read burst). It is possible to read MS ("n" field) to know
how much valid data remains in MD and when MD is empty (after ldf instructions). The
next read MD instruction sets the MS error flag to 2'b10 (error mode), and an error is sent
back to the SDMA core. In error mode, it is possible to read MSA, which gives the
address of the error data. Any attempt to read or write MD, or to modify MDA or MSA in
error mode, gives rise to an error; therefore, an error flag must be reset by clearing MS at
the end of the SDMA code section responsible for error management.
In "error read burst" mode, writing MDA, MSA, or MD, or starting a copy transfer by a
stf MD|COPY instruction will cancel the error mode. The following table shows when an
immediate error is sent back according to the executed instruction.
Table 7-28. Possibilities in ERROR READ BURST Mode
DMA Instruction Immediate Error Comments
stf rn, MD stf rn, MSA (|U |PF) stf rn, NO Error mode is reset. MSA, MDA, or MD are updated and a
MDA DMA cycle may start. For the stf MD|COPY, a copy loop is
executed.
stf rn,MD|COPY
stf rn, MS NO MS is updated.
ldf rn, MS ldf rn, MSA ldf rn, MDA NO MS, MSA, and MDA could be read in ERROR READ mode
without any side effects (for example, no DMA cycle is
triggered).
ldf rn, MD YES/NO Immediate error if there is no more data available for read in
the FIFO.

When an error is received during a write transfer, the error is reported to the next DMA
access. In this case, an error is sent to the SDMA core and the DMA goes to its error
mode. Reading MS gives the number of bytes that remain in MD; reading MDA gives the
address of the error data. Any attempt to read or write MD, or to modify MDA or MSA in
error mode, give rise to an error; therefore, an error flag must be reset by clearing MS at
the end of the SDMA code section responsible for error management.
Table 7-29. Possibilities in ERROR Mode
DMA Instruction Immediate Error Comments
stf rn, MD stf rn, MSA stf rn, MDA Yes Any attempt to modify MD, MSA, MDA will raise an
immediate error and burst DMA remains in error mode. When
address registers are write-accessed, an error is returned.
stf rn, MS No This is the only way to exit error mode. MS[9:8] must be reset
by an stf MS|SZ0 instruction.
ldf rn, MS ldf rn, MSA ldf rn, MDA No MS, MSA, and MDA could be read in error mode without any
side effects (for example, no DMA cycle is triggered).
ldf rn, MD Yes Whatever the DMA direction (read or write), an ldf rn triggers
an immediate error.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1085
Smart Direct Memory Access Controller (SDMA)

7.2.2.12.1.11 Conditional Yielding-Burst DMA Unit

The standard SDMA transfer is based upon a hardware loop that has the following
structure:
Hardware Loop
loop

load Rn,source // can be ldf or ld

<computation> // can be done through functional units

store Rn,dest // can be st or stf

done 0 // yield

This structure needs to be kept independent of the functional units' particularities

regarding the context switch. However, there can be variations in the context switch's
efficiency, which can depend on the number of data received up to that point, and on the
data itself.
The DMA, with its 8-word burst capability, has a preferable context switch period when
its address register is 8-word aligned: It is the only moment that occurs once every eight
loops when the succession of bursts is not broken by the context switch. When this is not
the case, a context switch requires the storing (or loading) of less than eight words, which
requires separate accesses and is far less efficient. The rest of the 8-word packet is stored
(or loaded) after the context restore, and this is done as separate accesses.
The proposed solution is a conditional yielding, which occurs only when the DMA is in
an optimum state. It does not require any modification to the scripts. The condition is
decided at the DMA level.
The DMA can be programmed in two modes-conditional or always-true-for every
channel, which provides complete flexibility. By default, the DMA is not in conditional
mode.
The DMA condition is computed from the FIFO fill level and the various modes, as
follows:
• When copy mode is selected, regardless of the transfer direction ('read' or 'write'), the
condition is always true.
• In read mode, the condition is always true.
• In write mode, the condition is true when there are four bytes or less in the FIFO; it is
false when there are more than four bytes. The 4-byte limit comes from the
possibility of saving those bytes as MD with absolutely no impact on the bus
accesses.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1086 NXP Semiconductors
 Chapter 7 Interrupts and DMA

The aim at conditional yielding is to avoid splitting bus accesses (especially bursts).

7.2.2.12.2 Peripheral DMA Unit Programming

The peripheral DMA unit is connected to the Multi-Layer DMA Crossbar Switch of the
Arm platform.
Its goal is to perform data transfers between any blocks connected to the DMA bus of this
platform. These blocks are either peripherals or memories. The peripheral DMA could be
seen as the Arm platform DMA controller.
The DMA performs data transfers in three modes:
• Read mode, where data is read from peripherals or from memory connected to the
Arm platform and copied in a SDMA general register.
• Write mode, where data of a general register has to be written in a peripheral or a
memory.
• Copy mode, where data is read from a peripheral (or memory) at a source address
(PSA) and automatically written to a peripheral (or memory) at a destination address
(PDA).
In copy mode, no SDMA general register is involved as transferred data only goes
through the data register of the DMA.
The peripheral DMA has three addressing modes: frozen, incremented, and decremented,
as follows:
• Frozen mode-When source or destination addresses are frozen, their value is not
modified after a transfer. This mode is typically used for addressing peripheral FIFOs
located at a fixed address.
• Incremented mode-When source or destination addresses are in incremented mode,
after every transfer they are incremented by the number of bytes transferred.
• Decremented mode-In decremented mode, addresses are decremented by the number
of bytes transferred.
The peripheral DMA registers are as follows:
• Two, 32-bit address registers (PSA and PDA) that respectively contain the source
address for a read access and the destination address for a write access
• A 32-bit status register (PS) that contains information on the peripheral DMA
configuration, such as the number of valid bytes in the data register, the error flag,
the source and destination address mode, and so on.
• A 32-bit data register (PD) that stores data involved in a data transfer

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1087
Smart Direct Memory Access Controller (SDMA)

7.2.2.12.2.1 Peripheral Source Address Register (PSA)

The source address register contains a pointer to a source peripheral or a memory
associated with the next read data transfer. It has byte granularity.
It is based on the following:
• A 32-bit register (PSA) to store the address value
• A 2-bit register (stype) to store the source address mode (frozen, incremented, or
decremented)
• A 2-bit register (ssize) to store the source target data path size (byte, half-word, or
word)
Reading the register with the ldf instruction has no side effects and gives the address
value of the next data that will be read by the SDMA during an ldf MD instruction.
Writing the source address register may have side effects. If there is valid write data in
the data register and the source address is changed, the write data is discarded. If the
prefetch bit is set, a DMA read cycle is issued with the new address.
When PSA is to be written, you must specify the source target address mode, providing
its size (byte, half-word, or word). This enables omission of the size field in all ldf MD
instructions. When DMA performs a read cycle, its size is given by the value of the PSA
source size register (ssize). If source is a memory in incremented mode, first programmed
in word mode (stf PSA|SZ32|I), and if an SDMA script needs to read bytes from this
memory, the size of the source target must be updated before executing new accesses.
The source address mode and its size are given by labels added to the stf PSA instruction
as described in the write section. The ssize and stype registers are part of the DMA status
register (PS).
Writing to PSA may issue an immediate error if the source size is not compatible with the
value to be written into the PSA register. For instance, writing a 2 in PSA and specifying
that it is memory-accessed in word mode creates an immediate error.

7.2.2.12.2.2 Peripheral Destination Address Register (PDA)

The destination address register contains a pointer to a source peripheral or a memory
associated with the next write data transfer. It has byte granularity.
It is based on the following:
• A 32-bit register (PDA) to store the address value
• A 2-bit register (dtype) to store the destination address mode (frozen, incremented, or
decremented)
• A 2-bit register (dsize) to store the destination target data path size (byte, half-word,
or word)
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
1088 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Reading the register with the ldf instruction has no side effects, and gives the address
value of the next data that will be written by SDMA during an stfMD instruction. Writing
the destination register has no side effect. Similar to the PSA register, the destination
address mode and source are specified in the stf PDA instruction and may also generate
an error in case of incorrect programming.

7.2.2.12.2.3 Peripheral Data Register (PD)

The data register of the peripheral DMA is a 32-bit register. When the destination address
is correctly set up, any writing to PD will automatically flush the new input data.
The number of SDMA bytes that will be transferred is given by the PDA size register.
Unlike other SDMA DMAs, PD is not a FIFO: It is not used to accumulate bytes that
from the SDMA and must be packed before being sent to external memories. In read
mode, and if the source address is correctly set up, an ldf instruction will empty PD. If a
prefetch is required along with the instruction, the DMA will initiate a new read transfer.
Reading PD in prefetch mode only stalls the SDMA when the prefetched data is not yet
available. Writing PD only stalls the SDMA if the previous write operation was not
completed. As soon as the previous operation is over, the acknowledge is sent back to the
SDMA RISC engine.
An error flag-part of PS-is set when an external access fails. The error is thus reported to
the next SDMA instruction that involves the peripheral DMA.

7.2.2.12.2.4 Peripheral State Register (PS)

The state register contains the DMA state-machine value. It can be accessed in case of an
error received during a transfer.
Although all PS fields can be written by an stf instruction, it is recommended to access
only the error bit (to reset it). Modifying other PS fields will provide an un-guaranteed
DMA behavior.
The initialization value of PS is 0, and it consists of the following structure:
Table 7-30. PS Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 ssize stype dsize dtype
W
R 0 0 0 0 0 d e 0 0 0 0 0 n
W

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1089
Smart Direct Memory Access Controller (SDMA)

Table 7-31. PS Field Descriptions

Field Description
31-24 Reserved
23-22 Source Target Size. Determines the size of the read transfers on the external bus. It should
match the accessed device characteristics.
ssize
00 reserved
01 Byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
21-20 Source address Mode. Determines whether PSA is incremented, decremented, or kept
unmodified after every read from the external bus.
stype
00 Frozen Mode
01 Incremented Mode
10 Decremented Mode
11 reserved
19-18 Destination Target Size. Determines the size of the write transfers on the external bus. It should
match the accessed device characteristics.
dsize
00 reserved
01 Byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
17-16 Destination address Mode. Determines whether PDA is incremented, decremented, or kept
unmodified after every write on the external bus.
dtype
00 Frozen Mode
01 Incremented Mode
10 Decremented Mode
11 reserved
15-11 Reserved
10 Direction Flag or DMA Mode. DMA is in write mode when data was written into PD by stf PD
instructions, or if a previous DMA cycle on the external bus was a write access. Writing PDA or
d
PSA does not change the DMA mode.
DMA is in read mode when a previous DMA cycle was a read access, and DMA stays in read
mode when data is read by the SDMA with an ldf PD instruction. Reading PDA or PSA does not
change the DMA mode.
0 Read Mode
1 Write Mode
9-8 Error. Indicates if the previous access was acknowledged with a bus error.
e 00 No error was received.
01 reserved
10 Error mode
11 Error read
7-3 Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1090 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-31. PS Field Descriptions (continued)

Field Description
2-0 number of bytes in PD
n

NOTE
dtype, dsize, stype, and ssize are updated when PSA and PDA
are written.

7.2.2.12.2.5 Peripheral DMA Write (stf)-Write Mode

When written by an stf instruction, the function code bits are interpreted as follows:
Table 7-32. STF Code Bits
Register 7 6 5 4 3 2 1 0
PSA s p ar am sz
PDA
PD pdsel
PS pssel

Table 7-33. STF Code Bits Field Descriptions

Field Description
7-6 Functional Unit selector
s 11 for Peripheral DMA
5 Prefetch Flag
p (PSA) 0 no prefetch
1 automatic prefetch
4 Address Register Selector
ar (PSA/PDA) 0 PSA
1 PDA
3-2 Address Mode. Determines how PSA or PDA is modified after every read or write access to the
PD.
am (PSA/PDA)
00 Frozen-Address registers are not modified after the transfer.
01 Incremented-Address registers are incremented by the number of transferred bytes.
10 Decremented-Address registers are decremented by the number of transferred bytes.
11 Updated-PSA and PDA are not modified. Either address mode is not modified, but the width
of the data path is updated by the sz field.
1-0 Transfer Size
sz 00 reserved
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1091
Smart Direct Memory Access Controller (SDMA)

Table 7-33. STF Code Bits Field Descriptions (continued)

Field Description
01 byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
5-0 PD access selector
pdsel 001000 is the only valid option
5-0 PS access selector
pssel 111111 writes to PS
001100 only clears the error flag in PS

Due to the large number of possible stf instructions, the following table provides only a
short list of all the possible write instructions:
Table 7-34. Peripheral DMA STF Instruction List
Binary Assembly Comments
11_00_00_01 stf Rn, PSA|SZ8 |F • Source is a byte, half-word, or word target at the Rn address. Any
11_00_00_10 further PD read instructions will trigger a byte, half-word, or word
stf Rn, PSA|SZ16|F
11_00_00_11 access to the source.
stf Rn, PSA|SZ32|F • Source address is frozen.
11_10_00_01 stf Rn,PSA|SZ8 |F|PF stf • Source is a byte, half-word, or word target at the Rn address. Any
11_10_00_10 Rn,PSA |SZ16|F|PF further PD read instructions will trigger a byte, half-word, or word
11_10_00_11 access to the source.
stf Rn,PSA |SZ32|F|PF
• 1, 2, or 4 bytes are fetched from the peripheral source.
• Source address is frozen.
11_00_01_01 stf Rn, PSA|SZ8 |I stf Rn, • Source is a byte, half-word, or word target at the Rn address. Any
11_00_01_10 PSA|SZ16|I stf Rn, PSA| further PD read instructions will trigger a byte, half-word, or word
11_00_01_11 SZ32|I access to the source.
• Source address is in incremented mode: PSA = PSA + 1,2 or 4
after read PD.
11_10_01_01 stf Rn, PSA|SZ8 |I|PF stf • Source is a byte, half-word, or word target at the Rn address. Any
11_10_01_10 Rn, PSA|SZ16|I|PF stf Rn, further PD read instructions will trigger a byte, half-word, or word
11_10_01_11 PSA|SZ32|I|PF access to the source.
• Source address is in incremented mode: PSA = PSA + 1, 2, or 4
after read PD.
• 1, 2, or 4 bytes are fetched from the peripheral source.
11_00_10_01 stf Rn, PSA|SZ8 |D • Source is a byte, half-word, or word target at the Rn address. Any
11_00_10_10 further PD read instructions will trigger a byte, half-word, or word
stf Rn, PSA|SZ16|D
11_00_10_11 access to the source.
stf Rn, PSA|SZ32|D • Source address is in incremented mode: PSA = PSA-1,2, or 4 after
read PD.
11_10_10_01 stf Rn, PSA|SZ8 |D|PF • Source is a byte, half-word, or word target at the Rn address. Any
11_10_10_10 further PD read instructions will trigger a byte, half-word, or word
stf Rn, PSA|SZ16|D|PF
11_10_10_11 access to the source.
stf Rn, PSA|SZ32|D|PF • Source address is in incremented mode: PSA = PSA-1,2, or 4 after
read PD.
• 1, 2, or 4 bytes are fetched from the peripheral source.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1092 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-34. Peripheral DMA STF Instruction List (continued)

Binary Assembly Comments
11_00_11_01 stf Rn, PSA|SZ8 |U stf Rn, • Update source pointer to memory, which becomes a pointer to a
11_00_11_10 PSA|SZ16 |U stf Rn, PSA| memory accessed in byte, half-word, or word.
11_00_11_11 SZ32 |U • PSA value is not modified by Rn.
• Bytes present in PD are lost.
11_10_11_01 stf Rn, PSA|SZ8 |PF|U stf • Update source pointer, which becomes a pointer to a target
11_10_11_10 Rn, PSA|SZ16 |PF|U accessed in byte, half-word, or word.
11_10_11_11 • PSA value is not modified by Rn.
stf Rn, PSA|SZ32 |PF|U
• Bytes present in PD are lost.
• 1, 2, or 4 bytes are fetched from the memory source.
11_01_00_01 stf Rn, PDA|SZ8 |F • Destination is a byte, half-word, or word target at the Rn address,
11_01_00_10 and any further PD write instructions will trigger byte, half-word, or
stf Rn, PDA|SZ16|F
11_01_00_11 word access to the destination.
stf Rn, PDA|SZ32|F • Destination address is frozen.
11_01_01_01 stf Rn, PDA|SZ8 |I stf Rn, • Destination is a byte, half-word, or word target at the Rn address,
11_01_01_10 PDA|SZ16|I stf Rn, PDA| and any further PD write instructions will trigger byte, half-word, or
11_01_01_11 SZ32|I word access to the destination.
• Destination address is in incremented mode: PDA = PDA + 1, 2, or
4 after write PD.
11_01_10_01 stf Rn, PDA|SZ8 |D • Destination is a byte, half-word, or word target at the Rn address,
11_01_10_10 and any further PD write instructions will trigger byte, half-word, or
stf Rn, PDA|SZ16|D
11_01_10_11 word access to the destination.
stf Rn, PDA|SZ32|D • Destination address is in incremented mode: PDA = PDA-1, 2, or 4
after write PD.
11_01_11_01 stf Rn, PDA|SZ8 |U stf Rn, • Update destination pointer to memory, which becomes a pointer to
11_01_11_10 PDA|SZ16 |U stf Rn, PDA| a memory accessed in byte, half-word, or word.
11_01_11_11 SZ32 |U • PDA value is not modified by Rn
• bytes present in PD are lost
11_00_10_00 stf Rn, PD • Write "dsize" bytes of Rn in PD and automatically flush to
destination target
11_11_11_11 stf Rn, PS • Write status register
11_00_11_00 stf Rn,clrefPS • Clear error flag if set

NOTE
When writing PD, size information is not important: It is
embedded in the dsize field of PDA register. If dsize is 1, 2, or
4, then one, two, or four bytes from Rn is written to the PD
register, and automatically flushed out to the destination target.

7.2.2.12.2.6 Peripheral DMA Read (ldf)-Read Mode

When received from an ldf instruction, the function code bits are interpreted as follows.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1093
Smart Direct Memory Access Controller (SDMA)

Table 7-35. LDF Code Bits

Register 7 6 5 4 3 2 1 0
PSA s ar a
PDA
PD p cpy
PS pssel

Table 7-36. LDF Code Bits Descriptions

Field Description
7-6 Functional Unit selector
s 11 for Peripheral DMA
5 Prefetch Flag
p (PD) 0 no prefetch
1 automatic prefetch
4 Address Register Selector
ar (PSA/PDA) 0 PSA
1 PDA
4 Copy Mode
cpy (PD) 0 standard access
1 copy mode access
3 Register Set selection
a 0 PSA or PDA
1 PD or PS
5-0 PS access selector
pssel 111111 is the only valid option to read PS

Table 7-37. Peripheral DMA LDF Instruction List

Binary Assembly Comments
11_0_0_0_000 ldf Rn, PSA Reads 32-bit of PSA value
11_0_1_0_000 ldf Rn, PDA Reads 32-bit of PDA value
11_0_0_1_000 ldf Rn, PD Reads programmed source size bytes of PD (0-extended)
11_1_0_1_000 ldf Rn, PD|PF Reads programmed source size bytes of PD (0-extended), and starts a
prefetch at PSA address.
11_0_1_1_000 ldf Rn, PD|COPY Starts a copy transfer from the source target at the PSA address to the
destination target at the PDA address. No data transmits through Rn, but
Rn contents are lost (Rn is loaded with PD temporary contents that are
not the copied data).
11_111111 ldf Rn, PS Reads 32-bit of PS value

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1094 NXP Semiconductors
 Chapter 7 Interrupts and DMA

NOTE
When reading PD, size information is not important: It is
embedded in the ssize field of the PSA register. If ssize is 1, 2,
or 4, the one, two, or four bytes is transferred from PD to Rn.
Read data is 0-extended.

7.2.2.12.2.7 Peripheral DMA Unit Copy Mode

Like burst DMA, the peripheral DMA unit has a copy mode that is used when data
transfers do not involve SDMA general registers.
Data is read from the source target at a PSA address, stored in PD, and then automatically
flushed to the destination target at the PDA address. Copy mode is only available for
transfers that involve two targets of the same data path width.
Since copy mode is invoked with an ldf instruction, the loaded general purpose register
loses its previous contents. (However, the new contents are unpredictable as they depend
on temporary values that are seen on the external DMA bus.)

7.2.2.12.2.8 Error Management

Peripheral DMA generates two kinds of errors: the immediate error that sanctioned
incorrect register programming; and the error triggered by the previous access and stored
in the error flag of PS until a DMA instruction is executed.

7.2.2.12.2.8.1 Immediate Errors

The following table lists all incorrect DMA register setups.
Table 7-38. Immediate Errors with Peripheral DMA
Rn[1:0] values DMA instruction Comments
0x01 stf Rn, PSA|SZ16|F If PSA points to a half-word peripheral or to a half-word
address in memory, its value must be 0 modulo 2.
0x11 stf Rn, PSA|SZ16|I
stf Rn, PDA|SZ16|F
stf Rn, PDA|SZ16|I
0x01 stf Rn, PSA|SZ32|F If PSA points to a word peripheral or to a word address in
memory, its value must be 0 modulo 4.
0x10 stf Rn, PSA|SZ32|I
0x11 stf Rn, PDA|SZ32|F
stf Rn, PDA|SZ32|I
PSA[1:0]-PDA[1:0] DMA instruction Comments

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1095
Smart Direct Memory Access Controller (SDMA)

Table 7-38. Immediate Errors with Peripheral DMA (continued)

Rn[1:0] values DMA instruction Comments
0x01 stf Rn, PSA|SZ32|U stf When PDA or PSA is updated and becomes a pointer to a
Rn, PDA|SZ32|U word address in memory, its content must be 0 modulo 4.
0x10
0x11
0x01 stf Rn, PSA|SZ16|U When PDA or PSA is updated and becomes a pointer to a
half-word address in memory, its content must be 0 modulo
0x11 stf Rn, PDA|SZ16|U
2.
Read/Write PD instruction Comments
stf Rn,PD If PDA size (dsize) has never been set up before an stf PD instruction (dsize=0) If
PSA size (ssize) has never been set up before an ldf PD instruction (ssize=0)
ldf Rn,PD
ldf Rn,PD|CPY Copy mode is possible only between two targets whose data path width is identical.
It is P8↔P8, P16↔P16, or P32↔P32 regardless of the way the address registers are
incremented.

7.2.2.12.2.8.2 Data Transfer Errors

When PSA and PDA are correctly set up, the only error that may arise for an ldf PD or stf
PD instruction would be the error of the previous DMA cycle.
Error handling is driven by a single consideration: When an error occurred during a data
read on the DMA interface, this error should appear as a transfer error to the core when
the core attempts to retrieve the data that was not successfully read from the accessed
device (memory or peripheral).
When an error occurred during a write access to the DMA interface, the data is still
available in PD and should not be destroyed by subsequent core accesses: The core must
be warned about the error issue.
There are three error handling mechanisms for each case: Read Error (First Phase), Write
Error and Read Error (Second Phase), and Copy Mode Errors handling.

7.2.2.12.2.8.3 Read Error (First Phase)

If an error occurred during a prefetch command, the peripheral DMA enters its ERROR
READ mode (PS[9:8]=11). In this mode, the error is reported on the next ldf PD
instruction and writing PSA, PDA, or PD will cancel the error flag.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1096 NXP Semiconductors
 Chapter 7 Interrupts and DMA

The block returns no error mode and instructions are normally executed (a DMA cycle
may be triggered). Similarly, initiating a copy transfer will reset the error flag and start a
copy transfer. The following table details which instructions can be executed in this
mode.
Table 7-39. Possibilities in ERROR READ Mode
DMA Instruction Immediate Error Comments
stf rn, PD stf rn, PSA (|U |PF) stf rn, NO Error mode is reset, PSA or PDA are updated, or a write
PDA cycle is started. For the ldf PD|COPY, a copy loop is
executed.
ldf rn,PD|COPY
stf rn, PS NO PS is updated.
ldf rn, PS ldf rn, PSA ldf rn, PDA NO PS, PSA, and PDA could be read in ERROR READ mode
without any side effects (for example, no DMA cycle is
triggered).
ldf rn, PD YES Error of the previous read access is reported here and the
peripheral DMA enters its ERROR mode.

7.2.2.12.2.8.4 Write Error and Read Error (Second Phase)

The peripheral DMA enters its ERROR mode (PS[9:8]=10) when the previous DMA
write cycle failed, or, as explained in Read Error (First Phase), when an ldf PD is
executed while the block is in ERROR READ mode. When a DMA cycle failed, address
registers (PSA, PDA) are not modified and continue to point to the problematic address.
In ERROR mode, stf instructions may raise an immediate error, and ldf instructions will
not (as detailed in the table below).
Table 7-40. Possibilities in ERROR Mode
DMA Instruction Immediate Error Comments
stf rn, PD stf rn, PSA stf rn, PDA YES Any attempt to modify PD, PSA, or PDA will raise an
immediate error, and the peripheral DMA stays in ERROR
mode. When address registers are write accessed, an error
is returned.
stf rn, PS NO This is the only way to exit the ERROR mode. PS[3] must be
reset by an stf PS instruction.
ldf rn, PS ldf rn, PSA ldf rn, PDA NO PS, PSA, and PDA could be read in ERROR mode without
any side effects (for example, no DMA cycle is triggered).
ldf rn, PD YES Whatever the DMA direction (read or write), an ldf rn, PD
instruction will show an immediate error.

7.2.2.12.2.8.5 Copy Mode Errors

Because copy mode is a write access that follows a read access, there are two possible
cases of bus error.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1097
Smart Direct Memory Access Controller (SDMA)

When the read access incurs a bus error, the peripheral DMA behaves exactly as
described in Read Error (First Phase) and Write Error and Read Error (Second Phase) : It
enters its ERROR READ mode, and so on.
When the error occurred during the write access of the copy transfer, the DMA enables
the core to retrieve the data that was read because it is assumed the read from the
peripheral removed the data from its source device. Therefore, the data to be flushed is
still in PD. Any subsequent access to PD triggers an error to the core, which should
execute its error handling procedure.
Once the ERROR mode is left (after writing to PS), it is possible for the core to retrieve
the data in PD with an ldf instruction or try to flush PD contents once again (for example,
when the error was due to a full FIFO and the script waited for the FIFO to be emptied)
with another ldf instruction in copy mode. This latter instruction detects that there is valid
data in PD, tries to flush it, and thus skips the read phase of the copy instruction. This is a
different behavior from the usual stf PD instruction that overwrites PD with the selected
General Purpose register contents. The same mechanism can be used any time PD holds
data that is not written because of a bus error on the DMA interface; when the data was
written via a copy instruction, or via the usual stf PD instruction.

7.2.2.12.2.8.6 Error Check Example

The following code illustrates an example checking for both immediate and data transfer
errors on a store to the PD register. The first bdf instruction checks for an immediate
error, but if a data transfer error occurred it is reported until the next instruction to access
the Peripheral DMA. A second check of the error flags is done after the ldf PS
instruction. The value of PS here can be ignored. The act of reading any register in
Peripheral DMA while it is in an error mode that returns the error to the core to set either
the SF or DF flag. Any error returned on an ldf command sets the SF flag and any error
returned on an stf instruction sets the DF flag. This can create a situation as shown in the
example where a bus error during a DMA write which would normally be considered as a
destination fault is reported as a source fault because the error was reported to the SDMA
core during an ldf instruction.
Table 7-41. Peripheral DMA Error Check
Function Instruction Comment
clrf 0 Clear SF and DF flags
stf R4, PD Write data to memory
bdf error_routine Check for immediate error from write to
PD.
ldf r3, PS Read PS (PS value in R3 can be
ignored)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1098 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-41. Peripheral DMA Error Check (continued)

Function Instruction Comment
bsf error_routine Check for bus error from "stf R4,PD". SF
is set because it is a ldf instruction, even
though the original error was a
destination fault.

7.2.2.12.2.9 Peripheral DMA Unit Prefetch/Flush Management

There is no flush bit because every time data is stored in PD by a stf PD instruction-
assuming PDA is correctly programmed-it is automatically flushed to the destination.
An acknowledge is returned in the cycle of the DMA instruction, and the SDMA is only
stalled by an instruction that addresses the peripheral DMA when the previous DMA
access is not over.

7.2.2.12.3 OnCE and Real-Time Debug

The On-Chip Emulation block (OnCE) is the debug interface to the SDMA.
It supports the access to all core internal devices (registers, memory, and so on), and
provides a set of mechanisms that control the core. The OnCE is accessed by JTAG ports
at the chip's board level, or by the host via its peripheral bus.
To reduce the size of the hardware material involved, all tasks supported by the OnCE are
performed on the SDMA core. The architecture of the SDMA OnCE is relatively simple
and very flexible.
The commands supported by the SDMA OnCE are listed in the following sections.

7.2.2.12.3.1 Memory and Register Access

A set of mechanisms is provided to access SDMA memory and register locations. Both
reading and writing are allowed. The access is supported if the processor is in debug
mode.
Those registers can also be accessed through the Arm platform Control interface when
the OnCE is controlled by the Arm platform, as described in the "Using BP" section.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1099
Smart Direct Memory Access Controller (SDMA)

7.2.2.12.3.2 Hardware Breakpoints

An event detection unit is implemented to support memory breakpoints. The unit watches
the data exchanged between the SDMA memory bus and the core.
A debug request is sent to the core when matching conditions occur. The unit supports
mixed conditions based on address range, access type, and data value. Event detection
unit configuration registers are memory mapped in the SDMA space (see Arm platform
Channel 0 Pointer (SDMAARM_MC0PTR)): You can modify them through a regular
memory access or the Arm platform control interface.

7.2.2.12.3.3 Watchpoints
One output pin is provided to monitor matching trigger conditions that are defined in the
event detection unit.

7.2.2.12.3.4 Software Breakpoints

The SDMA instruction set contains a software breakpoint. Upon executing a software
breakpoint instruction, the core suspends normal execution and enters debug mode.
No hardware step execution mode is implemented in the OnCE, but this feature may be
implemented at the software level with this instruction.

7.2.2.12.3.5 Core Control

Commands are provided to monitor and control processor activity. You can halt the core,
rerun the core from another address location, and get processor status.
Any hardware breakpoint on the instruction bus is not supported, but this feature may be
implemented by inserting a software breakpoints program.

7.2.2.13 The OnCE Controller

The OnCE controller receives commands from the Arm platform or from the JTAG
controller. Each command is interpreted before being sent to the core.

7.2.2.13.1 OnCE Commands

A small set of commands supports the communication between the OnCE and the
external world.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1100 NXP Semiconductors
 Chapter 7 Interrupts and DMA

This command set enables you to perform any of the following tasks: control processor
activity, save core context, and execute an SDMA instruction from the OnCE. Combined
together, these tasks perform more complex commands.
A full OnCE command contains a 4-bit instruction (the OnCE command opcode) and a
variable length data field (the OnCE data). During command execution, the OnCE data is
transferred in a OnCE internal register before being exchanged with the SDMA. Some
data values are also exported. This mechanism creates a link between the processor and
the external world. Nine commands are defined: The following table presents their
formats.
Table 7-42. OnCE Command Opcode Values
Instruction Name Action Register Data Mode
Opcode Field Size
0000 rstatus Reads the OnCE status register STATUS 16-bit normal/debug
0001 dmov Updates general register GReg1 GREG1 32-bit debug
0010 exec_once Runs the instruction from the SDMA INSTRUCTION 16-bit debug
instruction register
0011 run_core Returns to normal execution BYPASS 1-bit debug
0100 exec_core Returns to normal execution via a jump INSTRUCTION 16-bit debug
instruction that specifies the new address
0101 debug_rqst Stops the core after execution of current BYPASS 1-bit normal
instruction
0110 rbuffer Reads the real time buffer RTB 32-bit normal/debug
0111-1110 reserved Reserved BYPASS 1-bit normal/debug
1111 bypass Bypasses TARM platform controller BYPASS 1-bit normal/debug

Each instruction corresponds to a specific action performed on the OnCE. The nature of
the associated data field is clearly identified. The dmov command is followed by a 32-bit
data value (which is a data value for the SDMA); the exec_once and the exec_core
commands are followed by a 16-bit data value (which is an instruction for the SDMA);
the rstatus command is followed by a 16-bit control value (which is the content of the
OnCE status register); the rbuffer command is followed by a 32-bit data value. The
debug_rqst and the run_core commands are followed by a single bit data field (this is a
bypass value). Finally, the bypass instruction enables the SDMA JTAG TAP controller to
be daisy-chained with another JTAG TAP controller. This is a JTAG-only feature. The
set of commands is simple, but enables you to perform any possible task on the SDMA
during a debug process.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1101
Smart Direct Memory Access Controller (SDMA)

7.2.2.13.2 Sending Commands to the OnCE Controller

The JTAG access is the standard access to the OnCE, but sometimes the JTAG is not
available to fix some bugs (if the chip is in production for instance), an additional access
is then required. Therefore, one Arm platform access to the OnCE is provided.

7.2.2.13.2.1 Using the JTAG Interface

A serial access is performed through the five JTAG pins TCK, TRST, TMS, TDI, and
TDO. A Test Access Port controller is provided to decode the TMS control signal.
It produces shift-enable signals (shift_ir and shift_dr), and updates enable signals
(update_ir and update_dr). It is fully compliant with the IEEE 1149.1 testability (JTAG)
standard.
During the shift_ir state, the command opcode is shifted into the OnCE controller (for
example, the signal from the TDI pin is shifted into the command register and the TDO
pin receives the signal shifted out). After transferring the four bits of the command, an
update_ir signal is asserted and the command is decoded. The target data register is now
clearly identified and the corresponding control signal is produced, as follows: bypass
enable signal (bp_en), instruction enable signal (inst_en), data enable (data_en), and
status enable signal (stat_en).
During the shift_dr state, the TDI signal is shifted into one of the following target
registers: bypass register (1 bit), SDMA instruction register (16 bits), SDMA data register
(32 bits), or OnCE status register (16 bits). The TDO pin is connected to the output of the
selected register to receive the signals shifted out.
The JTAG access is disabled when the Arm platform access is enabled.

7.2.2.13.2.2 Using the Arm platform

The Arm platform access to the OnCE is not the standard access, but it is required if the
JTAG is not available.
For example, if the SDMA ROM is out of use on a chip in production, and the Arm
platform needs to download new code and restart the SDMA, the OnCE can easily
perform this operation. This type of debug operation justifies the use of an Arm platform
access to the OnCE.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1102 NXP Semiconductors
 Chapter 7 Interrupts and DMA

To drive the OnCE, the Arm platform uses some registers contained in the Arm platform
Control block of the SDMA. These registers are accessed through the Arm platform
peripheral bus. Most of these registers are connected to another register in the OnCE
controller. Thus, accessing one of these registers is equivalent to accessing the associated
register in the OnCE controller.
The set of registers in the Arm platform Control block is listed below:
• ONCE_ENB register (1 bit, read/write)-This 1-bit register enables the Arm platform
access to the OnCE. When this bit is set, the signals from the JTAG are ignored.
When it is cleared, all writing operations to the following registers through the Host
Control interface are ignored. This register is reset on a JTAG reset.
• ONCE_CMD register (4 bits, read/write)-This 4-bit register receives the command
opcode. It is connected to the command register in the controller. A write access to
this register causes the associated command to be executed on the OnCE. For
example, after writing "0001" in this register, a dmov command is executed.
NOTE
On the Arm platform side, the rstatus and bypass commands are
not supported. This register is reset on a JTAG reset.
• ONCE_DATA register (32 bits, read/write)-This 32-bit register is connected to the
SDMA data register. This register is used when executing a dmov or rbuffer
command.
NOTE
Before requesting a dmov command, the 32-bit data to transfer
must be written in the ONCE_DATA register. At the end of the
execution, the register is updated with GReg1 former value.
This register is reset on a JTAG reset.
• ONCE_INSTR register (16 bits, read/write)-This 16-bit register is connected to the
SDMA instruction register. This register is used when executing an exec_core or an
exec_once command.
NOTE
Before requesting an exec_core or an exec_once command, the
appropriate instruction must be written in the ONCE_INSTR
register. This register is reset on a JTAG reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1103
Smart Direct Memory Access Controller (SDMA)

• ONCE_STAT register (16 bits, read only)-A read access to the ONCE_STAT
register returns the content of the OnCE status register (OSTAT). This register is
read only.
• The bypass register is not useful when the Arm platform controls the OnCE,
therefore no register is defined in the Arm platform Control block to access the
bypass register.

7.2.2.13.2.3 Conflicts Between the JTAG and the Arm platform Accesses
When Arm platform access to the SDMA OnCE is enabled (that is, when the bit in the
ONCE_ENB register is set), the JTAG access is disabled. This guarantees that the block
is not accessed at the same time on both sides.
It is possible to check whether the JTAG access to the SDMA OnCE is enabled from the
JTAG port. When the JTAG access is disabled, the SDMA TDO always returns 1. The
check requires the following steps:
• Execute a dmov command from debug mode (with neither 0xffffffff nor 0x0 as dmov
value: 0x5a5a5a5a is good).
• Execute another dmov command (the value here is not important).
• The returned value from the latter dmov command should be the original one if the
JTAG access is enabled; if it is 0xffffffff instead of the original input value, this
means the JTAG access is disabled.

7.2.2.13.3 Executing a Command from the OnCE

All the commands defined in OnCE Commands can be accessed through the JTAG. The
Arm platform can access all these commands except the rstatus command.
On the Arm platform side, the OnCE status is directly accessed by reading the
ONCE_STAT register.

7.2.2.13.3.1 Nature of the Commands

Two types of commands may be distinguished. First, there are two commands that do not
interact with the core: rstatus and rbuffer. Those commands may be requested at any
time: They do not depend on the core status.
NOTE
Each of these commands exports a data value or a status value
from the SDMA.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1104 NXP Semiconductors
 Chapter 7 Interrupts and DMA

There are also commands that interact with the core: dmov, run_core, exec_core,
exec_once, and debug_rqst. These commands are core status dependent, as follows:
• During user mode only the debug_rqst is taken into account.
• During debug mode, all these commands are taken into account except the
debug_rqst. For example, an exec_once command requested while not in debug
mode has no effect.

7.2.2.13.3.2 Execution Request

The SDMA starts executing a task in debug mode when requested by the OnCE
controller. The execution starting time depends on the type of access used to
communicate with the OnCE.
If the JTAG is used, the request is send after decoding the update_dr state in the TAP
controller. Therefore, always cross this state when sending a command through the
JTAG. If the OnCE is driven from the Arm platform side, the request is sent after
detecting a write access to the ONCE_CMD register. All the registers involved in this
operation must be loaded first.
The following is an example of an exec_core command execution from the Arm platform
side: After writing '010' in the ONCE_CMD register, the OnCE controller asks the
SDMA to execute the instruction contained in the ONCE_INSTR register. The
instruction involved should be available in the ONCE_INSTR register before the
beginning of the execution.

7.2.2.13.3.3 Command Execution

The following list shows the commands and details how each command is executed:
• rstatus command execution-The rstatus command exports the content of the OnCE
status register (OSR). If the JTAG is used, the status information is captured in the
OnCE status register during the capture_dr state, and shifted out after 16 TCK clock
cycles in the shift_dr state. The rstatus command is not supported on the Arm
platform side, but a status register is provided instead. The rstatus may be performed
in both debug and user modes.
• dmov command execution-The dmov command accesses SDMA internal registers.
Executing a dmov instruction exchanges the 32-bit data values between the SDMA
data register and the general register GReg[1].
• If the JTAG is used, the content of GReg1 is captured in the SDMA data register
during the capture_dr state, then it is shifted out after 32 TCK clock cycles in the
shift_dr state. During the update_dr state, GReg1 is updated with the new, shifted-in

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1105
Smart Direct Memory Access Controller (SDMA)

32-bit data value. If the OnCE is driven from the Arm platform side, the data values
contained in GReg1 and the SDMA data register are exchanged after detecting a
write access to the ONCE_CMD register. The ONCE_DATA register must therefore
be loaded first.
• exec_once command execution-The exec_once command executes the instruction
loaded in the SDMA instruction register. The command may only be requested from
debug mode. The SDMA returns to debug mode at the end of the execution.
• Change of flow instructions as well as instructions that may cause a context switch
are not supported: The comprehensive list comprises done/yield/yiedge (except done
5), BF, BT, BSF, BDF, JMP, JSR, JMPR, JSRR, RET, and LOOP, as well as all the
illegal instructions.
No other command should be requested before the SDMA returns to debug mode.
The SDMA status (for example, whether it is in debug mode or not) can be detected
by polling with the rstatus OnCE command, monitoring the debug_mode pin, or
checking the OnCE Status Register (SDMAARM_ONCE_STAT) register via the
Arm platform control interface.
NOTE
Most of the instructions are single-cycle, which omits the
step of polling the status. Loads and stores to DMA units
are typical instructions that might require this polling.
If the JTAG is used, the 16-bit instruction is shifted in the SDMA instruction register
after 16 TCK clock cycles in the shift_dr state. A request is sent to the core when the
update_dr state is decoded in the TAP controller. If the OnCE is driven from the Arm
platform side, the request is sent to the SDMA when detecting a write access to the
ONCE_CMD register. The ONCE_INSTR register must be therefore be loaded first.
• run_core command execution-The run_core command leaves debug mode and
resume normal program execution. The next instruction executed is the last
instruction decoded before entering debug mode. Be sure to restore core context
before re-running the core. This procedure is detailed in Restoring the Context.
• If the JTAG is used, a 1-bit bypass value is shifted in the bypass register in the
shift_dr state. The SDMA is rerun when the update_dr state is decoded in the TAP
controller. If the OnCE is driven from the Arm platform side, the core is rerun when
detecting a write access to the ONCE_CMD register.
• exec_core command execution-The exec_core command resumes program execution
from any address. The 16-bit instruction provided with the exec_core overwrites the
last instruction decoded before entering debug mode. This command is designed to
support change of flow instructions, so that a program execution can be restarted

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1106 NXP Semiconductors
 Chapter 7 Interrupts and DMA

from any address. After executing an exec_core command, the SDMA leaves debug
mode. The exec_core command is usually used with a jmp instruction.
• If the JTAG is used, the 16-bit branch instruction is shifted in the SDMA instruction
register after 16 TCK clock cycles in the shift_dr state. The SDMA is rerun when the
update_dr state is decoded in the TAP controller. If the OnCE is driven from the Arm
platform side, the SDMA reruns when detecting a write access to the ONCE_CMD
register. The ONCE_INSTR register must therefore be loaded first. For example, to
restart the SDMA from the program address 0x100, the instruction loaded should be
a jump to address 0x100 instruction.
• debug_rqst command execution-The debug_rqst command puts the SDMA in debug
mode. If the JTAG is used, a 1-bit bypass value is shifted in the bypass register
during the shift_dr state. A debug request is sent to the SDMA when the update_dr
state is decoded in the TAP controller. If the OnCE is driven from the Arm platform
side, the debug request is sent when detecting a write access to the ONCE_CMD
register. When the SDMA is already in debug mode, this command is simply
ignored.
• rbuffer command execution-The rbuffer command exports the content of the real
time buffer (RTB). If the JTAG is used, the content of the real time buffer (RTB) is
captured in the SDMA data register during the capture_dr state. The register is
completely shifted out after maintaining the shift_dr state during 32 TCK clock
cycles. If the OnCE is driven from the Arm platform side, the content of the RTB is
captured in the ONCE_DATA register after detecting a write access to the
ONCE_CMD register.
• bypass command execution-This command is only available from the JTAG
interface. It enables daisy-chaining of the SDMA JTAG TAP controller with other
JTAG TAP controllers. This command does not change the SDMA state and can be
executed in any mode (run, debug, or sleep). It selects the bypass register of the TAP
controller.

7.2.2.13.4 Registers Descriptions

See SDMACORE, and SDMAARM, for detailed information on each register.

7.2.2.13.4.1 Event Cell Counter Register (ECOUNT)

The event cell counter register is a 16-bit register that contains the number of times minus
one that an event detection occurs before generating a debug request.
This register should be written before attempting to use the event detection counter
during an event detection process. The event cell counter register is cleared on a JTAG
reset.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 1107
Smart Direct Memory Access Controller (SDMA)

7.2.2.13.4.2 Event Cell Address Registers (EAA or EAB)

The event cell contains two address registers-the event cell address register (a), called
EAA, and the event cell address register (b), called EAB. Every address register is a 16-
bit register that stores a user-defined address value. This value computes one of the
following address conditions: addra_cond or addrb_cond. Every address register is
cleared on a JTAG reset.

7.2.2.13.4.3 Event Cell Address Mask Register (EAM)

The event cell address mask register is a 16-bit register that contains a user-defined
address mask value. This mask is applied to the address value latched from the memory
address bus before comparing addresses.
NOTE
There is a common address mask value for the two address
comparators. If bit i of this register is set, then bit i of the
address value latched from the memory bus does not influence
the result of the address comparison. The event cell address
mask register is cleared on a JTAG reset.

7.2.2.13.4.4 Event Cell Data Register (ED)

The event cell data register is a 32-bit register that contains a user-defined data value.
This data value is an input for the data comparator, which generates the data_cond
condition.
The event cell data register is cleared on a JTAG reset.

7.2.2.13.4.5 Event Cell Data Mask Register (EDM)

The event cell data mask register is a 32-bit register that contains a user-defined data
mask value. This mask is applied to the data value latched from the memory bus before
comparing data.
Setting bit i of the event cell data mask register means that bit i of the data value latched
from the address bus does not influence the result of the data comparison. The event cell
data mask register is cleared on a JTAG reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1108 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.13.4.6 Real Time Buffer Register (RTB)

The real Time Buffer register is a 32-bit register that stores and retrieves run-time
information without putting the SDMA in debug mode.
Refer to Real Time Buffer for more details.

7.2.2.13.4.7 Event Control Register (ECTL)

The event cell control register is a 16-bit register that defines cell event occurrence
conditions.
The event cell control register is cleared on a JTAG reset. See also OnCE Event
Detection Unit for more details.

7.2.2.13.4.8 Trace Buffer (TB)

The Trace Buffer register retrieves the information in the Trace Buffer.
See Trace Buffer for more details.

7.2.2.13.4.9 OnCE Status Register (OSTAT)

The OnCE status register is a 16-bit register that contains processor and event detection
unit status. The OSTAT is a read-only register.
Refer to OnCE Status Register (SDMAARM_ONCE_STAT) for detailed description of
the individual fields in the OSTAT register.
The following figure shows the OSTAT structure.
Table 7-43. OnCE Status Register (OnCE)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PST[3:0] RCV EDR ODR SWB MST ECDR[2:0]

Where PST[3:0] is the SDMA core state, RCV is set when the real-time buffer (RTB) is
modified. EDR, ODR, and SWB are set, respectively, when the SDMA has entered debug
mode because of an external debug request, a OnCE debug_rqst command, or a software
breakpoint. MST is set when the OnCE is controlled from the Arm platform control
interface, and when ECDR is a three-flag set that shows the event cell condition(s) that
put the core in debug mode. The OSTAT never provides more than one reason for
entering debug mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1109
Smart Direct Memory Access Controller (SDMA)

There are two ways of accessing OSTAT content, as follows:

1. Send an rstatus command to the OnCE controller through the JTAG, or read the
ONCE_STAT register through the Arm platform access. Executing the rstatus
command through the JTAG can be performed in both user and debug modes.
2. Perform an SDMA read access to the location in the SDMA core memory map
(OSTAT register) debug mode using the exec_once command. With this method of
access, the SDMA state reflected by the PST (processor status bit) is always DATA.
The register may also be accessed by a running application.

7.2.2.13.5 JTAG Interface Requirements

Because the signals received from the JTAG (running on TCK) are transferred to the
OnCE controller (running on the SDMA clock), a synchronization mechanism is
required.

7.2.2.13.5.1 TCK Speed Limitation

In the JTAG top-level layer, the TDO signal is always captured on a TCK falling edge.
To guarantee a stable TDO signal from the SDMA during this operation, a falling edge
detection is performed on TCK.
Before being latched in the I flip-flop (see Figure 7-11) on TCK falling edge, the TDO
signal must be stable at the input of the flip-flop. This condition is verified if the TCK
period is superior to the following delay:
worst-case edge detection delay + negative-edge signal propagation delay + JTAG top-
level logic propagation delay
The frequency relationship, TCK < CLK/8, limitation guarantees that all operations are
performed as expected.

7.2.2.13.5.2 Synchronization Implementation

The figure found here shows the synchronization mechanism.
Flip-flops tck0, tck1, and tck2 perform falling- and rising-edge detections on TCK. They
generate the posedge_detected and negedge_detected nets that are used to sample the TDI
and TMS inputs into the respective tdi and tms flip-flops, and update the tdo flip-flop to
yield the TDO output. In the design, the only signal that might go metastable is the output
of the tck0 flip-flop. This signal is captured in the tck1 flip-flop and no logical operation
is performed on it to minimize a metastability propagation risk.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1110 NXP Semiconductors
 Chapter 7 Interrupts and DMA

The TDI and TMS flip-flops also cannot go metastable: The propagation time of the
rising-edge detection signal through tck0, tck1, and tck2 guarantees that the TDI and
TMS inputs are stable when captured in the TDI and TMS flip-flops.

'0' tms
'1' tdi TMS/TDI internals
TMS/TDI

posedge_detected

tck0 tck1 tck2 negedge_detected

TCK

tdo '0'
TDO
'1' TDO internal

Figure 7-11. OnCE Synchronization Layer

The following figure shows synchronization timings. It takes three CLK clock cycles to
synchronize TDI on the SDMA clock.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1111
Smart Direct Memory Access Controller (SDMA)

TCK

CLK

posedge_det

TDI

internal TDI

negedge_det

TDO

tdo set-up tdo set-up

Figure 7-12. Synchronization Timings

7.2.2.13.5.3 JTAG Controller Start-Up Recommended Procedure

To ensure correct TAP controller initialization, it is recommended to use the following
procedure:
1. Assert JTAG reset TRSTB (for example, set low).
2. Set TMS low.
3. Wait for 1 TCK clock.
4. Release JTAG reset TRSTB (for example, set high).
5. Wait for a minimum of five TCK cycles.

7.2.2.14 Using the OnCE

This section provides the elements necessary to run the OnCE during a debug process.
In addition to the basic set of commandsdescribed in OnCE Commands, more complex
commands can be built to meet users' requirements.

7.2.2.14.1 Activating Clocks in Debug Mode

For power consumption issues, some clocks in the SDMA are disabled when not needed.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1112 NXP Semiconductors
 Chapter 7 Interrupts and DMA

This is the case for instances when the SDMA is in sleep mode. Clock gating
management depends on the interface used to control the OnCE.
• For the JTAG access, the SDMA clock gating must be turned off via the
clk_gating_off input.
• For the Arm platform access, the SDMA clock gating is automatically turned off
when the Arm platform access is enabled (see OnCE Enable
(SDMAARM_ONCE_ENB)).

7.2.2.14.2 Getting the Current Status

Most of the commands the OnCE supports have an impact on the status of the SDMA.
It is not permissible to request the execution of an instruction on the SDMA from the
OnCE while the SDMA is not in debug mode. Such a violation may cause unpredictable
behavior, and it might be necessary to reset the SDMA.
Therefore, the value of the PST bits provided in the OnCE status register should always
be checked before sending any request to the SDMA.

7.2.2.14.3 Methods of Entering Debug Mode

A debug request may be asserted at any time, but it is not always taken into account
immediately. Debug mode cannot be entered in the middle of an instruction, or during the
save or restore states of a context switch.
The request is ignored when the core is already in debug mode. Refer to Figure 7-4,
which shows all possible transitions to the debug state, as there are several ways to enter
debug mode.

7.2.2.14.3.1 External Debug Request During Reset

To enter debug mode after exiting reset, the external debug line has to be maintained
high. This line is handled by the JTAG top-level block.
NOTE
The SDMA detects the debug requests only if the SDMA clock
is running (see Activating Clocks in Debug Mode). The debug
request line should be not be maintained high when the SDMA
is in debug mode.
NOTE
The debug_rqst command (from the OnCE command set) is not
supported during system reset.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 1113
Smart Direct Memory Access Controller (SDMA)

7.2.2.14.3.2 Debug Request During Normal Activity

During normal activity, the SDMA enters debug mode when the following is true:
1. If the debug request line from the JTAG top-level is asserted, or
2. If the OnCE controller receives a debug_rqst command.
The debug_rqst command can be sent by the JTAG access or by an access on the
Arm platform side (if the Arm platform access is enabled).

7.2.2.14.3.3 Software Breakpoint Instruction

The SDMA enters debug mode at the end of the execution of a software breakpoint
instruction. This instruction must be inserted in program flow executed by the core.

7.2.2.14.3.4 Event Detection Unit Matching Condition

If the event detection is enabled, a debug request is sent to the core after detecting a
matching condition on the SDMA memory bus.
See OnCE Event Detection Unit for more details.

7.2.2.14.4 Executing Instructions in Debug Mode

The OnCE supports a mechanism to execute instructions in debug mode. If the SDMA is
in debug mode, then the exec_once command can be used to execute an SDMA
instruction from the OnCE controller. The SDMA returns to debug mode at the end of
each execution.
Some instructions are not supported by the exec_once command: done/yield/yiedge
(except done 5), BF, BT, BSF, BDF, JMP, JSR, JMPR, JSRR, RET, and LOOP, as well
as all the illegal instructions are not supported.
NOTE
While instructions are executed in debug mode from the OnCE,
the program counter of the SDMA is not incremented.

7.2.2.14.5 Command Sequences Examples

This section provides examples of command sequences that run the SDMA in debug
mode. These sequences are available for both the Arm platform and JTAG accesses.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1114 NXP Semiconductors
 Chapter 7 Interrupts and DMA

The following presents the syntax used in this section. The data field provided with each
command is put in parenthesis with the command name. A '-' is used if the data field
provided is a don't care value.
my_command(data_field); // executing my_command with a data field
my_command(-); // executing my_command with a don't care data field

The value returned by the command (if there is one) is referred by an assignment. In case
the value returned by the command is not used, the assignment is omitted. For an Arm
platform access, the value returned (it is always a data value) is obtained by reading back
into the SDMA data register.
data_out = my_command(data_in); // returning a data value

To clarify the syntax, the instructions' opcodes are referred to by their names. In practice,
use the corresponding 16-bit encoding.

7.2.2.14.5.1 Getting the SDMA Status

NOTE
Before executing any command that affects the SDMA (like
dmov or exec_once), check that the SDMA is in debug mode.
Use the following snippet:
rstatus(); // read SDMA status until the SDMA is in debug mode
...
rstatus();

If the SDMA is not in debug mode, then a debug request must be generated. In this case,
the SDMA enters debug mode at the end of the execution of the current instruction. Use
this snippet:
debug_rqst(-); // debug request

In the following sections, it is assumed that the SDMA was successfully put into debug
mode.

7.2.2.14.5.2 Saving the Context

The first debug task is to save the SDMA context, which is the content of the eight
general-purpose registers, the loop and PC-related registers, and the flags.
Use the general register GReg[1] as an intermediate register to export the entire context
of the SDMA.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1115
Smart Direct Memory Access Controller (SDMA)

The following example shows how to save GReg[0], GReg[1], GReg[2] and GReg[3].
The sequence of commands used to export additional general registers is very similar to
this.
Save GReg[0], GReg[1], GReg[2], and GReg[3]
GReg1_data = dmov(-); // the value exported is the content of
GReg[1]
exec_once("mov GReg1,GReg0"); // puts the content of GReg[0] into
GReg[1]
GReg0_data = dmov(-); // the value exported is the content of
GReg[0]
exec_once("mov GReg1, GReg2"); // puts the content of GReg[2] into
GReg[1]
GReg2_data = dmov(-); // the value exported is the content of
GReg[2]
exec_once("mov GReg1, GReg3"); // puts the content of GReg[3] into
GReg[1]
GReg3_data = dmov(-); // the value exported is the content of
GReg[3]

Get the value of the internal flags (SF, DF, T, and LM), of the loop related registers (EPC
and SPC), and of the PC-related registers (PC and RPC). Use a done 5, which is the
formatting instruction dedicated to the debug. This instruction formats the flags and the
values contained in the registers. It also writes the resulting values into the channel
context memory. It should not be used when entering debug from the IDLE state (for
example, with no active channel script running on the SDMA), because it will update a
channel context that may belong to any channel.
exec_once("done 5"); // formatting the value of flags and registers

At this point, the channel context should be up-to-date in memory, and debug operations
should now be possible. However, the context can be exported with the following
instructions:
Exporting the Context
dmov(ctx_base_addr); // loading GReg[1] with the channel
context base address
exec_once("ld GReg0,(GReg1,0)"); // get RPC-PC into GReg0
exec_once("ld GReg1, (GReg1,1)"); // get SPC-EPC into GReg1
Loop_data = dmov(-); // read back the value of Loop registers
exec_once("mov GReg1, GReg0"); // puts the PC info into GReg1
PC_data = dmov(-); // reads back the content of the PC registers

After this sequence of operations, the entire SDMA context is exported via the OnCE.

7.2.2.14.5.3 Restoring the Context

At this point in the operation, restore the context of the SDMA. It can be different from
the original context located in memory, and the content previously saved into the
debugging application via the OnCE.
The example found hereshows how it is possible to modify the current channel context.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
1116 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Modifying the Current Channel Context

dmov(Loop_data); // put Loop former value into GReg[1]
exec_once("mov GReg0, GReg1"); // copy to GReg[0]
dmov(PC_data); // put PC former value into GReg[1]
exec_once("mov GReg2, GReg1"); // copy to GReg[2]
dmov(ctx_base_addr); // put channel context base address into
GReg[1]
exec_once("st GReg0, (GReg1,1)"); // restore Loop context
exec_once("st GReg2, (GReg1,0)"); // restore PC context

Once the context in memory is the desired context (with or without applying the previous
instruction sequence), it can be restored to the real PC and loop registers in the SDMA
core:
exec_once("cpShReg"); // restore flags and PC & loop related registers

After this command, the SDMA core PC, RPC, SPC, EPC registers, as well as the flags
contain the same data as what is stored in the context RAM for the current channel.
The following example shows how to restore the context of general registers GReg[0],
GReg[1], GReg[2] and GReg[3].
Restoring the General Register Context
dmov(GReg3_data); // put GReg[3] restore value in GReg[1]
exec_once("mov GReg3, GReg1"); // restore GReg[3]
dmov(GReg2_data); // put GReg[2] restore value in GReg[1]
exec_once("mov GReg2, GReg1"); // restore GReg[2]
dmov(GReg0_data); // put GReg[0] restore value in GReg[1]
exec_once("mov GReg0, GReg1"); // restore GReg[0]
dmov(GReg1_data); // restore GReg[1]

At this point, it is possible to restart the normal program execution.

NOTE
Every SDMA core general register value can be modified by a
mov instruction, which makes modification of these registers
easy during debug. Unfortunately, there is no such instruction
as a mov to directly modify the contents of either PCU register
or flag (PC, RPC, SPC, EPC, T, LM, SF, or DF). The cpShReg
instruction is meant to provide a means for changing these
register contents via the context memory.

7.2.2.14.5.4 Accessing the Memory

In the example shown here, it is assumed that the SDMA context is entirely saved. If true,
it is permissible to modify the general purpose registers during debugging activity.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1117
Smart Direct Memory Access Controller (SDMA)

To perform a memory read access, the target address is stored via the OnCE in GReg[1],
then the load instruction is executed on the SDMA (the data loaded from the memory
overwrites the address contained in GReg[1]), and then the result value is read back via
the OnCE.
macro READ: dmov(target_addr); // put the target
address in GReg[1]
exec_once("ld GReg1,(GReg1,0)"); // execute the
load instruction
res_data = dmov(-); // exports the result
data value

For a memory write access, the target address is written in GReg[0], and the value to
store is written in GReg[1]. Then the store instruction is executed on the SDMA.
macro WRITE: dmov(target_addr); // puts the
target address in GReg[1]
exec_once("mov GReg0,GReg1"); // puts the target
address in GReg[0]
dmov(target_data); // puts the target
data in GReg[1]
exec_once("st GReg1,(GReg0,0)"); // performs the
store operation

This sequence is shown as an example; however, many other sequences are possible.
NOTE
This sequence of commands can also be applied to memory-
mapped registers.

7.2.2.14.5.5 Resuming Program Execution

Before resuming program execution, it is assumed that the SDMA context is properly
restored. There are two ways to restart the SDMA.
Start by executing the last instruction fetched before entering debug mode, as follows.
run_core(-); // resume execution from where we stopped before

If necessary, restart the execution from a different address. In this case, use the exec_core
command. The data field provided with this command must be the encoding of a jump
instruction.
exec_core("jmp start_addr"); // rerun the SDMA from another address

In these two examples, the SDMA exits debug mode and keeps executing the code
fetched from the memory.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1118 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.14.5.6 Single Stepping in RAM

To execute a program step-by-step from the RAM, insert software breakpoints in the
program flow at appropriate places so that the SDMA only executes one instruction
before returning to debug mode.
First, read the next instruction to execute in the RAM. Then, depending on the value of
this instruction, compute the address where a software breakpoint instruction should be
inserted. The instruction at the corresponding address must be saved, and, the software
breakpoint instruction is inserted. After restarting the SDMA, there is only one
instruction executed before meeting the software breakpoint.
The following example shows the macro functions READ and WRITE, which correspond
to the sequence of commands (described above) used to access the memory.
NOTE
The data read from the memory are 32-bit values, while the
instructions are 16-bit values only. This is why it is best to only
use addresses divided by two when accessing the memory.
READ and WRITE Macro Functions
next_instr = READ(run_addr/2); // read the next instruction to execute
// the tool now has to compute the address where the breakpoint
// instruction should be inserted, this address is the "bkpt_addr"
instr_save = READ(bkpt_addr/2); // save the instruction before
overwriting
STORE("bkpt instruction",bkpt_addr/2); // store the bkpt instruction
in memory
exec_core("jmp run_addr"); // rerun the SDMA
rstatus(-); // wait for the SDMA to enter debug mode
...
rstatus(-);
STORE(instr_save,bpkt_addr/2); // restore the instruction
overwritten

In case of branched conditional instructions, a breakpoint instruction should be written at

the two possible target addresses.

7.2.2.14.5.7 Single Stepping in ROM

No single-step mechanism is supported in ROM. The program code can be loaded in the
RAM, where the single-step mechanism can be executed.

7.2.2.14.6 OnCE Event Detection Unit

The event detection unit watches signals from the data memory bus (DMBUS), which the
SDMA core uses to access its RAM, ROM, and memory mapped registers.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1119
Smart Direct Memory Access Controller (SDMA)

A debug request is sent to the OnCE controller when user-defined conditions on address
and/or data values are true.

DMBUS Event detect Event event Event dbg_rqst

Detection Cell Detection
Cell Counter Logic

Figure 7-13. Event Detection Unit

A counter, provided with the detection cell, is decreased after an event detection. A
debug request is sent to the core only when the counter reaches the value of 0. It is
possible to disable the use of the counter if a debug request has to be generated after each
event detection.
The event cell is the basic block that supports hardware breakpoints on an address value
and/or data values coming from the SDMA memory bus. The trigger condition that
generates the debug request is a mixed condition based on those values.
The following figure shows the event cell architecture. The event cell contains the
address (stored in the memory address register) and the data (stored in the memory data
register) used during the last memory access. There are some user-defined reference
values located in memory mapped registers-the event cell addresses, the event cell
address mask, the event cell data, and the event cell data mask. These registers are
accessed by standard load/store instructions just like regular memory locations.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1120 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Event Cell Control Register

Event Cell Data Register Data Comparator Memory Data Register

Event Cell Data Mask Register data_cond

Event Cell Address Register (a) Address Comparator (a) Memory Access Type Register

Event Cell Address Mask Register addra_cond

Event Cell Address Register (b) Address Comparator (b) Memory Access Register

addrb_cond

Logic

addr_cond

Logic

event_detect

Figure 7-14. Event Cell Architecture

To define a memory breakpoint, three conditions are taken into account: The first two
conditions are comparisons of the current memory address with user-defined reference
addresses (these conditions are called addressA and addressB). The third condition
consists of a comparison between the data received on the DMBUS and a user-defined
reference data (this condition is called data). An intermediate address condition is set to
express a dependency between addressA and addressB conditions.

7.2.2.14.7 Clock Gating and Reset

This section details how to use the clocks and handle the reset signals.

7.2.2.14.7.1 Clocks
Because the SDMA uses clock gating to save power, it is necessary to disable the clock
gating and force the clocks to be enabled when using the OnCE.
When the OnCE is accessed through its JTAG interface, clock gating must be disabled
outside the SDMA via a dedicated SDMA input port clk_gating_off. The reason why
detection is not performed automatically by the SDMA internal hardware is that it would
cost power to monitor activity on the JTAG interface.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1121
Smart Direct Memory Access Controller (SDMA)

When the OnCE is accessed through the Arm platform Control interface, clock gating is
automatically turned off. This is done when bit 0 of the ONCE_ENB register (see OnCE
Enable (SDMAARM_ONCE_ENB)) is set. A write access to this register is possible
even when the OnCE clock is not running. If the Arm platform access is used, the bit in
the ONCE_ENB register must be set before any attempt to access any other OnCE
register.

7.2.2.14.7.2 Resets
The OnCE reset is different from the SDMA main reset.
Normally, activating the SDMA reset while keeping the OnCE reset inactive (when
possible) enables you to reset the core without having to reprogram the OnCE.

7.2.2.14.8 Real Time Features

To rebuild the skeleton of a program execution, it is necessary to store the addresses of
the program instructions where jumps are taken: A trace buffer is therefore provided. A
real time buffer has also been added to receive data values written during a program
execution.
The content of this register may be exported through JTAG ports without stopping the
core.

7.2.2.14.8.1 Trace Buffer

The Trace Buffer is a 32-stage buffer that contains appropriate information to identify the
32 last changes of flow detected during a program execution.
The following figure shows an overview of the Trace Buffer.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1122 NXP Semiconductors
 Chapter 7 Interrupts and DMA

input change of flow addresses

Trace buffer cell #0

Trace buffer cell #1

shift
...

Trace buffer cell #30

Trace buffer cell #31

output change of flow addresses

Figure 7-15. Trace Buffer

Each cell of the trace buffer contains two reference addresses and a flag. The flag is set
when the addresses stored in the cell correspond to a valid change of flow; otherwise, the
flag is cleared. The three most significant bits are unused.
After every change of flow detection, the address of current instruction and the address of
the target instruction are stored at the top of the Trace Buffer (cell #0). The flag in the
cell is set to indicate that a valid change of flow was detected. Former cell values are
shifted one level down. The Trace Buffer contains the 32 last changes of flow. All the
flags are reset on a software or a hardware reset, and after each transition from debug
mode to user mode.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1123
Smart Direct Memory Access Controller (SDMA)

A memory mapped register of SDMA core, the Trace Buffer register (TB), is provided to
read the content of the Trace Buffer. This operation should be done in debug mode.
Performing a read access to the Trace Buffer register returns the content of the bottom of
the Trace Buffer (cell #31). After every read access, the trace buffer is shifted one level
down, and the flag at the top of the trace buffer is cleared.
A typical OnCE command sequence that retrieves the oldest change-of-flow information
is a follows:
exec_once("mov r1, TB"); // stores the oldest change-of-flow in
GReg1
dmov(-); // retrieves GReg1 contents

This sequence requires the SDMA to be put in debug mode.

7.2.2.14.8.2 Real Time Buffer

The Real Time Buffer register (RTB) is a memory mapped register that can be accessed
as a regular memory location by the SDMA core during program execution. This register
is located in the OnCE.
Executing ar rbuffer command (see The OnCE Controller for further details) exports the
content of this register through JTAG ports.
When a write access is performed at the memory location corresponding to the RTB, the
receive flag (for example, the RCV bit) is set in the OnCE Status Register (OSR). This
flag is cleared at the end of the execution of a rbuffer command.
NOTE
Every write access to the RTB memory location updates the
RTB register even if the RCV flag is set. The RTB is cleared on
a JTAG reset.

7.2.2.14.8.3 Emulation Pin

The debug_matched_event emulation pin reflects the matching condition status detected
by the Event Detection Unit.
Since it can be necessary to detect conditions without triggering debug requests, it is
possible to disable the generation of debug requests by the Event Detection Unit and still
have the matching condition available on the emulation pin. This can be done by clearing
the EN flag in the ECTL register.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1124 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.2.14.8.4 Real-Time Debug Outputs

The table found here shows the debug signals that are available at the SDMA boundaries.
Their availability at chip boundaries depends on the project.
Table 7-44. Real-Time Debug Output Pins
Pin Description
debug_core_state[3:0] The core_state bits reflect the state of the SDMA core.
• The "Program" state is the usual instruction execution cycle.
• The "Data" state is inserted when there are wait-states during a load or a store on the
data bus (ld or st).
• The "Change of Flow" state is the second cycle of any instruction that breaks the
sequence of instructions (jumps and channel switching instructions).
• The "Change of Flow in Loop" state is used when an error causes a hardware loop exit.
• The "Debug" state means the SDMA is in debug mode.
• The "Functional Unit" state is inserted when there are wait-states during a load or a
store on the functional units bus (ldf or stf).
• In "Sleep" modes, no script is running (this is the core idle state); the "after Reset" is
slightly different because no context restoring phase will happen when a channel is
triggered: The script located at address 0 is executed (boot operation).
• The "in Sleep" states are the same as above except they do not have any
corresponding channel: they are used when entering debug mode after reset; the
reason is that it is necessary to return to the "Sleep after Reset" state when leaving
debug mode.

0 Program
1 Data
2 Change of Flow
3 Change of Flow in Loop
4 Debug
5 Functional Unit
6 Sleep
7 Context Switch Saving Channel
8 Program in Sleep
9 Data in Sleep
10 Change of Flow in Sleep
11 Change of Flow in Loop in Sleep
12 Debug in Sleep
13 Functional Unit in Sleep
14 Sleep after Reset
15 Context Switch Restoring Channel
debug_yield Pulse that is active when a yield (done 0) or a yieldge (done 1) instruction is executed.
0-
1 yield/yieldge executed
debug_core_run Active when the SDMA core is executing instructions.
0 Debug or sleep mode
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1125
Smart Direct Memory Access Controller (SDMA)

Table 7-44. Real-Time Debug Output Pins (continued)

Pin Description
1 Run mode
debug_event_channel_sel Indicates if debug_event_channel displays current channel or last received event
0- debug_event_channel[5:0] gives the number of the current channel
1- debug_event_channel[5:0] gives the number of the last received event
debug_event_channel[5:0] Gives the number of any DMA request as soon as it is received or the number of the current
channel.
The value of debug_event_channel_sel indicates if debug_event_channel displays the
current channel or last received event. The signal debug_event_channel_sel must be
observed to determine what information is provided on debug_event_chanel at any given
time.

debug_pc[13:0] Program Counter value; it has a meaning when the core is in run mode.
debug_mode Set when the core is in debug.
0-
1 Core is in debug
debug_bus_error Set when an error was received during a load or a store (ld, st, ldf, or stf instruction) and
registered in SF or DF flag.
0 No error during last load/store
1 Error during last load/store
debug_bus_device[4:0] Indicates the device or functional unit that is accessed by the current instruction. The
debug_bus_device output is always valid when in sleep mode, debug mode, or executing any
instruction that does not access the functional units or the memory mapped devices, "no
access" is output.
0 No access
1 MSA
2 MDA
3 MD
4 MS
5 PSA
6 PDA
7 PD
8 PS
9 RESERVED
10 RESERVED
11 RESERVED
12 RESERVED
13 CA
14 CS
15 Reserved
16 Memory (RAM or ROM)
17 Memory mapped register
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1126 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-44. Real-Time Debug Output Pins (continued)

Pin Description
18 Peripheral #1
19 Peripheral #2
20 Peripheral #3
21 Peripheral #4
22 Peripheral #5
23 Peripheral #6
24 Peripheral #7
25 Peripheral #8
26 Peripheral #9
27 Peripheral #10
28 Peripheral #11
29 Peripheral #12
30 Peripheral #13
31 Peripheral #14
debug_bus_rwb Indicates the direction of the access given by debug_bus_device
0 Write access (st or stf)
1 Read access (ld or ldf)
debug_matched_dmbus Pulse indicating the OnCE event detection unit has detected a match on the data bus during
an access to memory (RAM or ROM), a memory mapped register or a peripheral that is
hooked to the SDMA.
0-
1 data bus match detected
debug_rtbuffer_write Pulse indicating when the real-time buffer is written by the core.
0-
1 RTB was modified
debug_evt_chn_lines[7:0] Eight lines that generate short pulses when DMA requests are received or channels are
(re)started. Every line is controlled through two parameters defined in registers Cross-Trigger
Events Configuration Register 1 (SDMAARM_XTRIG_CONF1) (as described in SDMAARM).
The following two parameters are available for every line:
• CNF-Indicates what is monitored on the line: 0 for a channel start, 1 for a DMA request
reception
• NUM[ 5:0]-Gives the number of the DMA request or channel to monitor

The matched_event emulation pin reflects the matching condition status detected by the
Event Detection Unit. Because it can be necessary to detect conditions without triggering
debug requests, it is possible to disable the generation of debug requests by the Event
Detection Unit and still have the matching condition available on the emulation pin. This
can be done by clearing the EN flag in the ECTL register.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1127
Smart Direct Memory Access Controller (SDMA)

All real-time debug outputs are disabled by default (for example, they are stuck to 0) to
avoid power consumption when they are not used. They are enabled when bit 11
(RTDOBS) of the Configuration Register (SDMAARM_CONFIG) is set. Signals
provided to the system JTAG controller for SDMA debug mode status will also be
enabled when the clk_gating_off input is asserted.

7.2.3 Instruction Set

7.2.3.1 Instruction Encoding

This section presents a short summary of the instruction codes. All context switch
instructions are listed for information only; they cannot function properly out of the
context switch routine.

x...x - don't care

rrr - destination/source general register

sss - additional source general register

bbb - general register used as address base register

ddddd - address displacement

nnnnn - bit number

uuuuuuuu - function unit command bits

pppppppp - branch displacement (signed)

iiiiiiii - 8-bit immediate

jjj - control bit to clear

ff - flag to clear
00000jjj00000000 - done (done,yield,wait)
00000jjj00000001 - notify
00000xxx00000010 - reserved
00000xxx00000011 - reserved
00000xxx00000100 - reserved
0000000000000101 - softBkpt
0000000100000101 - reserved
0000001000000101 - reserved
0000001100000101 - reserved
0000010000000101 - reserved
0000010100000101 - reserved
0000011000000101 - reserved
0000011100000101 - reserved
0000000000000110 - ret
0000000100000110 - reserved
0000001000000110 - reserved
0000001100000110 - reserved
0000010000000110 - reserved
0000010100000110 - reserved
0000011000000110 - reserved
0000011100000110 - reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1128 NXP Semiconductors
 Chapter 7 Interrupts and DMA
000000ff00000111 - clrf ff
0000010000000111 - reserved
0000010100000111 - reserved
0000011000000111 - reserved
0000011100000111 - illegal
00000rrr00001000 - jmpr r
00000rrr00001001 - jsrr
00000rrr00001010 - ldrpc r
00000rrr00001011 - reserved
00000rrr000011xx - reserved
00000rrr00010000 - revb
00000rrr00010001 - revblo
00000rrr00010010 - rorb
00000rrr00010011 - reserved
00000rrr00010100 - ror1
00000rrr00010101 - lsr1
00000rrr00010110 - asr1
00000rrr00010111 - lsl1
00000rrr001nnnnn - bclri r,n
00000rrr010nnnnn - bseti r,n
00000rrr011nnnnn - btsti r,n
00000xxx10000xxx - reserved
00000rrr10001sss - mov
00000rrr10010sss - xor
00000rrr10011sss - add
00000rrr10100sss - sub
00000rrr10101sss - or
00000rrr10110sss - andn
00000rrr10111sss - and
00000rrr11000sss - tst
00000rrr11001sss - cmpeq
00000rrr11010sss - cmplt
00000rrr11011sss - cmphs
0000011011100000 - reserved
0000011011100001 - reserved
0000011011100010 - cpShReg
0000011011100011 - reserved
0000011011100100 - reserved
0000011011100101 - reserved
0000011011100110 - reserved
0000011011100111 - reserved
00000xxx11101xxx - reserved
00000xxx11110xxx - reserved
00000xxx11111xxx - reserved
00001rrriiiiiiii - ldi r,i
00010rrriiiiiiii - xori r,i
00011rrriiiiiiii - addi r,i
00100rrriiiiiiii - subi r,i
00101rrriiiiiiii - ori r,i
00110rrriiiiiiii - andni r,i
00111rrriiiiiiii - andi r,i
01000rrriiiiiiii - tsti r,i
01001rrriiiiiiii - cmpeqi r,i
01010rrrdddddbbb - ld r,(d,b)
01011rrrdddddbbb - st r,u
01100rrruuuuuuuu - ldf r,u
01101rrruuuuuuuu - stf r,u
011100xxxxxxxxxx - reserved
011101xxxxxxxxxx - reserved
011110ffnnnnnnnn - Loop ff flags are reset
01111100pppppppp - bf pc=pc+signed(pppppppp)+1
01111101pppppppp - bt pc=pc+signed(pppppppp)+1
01111110pppppppp - bsf pc=pc+signed(pppppppp)+1
01111111pppppppp - bdf pc=pc+signed(pppppppp)+1
10aaaaaaaaaaaaaa - jmp absolute
11aaaaaaaaaaaaaa - jsr absolute

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1129
Smart Direct Memory Access Controller (SDMA)

7.2.3.2 SDMA Instruction Set

This section describes all the useful instructions from the SDMA set.
Table 7-45. SDMA Instruction List
Instruction Description Page
ADD Addition ADD (Addition)
ADDI Add with Immediate Value ADDI (Add with Immediate Value)
AND Logical AND AND (Logical AND)
ANDI Logical AND with Immediate Value ANDI (Logical AND with Immediate
Value)
ANDN Logical AND NOT ANDN (Logical AND NOT)
ANDNI Logical AND with Negated Immediate ANDNI (Logical AND with Negated
Value Immediate Value)
ASR1 Arithmetic Shift Right by 1 Bit ASR1 (Arithmetic Shift Right by 1 Bit)
BCLRI Bit Clear Immediate BCLRI1 (Bit Clear Immediate)
BDF Conditional Branch if Destination Fault BDF (Conditional Branch if Destination
Fault)
BF Conditional Branch if False Functional Units Programming Model
BSETI Bit Set Immediate BSETI (Bit Set Immediate)
BSF Conditional Branch if Source Fault BSF (Conditional Branch if Source Fault)
BT Conditional Branch if True BT (Conditional Branch if True)
BTSTI Bit Test immediate BTSTI (Bit Test immediate)
CLRF Clear Arm platform flags CLRF (Clear Arm platform flags)
CMPEQ Compare for Equal CMPEQ (Compare for Equal)
CMPEQI Compare with Immediate for Equal CMPEQI (Compare with Immediate for
Equal)
CMPHS Compare for Higher or Same CMPHS (Compare for Higher or Same)
CMPLT Compare for Less Than CMPLT (Compare for Less Than)
cpShReg Update Context of PCU Registers and cpShReg (Update Context of PCU
Flags Registers and Flag)
DONE DONE, Yield DONE (DONE, Yield)
ILLEGAL ILLEGAL Instruction ILLEGAL (ILLEGAL Instruction)
JMP Unconditional Jump Immediate JMP (Unconditional Jump Immediate)
JMPR Unconditional Jump JMPR (Unconditional Jump)
JSR Unconditional Jump to Subroutine JSR (Unconditional Jump to Subroutine
Immediate Immediate)
JSRR Unconditional Jump to Subroutine JSRR (Unconditional Jump to
Subroutine)
LD Load Register LD (Load Register)
LDF Load Register from Functional Unit LDF (Load Register from Functional
Unit)
LDI Load Register with Immediate Value LDI (Load Register with Immediate
Value)
LDRPC Load from RPC to Register LDRPC (Load from RPC to Register)

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1130 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Table 7-45. SDMA Instruction List

(continued)
Instruction Description Page
LOOP Hardware Loop LOOP (Hardware Loop)
LSL1 Logical Shift Left by 1 Bit LSL1 (Logical Shift Left by 1 Bit)
LSR1 Logical Shift Right by 1 Bit LSR1 (Logical Shift Right by 1 Bit)
MOV Logical Move MOV (Logical Move)
NOTIFY Notify to Arm platform NOTIFY (Notify to Arm platform)
OR Logical OR OR (Logical OR)
ORI Logical OR with Immediate Value ORI (Logical OR with Immediate Value)
RET Return from Subroutine RET (Return from Subroutine)
REVB Reverse Byte Order REVB (Reverse Byte Order)
REVBLO Reverse Low Order Bytes Reverse Low Order Bytes(REVBLO)
ROR1 Rotate Right by 1 Bit ROR1 (Rotate Right by 1 Bit)
RORB Rotate Right by 1 Byte RORB (Rotate Right by 1 Byte)
SOFTBKPT Software Breakpoint SOFTBKPT (Software Breakpoint)
ST Store Register ST (Store Register)
STF Store Register in Functional Unit STF (Store Register in Functional Unit)
SUB Subtract SUB (Subtract)
SUBI Subtract with Immediate SUBI (Subtract with Immediate)
TST Test with Zero TST (Test with Zero)
TSTI Test Immediate TSTI (Test Immediate)
XOR Logical Exclusive OR XOR (Logical Exclusive OR)
XORI Exclusive OR with Immediate XORI (Exclusive OR with Immediate)

7.2.3.2.1 ADD (Addition)

Operation:
GReg[r] ← GReg[s] + GReg[r]

T ← (GReg[r] == 0)

Assembler:
Syntax: add r,s

Example: add 0,3

ADD GReg[3] and GReg[0] and store the result in GReg[0]

CPU Flags: T
Cycles: 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1131
Smart Direct Memory Access Controller (SDMA)

Description: Performs the ADDition of the source general register s and the destination
general register r, and stores the result in the destination general register r. The T flag is
set if the result of the operation is 0. It is cleared if the result is not 0.
Instruction Format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 0 1 1 s s s

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.2 ADDI (Add with Immediate Value)

Operation:
GReg[r] ← GReg[r] + immediate

T ← (GReg[r] == 0)

Assembler:
Syntax: addi r,immediate

Example: add 6,112

ADD GReg[6] and decimal value 112 and store the result in GReg[6]
CPU Flags: T
Cycles: 1
Description: Adds a 0-extended immediate value to a general register; stores the result in
the general register. The flag T is set when the result of the operation is 0; otherwise, it is
cleared. The immediate value is the low-order byte of the instruction and has a maximum
value of 255 (0xFF).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1132 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 r r r i i i i i i i i

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.3 AND (Logical AND)

Operation:
GReg[r] ← GReg[s] & GReg[r]

Assembler:
Syntax: and r,s

Example: and 1,2

AND GReg[1] and GReg[2] and store the result in GReg[1]

CPU Flags: Unaffected
Cycles: 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1133
Smart Direct Memory Access Controller (SDMA)

Description: Performs the AND of the source general register s and the destination
general register r, and stores the result in the destination general register r.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 1 1 s s s

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.4 ANDI (Logical AND with Immediate Value)

Operation:
GReg[r] ← GReg[r] & immediate

Assembler:
Syntax: andi r,immediate

Example: andi 7,45

AND GReg[7] and decimal value 45 and store the result in GReg[7]
CPU Flags: unaffected
Cycles: 1
Description: Performs an AND between a 0-extended immediate value and a general
register; stores the result in the general register. The immediate value is the low-order
byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 1 r r r i i i i i i i i

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1134 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.5 ANDN (Logical AND NOT)

Operation:
GReg[r] ← ~GReg[s] & GReg[r]

Assembler:
Syntax:andn r,s

Example: andn 3,4

AND GReg[3] and NOT GReg[4] (bit inverted) and store the result in GReg[3]
CPU Flags: Unaffected
Cycles: 1
Description: Performs the AND of the negation of the source general register s and the
destination general register r, and stores the result in the destination general register r.
Instruction Format:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1135
Smart Direct Memory Access Controller (SDMA)

Table 7-46. Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 1 0 s s s

Instruction Fields:
rrr /sss - destination register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.6 ANDNI (Logical AND with Negated Immediate Value)

Operation:
GReg[r] ← GReg[r] & ~immediate

Assembler:
Syntax: andni r,immediate

Example: andni 0,2

AND GReg[0] and decimal value -3 (inverted 32-bit value 2) and store the result in
GReg[0]
CPU Flags: unaffected
Cycles: 1
Description: Performs an AND between the negation of a 0-extended 8-bit immediate
value and a general register; stores the result in the general register. The immediate value
is the low-order byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0 r r r i i i i i i i i

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1136 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.7 ASR1 (Arithmetic Shift Right by 1 Bit)

Operation:
GReg[r]:{b31,b30,...,b1,b0} ← GReg[r]:{b31,b31,b30,...,b1}

Assembler:
Syntax: asr1 r

Example: asr1 3

divide by 2 the signed value of GReg[3] and store the result in GReg[3]
CPU Flags: Unaffected
Cycles: 1
Description: Shift the bits of any general register to the right and keep the same sign: The
left bit (bit 31) is kept untouched.
Instruction Format:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1137
Smart Direct Memory Access Controller (SDMA)

Table 7-47. Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 1 0

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.8 BCLRI1 (Bit Clear Immediate)

Operation:
GReg[r]:{b31,...,b(i+1),0,b(i-1),...,b0} ← GReg[r]:{b31,...,b(i+1),b(i),b(i-1),...,b0}

Assembler:
Syntax: bclri r,i

Example: bclri 1,12

clear bit 12 in GReg[1]

CPU Flags: Unaffected
Cycles: 1
Description: Clear the bit of register r specified by the 5-bit immediate field
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 1 i i i i i

rrr - register field:

000 - GReg[0]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1138 NXP Semiconductors
 Chapter 7 Interrupts and DMA
001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiii - immediate value:

00000 - 0

00001 - 1

...

11110 - 30

11111 - 31

7.2.3.2.9 BDF (Conditional Branch if Destination Fault)

Operation:
if (DF == 1) PC ← PC + 1 + displacement else PC ← PC + 1

Assembler:
Syntax:bdf label

Example: bdf LLL

Jump to LLL if DF is set, or go to the next instruction if DF is cleared; the displacement

value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: If flag DF is set, jump to the new address that is calculated by adding the
sign-extended 8-bit displacement to the next PC address. If flag DF is cleared, no jump is
performed: The next instruction is located at the next PC address.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 p p p p p p p p

Instruction Fields:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1139
Smart Direct Memory Access Controller (SDMA)

pppppppp - signed displacement field:

00000000 - 0

00000001 - 1

...

01111110 - 126

01111111 - 127

10000000 - (-128)

10000001 - (-127)

...

11111110 - (-2)

11111111 - (-1)

7.2.3.2.10 BF (Conditional Branch if False)

Operation:
if (T == 0)

PC ← PC + 1 + displacement

else

PC ← PC + 1

Assembler:
Syntax: bf label

Example: bf LLL

Jump to LLL if T is cleared, or go to the next instruction if T is set. The displacement

value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: Conditional branch: If flag T is cleared, jump to the new address that is
calculated by adding the sign-extended 8-bit displacement to the next PC address. If flag
T is set, no jump is performed: The next instruction is located at the next PC address.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 0 0 p p p p p p p p

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1140 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Instruction Fields:
pppppppp - signed displacement field:
00000000 - 0

00000001 - 1

...

01111110 - 126

01111111 - 127

10000000 - (-128)

10000001 - (-127)

...

11111110 - (-2)

11111111 - (-1)

7.2.3.2.11 BSETI (Bit Set Immediate)

Operation:
GReg[r]:{b31,...,b(i+1),1,b(i-1),...,b0} ← GReg[r]:{b31,...,b(i+1),b(i),b(i-1),...,b0}

Assembler:
Syntax: bseti r,i

Example: bseti 6,5

Set bit 5 in GReg[6]

CPU Flags: Unaffected
Cycles: 1
Description: Sets bit number i in the selected General Register.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 1 0 i i i i i

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1141
Smart Direct Memory Access Controller (SDMA)
010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiii - bit number field:

00000 - 0

00001 - 1

...

11110 - 30

11111 - 31

7.2.3.2.12 BSF (Conditional Branch if Source Fault)

Operation:
if (SF == 1) PC ← PC + 1 + displacement else PC ← PC + 1

Assembler:
Syntax: bsf label

Example: bsf LLL

Jump to LLL if SF is set, or go to the next instruction if SF is cleared. The displacement

value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: Conditional branch: If flag SF is set, jump to the new address that is
calculated by adding the sign-extended 8-bit displacement to the next PC address. If flag
SF is cleared, no jump is performed: The next instruction is located at the next PC
address.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 0 p p p p p p p p

Instruction Fields:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1142 NXP Semiconductors
 Chapter 7 Interrupts and DMA

pppppppp - signed displacement field:

00000000 - 0

00000001 - 1

...

01111110 - 126

01111111 - 127

10000000 - (-128)

10000001 - (-127)

...

11111110 - (-2)

11111111 - (-1)

7.2.3.2.13 BT (Conditional Branch if True)

Operation
if (T == 1)

PC ← PC + 1 + displacement

else

PC ← PC + 1

Assembler
Syntax: bt label

bt LLL

Jump to LLL if T is set, or go to the next instruction if T is cleared. The displacement

value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: Conditional branch: If flag T is set, jump to the new address that is
calculated by adding the sign-extended 8-bit displacement to the next PC address. If flag
T is cleared, no jump is performed: The next instruction is located at the next PC address.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 0 1 p p p p p p p p

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1143
Smart Direct Memory Access Controller (SDMA)

pppppppp - signed displacement field:

00000000 - 0

00000001 - 1

...

01111110- 126

01111111 - 127

10000000 - (-128)

10000001 - (-127)

...

11111110 - (-2)

11111111 - (-1)

7.2.3.2.14 BTSTI (Bit Test immediate)

Operation:
T ← GReg[r]:b(i)

Assembler:
Syntax: btsti r,i

Example: btsti 2,29

Test bit 29 in GReg[2] and copy its value in flag T

CPU flags: T
Cycles: 1
Description: T is loaded with the value of bit number i from the selected general register.
Instruction Format:
Table 7-48. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 1 1 i i i i i

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1144 NXP Semiconductors
 Chapter 7 Interrupts and DMA
010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiii - bit number field:

0000 - 0

0001 - 1

...

11110 - 30

11111 - 31

7.2.3.2.15 CLRF (Clear Arm platform flags)

Operation:
if (ff%2 == 0)

SF ← 0

if (ff/2 == 0)

DF ← 0

Assembler:
Syntax: clrf ff

Example: clrf 2

Clear flag SF and keep flag DF unchanged

CPU Flags: SF, DF
Cycles: 1
Description: Clears a selection of the Arm platform fault flags: SF, DF, both SF and DF
or none can be cleared.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 f f 0 0 0 0 0 1 1 1

Instruction Fields:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1145
Smart Direct Memory Access Controller (SDMA)

ff - flags field:
00 - clear SF and clear DF

01 - clear DF

10 - clear

SF 11 - no clear

7.2.3.2.16 CMPEQ (Compare for Equal)

Operation:
T ← (GReg[s] == GReg[r])

Assembler:
Syntax: cmpeq r,s

Example: cmpeq 7,5

Compare GReg[7] and GReg[5] and set flag T if they are equal
CPU flags: T
Cycles: 1
Description: Subtracts the destination general register r from the source general register s,
and sets T if the result is 0, clears T if the result is not 0.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 0 1 s s s

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1146 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.3.2.17 CMPEQI (Compare with Immediate for Equal)

Operation:
T ← (GReg[r] == immediate)

Assembler:
Syntax: cmpeqi r,immediate

Example: cmpeqi 2,13

Compare GReg[2] and decimal value 13 and set flag T if they are equal
CPU Flags: T
Cycles: 1
Description: Subtracts the 0-extended 8-bit immediate value from the general register,
and sets T if the result is 0, clears T if the result is not 0. The immediate value is the low-
order byte of the instruction.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 1 r r r i i i i i i i i

Instruction Fields:
rrr - destination register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1147
Smart Direct Memory Access Controller (SDMA)
11111111 - 255

7.2.3.2.18 CMPHS (Compare for Higher or Same)

Operation:
T ← (GReg[r] ≥ GReg[s])

Assembler:
Syntax: cmphs r,s

Example: cmphs 0,1

Compare GReg[0] and GReg[1] and set flag T if GReg[0] is higher than or equal to
GReg[1]
CPU Flags: T
Cycles: 1
Description: Compares the destination general register r and the source general register s,
and sets T if the destination general register r is higher than or equal to the source general
register s, clears T otherwise. The comparison is unsigned.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 1 1 s s s

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.19 CMPLT (Compare for Less Than)

Operation:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1148 NXP Semiconductors
 Chapter 7 Interrupts and DMA
T ← (GReg[r] < GReg[s])

Assembler:
Syntax: cmplt r,s

Example: cmplt 7,4

Compare GReg[7] and GReg[4] and set flag T if GReg[7] is lower than GReg[4]
CPU Flags: T
Cycles: 1
Description: Compares the destination general register r and the source general register s,
and sets T if the destination general register r is lower than the source general register s,
clears T otherwise. The comparison is signed.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 1 0 s s s

rrr / sss - register field:

000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.20 cpShReg (Update Context of PCU Registers and Flag)

Assembler:
Syntax: cpShReg

CPU Flags: none

Cycles: 1
Description: SF, RPC, T, PC,LM, EPC, DF, and SPC registers are updated according to
the value of their corresponding bits in the context memory. This instruction must only be
used in debug mode via the OnCE. It reverses the done 5 operation.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1149
Smart Direct Memory Access Controller (SDMA)

Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0

7.2.3.2.21 DONE (DONE, Yield)

Operation:
if (jjj&6 == 2) HE[CCR] ← 0

if (jjj == 3) HI[CCR] ← 1

if (jjj == 4) EP[CCR] ← 0

if ((jjj == 0) && (NCP > CCP)) CCR ← NCR

else if ((jjj == 1) && (NCP >= CCP))

CCR ← NCR

else

CCR ← NCR

(CCR stands for Current Channel Register; NCR stands for Next Channel Register)
Assembler:
Syntax: done jjj

Example: done 3

Clear HE bit for the current channel, send an interrupt to the Arm platform for the current
channel and reschedule.
CPU Flags: Unaffected
Cycles: Variable if a context switch is done, 1 otherwise
Description: Clears one of the channel enabling bits (HE or EP for the corresponding
channel number) if required. Sends an interrupt to the corresponding Arm platform by
setting the appropriate flag, if required (HI for the corresponding channel number).
Reschedules according to the mode and the NCP (Next Channel Priority) and CCP
(Current Channel Priority) values. According to the scheduling decision, the NCR (Next
Channel Register) is copied to the CCR (Current Channel Register) and channel contexts
are switched. If several channels with the same highest priority are pending, they are
ordered by their number from 31 down to 0. The higher number is selected (for example,
channel 26 is selected if channels 3, 12, 14, and 26 with the same highest priority are
pending). If no flag is modified, the reschedule can allow the replacement of the current
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
1150 NXP Semiconductors
 Chapter 7 Interrupts and DMA

channel by another channel with a priority strictly greater than the current channel
priority (yield). Or, it can allow the replacement of the current channel by another
channel with a priority greater than or equal to the current channel priority (yieldge). In
the latter case, the selected channel will always be the first one with the same priority,
starting from channel number 31 down to channel 0 (the current channel does not belong
to the set of selectable channels).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 j j j 0 0 0 0 0 0 0 0

jjj - Channel Flags field:

000 - No channel flags affected: Reschedule only if the next channel priority is greater
than current channel priority (yield)
001 - No channel flags affected: Reschedule only if the next channel priority is greater
than or equal to the current channel priority (yieldge)
010 - Clear HE for the current channel and reschedule 011 - Clear HE, set HI for the
current channel and reschedule 100 - Clear EP for the current channel and reschedule
101 - Reserved for debug to copy relevant registers into context memory
110 - RESERVED
111 - RESERVED
For the scheduling rules, refer to Scheduler Functional Description. Every possible done
instruction is further described as follows:
• done 0/yield is executed by a channel script when it accepts preemption by a higher
priority channel;
• done 1/yieldge is executed by a channel script when it accepts preemption by a
higher priority channel and it also accepts a roll-up with other channels that have the
same priority;
• done 2 is executed by a channel script that was triggered by a Arm platform start via
the Channel Start (SDMAARM_HSTART) register, when its task is completed and it
requires termination;
• done 3 is executed by a channel script that was triggered by a Arm platform start via
the Channel Start (SDMAARM_HSTART) register, when its task is completed, it
requires termination and it needs to trigger an interrupt to the Arm platform upon
closure;

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1151
Smart Direct Memory Access Controller (SDMA)

• done 4 is executed by a channel script that was triggered by a DMA request, when its
task is completed and it requires termination;
• done 5 is used in debug mode only; it copies the PCU registers and flags to the
context memory of the current channel;

7.2.3.2.22 ILLEGAL (ILLEGAL Instruction)

Operation:
PC ← 0001

Assembler:
Syntax: illegal

CPU Flags: Unaffected

Cycles: 2
Description: Jumps to the Illegal instruction routine located at address 0001. All
unauthorized instructions result in an Illegal instruction behavior; however, the
ILLEGAL instruction must be used to guarantee software compatibility with future
versions of the SDMA.
Instruction Format
Table 7-49. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1

7.2.3.2.23 JMP (Unconditional Jump Immediate)

Operation:
PC ← absolute_address

Assembler:
Syntax: jmp label

Example: jmp LLL

The assembler translates the label to the exact address

CPU Flags:Unaffected
Cycles: 2

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1152 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Description: Jumps to the absolute address contained the lower 14 bits of the instruction
(the PC is a 14-bit register).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 a a a a a a a a a a a a a a

aaaaaaaaaaaaaa - address field:

00000000000000 - 0

00000000000001 - 1

...

11111111111110 - 16382

11111111111111 - 16383

7.2.3.2.24 JMPR (Unconditional Jump)

Operation:
PC ← GReg[r]

Assembler:
Syntax: jmpr r

Example: jmpr 0

Jump to address stored in GReg[0]

CPU Flags: Unaffected
Cycles: 2
Description: Jumps to the absolute address contained in a General Register.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 0 1 0 0 0

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1153
Smart Direct Memory Access Controller (SDMA)
010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.25 JSR (Unconditional Jump to Subroutine Immediate)

Operation:
RPC ← PC + 1

PC ← absolute_address

Assembler:
Syntax: jsr r

Example:jsr LLL

Jumps to subroutine starting at LLL; the assembler translates the label to exact address
CPU Flags: Unaffected
Cycles: 2
Description: Jumps to the subroutine located at the absolute address contained the lower
14 bits of the instruction (the PC is a 14-bit register).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 a a a a a a a a a a a a a a

aaaaaaaaaaaaaa - address field:

00000000000000 - 0

00000000000001 - 1

...

11111111111110 - 16382

11111111111111 - 16383

7.2.3.2.26 JSRR (Unconditional Jump to Subroutine)

Operation:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1154 NXP Semiconductors
 Chapter 7 Interrupts and DMA
RPC ← PC + 1

PC ← GReg[r]

Assembler:
Syntax: jsrr r

Example:jsrr 5

Jumps to subroutine located at address stored in GReg[5]

CPU Flags: Unaffected
Cycles: 2
Description: Jumps to the subroutine at address contained in a General Register
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 0 1 0 0 1

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.27 LD (Load Register)

Operation:
GReg[r] ← [GReg[b] + displacement]

if (transfer_error)

SF ← 1

else

SF ← 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1155
Smart Direct Memory Access Controller (SDMA)

Assembler:
Syntax: ld r,(b,displacement)

Example: ld 1,(2,23)

Loads data into GReg[1]; the data is located at address obtained by adding decimal value
23 to GReg[2]
CPU Flags: SF
Cycles: 2+n where n is 0 for ROM, RAM or memory mapped registers, and n is the
number of wait-states of the peripheral for a peripheral access
Description: Adds a 5-bit 0-extended displacement to a base address in General Register
b; the result is the address of the data to fetch on the DM bus. The data received from the
bus is stored in the destination General Register r. If an error occurs during the transfer,
the flag SF is set, else it is cleared.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 r r r d d d d d b b b

rrr / bbb - register field:

000 - GReg[0]

001 - GReg[1]

...

111 - GReg[7]

ddddd - displacement value:

00000 - 0

00001 - 1

...

11111 - 31

7.2.3.2.28 LDF (Load Register from Functional Unit)

Operation:
GReg[r] ← [fu_address]

if (transfer_error)

SF ← 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1156 NXP Semiconductors
 Chapter 7 Interrupts and DMA
else

SF ←0

fu_address is an 8-bit field and depends on addressed functional unit

Assembler:
Syntax: ldf r,fu_address

Example: ldf 0,13

Loads data coming from the Burst DMA register MD into GReg[0]; it is a 32-bit access
with no prefetch
CPU Flags: SF
Cycles: 1+n where n is the number of wait-states that may be inserted by the functional
unit
Description: Sends an 8-bit address on the Functional Unit Bus (FU bus) and stores the
data received from the bus in the destination General Register r. If an error occurs during
the transfer, the flag SF is set, else it is cleared.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 r r r f f f f f f f f

See the following sections for more details of the LDF instruction usage with each
functional unit:
• Burst DMA Read (ldf) for Burst DMA
• Peripheral DMA Read (ldf)-Read Mode for Peripheral DMA
Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1157
Smart Direct Memory Access Controller (SDMA)

ffffffff - functional unit source register and action (unspecified values are reserved):
00000000 - MSA

00000100 - MDA

00001001 - MD byte

00001010 - MD halfword

00001011 - MD word

00001100 - MS

00101001 - MD byte - prefetch

00101010 - MD halfword - prefetch

00101011 - MD word - prefetch

01000000 - DSA

11000000 - PSA

11001000 - PD

11010000 - PDA

11011000 - PD in copy mode (rrr contents are lost)

11101000 - PD - prefetch next data

11111111 - PS

7.2.3.2.29 LDI (Load Register with Immediate Value)

Operation:
GReg[r] ← immediate

Assembler:
Syntax: ldi r,immediate

Example: ldi 6,1

loads decimal value 1 into GReg[6]

CPU Flags: Unaffected
Cycles: 1
Description: Stores a 0-extended immediate value in a General Register. The immediate
value is the low-order byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1158 NXP Semiconductors
 Chapter 7 Interrupts and DMA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 1 r r r i i i i i i i i

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.30 LDRPC (Load from RPC to Register)

Operation:
GReg[r] ← RPC

Assembler:
Syntax: ldrpc r

Example: ldrpc 3

copies RPC to GReg[3]

CPU Flags: Unaffected
Cycles: 1
Description: Stores the contents of the RPC in a General Register. That instruction may
be used to have more than one level of subroutines.
Instruction Format

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1159
Smart Direct Memory Access Controller (SDMA)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 0 1 0 1 0

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.31 LOOP (Hardware Loop)

Operation:
if (ff%2 == 0)

SF ← 0

if (ff/2 == 0)

DF ← 0

if ((GReg[0] == 0) || (SF == 1) || (DF == 1))

PC ← PC + loop_size + 1

else

SPC ← PC + 1

EPC ← PC + loop_size + 1

LM ← 1

PC ← PC + 1

during every instruction execution in the loop:

if ((SF == 1) || (DF == 1))

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1160 NXP Semiconductors
 Chapter 7 Interrupts and DMA
LM ← 0

PC ← EPC

else if ((PC + 1) == EPC)

GReg[0] ← GReg[0] - 1

if (GReg[0] == 0)

LM ← 0

PC ← EPC

else

PC ← SPC

else

PC ← nextPC(instruction)

after the execution of the last instruction of the loop body:

if (GReg[0] == 0)

T ← 1

else

T ← 0

Assembler:
Syntax: loop n{,ff}

Example: loop 3,1

Executes GReg[0] times the instructions comprised between PC+1 and PC+3 (included);
ff=1 clears the DF flag before starting the loop. When omitted, the ff field is set to 0
(clearing both SF and DF).
CPU Flags: LM[1:0], T
Cycles: 2 when the loop count (GReg[0]) is 0 or SF or DF is set at loop start, 1+1 when
the loop starts but exits abnormally (SF or DF set inside the loop which adds 1 cycle to
the offending load or store to jump to EPC), 1 when the loop is executed normally

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1161
Smart Direct Memory Access Controller (SDMA)

Description: The loop instruction executes a sequence of instructions several times. The
number of times is given by the contents of GReg[0], the loop counter. SDMA will jump
to the first instruction after the end of the loop if the value in GReg[0] is 0. Otherwise the
SDMA enters loop mode. It sets the most significant bit of the LM flag that will only be
reset once the last instruction of the last loop is executed. The instructions in the loop are
executed GReg[0] times. The management of fault flags (SF and DF) is as follows. When
entering the hardware loop, SF and DF can be cleared according to the ff field of the
instruction. After that operation, if any flag is still set the loop will not be executed. The
SDMA will jump to the first instruction after the end of the loop without entering loop
mode. During the execution of the loop, if any fault flag is set by a LD, LDF, ST, or STF
instruction, the SDMA will immediately exit loop mode and jump to the first instruction
after the end of the loop. In that case, GReg0 is not decremented for that last piece of the
loop body execution (even if the SF or DF flag is set at the last instruction of the loop
body). The T flag reflects the state of GReg[0] after the end of the loop, which is an
indicator of the complete execution of the loop. If the loop exited because of an error (SF
or DF set), GReg[0] will not be 0 at the end of the loop, hence T will be cleared. If the
loop executes without fault, GReg[0] will be 0 at the end of the loop, hence T will be set.
The boundary case when a source or destination fault occurs at the last instruction of the
last loop is considered as an anticipated exit of the loop, which causes the T flag to be
cleared. If the last instruction executed before leaving the hardware loop also tries to
modify the T flag, the flag is updated according to the value of GReg[0], NOT according
to the result of the last executed instruction.
Limitations:
1. 1. Jump instructions (JMP, JMPR, JSR, JSRR, BF, BT, BSF, BDF) are not allowed
inside the hardware loop.
2. 2. GReg[0] cannot be written to inside the hardware loop (it can be read).
3. 3. The empty loop (0 instruction in the body) is forbidden.
4. 4. If GReg[0] == 0 at the start of the loop, which causes a jump to EPC, the T flag is
not updated.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 0 f f n n n n n n n n

Instruction Fields:
ff - flags field:

00 - clear SF and clear DF

01 - clear DF

10 - clear SF

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1162 NXP Semiconductors
 Chapter 7 Interrupts and DMA
11 - no clear

nnnnnnnn - loop size

00000000 - empty loop: forbidden value

00000001 - 1 instruction in the loop

00000010 - 2 instructions in the loop

...

11111111 - 255 instructions in the loop

7.2.3.2.32 LSL1 (Logical Shift Left by 1 Bit)

Operation:
GReg[r]:{b30,...,b1,b0,0} ← GReg[r]:{b31,b30,...,b1,b0}

Assembler:
Syntax: lsl1 r

Example: lsl1 2

multiplies by 2 the value in GReg[2]

CPU Flags: Unaffected
Cycles: 1
Description: Shift the bits of any General Register to the left. The right bit (bit 0) is set to
0. No overflow is detected by the hardware.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 1 1

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1163
Smart Direct Memory Access Controller (SDMA)
111 - GReg[7]

7.2.3.2.33 LSR1 (Logical Shift Right by 1 Bit)

Operation:
GReg[r]:{0,b31,b30,...,b1} ← GReg[r]:{b31,b30,...,b1,b0}

Assembler:
Syntax: lsr1 r

Example: lsr1 4

divides by 2 the unsigned value contained in GReg[4]

CPU Flags: Unaffected
Cycles: 1
Description: Shift the bits of any General Register to the right. The left bit (bit 31) is set
to 0.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 0 1

Instruction Fields:
rrr - destination register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.34 MOV (Logical Move)

Operation:
GReg[r] ← GReg[s]

Assembler:
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
1164 NXP Semiconductors
 Chapter 7 Interrupts and DMA
Syntax: mov r,s

Example: mov 4,0

copies GReg[0] to GReg[4]

CPU Flags: Unaffected
Cycles: 1
Description: Move the contents of the source General Register s to the destination
General Register r.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 0 0 1 s s s

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.35 NOTIFY (Notify to Arm platform)

Operation:
if (jjj & 4 == 0)

if (jjj&2 == 2)

HE[CCR] ← 0

if (jjj&1== 1)

HI[CCR] ← 1

else if (jjj == 4)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1165
Smart Direct Memory Access Controller (SDMA)
EP[CCR] ← 0

else

(CCR stands for Current Channel Register)

Assembler:
Syntax: notify jjj

Example: notify 3

clears the HE bit for the current channel and sends an interrupt to the Host for the current
channel
CPU Flags: Unaffected
Cycles: 1
Description: Clears one of the channel enabling bits (HE or EP for the corresponding
channel number) if required, sends an interrupt to the corresponding Arm platform by
setting the appropriate flag if required (HI for the corresponding channel number).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 j j j 0 0 0 0 0 0 0 1

jjj - Channel Flags field:

000 - unused

001 - set HI for the current channel

010 - clear HE for the current channel

011 - clear HE, set HI for the current channel

100 - clear EP for the current channel

101 - RESERVED

110 - RESERVED

111 - RESERVED

7.2.3.2.36 OR (Logical OR)

Operation:
GReg[r] ← GReg[s] | GReg[r]

Assembler:
Syntax: or r,s

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1166 NXP Semiconductors
 Chapter 7 Interrupts and DMA
Example: or 3,6

ORs GReg[3] and GReg[6] and stores the result in GReg[3]

CPU Flags: Unaffected
Cycles: 1
Description: Performs the OR of the source General Register s and the destination
General Register r, and stores the result in the destination General Register r.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 0 1 s s s

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.37 ORI (Logical OR with Immediate Value)

Operation:
GReg[r] ← GReg[r] | immediate

Assembler:
Syntax: ori r,immediate

Example: ori 1,56

ORs GReg[1] and the decimal value 56 and stores the result in GReg[1]
CPU Flags: unaffected
Cycles: 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1167
Smart Direct Memory Access Controller (SDMA)

Description: Performs an OR between a 0-extended 8-bit immediate value and a General

Register; stores the result in the General Register. The immediate value is the low-order
byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 1 r r r i i i i i i i i

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.38 RET (Return from Subroutine)

Operation:
PC ← RPC

Assembler:
Syntax: ret

CPU Flags: Unaffected

Cycles: 2
Description: Return from subroutine.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
1168 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

7.2.3.2.39 REVB (Reverse Byte Order)

Operation:
GReg[r]:{B3,B2,B1,B0} ← GReg[r]:{B0,B1,B2,B3}

Assembler:
Syntax: revb r

Example: revb 5

reverses bytes order in GReg[5]

CPU Flags: Unaffected
Cycles: 1
Description: Reverse the byte order of any General Register.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 0 0 0

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1169
Smart Direct Memory Access Controller (SDMA)

7.2.3.2.40 Reverse Low Order Bytes(REVBLO)

Operation:
GReg[r]:{B3,B2,B0,B1} ← GReg[r]:{B3,B2,B1,B0}

Assembler:
Syntax: revblo r

Example: revblo 0

reverses low order bytes in GReg[0]

CPU Flags: Unaffected
Cycles: 1
Description: Reverse both low order bytes of any General Register.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 0 0 1

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.41 ROR1 (Rotate Right by 1 Bit)

Operation:
GReg[r]:{b0,b31,b30,...,b1} ← GReg[r]:{b31,b30,...,b1,b0}

Assembler:
Syntax: ror1 r

Example: ror1 3

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1170 NXP Semiconductors
 Chapter 7 Interrupts and DMA

rotates bits to the right in GReg[3]

CPU Flags: Unaffected
Cycles: 1
Description: Rotate the bits of any General Register to the right.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 0 0

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.42 RORB (Rotate Right by 1 Byte)

Operation:
GReg[r]:{B0,B3,B2,B1} ← GReg[r]:{B3,B2,B1,B0}

Assembler:
Syntax: rorb r

Example: rorb 2

rotates bytes to the right in GReg[2]

CPU Flags: Unaffected
Cycles: 1
Description: Rotate the bytes of any General Register to the right.
Instruction Format

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1171
Smart Direct Memory Access Controller (SDMA)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 0 1 0

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.43 SOFTBKPT (Software Breakpoint)

Operation:
Stops the current script and enters debug mode
Assembler:
softbkpt

CPU Flags: Unaffected

Description: When the core executes this instruction, it has the same effect as receiving a
debug request from the OnCE or via the external debug request input: the script execution
halts, the PCU enters its debug state and waits for the OnCE commands that are described
in OnCE and Real-Time Debug.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

7.2.3.2.44 ST (Store Register)

Operation:
[GReg[b] + displacement] ← GReg[r]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1172 NXP Semiconductors
 Chapter 7 Interrupts and DMA
if (transfer_error)

DF ← 1

else

DF ← 0

Assembler:
Syntax: st r,(b,displacement)

Example: st 7,(0,9)

stores the value from GReg[7] into memory at address obtained by adding decimal value
9 to GReg[0]
CPU Flags: DF
Cycles: 2+n where n is 0 for ROM, RAM or memory mapped registers, and n is the
number of wait-states of the peripheral for a peripheral access
Description: Adds a 5-bit 0-extended displacement to a base address in General Register
b; the result is the address of the data to store on the DM bus. The data sent on the bus
comes from the source General Register r. If an error occurs during the transfer, the flag
DF is set, else it is cleared.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 1 r r r d d d d d b b b

Instruction Fields:
rrr / bbb - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

ddddd - displacement value:

00000 - 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1173
Smart Direct Memory Access Controller (SDMA)
00001 - 1

...

11111 - 31

7.2.3.2.45 STF (Store Register in Functional Unit)

Operation:
[fu_address] ← GReg[r] 0

if (transfer_error) 0

DF ← 1 0

else 0

DF ← 0

fu_address is an 8-bit field

Assembler:
Syntax: stf r,fu_address

Example: stf 3,0x2B

stores the 32-bit contents of GReg[3] to the Burst DMA register MD; waits until the flush
to external memory is completed
CPU Flags: DF
Cycles: 1+n where n is the number of wait-states that may be inserted by the functional
unit
Description: Sends an 8-bit address on the Functional Unit Bus (FU bus) and sends the
contents of the source General Register r on the bus. If an error occurs during the transfer,
the flag DF is set, else it is cleared.
Table 7-50. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 1 r r r f f f f f f f f

See the following sections for more details of the STF instruction usage with each
functional unit:
• Burst DMA Write (stf) for Burst DMA
• Peripheral DMA Write (stf)-Write Mode for Peripheral DMA
Instruction Fields:

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1174 NXP Semiconductors
 Chapter 7 Interrupts and DMA

rrr - register field:

000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

ffffffff - functional unit destination register and action (unspecified values are reserved):
00000000 - MSA in incremented mode

00000100 - MDA in incremented mode

00001001 - MD byte
00001010 - MD halfword
00001011 - MD word
00001100 - clear MS error flag
00001111 - MS
00010000 - MSA in frozen mode

00010100 - MDA in frozen mode

00011000 - MD in copy mode - number of words in rrr

00100000 - MSA in incremented mode - start prefetch

00101000 - MD no data - flush

00101001 - MD byte - flush
00101010 - MD halfword - flush
00101011 - MD word - flush
00110000 - MSA in frozen mode - start prefetch

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1175
Smart Direct Memory Access Controller (SDMA)

11000001 - PSA in frozen mode - 8-bit data width

11000010 - PSA in frozen mode - 16-bit data width
11000011 - PSA in frozen mode - 32-bit data width
11000101 - PSA in incremented mode - 8-bit data width
11000110 - PSA in incremented mode - 16-bit data width
11000111 - PSA in incremented mode - 32-bit data width
11001000 - PD
11001001 - PSA in decremented mode - 8-bit data width
11001010 - PSA in decremented mode - 16-bit data width
11001011 - PSA in decremented mode - 32-bit data width
11001100 - clear PS error flag
11001101 - PSA data width becomes 8-bit
11001110 - PSA data width becomes 16-bit
11001111 - PSA data width becomes 32-bit
11010001 - PDA in frozen mode - 8-bit data width
11010010 - PDA in frozen mode - 16-bit data width
11010011 - PDA in frozen mode - 32-bit data width
11010101 - PDA in incremented mode - 8-bit data width
11010110 - PDA in incremented mode - 16-bit data width
11010111 - PDA in incremented mode - 32-bit data width
11011001 - PDA in decremented mode - 8-bit data width
11011010 - PDA in decremented mode - 16-bit data width
11011011 - PDA in decremented mode - 32-bit data width
11011101 - PDA data width becomes 8-bit
11011110 - PDA data width becomes 16-bit
11011111 - PDA data width becomes 32-bit

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1176 NXP Semiconductors
 Chapter 7 Interrupts and DMA

11100001 - PSA in frozen mode - 8-bit data width - prefetch data

11100010 - PSA in frozen mode - 16-bit data width - prefetch data
11100011 - PSA in frozen mode - 32-bit data width - prefetch data
11100101 - PSA in incremented mode - 8-bit data width - prefetch data
11100110 - PSA in incremented mode - 16-bit data width - prefetch data
11100111 - PSA in incremented mode - 32-bit data width - prefetch data
11101001 - PSA in decremented mode - 8-bit data width - prefetch data
11101010 - PSA in decremented mode - 16-bit data width - prefetch data
11101011 - PSA in decremented mode - 32-bit data width - prefetch data
11101101 - PSA data width becomes 8-bit - prefetch data
11101110 - PSA data width becomes 16-bit - prefetch data
11101111 - PSA data width becomes 32-bit - prefetch data
11111111- PS

7.2.3.2.46 SUB (Subtract)

Operation:
GReg[r] ← GReg[r] - GReg[s]

T ← (GReg[r] == 0)

Assembler:
Syntax: sub r,s

Example: sub 4,7

SUBtracts GReg[7] from GReg[4] and stores the result in GReg[4]

CPU Flags: T
Cycles: 1
Description: Subtracts the source General Register s from the destination General
Register r, and stores the result in the destination General Register r. The T flag is set if
the result of the operation is 0; it is cleared if the result is not 0.
Instruction Format

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1177
Smart Direct Memory Access Controller (SDMA)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 0 0 s s s

Instruction Fields:
rrr / sss - register fields:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.47 SUBI (Subtract with Immediate)

Operation:
GReg[r] ← GReg[r] - immediate

T ← (GReg[r] == 0)

Assembler:
Syntax: sub r,immediate

Example: sub 1,255

SUBtracts decimal value 255 from GReg[1] and stores the result in GReg[1]
CPU Flags: T
Cycles: 1
Description: Subtracts a 0-extended 8-bit immediate value from a General Register;
stores the result in the General Register. The flag T is set when the result of the operation
is 0; otherwise, it is cleared. The immediate value is the low-order byte of the instruction
and has a maximum value of 255 (0xFF).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 r r r i i i i i i i i

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1178 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.48 TST (Test with Zero)

Operation:
T ← ((GReg[s] & GReg[r]) != 0)

Assembler:
Syntax: tst r,s

Example: tst 2,3

ANDs GReg[2] and GReg[3] and sets T if the result is non-null

CPU Flags: T
Cycles: 1
Description: Performs the AND of the source General Register s and the destination
General Register r, and sets T if the result is not 0, clears T if the result is 0.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 0 0 s s s

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1179
Smart Direct Memory Access Controller (SDMA)

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.49 TSTI (Test Immediate)

Operation:
T ← ((GReg[r] & immediate) != 0)

Assembler:
Syntax: tsti r,immediate

Example: tsti 5,13

ANDs GReg[5] and decimal value 13 and sets T if the result is non-null
CPU Flags: T
Cycles: 1
Description: Performs the AND of a 0-extended 8-bit immediate value and the
destination General Register r, and sets T if the result is not 0, clears T if the result is 0.
The immediate value is the low-order byte of the instruction and has a maximum value of
255 (0xFF).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 r r r i i i i i i i i

Instruction Fields:
rrr - destination register field:
000 - GReg[0]

001 - GReg[1]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1180 NXP Semiconductors
 Chapter 7 Interrupts and DMA
010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.50 XOR (Logical Exclusive OR)

Operation:
GReg[r] ← GReg[s] ^ GReg[r]

Assembler:
Syntax: xor r,s

Example: xor 0,3

XORs GReg[0] and GReg[3] and stores the result in GReg[0]

CPU Flags: Unaffected
Cycles: 1
Description: Performs the eXclusive OR of the source General Register s and the
destination General Register r, and stores the result in the destination General Register r.
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 0 1 0 s s s

Instruction Fields:
rrr / sss - register field:
000 - GReg[0]

001 - GReg[1]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1181
Smart Direct Memory Access Controller (SDMA)
010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

111 - GReg[7]

7.2.3.2.51 XORI (Exclusive OR with Immediate)

Operation:
GReg[r] ← GReg[r] ^ immediate

Assembler:
Syntax: xori r,immediate

Example: xor 7,5

XORs GReg[5] and decimal value 5 and stores the result in GReg[7]
CPU Flags: Unaffected
Cycles: 1
Description: Performs an eXclusive OR between a 0-extended 8-bit immediate value and
a General Register; stores the result in the General Register. The immediate value is the
low-order byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 r r r i i i i i i i i

Instruction Fields:
rrr - register field:
000 - GReg[0]

001 - GReg[1]

010 - GReg[2]

011 - GReg[3]

100 - GReg[4]

101 - GReg[5]

110 - GReg[6]

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1182 NXP Semiconductors
 Chapter 7 Interrupts and DMA
111 - GReg[7]

iiiiiiii - immediate value:

00000000 - 0

00000001 - 1

...

11111110 - 254

11111111 - 255

7.2.3.2.52 YIELD, YIELDGE (DONE, Yield)

By default, unsupported assembler syntax. Can be aliased to the corresponding done
instructions (yield = done 0; yieldge = done 1). Refer to the done instruction description
DONE (DONE, Yield) .

7.2.4 Software Restrictions

7.2.4.1 Unsupported Burst DMA Access Sequence

The SDMA does not support triggering a pre-fetch followed by a flush of the Burst DMA
without reading or writing any data. If the flush occurs while the background pre-fetch
DMA operation is still in progress, it could result in un-defined behavior.
An example of the sequence which could result in undefined results is shown in the
following example:
Instruction sequence not supported

stf r1, MSA|PF ; Update source address, triggers data pre-fetch in the
; background
mov R0,R0 ; Execute multiple assembly instructions, none of which
; read
mov R0,R0 ; or write data to/from MD
stf MD|SZ0|FL ; Flush FIFO without writing data. If the pre-fetch is still
; in progress when this instruction is executed, there
; could be undefined operation

A work-around to avoid any undesirable results is to first read MD to ensure the pre-fetch
is complete before the flush is attempted.
Work-Around to previous example

stf r1, MSA|PF ; Update source address, triggers data pre-fetch.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1183
Smart Direct Memory Access Controller (SDMA)
mov R0,R0 ; Execute multiple assembly instructions, none of which
; read
mov R0,R0 ; or write data to/from MD
ldf r2, MD ; dummy read of MD to ensure pre-fetch is complete
; before the next instruction
stf MD|SZ0|FL ; Flush FIFO without writing data

7.2.5 Application Notes

7.2.5.1 Data Structures for Boot Code and Channel Scripts

SDMA boot code downloads the different channel contexts and the scripts that will be
executed on SDMA channels during the application.
The boot code is run after reset when channel 0 is started by the Arm platform. The boot
code is also known as channel 0 script.
The boot code is based on the Channel Control Block (CCB) and Buffer Descriptor (BD)
mechanisms that are data structures located into the Arm platform memory space. With
these data structures, it is possible to instruct SDMA to download scripts and contexts but
also to dump a context or a script to a destination data buffer. Channel scripts also use the
CCB and BD data structures to pass instructions and/or pointers to data to be copied.
The format, processing, and field definition of the CCB and BD are defined and
performed entirely by the software script rather than the SDMA hardware. An overview
of the format and structure is provided here, but for complete details refer to the SDMA
software documentation (see SDMA Scripts).
The CCB and BD data structures are accessed by SDMA using DMA and processed by
the SDMA scripts. The ROM contains common sub-routines for processing these data
structures which may be called by the bootload and channel scripts.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1184 NXP Semiconductors
 Chapter 7 Interrupts and DMA

Channel Control Block Buffer Descriptor Array

MC0PTR
currentBDptr Command Flags Count
baseBDptr Buffer Address
CCB0
chanDesc Extended Buffer Address
status Command Flags Count
currentBDptr Buffer Address
baseBDptr Extended Buffer Address
CCB1
chanDesc
status

Data Buffer
currentBDptr
baseBDptr
CCB31
chanDesc Data Buffer
status

Figure 7-16. Data Structures Layout

The previous figure shows an example how these data structures are linked to pass
command and pointers to data buffers. The SDMA's MC0PTR register holds the base
address of the Channel 0 Control Block (CCB0). The Channel 0 control block holds a
pointer to the array of buffer descriptors. The buffer descriptors are used to tell the
channel 0 (boot channel) what to do as described Buffer Descriptor Format.

7.2.5.1.1 Buffer Descriptor Format

Buffer descriptors are three longs (32-bit words) in size as, shown in the figure found
here.
A buffer descriptor describes the properties of the data buffer it points to. The buffer
descriptors can be used for linear or circular data buffers in the Arm platform processor
memory. The CCB contains a pointer to the base BD as well as the current BD.
Table 7-51. Buffer Descriptor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Command - - L R I C W D Count
Buffer Address
Extended Buffer Address

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1185
Smart Direct Memory Access Controller (SDMA)

Table 7-52. Buffer Descriptor Field Descriptions

Field Description
31-24 Command. The command field is used to differentiate operations performed within a script when the script
accesses this particular buffer descriptor. The use of this field can be defined by the script. The command values
Command
defined for the bootload script are defined in Buffer Descriptor Commands for Bootload scripts. Refer to the
individual script definition in script library documents in SDMA Scripts for command field definitions for other
scripts.
23 Reserved
22 Reserved
21 Last Buffer Descriptor: This bit is set in SDMA IPC scripts to indicate to the receiving Core that the transfer has
ended. Whenever the source finishes transferring the count it wanted to transfer, it sets LAST_BIT in the
L
destination BD, to let the destination know that transfer is over.This bit also tells the destination software that
when it processes the destination BDs, they need not process any BD after the BD with the LAST_BIT set.For
example, when the DSP prepares a single buffer descriptor with count equals to 25 and Arm platform prepares a
single buffer descriptor with count equals 100. When 25 bytes have been transferred from DSP to Arm platform,
the DSP buffer descriptor is normally closed while the Arm platform buffer descriptor will have the L bit set and
the byte count updated to 25.
20 erroR. Indicates an error occurred on the channel's buffer descriptor requested command. Some scripts may
overwrite the command field with an error code indicating the source of the error.
R
0 No Error
1 Error
19 Interrupt. When SDMA has finished to process data transfer attached to this buffer descriptor, send an interrupt
to the Arm platform.
I
0 No Interrupt
1 Interrupt the processor when BD is complete
18 Continuous. This buffer is allowed to receive multiple transmit buffers or is allowed to transmit to multiple receive
buffers.The Continuous bit is decoded at the end of the processing of a BD to determine if the SDMA script must
C
open a new BD to potentially continue the data transfer.
0 No further buffer descriptors
1 SDMA should move to the next Buffer descriptor after this one
17 Wrap. Indicates if this buffer descriptor is the last one for the channel control block. When encountering this bit
set, the SDMA scripts updates the CurrentBD pointer to point to the first Buffer Descriptor of the array. This bit is
W
set if the Arm platform wants to organize the array of BD in a circular way (like a ring). When all BD have been
processed and if Wrap bit and CONtinuous bit are set in the last BD, the SDMA script will wrap around and it will
try to re-open the first BD.
0 No Error
1 Wrap to first buffer descriptor after this one is processed.
16 D - "Done": bit 16: indicates the "ownership" of the buffer descriptor. When D=0 the host owns the buffer
descriptor; when D=1 SDMA owns the buffer descriptor. In the case of the channel 0, D=1 indicates the SDMA
D
has not yet processed this buffer, D=0 indicates the SDMA has processed this buffer.
0 Arm platform owns the buffer.
1 SDMA owns the buffer
15-0 Count. the count field (bit 15-0) indicates the size of the data to be transmitted, the size of the data buffer pointed
to by the buffer descriptor. The SDMA memory structure is different for program memory (16-bits shorts/half-
Count
words) and data memory (32-bits long). For channel 0 buffer descriptors, Count is expressed in 16-bit half-words
when PM is addressed and in 32-bit words when DM is addressed. Count is typically expressed in bytes for
other channel scripts, but the unit is dependant on the script.
31-0 Buffer address. Address pointer to the data buffer.
31-0 Extended buffer address. Additional pointer or other information required by some scripts.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1186 NXP Semiconductors
 Chapter 7 Interrupts and DMA

The buffer descriptors form an array of programmable size. If the last buffer descriptor is
marked by the Wrap flag-bit W=1, the array of buffer descriptor is treated as a ring with
some logically continuous portion owned by the Arm platform with D=0, and the
remainder owned by the SDMA with D=1. The count field of the buffer descriptor
indicates how much data has been transmitted.
If Arm platform has prepared 3 buffers to be filled by the SDMA script, it has also
prepared 3 BD, one for each buffer. The Cont and Wrap bits are used to organize the
buffers in a circular way. For example, CONTinous bit is set to 1 in the 2 first BDs and
Wrap is set in the 3rd BD. The SDMA script opens and processes BD#1. Since
CONTinous bit is set for this BD, the SDMA will open the second BD and it will process
it. Each time a BD is processed, its Done bit is reset by the SDMA. After the 3rd BD, if
CONTinous is not set but if Wrap is set, the SDMA script stops here and the next time the
channel will be triggered, the script will open the BD pointed by the currentBDptr pointer
of the CCB and it will correspond to the first buffer descriptor.
If the CONTinous bit and Wrap bits are both set in the 3rd BD, the script will close it and
it will try to open the first BD. An error may occur at this point if the BD#1 has already
been processed and its Done bit is 0. The SDMA script cannot process a BD with a Done
bit to 0. It means the BD is not ready to be processed. To avoid this situation, the
CONTinous bit should not be set for the last BD if Wrap is set, and the Interrupt flag
must set for the last BD. It will warn the owner of the BD that all the BDs have been
processed and it has to re-set to 1 the Done bit of all the BD's if it desires the SDMA to
fill them again. Basically, if the Arm platform expects the SDMA to fill up the buffers in
a circular fashion, then it's the responsibility of the Arm platform to set the Done bit of a
buffer descriptor at an appropriate time.

AP MEM
AP BD1, BD2 & BD3
Buffer 1 CD 25
(25 bytes)
CD 50
Buffer 2
Incoming Data SDMA
(50 bytes)
IWD 25

Buffer 3
(25 bytes) Interrupt to AP
(HI)

Figure 7-17. Buffer Descriptor Flow

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1187
Smart Direct Memory Access Controller (SDMA)

The previous figure shows an example buffer descriptor flow. When the incoming data is
stored and fills the first buffer of 25 bytes, the SDMA script opens the second BD
because the CONTinuous bit was set. Then next incoming data is put in the second
buffer. After receiving 50 bytes, the second buffer descriptor is also closed. The Done bit
is reset and the third BD is opened. After receiving another 25 bytes, the third buffer is
full and an interrupt is sent to the Arm platform because the Interrupt flag is set in the 3rd
BD. The CONTinuous flag is not present the transfer is over. The next time the script will
be triggered, the BD to be opened will be the first buffer descriptor since the Wrap flag
was set in the 3rd BD. It is the Arm platform responsibility to set the Done bit of all the
BD if it wants to use the same buffers.

7.2.5.1.2 Buffer Descriptor Commands for Bootload scripts

The command field of the buffer descriptor is defined separately for each script.
The following table lists the buffer descriptor commands defined for the channel 0
bootload script.
Table 7-53. Channel Zero Buffer Descriptor Commands
Command Command Description Buffer Address Extended Buffer
Address
Field
(binary)
0000_0001 C0_SET_DM Load SDMA data memory (RAM) from Arm Arm platform memory SDMA memory
platform memory buffer source address destination address
(0x01)
0000_0010 C0_GET_DM Copy SDMA data memory (RAM) to Arm Arm platform memory SDMA memory source
platform memory buffer destination address address
(0x02)
0000_0100 C0_SET_PM Load SDMA program memory (RAM) from Arm platform memory SDMA memory
Arm platform memory buffer source address destination address
(0x04)
0000_0110 C0_GET_PM Copy SDMA program memory (RAM) to Arm Arm platform memory SDMA memory source
platform memory buffer destination address address
(0x06)
cccc_c111 C0_SETCTX Load Context for channel cccc into SDMA Arm Platform memory -
RAM from Arm platform memory buffer source address
(0x07 | CHN)
cccc_c011 C0_GETCTXT Copy Context for channel ccccc from SDMA Arm platform memory -
RAM to Arm platform memory buffer destination address
(0x03 | CHN)

The Channel 0 bootload commands are summarized as follows:

• C0_SET_[PM-DM]: load the buffer descriptor data in the SDMA local memory at
the address pointed to by the "extended buffer address" field. The SDMA RAM can
be seen as a Program Memory (PM, 16-bit address) or Data Memory (DM 32-bit
address). When C0_SET_PM is used, the count field is expressed in "shorts" (16-bit
half words), this command can be used to download scripts. When C0_SET_DM is

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1188 NXP Semiconductors
 Chapter 7 Interrupts and DMA

used, the count field is expressed in "long" (32-bit words), this command can be used
to download channel contexts to the context channel area in RAM.
• C0_GET_[PM-DM]: write to the buffer descriptor's data buffer the content of the
SDMA local memory from the address pointed to by the "extended buffer address"
field for the length defined by the count in the buffer descriptor. C0_GET_PM is
used to dump some part of the Program Memory (may be used to dump context of a
channel), therefore count is expressed in "shorts"; while C0_GET_DM is used to
dump to the buffer descriptor's data buffer, so the count field is in "longs."
• C0_SETCTX: load a context into the SDMA context page area. The handling script
decodes the channel number from the 5 MSB of the command field of the buffer
descriptor. Using the channel number the script computes the offset of the context
data pointer for the channel relative to the context page base to use as the destination
address in SDMA memory. Then the C0_SET_DM command explained above is
invoked to load SDMA RAM from memory. The counter indicates the size in words
of the context structure.
• Command value: (in binary) cccc c111, where ccccc is the channel number (5 bits).
For instance, 0x0F means set context for channel 1, 0xFF means set context for
channel 31.
• C0_GETCTX: write to the buffer descriptor's data buffer the content of the SDMA
context page area. The handling script decodes the channel number from the 5 MSB
of the command field of the buffer descriptor. Using this channel number, the script
computes the offset of the context data pointer for the channel relative to the context
page base to use as the source address for the copy. Then the C0_GET_DM
command explained above is invoked to copy the context to memory. The counter
indicates the size in words of the context structure.
• Command value: (in binary): cccc c011, where ccccc is the channel number (5 bits).
For instance, 0x03 means get context of channel 1, 0xFB means get context of
channel 31.
NOTE
To download channel context, C0_SETDM and
C0_SETCTXT command can be used but the second one is
easier because the channel number is embedded into the
command field, whereas with the C0_SETDM, the pointer
to the channel context area must be written into the
extended buffer address field of the buffer descriptor.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1189
Smart Direct Memory Access Controller (SDMA)

7.2.5.1.3 Example of Buffer Descriptors for Channel 0.

Figure 7-19 illustrates the buffer descriptors that must be set in Arm platform memory
space, before execution of boot code, to download contexts and scripts of channels 1, 4,
and 10. After boot code execution, SDMA memory will be populated with the different
contexts and scripts as presented in the following figure.

SDMA RAM 0x800

0x820
Channel 1 Context
0x880
Channel 4 Context

0x960 Content
Channel 10 Context Area

0xC00

Channel 1 Script

Channel 4 Script
Scripts and Data
Area
Channel 10 Script

Figure 7-18. Example of SDMA RAM After Boot Session

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1190 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMA Register
MC0PTR

Channel Control Block

CurrentBDptr
Channel 0 Buffer Descriptor Array
BaseBDptr
chanDesc
status 31 24 23 22 21 20 19 18 17 16 15 0
00001111 0 0 1 0 1 20

Buffer Address

Extended Buffer Address (Unused)

00100111 0 0 1 0 1 20
BD1 - SET CONTEXT CH#1 Buffer Address
Interrupt = 0,
Cont=1, Done = 1
Extended Buffer Address (Unused)
BD2 - SET CONTEXT CH#4
Interrupt = 0, 01010111 0 0 1 0 1 20
Cont=1, Done = 1
Buffer Address
BD3 - SET CONTEXT CH#10
Interrupt = 0, Extended Buffer Address (Unused)
Cont=1, Done = 1
00000100 0 0 1 0 1 10
BD4 - SET_PM
Interrupt = 0, Buffer Address
Cont=1, Done = 1
Extended Buffer Address
BD5 - SET_PM
Interrupt = 0, 00000100 0 0 1 0 1 40
Cont=1, Done = 1
Buffer Address
BD6 - SET_PM
Interrupt = 1, Extended Buffer Address
Cont=0, Done = 1
00000100 0 1 0 0 1 50

Buffer Address

Extended Buffer Address

AP Memory Space

SDMA RAM Channel 1 context

(32 longs)

Channel 4 context
(32) longs)
Context Area
Channel 10 context
(32 longs)

Scripts Area

Channel 1 script
(16 shorts)

Channel 4 script
(64 shorts)

Channel 10 script
(80 shorts)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1191
Smart Direct Memory Access Controller (SDMA)

7.2.5.1.4 Channel Context

There are 32 channel context memory structures pointed to by the local save area pointer.
These channel context memory structures are fixed.
The script in the SDMA computes the memory offset for a given channel based on the
structure length and channel number. Figure below shows the structure of the channel
context as it is saved in the SDMA local memory (RAM).
A channel context consists in 24 words, one per register. A total of 32 words are reserved
for every channel. The additional 8 words are called scratch ram and they are dedicated to
each channel. This memory area is commonly used for stack management.
The structure is divided in 4 areas:
• Channel status registers
• General purpose registers
• Functional units state registers reflecting the state of the Arm platform DMAs (Burst
and Peripheral DMA).
• Scratch RAM
The details of the channel context status registers are described in the following figure.
The PC field of the first long register must point to the SDMA RAM address where the
script that will be executed on the channel is located and this value equals the one stored
in the extended buffer address of the buffer descriptor with C0_SETPM command.

31 30 29 16 15 14 13 0
_ _
SF RPC T PC
_
LM EPC DF SPC

SF: Source fault while loading data

RPC: Return program counter
T: Test bit: status of arithmetic and test instructions
PC: Program counter
LM: Loop mode
EPC: Loop end program counter
DF: Destination fault while storing data
SPC: Loop Start program counter

Figure 7-20. SDMA State Registers (ShPC, ShLoop)

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1192 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.5.2 Typical Data Transfer Supported by SDMA DMA Units

This section presents a library of SDMA scripts that perform data transfers through the
peripheral DMA and the burst DMA units.
The Arm platform memory and peripherals are devices that either the peripheral DMA or
the burst DMA can access. The scripts are given for a peripheral DMA whose address
registers are programmed in incremented mode when internal memory is involved. See
the following table for the summary.
Table 7-54. Typical Data Transfers Summary
Data Transfer Peripheral DMA Burst DMA Comments
Arm platform External Memory ↔ 3 Copy mode
Arm platform External Memory
Script example, see Burst DMA Unit Copy
Mode and External Memory to External
Memory.
Arm platform Peripheral ↔ Arm 3 Copy mode if same data path width
platform Peripheral
Script example, see Peripheral to Peripheral
Transfer.
Arm platform External Memory ↔ 3 3 Data transit through SDMA
Arm platform Peripheral
Script example, see Transfer Between
Peripheral and External Memory.
Arm platform External Memory ↔ 3 Copy mode
Arm platform Internal Memory
Script example, see Transfer Between
External Memory and Internal Memory.
Arm platform Internal Memory ↔ Arm 3 Copy mode
platform Internal Memory
Script example, see Internal Memory to
Internal Memory.
Arm platform Internal memory ↔ Arm 3 Data transit through SDMA
platform Peripheral
Script example, see Transfer Between
Peripheral and Internal Memory.

NOTE
These scripts are provided as examples of how to use DMA
blocks to perform required data transfers: They are not
"official" programs.

7.2.5.2.1 External Memory to External Memory

This section describes the SDMA script that performs data moves in external memory.
For this particular data transfer, only the burst DMA is used. It is programmed in copy
mode, so no data transmits through an SDMA general register.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1193
Smart Direct Memory Access Controller (SDMA)

The SDMA core only monitors data transfer status. It is assumed source and destination
address values are already present in two SDMA general registers (r1 and r2). For this
example, it is also assumed that a 32-bit word-to-move for source-to-destination address
is present in r0 and equals 64.
Data Moves in External Memory
1 stf r1,MSA // Source address setup

2 stf r2,MDA // Destination address setup

3 ldi r0,0x64 // 64 words must be transferred from MSA to

MDA

4 ldi r1,0x8

MAIN_XFER:

5 cmphs r0,r1 // Is r0 >= 0x8

6 bf LAST_XFER // If not, jump to last transfer label

7 stf r1,MD|CPY // Copy 8 words from MSA to MDA address.

8 subi r0,0x8 // Decrement counter

9 jmp MAIN_XFER // return to main transfer loop

LAST_XFER:

10 stf r0,MD|CPY // perform last transfer

All instructions are performed in one cycle (jumps excepted). Instruction 7 triggers a
copy transfer: A read burst access of 8-word starts, data is staged in MD and then a write
burst of 8 words is executed. Instruction 8, 9, 5, and 6 are executed while the burst access
is in progress. If this access is not complete when instruction 7 is executed a second time,
SDMA stalls on this instruction as long as the previous copy transfer is not over. In this
case, the instruction is no longer a one-cycle instruction.
During the main loop (MAIN_XFER), r1 always equals 8, so burst lengths are 8 words.
On the last ldf |CPY instruction (10), r1 equals the reminder of r0 divided by 8; therefore,
the length of bursts triggered in copy mode equal r1 value, which is between 1 and 7.

7.2.5.2.2 Peripheral to Peripheral Transfer

For this data transfer, only the peripheral DMA is used.
It is programmed in copy mode, so no data will transmit through the SDMA general
register used in the ldf instruction, but the contents of the general register are lost. The
SDMA core only monitors the transfer.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1194 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.5.2.2.1 Source and Destination Target Have the Same Data Path Width
When the source and destination target have the same data path width, the following is
true:
• Source target is a half-word (16-bit) peripheral located at address 0x1002.
• Destination is a half-word (16-bit) peripheral located at address 0x2006.
It is assumed the address values are already present in two SDMA general registers (r1,
r2). The script for a transfer of 10 half-word is as follows:
Same Data Path Width for Source and Destination
//SETUP SECTION
1 stf r1, PSA|SZ16|F //r1=0x1002 Source address register setup
2 stf r2, PDA|SZ16|F //r2=0x2006 Destination address register
setup
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0xa //loop counter is 10
//MAIN LOOP TRANFER
copy_loop:

5 loop 2,0
6 ldf r7,PD|CPY //Reads 1 half-word from src and writes to
dest.
7 yield
8 bdf ERROR_DURING_XFER
ERROR_ADDR_SETUP:
//correction of PSA/PDA setup and jumps to main loop transfer
ERROR_DURING_XFER:
//flag error is set,
//PS can be read to know if error occurs during read or write access.

If a data transfer must occur between two word peripherals, only the setup section should
be updated. The transfer itself is always performed by the hardware loop instruction.
All instructions are executed in one cycle (change of flow excepted). On instruction 6, a
single read access is triggered, read data is staged in PD, and a write-to-destination is
executed. When the transfers are in progress, the SDMA can execute he next instructions
in parallel. If instruction 6, which performs the copy transfer, is executed while the
previous access is not over, SDMA is stalled and instruction ldf is a multi-cycle
instruction.

7.2.5.2.2.2 Source and Destination Target Have a Different Data Path Width
When the source and destination target have a different data path width, copy mode
cannot be used, and any attempt to initiate a copy transfer immediately raises an error,
which is stored in the SF flag.
The following example shows the SDMA code that could transfer 10 words from a word
(32-bit) peripheral to a half-word peripheral whose addresses are preliminary and stored
in r1 and r2.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1195
Smart Direct Memory Access Controller (SDMA)

Different Data Path Width for Source and Destination

//SETUP SECTION
1 stf r1, PSA|SZ32|F|PF //r1=0x1000 and prefetch data
2 stf r2, PDA|SZ16|F //r2=0x2006
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0xa //loop counter is 10
//MAIN LOOP TRANFER
main_loop_xfer_16_16:
5 loop 6,0
6 ldf r7,PD //copy 32-bit of PD in r7
7 stf r7,PD //store 16 LSB of r7 in PD and a flush is
executed
8 rorb r7
9 rorb r7 //16 MSB --> 16 LSB
10 stf r7,PD //store 16 LSB of r6 in PD and a flush.
11 yield

On instruction 1, when the source address register is programmed and a data prefetch is
required, a read access is executed. In parallel, the SDMA executes instructions 2 to 5.
On instruction 6, the SDMA tries to read data that was fetched by instruction 1. If data is
ready, the ldf will be a one cycle instruction; otherwise, the SDMA is stalled as long as
the read access is not finished. Then, the 16 LSB of the read data is stored in PD and
automatically flushed to the destination peripheral. In parallel, the SDMA executes the
rotation instructions (8, 9), and stores the 16 MSB of the read data into PD. If a previous
write access is finished, instruction 10 will be a one-cycle instruction.
The main loop transfer may appear inefficient, but due to wait states imposed to the
peripheral DMA each time an external access is performed, a software pipeline is in
place. During the time needed to flush PD, the SDMA executes the move and rotation
operations. SDMA executes instructions in parallel with DMA accesses.

7.2.5.2.3 Transfer Between Peripheral and External Memory

7.2.5.2.3.1 Peripheral to External Memory Transfer

A transfer from a peripheral to the external memory controller involves the peripheral
DMA and the burst DMA.
The code for transferring 100 word from word peripheral to the external memory would
be as follows:
Peripheral to External Memory Transfer
//SETUP SECTION source and destination addresses are already in r1 and r2
1 stf r1, PSA|SZ16|F|PF //r1=0x1000 and prefetch 32-bit data
2 stf r2, MDA //r2=0x2000, setup burst DMA destination
address
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0x64 //loop counter is 100
5
//MAIN LOOP TRANFER
6 loop 3,0
7 ldf r1,PD|PF // read 32 bits of PD and initiate a new read

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1196 NXP Semiconductors
 Chapter 7 Interrupts and DMA
access.
8 stf r1,MD|32 // store 32 bits of r1 in the MD fifo.
9 yield
10 ldf r1,PD // last word data is read
11 stf r1,MD|32|FL // to flush all remaining bytes of MD

On instruction 1, the source address register of the peripheral DMA is programmed and
data is fetched. This data is stored in PD and the SDMA reads PD during instruction 7,
which is a one-cycle instruction that is read-access finished. On the same instruction (7),
a data prefetch is required and a read access to the source peripheral is executed. In
parallel, the SDMA stored the previous read data into the data register of MD. When MD
(which is an eight-word FIFO) is full, a burst write access is executed to empty the FIFO.
As long as the next SDMA instructions do not access the burst DMA, they will be one-
cycle instructions. The following figures show how the peripheral DMA and burst DMA
work in parallel.

1 2 3
Clk

SDMA
ldf PD stf MD yield ldf PD stf MD yield Idf PD stf MD yield
Instruction

peripheral
data 0 data 1
DMA port
1 wait state 2 wait states

PD data -1 data 0 data 1

r1 data -1 data 0 data 1

MD data -1 data -1 data -1

data 0 data 0
data 1

Figure 7-21. Peripheral to External Memory Example (1)

As seen in the figure above, the read access triggered by the ldf PD instruction is
symbolized by the blue bar when in progress. After wait states, the read data (data 0, data
1) is stored in PD on the clk rising edge. On edge 2, data 0 is available in PD so it can be
transferred to the SDMA general register r1, and then stored in MD FIFO. On edge 3,
data 1 is not in PD; therefore, SDMA is stalled on the ldf instruction, which lasts two
cycles. The figure below shows an example of when MD FIFO is full with data.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1197
Smart Direct Memory Access Controller (SDMA)

1 2 3
Clk

SDMA
ldf PD stf MD yield ldf PD stf MD yield Idf PD stf MD
Instruction

peripheral
data 8 data9
DMA port

8-word burst
Burst DMA
4 wait-states ack ack ack ack
port

PD data 7 data 8 data 9

r1 data 7 data 8 data 9

MD
data 0 data 1 data 2 data 3
data 1 data 2 data 3 data 4
data 2 data 3 data 4 data 5
data 3 data 4 data 5 data 6
data 4 data 5 data 6 data 7
data 5 data 6 data 7 data 8
data 6 data 7 data 8
data 7 data 8

Figure 7-22. Peripheral to External Memory Example (2)

In the previous figure, the write bar means the burst DMA is performing a write burst
access. The latency to have the first write acknowledge is four cycles. SDMA is stalled
on instruction stf because no acknowledge was received, MD FIFO is full, and there is no
empty slot to store data 9. When an acknowledge is sampled by the burst DMA, FIFO is
shifted and data 8 is written. As long as there is at least one empty slot in MD FIFO, the
stf MD instruction lasts one cycle.

7.2.5.2.3.2 External Memory to Peripheral Transfer

A transfer from the external memory to a peripheral involves the peripheral DMA and the
burst DMA.
The code for transferring 100 word from external memory to a word peripheral would be
as follows:
External Memory to Peripheral Transfer
//SETUP SECTION source and destination addresses are already in r1 and r2
1 stf r1, MSA|PF //r1=0x1000 and starts a 8-word read burst
2 stf r2, PDA|SZ32|P //r2=0x2010, setup peripheral DMA destination address
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0x64 //loop counter is 100
//MAIN LOOP TRANFER

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1198 NXP Semiconductors
 Chapter 7 Interrupts and DMA
6 loop 3,0
7 ldf r1,MD|32|PF // read 32 bits of MD and initiate a new read access
// if MD is empty after this reading.
8 stf r1,PD // store 32 bits of r1 in the PD.
9 yield
10 ldf r1,MD|32 // last word data is read
11 stf r1,PD // last write access

On instruction 1, a read burst of 8 words begins. Read data is staged into MD. On
instruction 7 (and if data is available in MD), 32 bits are copied into r1. Then instruction
8 writes them into PD and an automatic flush is executed. The SDMA core, peripheral
DMA, and burst DMA can work in parallel as long as no SDMA instruction tries to start
a new write access on the peripheral DMA while the previous access is still in progress,
or as long as there is data in MD when the SDMA tries to read it.

7.2.5.2.4 Transfer Between External Memory and Internal Memory

Since the internal memory (Arm platform RAM) is accessed via the peripheral DMA and
the external memory is accessed via the burst DMA, the SDMA scripts that are described
in Transfer Between Peripheral and External Memory can be reused. The exception is
that the peripheral DMA address registers (PSA or PDA, depending on the script) should
be programmed in incremented mode rather than frozen mode.

7.2.5.2.4.1 Internal Memory to Internal Memory

The internal memory can only be accessed via the peripheral DMA, so the script
described in Peripheral to Peripheral Transfer can be reused with a different
programming of the peripheral DMA address registers.

7.2.5.2.4.2 Transfer Between Peripheral and Internal Memory

For this transfer, the peripheral DMA is also used in copy mode.
The SDMA script is very similar to the one described in Peripheral to Peripheral
Transfer, except for the peripheral DMA address registers programming.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1199
Smart Direct Memory Access Controller (SDMA)

7.2.6 Arm Platform Memory Map and Control Register Definitions

The Arm platform controls the SDMA by means of several interface registers. Those
registers are described in the current section.
All registers are clocked with the SDMA clock (which means the Arm platform must
ensure that the SDMA clock is running when it wants to access any register).
SDMAARM memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.1/
302B_0000 Arm platform Channel 0 Pointer (SDMAARM3_MC0PTR) 32 R/W 0000_0000h
1215
7.2.6.2/
302B_0004 Channel Interrupts (SDMAARM3_INTR) 32 w1c 0000_0000h
1215
7.2.6.3/
302B_0008 Channel Stop/Channel Status (SDMAARM3_STOP_STAT) 32 w1c 0000_0000h
1215
7.2.6.4/
302B_000C Channel Start (SDMAARM3_HSTART) 32 R/W 0000_0000h
1216
7.2.6.5/
302B_0010 Channel Event Override (SDMAARM3_EVTOVR) 32 R/W 0000_0000h
1216
7.2.6.6/
302B_0014 Channel BP Override (SDMAARM3_DSPOVR) 32 R/W FFFF_FFFFh
1217
7.2.6.7/
302B_0018 Channel Arm platform Override (SDMAARM3_HOSTOVR) 32 R/W 0000_0000h
1217
7.2.6.8/
302B_001C Channel Event Pending (SDMAARM3_EVTPEND) 32 w1c 0000_0000h
1217
7.2.6.9/
302B_0024 Reset Register (SDMAARM3_RESET) 32 R 0000_0000h
1218
7.2.6.10/
302B_0028 DMA Request Error Register (SDMAARM3_EVTERR) 32 R 0000_0000h
1219
Channel Arm platform Interrupt Mask 7.2.6.11/
302B_002C 32 R/W 0000_0000h
(SDMAARM3_INTRMASK) 1219
7.2.6.12/
302B_0030 Schedule Status (SDMAARM3_PSW) 32 R 0000_0000h
1220
7.2.6.13/
302B_0034 DMA Request Error Register (SDMAARM3_EVTERRDBG) 32 R 0000_0000h
1220
7.2.6.14/
302B_0038 Configuration Register (SDMAARM3_CONFIG) 32 R/W 0000_0003h
1221
7.2.6.15/
302B_003C SDMA LOCK (SDMAARM3_SDMA_LOCK) 32 R/W 0000_0000h
1222
7.2.6.16/
302B_0040 OnCE Enable (SDMAARM3_ONCE_ENB) 32 R/W 0000_0000h
1223
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1200 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.17/
302B_0044 OnCE Data Register (SDMAARM3_ONCE_DATA) 32 R/W 0000_0000h
1223
7.2.6.18/
302B_0048 OnCE Instruction Register (SDMAARM3_ONCE_INSTR) 32 R/W 0000_0000h
1224
7.2.6.19/
302B_004C OnCE Status Register (SDMAARM3_ONCE_STAT) 32 R 0000_E000h
1224
7.2.6.20/
302B_0050 OnCE Command Register (SDMAARM3_ONCE_CMD) 32 R/W 0000_0000h
1226
Illegal Instruction Trap Address 7.2.6.21/
302B_0058 32 R/W 0000_0001h
(SDMAARM3_ILLINSTADDR) 1226
7.2.6.22/
302B_005C Channel 0 Boot Address (SDMAARM3_CHN0ADDR) 32 R/W 0000_0050h
1227
7.2.6.23/
302B_0060 DMA Requests (SDMAARM3_EVT_MIRROR) 32 R 0000_0000h
1228
7.2.6.24/
302B_0064 DMA Requests 2 (SDMAARM3_EVT_MIRROR2) 32 R 0000_0000h
1228
Cross-Trigger Events Configuration Register 1 7.2.6.25/
302B_0070 32 R/W 0000_0000h
(SDMAARM3_XTRIG_CONF1) 1229
Cross-Trigger Events Configuration Register 2 7.2.6.26/
302B_0074 32 R/W 0000_0000h
(SDMAARM3_XTRIG_CONF2) 1230
7.2.6.27/
302B_0100 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI0) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_0104 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI1) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_0108 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI2) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_010C Channel Priority Registers (SDMAARM3_SDMA_CHNPRI3) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_0110 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI4) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_0114 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI5) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_0118 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI6) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_011C Channel Priority Registers (SDMAARM3_SDMA_CHNPRI7) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_0120 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI8) 32 R/W 0000_0000h
1231
7.2.6.27/
302B_0124 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI9) 32 R/W 0000_0000h
1231
Channel Priority Registers 7.2.6.27/
302B_0128 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI10) 1231
Channel Priority Registers 7.2.6.27/
302B_012C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI11) 1231
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1201
Smart Direct Memory Access Controller (SDMA)

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Channel Priority Registers 7.2.6.27/
302B_0130 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI12) 1231
Channel Priority Registers 7.2.6.27/
302B_0134 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI13) 1231
Channel Priority Registers 7.2.6.27/
302B_0138 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI14) 1231
Channel Priority Registers 7.2.6.27/
302B_013C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI15) 1231
Channel Priority Registers 7.2.6.27/
302B_0140 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI16) 1231
Channel Priority Registers 7.2.6.27/
302B_0144 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI17) 1231
Channel Priority Registers 7.2.6.27/
302B_0148 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI18) 1231
Channel Priority Registers 7.2.6.27/
302B_014C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI19) 1231
Channel Priority Registers 7.2.6.27/
302B_0150 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI20) 1231
Channel Priority Registers 7.2.6.27/
302B_0154 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI21) 1231
Channel Priority Registers 7.2.6.27/
302B_0158 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI22) 1231
Channel Priority Registers 7.2.6.27/
302B_015C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI23) 1231
Channel Priority Registers 7.2.6.27/
302B_0160 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI24) 1231
Channel Priority Registers 7.2.6.27/
302B_0164 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI25) 1231
Channel Priority Registers 7.2.6.27/
302B_0168 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI26) 1231
Channel Priority Registers 7.2.6.27/
302B_016C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI27) 1231
Channel Priority Registers 7.2.6.27/
302B_0170 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI28) 1231
Channel Priority Registers 7.2.6.27/
302B_0174 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI29) 1231
Channel Priority Registers 7.2.6.27/
302B_0178 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI30) 1231
Channel Priority Registers 7.2.6.27/
302B_017C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI31) 1231
7.2.6.28/
302B_0200 Channel Enable RAM (SDMAARM3_CHNENBL0) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0204 Channel Enable RAM (SDMAARM3_CHNENBL1) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1202 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.28/
302B_0208 Channel Enable RAM (SDMAARM3_CHNENBL2) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_020C Channel Enable RAM (SDMAARM3_CHNENBL3) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0210 Channel Enable RAM (SDMAARM3_CHNENBL4) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0214 Channel Enable RAM (SDMAARM3_CHNENBL5) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0218 Channel Enable RAM (SDMAARM3_CHNENBL6) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_021C Channel Enable RAM (SDMAARM3_CHNENBL7) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0220 Channel Enable RAM (SDMAARM3_CHNENBL8) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0224 Channel Enable RAM (SDMAARM3_CHNENBL9) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0228 Channel Enable RAM (SDMAARM3_CHNENBL10) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_022C Channel Enable RAM (SDMAARM3_CHNENBL11) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0230 Channel Enable RAM (SDMAARM3_CHNENBL12) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0234 Channel Enable RAM (SDMAARM3_CHNENBL13) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0238 Channel Enable RAM (SDMAARM3_CHNENBL14) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_023C Channel Enable RAM (SDMAARM3_CHNENBL15) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0240 Channel Enable RAM (SDMAARM3_CHNENBL16) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0244 Channel Enable RAM (SDMAARM3_CHNENBL17) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0248 Channel Enable RAM (SDMAARM3_CHNENBL18) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_024C Channel Enable RAM (SDMAARM3_CHNENBL19) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0250 Channel Enable RAM (SDMAARM3_CHNENBL20) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0254 Channel Enable RAM (SDMAARM3_CHNENBL21) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0258 Channel Enable RAM (SDMAARM3_CHNENBL22) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_025C Channel Enable RAM (SDMAARM3_CHNENBL23) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1203
Smart Direct Memory Access Controller (SDMA)

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.28/
302B_0260 Channel Enable RAM (SDMAARM3_CHNENBL24) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0264 Channel Enable RAM (SDMAARM3_CHNENBL25) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0268 Channel Enable RAM (SDMAARM3_CHNENBL26) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_026C Channel Enable RAM (SDMAARM3_CHNENBL27) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0270 Channel Enable RAM (SDMAARM3_CHNENBL28) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0274 Channel Enable RAM (SDMAARM3_CHNENBL29) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0278 Channel Enable RAM (SDMAARM3_CHNENBL30) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_027C Channel Enable RAM (SDMAARM3_CHNENBL31) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0280 Channel Enable RAM (SDMAARM3_CHNENBL32) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0284 Channel Enable RAM (SDMAARM3_CHNENBL33) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0288 Channel Enable RAM (SDMAARM3_CHNENBL34) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_028C Channel Enable RAM (SDMAARM3_CHNENBL35) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0290 Channel Enable RAM (SDMAARM3_CHNENBL36) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0294 Channel Enable RAM (SDMAARM3_CHNENBL37) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_0298 Channel Enable RAM (SDMAARM3_CHNENBL38) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_029C Channel Enable RAM (SDMAARM3_CHNENBL39) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_02A0 Channel Enable RAM (SDMAARM3_CHNENBL40) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_02A4 Channel Enable RAM (SDMAARM3_CHNENBL41) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_02A8 Channel Enable RAM (SDMAARM3_CHNENBL42) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_02AC Channel Enable RAM (SDMAARM3_CHNENBL43) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_02B0 Channel Enable RAM (SDMAARM3_CHNENBL44) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_02B4 Channel Enable RAM (SDMAARM3_CHNENBL45) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1204 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.28/
302B_02B8 Channel Enable RAM (SDMAARM3_CHNENBL46) 32 R/W 0000_0000h
1232
7.2.6.28/
302B_02BC Channel Enable RAM (SDMAARM3_CHNENBL47) 32 R/W 0000_0000h
1232
SDMA DONE0 Configuration 7.2.6.29/
302B_1000 32 R/W 1F1F_1F1Fh
(SDMAARM3_DONE0_CONFIG) 1232
SDMA DONE1 Configuration 7.2.6.30/
302B_1004 32 R/W 1F1F_1F1Fh
(SDMAARM3_DONE1_CONFIG) 1234
7.2.6.1/
302C_0000 Arm platform Channel 0 Pointer (SDMAARM2_MC0PTR) 32 R/W 0000_0000h
1215
7.2.6.2/
302C_0004 Channel Interrupts (SDMAARM2_INTR) 32 w1c 0000_0000h
1215
7.2.6.3/
302C_0008 Channel Stop/Channel Status (SDMAARM2_STOP_STAT) 32 w1c 0000_0000h
1215
7.2.6.4/
302C_000C Channel Start (SDMAARM2_HSTART) 32 R/W 0000_0000h
1216
7.2.6.5/
302C_0010 Channel Event Override (SDMAARM2_EVTOVR) 32 R/W 0000_0000h
1216
7.2.6.6/
302C_0014 Channel BP Override (SDMAARM2_DSPOVR) 32 R/W FFFF_FFFFh
1217
7.2.6.7/
302C_0018 Channel Arm platform Override (SDMAARM2_HOSTOVR) 32 R/W 0000_0000h
1217
7.2.6.8/
302C_001C Channel Event Pending (SDMAARM2_EVTPEND) 32 w1c 0000_0000h
1217
7.2.6.9/
302C_0024 Reset Register (SDMAARM2_RESET) 32 R 0000_0000h
1218
7.2.6.10/
302C_0028 DMA Request Error Register (SDMAARM2_EVTERR) 32 R 0000_0000h
1219
Channel Arm platform Interrupt Mask 7.2.6.11/
302C_002C 32 R/W 0000_0000h
(SDMAARM2_INTRMASK) 1219
7.2.6.12/
302C_0030 Schedule Status (SDMAARM2_PSW) 32 R 0000_0000h
1220
7.2.6.13/
302C_0034 DMA Request Error Register (SDMAARM2_EVTERRDBG) 32 R 0000_0000h
1220
7.2.6.14/
302C_0038 Configuration Register (SDMAARM2_CONFIG) 32 R/W 0000_0003h
1221
7.2.6.15/
302C_003C SDMA LOCK (SDMAARM2_SDMA_LOCK) 32 R/W 0000_0000h
1222
7.2.6.16/
302C_0040 OnCE Enable (SDMAARM2_ONCE_ENB) 32 R/W 0000_0000h
1223
7.2.6.17/
302C_0044 OnCE Data Register (SDMAARM2_ONCE_DATA) 32 R/W 0000_0000h
1223
7.2.6.18/
302C_0048 OnCE Instruction Register (SDMAARM2_ONCE_INSTR) 32 R/W 0000_0000h
1224
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1205
Smart Direct Memory Access Controller (SDMA)

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.19/
302C_004C OnCE Status Register (SDMAARM2_ONCE_STAT) 32 R 0000_E000h
1224
7.2.6.20/
302C_0050 OnCE Command Register (SDMAARM2_ONCE_CMD) 32 R/W 0000_0000h
1226
Illegal Instruction Trap Address 7.2.6.21/
302C_0058 32 R/W 0000_0001h
(SDMAARM2_ILLINSTADDR) 1226
7.2.6.22/
302C_005C Channel 0 Boot Address (SDMAARM2_CHN0ADDR) 32 R/W 0000_0050h
1227
7.2.6.23/
302C_0060 DMA Requests (SDMAARM2_EVT_MIRROR) 32 R 0000_0000h
1228
7.2.6.24/
302C_0064 DMA Requests 2 (SDMAARM2_EVT_MIRROR2) 32 R 0000_0000h
1228
Cross-Trigger Events Configuration Register 1 7.2.6.25/
302C_0070 32 R/W 0000_0000h
(SDMAARM2_XTRIG_CONF1) 1229
Cross-Trigger Events Configuration Register 2 7.2.6.26/
302C_0074 32 R/W 0000_0000h
(SDMAARM2_XTRIG_CONF2) 1230
7.2.6.27/
302C_0100 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI0) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_0104 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI1) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_0108 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI2) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_010C Channel Priority Registers (SDMAARM2_SDMA_CHNPRI3) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_0110 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI4) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_0114 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI5) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_0118 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI6) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_011C Channel Priority Registers (SDMAARM2_SDMA_CHNPRI7) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_0120 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI8) 32 R/W 0000_0000h
1231
7.2.6.27/
302C_0124 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI9) 32 R/W 0000_0000h
1231
Channel Priority Registers 7.2.6.27/
302C_0128 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI10) 1231
Channel Priority Registers 7.2.6.27/
302C_012C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI11) 1231
Channel Priority Registers 7.2.6.27/
302C_0130 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI12) 1231
Channel Priority Registers 7.2.6.27/
302C_0134 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI13) 1231
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1206 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Channel Priority Registers 7.2.6.27/
302C_0138 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI14) 1231
Channel Priority Registers 7.2.6.27/
302C_013C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI15) 1231
Channel Priority Registers 7.2.6.27/
302C_0140 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI16) 1231
Channel Priority Registers 7.2.6.27/
302C_0144 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI17) 1231
Channel Priority Registers 7.2.6.27/
302C_0148 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI18) 1231
Channel Priority Registers 7.2.6.27/
302C_014C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI19) 1231
Channel Priority Registers 7.2.6.27/
302C_0150 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI20) 1231
Channel Priority Registers 7.2.6.27/
302C_0154 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI21) 1231
Channel Priority Registers 7.2.6.27/
302C_0158 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI22) 1231
Channel Priority Registers 7.2.6.27/
302C_015C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI23) 1231
Channel Priority Registers 7.2.6.27/
302C_0160 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI24) 1231
Channel Priority Registers 7.2.6.27/
302C_0164 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI25) 1231
Channel Priority Registers 7.2.6.27/
302C_0168 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI26) 1231
Channel Priority Registers 7.2.6.27/
302C_016C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI27) 1231
Channel Priority Registers 7.2.6.27/
302C_0170 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI28) 1231
Channel Priority Registers 7.2.6.27/
302C_0174 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI29) 1231
Channel Priority Registers 7.2.6.27/
302C_0178 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI30) 1231
Channel Priority Registers 7.2.6.27/
302C_017C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI31) 1231
7.2.6.28/
302C_0200 Channel Enable RAM (SDMAARM2_CHNENBL0) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0204 Channel Enable RAM (SDMAARM2_CHNENBL1) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0208 Channel Enable RAM (SDMAARM2_CHNENBL2) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_020C Channel Enable RAM (SDMAARM2_CHNENBL3) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1207
Smart Direct Memory Access Controller (SDMA)

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.28/
302C_0210 Channel Enable RAM (SDMAARM2_CHNENBL4) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0214 Channel Enable RAM (SDMAARM2_CHNENBL5) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0218 Channel Enable RAM (SDMAARM2_CHNENBL6) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_021C Channel Enable RAM (SDMAARM2_CHNENBL7) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0220 Channel Enable RAM (SDMAARM2_CHNENBL8) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0224 Channel Enable RAM (SDMAARM2_CHNENBL9) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0228 Channel Enable RAM (SDMAARM2_CHNENBL10) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_022C Channel Enable RAM (SDMAARM2_CHNENBL11) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0230 Channel Enable RAM (SDMAARM2_CHNENBL12) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0234 Channel Enable RAM (SDMAARM2_CHNENBL13) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0238 Channel Enable RAM (SDMAARM2_CHNENBL14) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_023C Channel Enable RAM (SDMAARM2_CHNENBL15) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0240 Channel Enable RAM (SDMAARM2_CHNENBL16) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0244 Channel Enable RAM (SDMAARM2_CHNENBL17) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0248 Channel Enable RAM (SDMAARM2_CHNENBL18) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_024C Channel Enable RAM (SDMAARM2_CHNENBL19) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0250 Channel Enable RAM (SDMAARM2_CHNENBL20) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0254 Channel Enable RAM (SDMAARM2_CHNENBL21) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0258 Channel Enable RAM (SDMAARM2_CHNENBL22) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_025C Channel Enable RAM (SDMAARM2_CHNENBL23) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0260 Channel Enable RAM (SDMAARM2_CHNENBL24) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0264 Channel Enable RAM (SDMAARM2_CHNENBL25) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1208 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.28/
302C_0268 Channel Enable RAM (SDMAARM2_CHNENBL26) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_026C Channel Enable RAM (SDMAARM2_CHNENBL27) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0270 Channel Enable RAM (SDMAARM2_CHNENBL28) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0274 Channel Enable RAM (SDMAARM2_CHNENBL29) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0278 Channel Enable RAM (SDMAARM2_CHNENBL30) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_027C Channel Enable RAM (SDMAARM2_CHNENBL31) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0280 Channel Enable RAM (SDMAARM2_CHNENBL32) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0284 Channel Enable RAM (SDMAARM2_CHNENBL33) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0288 Channel Enable RAM (SDMAARM2_CHNENBL34) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_028C Channel Enable RAM (SDMAARM2_CHNENBL35) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0290 Channel Enable RAM (SDMAARM2_CHNENBL36) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0294 Channel Enable RAM (SDMAARM2_CHNENBL37) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_0298 Channel Enable RAM (SDMAARM2_CHNENBL38) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_029C Channel Enable RAM (SDMAARM2_CHNENBL39) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02A0 Channel Enable RAM (SDMAARM2_CHNENBL40) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02A4 Channel Enable RAM (SDMAARM2_CHNENBL41) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02A8 Channel Enable RAM (SDMAARM2_CHNENBL42) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02AC Channel Enable RAM (SDMAARM2_CHNENBL43) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02B0 Channel Enable RAM (SDMAARM2_CHNENBL44) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02B4 Channel Enable RAM (SDMAARM2_CHNENBL45) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02B8 Channel Enable RAM (SDMAARM2_CHNENBL46) 32 R/W 0000_0000h
1232
7.2.6.28/
302C_02BC Channel Enable RAM (SDMAARM2_CHNENBL47) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1209
Smart Direct Memory Access Controller (SDMA)

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SDMA DONE0 Configuration 7.2.6.29/
302C_1000 32 R/W 1F1F_1F1Fh
(SDMAARM2_DONE0_CONFIG) 1232
SDMA DONE1 Configuration 7.2.6.30/
302C_1004 32 R/W 1F1F_1F1Fh
(SDMAARM2_DONE1_CONFIG) 1234
7.2.6.1/
30BD_0000 Arm platform Channel 0 Pointer (SDMAARM1_MC0PTR) 32 R/W 0000_0000h
1215
7.2.6.2/
30BD_0004 Channel Interrupts (SDMAARM1_INTR) 32 w1c 0000_0000h
1215
7.2.6.3/
30BD_0008 Channel Stop/Channel Status (SDMAARM1_STOP_STAT) 32 w1c 0000_0000h
1215
7.2.6.4/
30BD_000C Channel Start (SDMAARM1_HSTART) 32 R/W 0000_0000h
1216
7.2.6.5/
30BD_0010 Channel Event Override (SDMAARM1_EVTOVR) 32 R/W 0000_0000h
1216
7.2.6.6/
30BD_0014 Channel BP Override (SDMAARM1_DSPOVR) 32 R/W FFFF_FFFFh
1217
7.2.6.7/
30BD_0018 Channel Arm platform Override (SDMAARM1_HOSTOVR) 32 R/W 0000_0000h
1217
7.2.6.8/
30BD_001C Channel Event Pending (SDMAARM1_EVTPEND) 32 w1c 0000_0000h
1217
7.2.6.9/
30BD_0024 Reset Register (SDMAARM1_RESET) 32 R 0000_0000h
1218
7.2.6.10/
30BD_0028 DMA Request Error Register (SDMAARM1_EVTERR) 32 R 0000_0000h
1219
Channel Arm platform Interrupt Mask 7.2.6.11/
30BD_002C 32 R/W 0000_0000h
(SDMAARM1_INTRMASK) 1219
7.2.6.12/
30BD_0030 Schedule Status (SDMAARM1_PSW) 32 R 0000_0000h
1220
7.2.6.13/
30BD_0034 DMA Request Error Register (SDMAARM1_EVTERRDBG) 32 R 0000_0000h
1220
7.2.6.14/
30BD_0038 Configuration Register (SDMAARM1_CONFIG) 32 R/W 0000_0003h
1221
7.2.6.15/
30BD_003C SDMA LOCK (SDMAARM1_SDMA_LOCK) 32 R/W 0000_0000h
1222
7.2.6.16/
30BD_0040 OnCE Enable (SDMAARM1_ONCE_ENB) 32 R/W 0000_0000h
1223
7.2.6.17/
30BD_0044 OnCE Data Register (SDMAARM1_ONCE_DATA) 32 R/W 0000_0000h
1223
7.2.6.18/
30BD_0048 OnCE Instruction Register (SDMAARM1_ONCE_INSTR) 32 R/W 0000_0000h
1224
7.2.6.19/
30BD_004C OnCE Status Register (SDMAARM1_ONCE_STAT) 32 R 0000_E000h
1224
7.2.6.20/
30BD_0050 OnCE Command Register (SDMAARM1_ONCE_CMD) 32 R/W 0000_0000h
1226
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1210 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Illegal Instruction Trap Address 7.2.6.21/
30BD_0058 32 R/W 0000_0001h
(SDMAARM1_ILLINSTADDR) 1226
7.2.6.22/
30BD_005C Channel 0 Boot Address (SDMAARM1_CHN0ADDR) 32 R/W 0000_0050h
1227
7.2.6.23/
30BD_0060 DMA Requests (SDMAARM1_EVT_MIRROR) 32 R 0000_0000h
1228
7.2.6.24/
30BD_0064 DMA Requests 2 (SDMAARM1_EVT_MIRROR2) 32 R 0000_0000h
1228
Cross-Trigger Events Configuration Register 1 7.2.6.25/
30BD_0070 32 R/W 0000_0000h
(SDMAARM1_XTRIG_CONF1) 1229
Cross-Trigger Events Configuration Register 2 7.2.6.26/
30BD_0074 32 R/W 0000_0000h
(SDMAARM1_XTRIG_CONF2) 1230
7.2.6.27/
30BD_0100 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI0) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_0104 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI1) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_0108 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI2) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_010C Channel Priority Registers (SDMAARM1_SDMA_CHNPRI3) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_0110 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI4) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_0114 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI5) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_0118 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI6) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_011C Channel Priority Registers (SDMAARM1_SDMA_CHNPRI7) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_0120 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI8) 32 R/W 0000_0000h
1231
7.2.6.27/
30BD_0124 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI9) 32 R/W 0000_0000h
1231
Channel Priority Registers 7.2.6.27/
30BD_0128 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI10) 1231
Channel Priority Registers 7.2.6.27/
30BD_012C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI11) 1231
Channel Priority Registers 7.2.6.27/
30BD_0130 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI12) 1231
Channel Priority Registers 7.2.6.27/
30BD_0134 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI13) 1231
Channel Priority Registers 7.2.6.27/
30BD_0138 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI14) 1231
Channel Priority Registers 7.2.6.27/
30BD_013C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI15) 1231
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1211
Smart Direct Memory Access Controller (SDMA)

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Channel Priority Registers 7.2.6.27/
30BD_0140 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI16) 1231
Channel Priority Registers 7.2.6.27/
30BD_0144 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI17) 1231
Channel Priority Registers 7.2.6.27/
30BD_0148 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI18) 1231
Channel Priority Registers 7.2.6.27/
30BD_014C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI19) 1231
Channel Priority Registers 7.2.6.27/
30BD_0150 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI20) 1231
Channel Priority Registers 7.2.6.27/
30BD_0154 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI21) 1231
Channel Priority Registers 7.2.6.27/
30BD_0158 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI22) 1231
Channel Priority Registers 7.2.6.27/
30BD_015C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI23) 1231
Channel Priority Registers 7.2.6.27/
30BD_0160 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI24) 1231
Channel Priority Registers 7.2.6.27/
30BD_0164 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI25) 1231
Channel Priority Registers 7.2.6.27/
30BD_0168 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI26) 1231
Channel Priority Registers 7.2.6.27/
30BD_016C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI27) 1231
Channel Priority Registers 7.2.6.27/
30BD_0170 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI28) 1231
Channel Priority Registers 7.2.6.27/
30BD_0174 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI29) 1231
Channel Priority Registers 7.2.6.27/
30BD_0178 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI30) 1231
Channel Priority Registers 7.2.6.27/
30BD_017C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI31) 1231
7.2.6.28/
30BD_0200 Channel Enable RAM (SDMAARM1_CHNENBL0) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0204 Channel Enable RAM (SDMAARM1_CHNENBL1) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0208 Channel Enable RAM (SDMAARM1_CHNENBL2) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_020C Channel Enable RAM (SDMAARM1_CHNENBL3) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0210 Channel Enable RAM (SDMAARM1_CHNENBL4) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0214 Channel Enable RAM (SDMAARM1_CHNENBL5) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1212 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.28/
30BD_0218 Channel Enable RAM (SDMAARM1_CHNENBL6) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_021C Channel Enable RAM (SDMAARM1_CHNENBL7) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0220 Channel Enable RAM (SDMAARM1_CHNENBL8) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0224 Channel Enable RAM (SDMAARM1_CHNENBL9) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0228 Channel Enable RAM (SDMAARM1_CHNENBL10) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_022C Channel Enable RAM (SDMAARM1_CHNENBL11) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0230 Channel Enable RAM (SDMAARM1_CHNENBL12) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0234 Channel Enable RAM (SDMAARM1_CHNENBL13) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0238 Channel Enable RAM (SDMAARM1_CHNENBL14) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_023C Channel Enable RAM (SDMAARM1_CHNENBL15) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0240 Channel Enable RAM (SDMAARM1_CHNENBL16) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0244 Channel Enable RAM (SDMAARM1_CHNENBL17) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0248 Channel Enable RAM (SDMAARM1_CHNENBL18) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_024C Channel Enable RAM (SDMAARM1_CHNENBL19) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0250 Channel Enable RAM (SDMAARM1_CHNENBL20) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0254 Channel Enable RAM (SDMAARM1_CHNENBL21) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0258 Channel Enable RAM (SDMAARM1_CHNENBL22) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_025C Channel Enable RAM (SDMAARM1_CHNENBL23) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0260 Channel Enable RAM (SDMAARM1_CHNENBL24) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0264 Channel Enable RAM (SDMAARM1_CHNENBL25) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0268 Channel Enable RAM (SDMAARM1_CHNENBL26) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_026C Channel Enable RAM (SDMAARM1_CHNENBL27) 32 R/W 0000_0000h
1232
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1213
Smart Direct Memory Access Controller (SDMA)

SDMAARM memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.6.28/
30BD_0270 Channel Enable RAM (SDMAARM1_CHNENBL28) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0274 Channel Enable RAM (SDMAARM1_CHNENBL29) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0278 Channel Enable RAM (SDMAARM1_CHNENBL30) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_027C Channel Enable RAM (SDMAARM1_CHNENBL31) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0280 Channel Enable RAM (SDMAARM1_CHNENBL32) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0284 Channel Enable RAM (SDMAARM1_CHNENBL33) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0288 Channel Enable RAM (SDMAARM1_CHNENBL34) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_028C Channel Enable RAM (SDMAARM1_CHNENBL35) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0290 Channel Enable RAM (SDMAARM1_CHNENBL36) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0294 Channel Enable RAM (SDMAARM1_CHNENBL37) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_0298 Channel Enable RAM (SDMAARM1_CHNENBL38) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_029C Channel Enable RAM (SDMAARM1_CHNENBL39) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02A0 Channel Enable RAM (SDMAARM1_CHNENBL40) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02A4 Channel Enable RAM (SDMAARM1_CHNENBL41) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02A8 Channel Enable RAM (SDMAARM1_CHNENBL42) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02AC Channel Enable RAM (SDMAARM1_CHNENBL43) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02B0 Channel Enable RAM (SDMAARM1_CHNENBL44) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02B4 Channel Enable RAM (SDMAARM1_CHNENBL45) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02B8 Channel Enable RAM (SDMAARM1_CHNENBL46) 32 R/W 0000_0000h
1232
7.2.6.28/
30BD_02BC Channel Enable RAM (SDMAARM1_CHNENBL47) 32 R/W 0000_0000h
1232
SDMA DONE0 Configuration 7.2.6.29/
30BD_1000 32 R/W 1F1F_1F1Fh
(SDMAARM1_DONE0_CONFIG) 1232
SDMA DONE1 Configuration 7.2.6.30/
30BD_1004 32 R/W 1F1F_1F1Fh
(SDMAARM1_DONE1_CONFIG) 1234

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1214 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.6.1 Arm platform Channel 0 Pointer (SDMAARMx_MC0PTR)

Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MC0PTR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_MC0PTR field descriptions

Field Description
MC0PTR Channel 0 Pointer contains the 32-bit address, in Arm platform memory, of channel 0 control block (the
boot channel). Appendix A fully describes the SDMA Application Programming Interface (API). The Arm
platform has a read/write access and the SDMA has a read-only access.

7.2.6.2 Channel Interrupts (SDMAARMx_INTR)

Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R HI[31:0]
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_INTR field descriptions

Field Description
HI[31:0] The Arm platform Interrupts register contains the 32 HI[i] bits. If any bit is set, it will cause an interrupt to
the Arm platform. This register is a "write-ones" register to the Arm platform. When the Arm platform sets a
bit in this register the corresponding HI[i] bit is cleared. The interrupt service routine should clear individual
channel bits when their interrupts are serviced, failure to do so will cause continuous interrupts. The
SDMA is responsible for setting the HI[i] bit corresponding to the current channel when the corresponding
done instruction is executed.

7.2.6.3 Channel Stop/Channel Status (SDMAARMx_STOP_STAT)

Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R HE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1215
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_STOP_STAT field descriptions

Field Description
HE This 32-bit register gives access to the Arm platform Enable bits. There is one bit for every channel. This
register is a "write-ones" register to the Arm platform. When the Arm platform writes 1 in bit i of this
register, it clears the HE[i] and HSTART[i] bits. Reading this register yields the current state of the HE[i]
bits.

7.2.6.4 Channel Start (SDMAARMx_HSTART)

Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R HSTART_HE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_HSTART field descriptions

Field Description
HSTART_HE The HSTART_HE registers are 32 bits wide with one bit for every channel. When a bit is written to 1, it
enables the corresponding channel. Two physical registers are accessed with that address (HSTART and
HE), which enables the Arm platform to trigger a channel a second time before the first trigger is
processed.
• This register is a "write-ones" register to the Arm platform. Neither HSTART[i] bit can be set while
the corresponding HE[i] bit is cleared.
• When the Arm platform tries to set the HSTART[i] bit by writing a one (if the corresponding HE[i] bit
is clear), the bit in the HSTART[i] register will remain cleared and the HE[i] bit will be set.
• If the corresponding HE[i] bit was already set, the HSTART[i] bit will be set. The next time the SDMA
channel i attempts to clear the HE[i] bit by means of a done instruction, the bit in the HSTART[i]
register will be cleared and the HE[i] bit will take the old value of the HSTART[i] bit.
• Reading this register yields the current state of the HSTART[i] bits. This mechanism enables the
Arm platform to pipeline two HSTART commands per channel.

7.2.6.5 Channel Event Override (SDMAARMx_EVTOVR)

Address: Base address + 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_EVTOVR field descriptions

Field Description
EO The Channel Event Override register contains the 32 EO[i] bits. A bit set in this register causes the SDMA
to ignore DMA requests when scheduling the corresponding channel.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1216 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.6.6 Channel BP Override (SDMAARMx_DSPOVR)

Address: Base address + 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SDMAARMx_DSPOVR field descriptions

Field Description
DO This register is reserved. All DO bits should be set to the reset value of 1. A setting of 0 will prevent SDMA
channels from starting according to the condition described in Runnable Channels Evaluation.

0 - Reserved
1 - Reset value.

7.2.6.7 Channel Arm platform Override (SDMAARMx_HOSTOVR)

Address: Base address + 18h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
HO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_HOSTOVR field descriptions

Field Description
HO The Channel Arm platform Override register contains the 32 HO[i] bits. A bit set in this register causes the
SDMA to ignore the Arm platform enable bit (HE) when scheduling the corresponding channel.

7.2.6.8 Channel Event Pending (SDMAARMx_EVTPEND)

Address: Base address + 1Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R EP
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_EVTPEND field descriptions

Field Description
EP The Channel Event Pending register contains the 32 EP[i] bits. Reading this register enables the Arm
platform to determine what channels are pending after the reception of a DMA request.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1217
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_EVTPEND field descriptions (continued)

Field Description
• Setting a bit in this register causes the SDMA to reevaluate scheduling as if a DMA request mapped
on this channel had occurred. This is useful for starting up channels, so that initialization is done
before awaiting the first request. The scheduler can also set bits in the EVTPEND register according
to the received DMA requests.
• The EP[i] bit may be cleared by the done instruction when running the channel i script. This a "write-
ones" mechanism: Writing a '0' does not clear the corresponding bit.

7.2.6.9 Reset Register (SDMAARMx_RESET)

Address: Base address + 24h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESCHED

RESET
R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_RESET field descriptions

Field Description
31–2 This read-only field is reserved and always has the value 0.
Reserved
1 When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction. This
RESCHED enables the Arm platform to recover from a runaway script on a channel by clearing its HE[i] bit via the
STOP register, and then forcing a reschedule via the RESCHED bit. The RESCHED bit is cleared when
the context switch starts.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1218 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARMx_RESET field descriptions (continued)

Field Description
0 When set, this bit causes the SDMA to be held in a software reset. The internal reset signal is held low 16
RESET cycles; the RESET bit is automatically cleared when the internal reset signal rises.

7.2.6.10 DMA Request Error Register (SDMAARMx_EVTERR)

Address: Base address + 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CHNERR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_EVTERR field descriptions

Field Description
CHNERR This register is used by the SDMA to warn the Arm platform when an incoming DMA request was detected
and it triggers a channel that is already pending or being serviced. This probably means there is an
overflow of data for that channel.
• An interrupt is sent to the Arm platform if the corresponding channel bit is set in the INTRMASK
register.
• This is a "write-ones" register for the scheduler. It is only able to set the flags. The flags are cleared
when the register is read by the Arm platform or during SDMA reset.
• The CHNERR[i] bit is set when a DMA request that triggers channel i is received through the
corresponding input pins and the EP[i] bit is already set; the EVTERR[i] bit is unaffected if the Arm
platform tries to set the EP[i] bit, whereas, that EP[i] bit is already set.

7.2.6.11 Channel Arm platform Interrupt Mask

(SDMAARMx_INTRMASK)
Address: Base address + 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
HIMASK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_INTRMASK field descriptions

Field Description
HIMASK The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit HIMASK[i] is set, the HI[i] bit
is set and an interrupt is sent to the Arm platform when a DMA request error is detected on channel i (for
example, EVTERR[i] is set).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1219
Smart Direct Memory Access Controller (SDMA)

7.2.6.12 Schedule Status (SDMAARMx_PSW)

Address: Base address + 30h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 NCP[2:0] NCR[4:0] CCP[2:0] CCR[4:0]

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_PSW field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
15–13 The Next Channel Priority gives the next pending channel priority. When the priority is 0, it means there is
NCP[2:0] no pending channel and the NCR value has no meaning.

0 No running channel
1 Active channel priority
12–8 The Next Channel Register indicates the number of the next scheduled pending channel with the highest
NCR[4:0] priority.
7–4 The Current Channel Priority indicates the priority of the current active channel. When the priority is 0, no
CCP[2:0] channel is running: The SDMA is idle and the CCR value has no meaning. In the case that the SDMA has
finished running the channel and has entered sleep state, CCP will indicate the priority of previous running
channel.

0 No running channel
1 Active channel priority
CCR[4:0] The Current Channel Register indicates the number of the channel that is being executed by the SDMA.
SDMA. In the case that the SDMA has finished running the channel and has entered sleep state, CCR will
indicate the previous running channel.

7.2.6.13 DMA Request Error Register (SDMAARMx_EVTERRDBG)

Address: Base address + 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CHNERR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_EVTERRDBG field descriptions

Field Description
CHNERR This register is the same as EVTERR, except reading it does not clear its contents. This address is meant
to be used in debug mode. The Arm platform OnCE may check this register value without modifying it.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1220 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.6.14 Configuration Register (SDMAARMx_CONFIG)

Address: Base address + 38h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0
DSPDMA

RTDOBS

ACR CSM
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

SDMAARMx_CONFIG field descriptions

Field Description
31–13 This read-only field is reserved and always has the value 0.
Reserved
12 This bit's function is reserved and should be configured as zero.
DSPDMA
0 - Reset Value
1 - Reserved
11 Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power
RTDOBS consumption.

0 RTD pins disabled

1 RTD pins enabled
10–5 This read-only field is reserved and always has the value 0.
Reserved
4 Arm platform DMA / SDMA Core Clock Ratio. Selects the clock ratio between Arm platform DMA
ACR interfaces (burst DMA and peripheral DMA) and the internal SDMA core clock. The frequency selection is
determined separately by the chip clock controller. This bit has to match the configuration of the chip clock
controller that generates the clocks used in the SDMA.

0 Arm platform DMA interface frequency equals twice core frequency

1 Arm platform DMA interface frequency equals core frequency
3–2 This read-only field is reserved and always has the value 0.
Reserved
CSM Selects the Context Switch Mode. The Arm platform has a read/write access. The SDMA cannot modify
that register. The value at reset is 3, which selects the dynamic context switch by default. That register can
be modified at anytime but the new context switch configuration will only be taken into account at the start
of the next restore phase.
NOTE: The first call to SDMA's channel 0 Bootload script after reset should use static context switch mode
to ensure the context RAM for channel 0 is initialized in the channel SAVE Phase. After Channel 0 is run
once, then any of the dynamic context modes can be used.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1221
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_CONFIG field descriptions (continued)

Field Description
0 static
1 dynamic low power
2 dynamic with no loop
3 dynamic

7.2.6.15 SDMA LOCK (SDMAARMx_SDMA_LOCK)

Address: Base address + 3Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SRESET_LOCK_
R 0

LOCK
CLR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_SDMA_LOCK field descriptions

Field Description
31–2 This read-only field is reserved and always has the value 0.
Reserved
1 The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing
SRESET_LOCK_ to the RESET register. This bit cannot be changed if LOCK=1. SREST_LOCK_CLR is cleared by
CLR conditions that clear the LOCK bit.

0 Software Reset does not clear the LOCK bit.

1 Software Reset clears the LOCK bit.
0 The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts
LOCK and through the OnCE interface under Arm platform control.
The LOCK bit is set:
• The SDMA_LOCK, ONCE_ENB,CH0ADDR, and ILLINSTADDR registers cannot be written. These
registers can be read, but writes are ignored.
• SDMA software executing out of ROM or RAM may check the LOCK bit in the LOCK register Lock
Status Register (SDMACORE_SDMA_LOCK) to determine if certain operations are allowed, such
as up-loading new scripts.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1222 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARMx_SDMA_LOCK field descriptions (continued)

Field Description
Once the LOCK bit is set to 1, only a reset can clear it. The LOCK bit is cleared by a hardware reset.
LOCK is cleared by a software reset only if SRESET_LOCK_CLR is set.

0 LOCK disengaged.
1 LOCK enabled.

7.2.6.16 OnCE Enable (SDMAARMx_ONCE_ENB)

Address: Base address + 40h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ENB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_ONCE_ENB field descriptions

Field Description
31–1 This read-only field is reserved and always has the value 0.
Reserved
0 The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are
ENB accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the Arm
platform through the addresses described, as follows.
• After reset, the OnCE registers are accessed through the JTAG interface.
• Writing a 1 to ENB enables the Arm platform to access the ONCE_* as any other SDMA control
register.
• When cleared (0), all the ONCE_xxx registers cannot be written.

The value of ENB cannot be changed if the LOCK bit in the SDMA_LOCK register is set.

7.2.6.17 OnCE Data Register (SDMAARMx_ONCE_DATA)

Address: Base address + 44h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1223
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_ONCE_DATA field descriptions

Field Description
DATA Data register of the OnCE JTAG controller. Refer to OnCE and Real-Time Debug for information on this
register.

7.2.6.18 OnCE Instruction Register (SDMAARMx_ONCE_INSTR)

Address: Base address + 48h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INSTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_ONCE_INSTR field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
INSTR Instruction register of the OnCE JTAG controller. Refer to OnCE and Real-Time Debug for information on
this register.

7.2.6.19 OnCE Status Register (SDMAARMx_ONCE_STAT)

Address: Base address + 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PST[3:0] RCV EDR ODR SWB MST 0 ECDR

W

Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_ONCE_STAT field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
15–12 The Processor Status bits reflect the state of the SDMA RISC engine. Its states are as follows:
PST[3:0] • The "Program" state is the usual instruction execution cycle.
• The "Data" state is inserted when there are wait-states during a load or a store on the data bus (ld or
st).
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1224 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARMx_ONCE_STAT field descriptions (continued)

Field Description
• The "Change of Flow" state is the second cycle of any instruction that breaks the sequence of
instructions (jumps and channel switching instructions).
• The "Change of Flow in Loop" state is used when an error causes a hardware loop exit.
• The "Debug" state means the SDMA is in debug mode.
• The "Functional Unit" state is inserted when there are wait-states during a load or a store on the
functional units bus (ldf or stf).
• In "Sleep" modes, no script is running (this is the RISC engine idle state). The "after Reset" is
slightly different because no context restoring phase will happen when a channel is triggered: The
script located at address 0 will be executed (boot operation).
• The "in Sleep" states are the same as above except they do not have any corresponding channel:
They are used when entering debug mode after reset. The reason is that it is necessary to return to
the "Sleep after Reset" state when leaving debug mode.

0 Program
1 Data
2 Change of Flow
3 Change of Flow in Loop
4 Debug
5 Functional Unit
6 Sleep
7 Save
8 Program in Sleep
9 Data in Sleep
10 Change of Flow in Sleep
11 Change Flow in Loop in Sleep
12 Debug in Sleep
13 Functional Unit in Sleep
14 Sleep after Reset
15 Restore
11 After each write access to the real time buffer (RTB), the RCV bit is set. This bit is cleared after execution
RCV of an rbuffer command and on a JTAG reset.
10 This flag is raised when the SDMA has entered debug mode after an external debug request.
EDR
9 This flag is raised when the SDMA has entered debug mode after a OnCE debug request.
ODR
8 This flag is raised when the SDMA has entered debug mode after a software breakpoint.
SWB
7 This flag is raised when the OnCE is controlled from the Arm platform peripheral interface.
MST
0 The JTAG interface controls the OnCE.
1 The Arm platform peripheral interface controls the OnCE.
6–3 This read-only field is reserved and always has the value 0.
Reserved
ECDR Event Cell Debug Request. If the debug request comes from the event cell, the reason for entering debug
mode is given by the EDR bits. If all three bits of the EDR are reset, then it did not generate any debug
request. If the cell did generate a debug request, then at least one of the EDR bits is set (the meaning of
the encoding is given below). The encoding of the EDR bits is useful to find out more precisely why the
debug request was generated. A debug request from an event cell is generated for a specific combination
of the addra_cond, addrb_cond, and data_cond conditions. The value of those fields is given by the EDR
bits.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1225
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_ONCE_STAT field descriptions (continued)

Field Description
0 1 matched addra_cond
1 1 matched addrb_cond
2 1 matched data_cond

7.2.6.20 OnCE Command Register (SDMAARMx_ONCE_CMD)

Address: Base address + 50h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CMD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_ONCE_CMD field descriptions

Field Description
31–4 This read-only field is reserved and always has the value 0.
Reserved
CMD Writing to this register will cause the OnCE to execute the command that is written. When needed, the
ONCE_DATA and ONCE_INSTR registers should be loaded with the correct value before writing the
command to that register. For a list of the OnCE commands and their usage, see OnCE and Real-Time
Debug.

NOTE: 7-15 reserved

0 rstatus
1 dmov
2 exec_once
3 run_core
4 exec_core
5 debug_rqst
6 rbuffer

7.2.6.21 Illegal Instruction Trap Address (SDMAARMx_ILLINSTADDR)

Address: Base address + 58h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ILLINSTADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1226 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARMx_ILLINSTADDR field descriptions

Field Description
31–14 This read-only field is reserved and always has the value 0.
Reserved
ILLINSTADDR The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is
executed. It is 0x0001 after reset.
The value of ILLINSTADDR cannot be changed if the LOCK bit in the SDMA_LOCK register is set.

7.2.6.22 Channel 0 Boot Address (SDMAARMx_CHN0ADDR)

Address: Base address + 5Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0
SMSZ

CHN0ADDR
W

Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0

SDMAARMx_CHN0ADDR field descriptions

Field Description
31–15 This read-only field is reserved and always has the value 0.
Reserved
14 The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel
SMSZ context. After reset, it is equal to 0, which defines a RAM space of 24 words for each channel. All of this
area stores the channel context. By setting this bit, 32 words are reserved for every channel context,
which gives eight additional words that can be used by the channel script to store any type of data. Those
words are never erased by the context switching mechanism.
The value of SMSZ cannot be changed if the LOCK bit in the SDMA_LOCK register is set.

0 24 words per context

1 32 words per context
CHN0ADDR This 14-bit register is used by the boot code of the SDMA. After reset, it points to the standard boot routine
in ROM (channel 0 routine). By changing this address, you can perform a boot sequence with your own
routine. The very first instructions of the boot code fetch the contents of this register (it is also mapped in
the SDMA memory space) and jump to the given address. The reset value is 0x0050 (decimal 80).
The value of CHN0ADDR cannot be changed if the LOCK bit in the SDMA_LOCK register is set.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1227
Smart Direct Memory Access Controller (SDMA)

7.2.6.23 DMA Requests (SDMAARMx_EVT_MIRROR)

Address: Base address + 60h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R EVENTS
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_EVT_MIRROR field descriptions

Field Description
EVENTS This register reflects the DMA requests received by the SDMA for events 31-0. The Arm platform and the
SDMA have a read-only access. There is one bit associated with each of 32 DMA request events. This
information may be useful during debug of the blocks that generate the DMA requests. The EVT_MIRROR
register is cleared following read access.

0 DMA request event not pending

1 DMA request event pending

7.2.6.24 DMA Requests 2 (SDMAARMx_EVT_MIRROR2)

Address: Base address + 64h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 EVENTS[47:32]
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_EVT_MIRROR2 field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EVENTS[47:32] This register reflects the DMA requests received by the SDMA for events 47-32. The Arm platform and the
SDMA have a read-only access. There is one bit associated with each of DMA request events. This
information may be useful during debug of the blocks that generate the DMA requests. The
EVT_MIRROR2 register is cleared following read access.

0 - DMA request event not pending

1- DMA request event pending

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1228 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.6.25 Cross-Trigger Events Configuration Register 1

(SDMAARMx_XTRIG_CONF1)
Address: Base address + 70h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0
CNF3

CNF2
NUM3[5:0] NUM2[5:0]
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0
CNF1

CNF0
NUM1[5:0] NUM0[5:0]
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_XTRIG_CONF1 field descriptions

Field Description
31 This read-only field is reserved and always has the value 0.
Reserved
30 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF3 whether the event line pulse is generated by the reception of a DMA request or by the starting of a
channel script execution.

0 channel
1 DMA request
29–24 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM3[5:0] number i.
23 This read-only field is reserved and always has the value 0.
Reserved
22 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF2 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.

0 channel
1 DMA request
21–16 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM2[5:0] number i.
15 This read-only field is reserved and always has the value 0.
Reserved
14 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF1 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1229
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_XTRIG_CONF1 field descriptions (continued)

Field Description
0 channel
1 DMA request
13–8 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM1[5:0] number i.
7 This read-only field is reserved and always has the value 0.
Reserved
6 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF0 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.

0 channel
1 DMA request
NUM0[5:0] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
number i.

7.2.6.26 Cross-Trigger Events Configuration Register 2

(SDMAARMx_XTRIG_CONF2)
Address: Base address + 74h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 0
CNF7

CNF6

NUM7[5:0] NUM6[5:0]
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0
CNF5

CNF4

NUM5[5:0] NUM4[5:0]
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_XTRIG_CONF2 field descriptions

Field Description
31 This read-only field is reserved and always has the value 0.
Reserved
30 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF7 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.

0 channel
1 DMA request

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1230 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARMx_XTRIG_CONF2 field descriptions (continued)

Field Description
29–24 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM7[5:0] number i.
23 This read-only field is reserved and always has the value 0.
Reserved
22 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF6 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.

0 channel
1 DMA request
21–16 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM6[5:0] number i.
15 This read-only field is reserved and always has the value 0.
Reserved
14 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF5 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution

0 channel
1 DMA request
13–8 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM5[5:0] number i.
7 This read-only field is reserved and always has the value 0.
Reserved
6 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF4 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.

0 channel
1 DMA request
NUM4[5:0] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
number i.

7.2.6.27 Channel Priority Registers (SDMAARMx_SDMA_CHNPRIn)

Address: Base address + 100h offset + (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CHNPRIn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1231
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_SDMA_CHNPRIn field descriptions

Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
CHNPRIn This contains the priority of channel number n. Useful values are between 1 and 7; 0 is reserved by the
SDMA hardware to determine when there is no pending channel. Reset value is 0, which prevents the
channels from starting.

7.2.6.28 Channel Enable RAM (SDMAARMx_CHNENBLn)

Address: Base address + 200h offset + (4d × i), where i=0d to 47d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ENBLn
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMAARMx_CHNENBLn field descriptions

Field Description
ENBLn This 32-bit value selects the channels that are triggered by the DMA request number n. If ENBLn[i] is set
to 1, bit EP[i] will be set when the DMA request n is received. These 48 32-bit registers are physically
located in a RAM, with no known reset value. It is thus essential for the Arm platform to program them
before any DMA request is triggered to the SDMA, otherwise an unpredictable combination of channels
may be started.

7.2.6.29 SDMA DONE0 Configuration (SDMAARMx_DONE0_CONFIG)

Address: Base address + 1000h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE_SEL3

DONE_SEL2
SW_DONE_

SW_DONE_

R 0 0
DIS3

DIS2

CH_SEL3 CH_SEL2
W

Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DONE_SEL1

DONE_SEL0
SW_DONE_

SW_DONE_

R 0 0
DIS1

DIS0

CH_SEL1 CH_SEL0
W

Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1232 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARMx_DONE0_CONFIG field descriptions

Field Description
31 Select Done from SW or HW for channel 3
DONE_SEL3
0 HW
1 SW
30 Disable SW Done for channel 3
SW_DONE_DIS3
0 Enable
1 Disable
29 This read-only field is reserved and always has the value 0.
Reserved
28–24 Select event for channel 3 when Done is selected from HW.
CH_SEL3
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
23 Select Done from SW or HW for channel 2
DONE_SEL2
0 HW
1 SW
22 Disable SW Done for channel 2
SW_DONE_DIS2
0 Enable
1 Disable
21 This read-only field is reserved and always has the value 0.
Reserved
20–16 Select event for channel 2 when Done is selected from HW.
CH_SEL2
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
15 Select Done from SW or HW for channel 1
DONE_SEL1
0 HW
1 SW
14 Disable SW Done for channel 1
SW_DONE_DIS1
0 Enable
1 Disable
13 This read-only field is reserved and always has the value 0.
Reserved
12–8 Select event for channel 1 when Done is selected from HW.
CH_SEL1
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1233
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_DONE0_CONFIG field descriptions (continued)

Field Description
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
7 Select Done from SW or HW for channel 0
DONE_SEL0
0 HW
1 SW
6 Disable SW Done for channel 0
SW_DONE_DIS0
0 Enable
1 Disable
5 This read-only field is reserved and always has the value 0.
Reserved
CH_SEL0 Select event for channel 0 when Done is selected from HW.
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31

7.2.6.30 SDMA DONE1 Configuration (SDMAARMx_DONE1_CONFIG)

Address: Base address + 1004h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE_SEL7

DONE_SEL6
SW_DONE_

SW_DONE_

R 0 0
DIS7

DIS6

CH_SEL7 CH_SEL6
W

Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DONE_SEL5

DONE_SEL4
SW_DONE_

SW_DONE_

R 0 0
DIS5

DIS4

CH_SEL5 CH_SEL4
W

Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1234 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMAARMx_DONE1_CONFIG field descriptions

Field Description
31 Select Done from SW or HW for channel 7
DONE_SEL7
0 HW
1 SW
30 Disable SW Done for channel 7
SW_DONE_DIS7
0 Enable
1 Disable
29 This read-only field is reserved and always has the value 0.
Reserved
28–24 Select event for channel 7 when Done is selected from HW.
CH_SEL7
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
23 Select Done from SW or HW for channel 6
DONE_SEL6
0 HW
1 SW
22 Disable SW Done for channel 6
SW_DONE_DIS6
0 Enable
1 Disable
21 This read-only field is reserved and always has the value 0.
Reserved
20–16 Select event for channel 6 when Done is selected from HW.
CH_SEL6
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
15 Select Done from SW or HW for channel 5
DONE_SEL5
0 HW
1 SW
14 Disable SW Done for channel 5
SW_DONE_DIS5
0 Enable
1 Disable
13 This read-only field is reserved and always has the value 0.
Reserved
12–8 Select event for channel 5 when Done is selected from HW.
CH_SEL5
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1235
Smart Direct Memory Access Controller (SDMA)

SDMAARMx_DONE1_CONFIG field descriptions (continued)

Field Description
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
7 Select Done from SW or HW for channel 4
DONE_SEL4
0 HW
1 SW
6 Disable SW Done for channel 4
SW_DONE_DIS4
0 Enable
1 Disable
5 This read-only field is reserved and always has the value 0.
Reserved
CH_SEL4 Select event for channel 4 when Done is selected from HW.
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31

7.2.7 BP Memory Map and Control Register Definitions

The following section describes SDMA control registers available to the BP.
NOTE
These registers are physically implemented in all platforms, but
are not accessible when the SDMA BP control port is not
connected. Reset values are calculated to allow the system to
work when those registers cannot be accessed.
All registers are clocked with the SDMA clock (which means the SDMA clock must be
running when the BP wants to access any register).

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1236 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMABP memory map

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.1/
302B_0000 Channel 0 Pointer (SDMABP3_DC0PTR) 32 R/W 0000_0000h
1238
7.2.7.2/
302B_0004 Channel Interrupts (SDMABP3_INTR) 32 w1c 0000_0000h
1238
7.2.7.3/
302B_0008 Channel Stop/Channel Status (SDMABP3_STOP_STAT) 32 R/W 0000_0000h
1238
7.2.7.4/
302B_000C Channel Start (SDMABP3_DSTART) 32 R 0000_0000h
1239
7.2.7.5/
302B_0028 DMA Request Error Register (SDMABP3_EVTERR) 32 R 0000_0000h
1239
7.2.7.6/
302B_002C Channel DSP Interrupt Mask (SDMABP3_INTRMASK) 32 R/W 0000_0000h
1240
7.2.7.7/
302B_0034 DMA Request Error Register (SDMABP3_EVTERRDBG) 32 R 0000_0000h
1240
7.2.7.1/
302C_0000 Channel 0 Pointer (SDMABP2_DC0PTR) 32 R/W 0000_0000h
1238
7.2.7.2/
302C_0004 Channel Interrupts (SDMABP2_INTR) 32 w1c 0000_0000h
1238
7.2.7.3/
302C_0008 Channel Stop/Channel Status (SDMABP2_STOP_STAT) 32 R/W 0000_0000h
1238
7.2.7.4/
302C_000C Channel Start (SDMABP2_DSTART) 32 R 0000_0000h
1239
7.2.7.5/
302C_0028 DMA Request Error Register (SDMABP2_EVTERR) 32 R 0000_0000h
1239
7.2.7.6/
302C_002C Channel DSP Interrupt Mask (SDMABP2_INTRMASK) 32 R/W 0000_0000h
1240
7.2.7.7/
302C_0034 DMA Request Error Register (SDMABP2_EVTERRDBG) 32 R 0000_0000h
1240
7.2.7.1/
30BD_0000 Channel 0 Pointer (SDMABP1_DC0PTR) 32 R/W 0000_0000h
1238
7.2.7.2/
30BD_0004 Channel Interrupts (SDMABP1_INTR) 32 w1c 0000_0000h
1238
7.2.7.3/
30BD_0008 Channel Stop/Channel Status (SDMABP1_STOP_STAT) 32 R/W 0000_0000h
1238
7.2.7.4/
30BD_000C Channel Start (SDMABP1_DSTART) 32 R 0000_0000h
1239
7.2.7.5/
30BD_0028 DMA Request Error Register (SDMABP1_EVTERR) 32 R 0000_0000h
1239
7.2.7.6/
30BD_002C Channel DSP Interrupt Mask (SDMABP1_INTRMASK) 32 R/W 0000_0000h
1240
7.2.7.7/
30BD_0034 DMA Request Error Register (SDMABP1_EVTERRDBG) 32 R 0000_0000h
1240

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1237
Smart Direct Memory Access Controller (SDMA)

7.2.7.1 Channel 0 Pointer (SDMABPx_DC0PTR)

Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DC0PTR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMABPx_DC0PTR field descriptions

Field Description
DC0PTR Channel 0 Pointer contains the 32-bit address, in BP memory, of the array of channel control blocks
starting with the one for channel 0 (the control channel). This register should be initialized by the BP
before it enables a channel (for example, channel 0). See the API document SDMA Scripts User Manual
for the use of this register. The BP has a read/write access and the SDMA has a read-only access.

7.2.7.2 Channel Interrupts (SDMABPx_INTR)

Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R DI
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMABPx_INTR field descriptions

Field Description
DI The BP Interrupts register contains the 32 DI[i] bits. If any bit is set, it will cause an interrupt to the BP.
• This register is a "write-ones" register to the BP. When the BP sets a bit in this register, the
corresponding DI[i] bit is cleared.
• The interrupt service routine should clear individual channel bits when their interrupts are serviced;
failure to do so will cause continuous interrupts.
• The SDMA is responsible for setting the DI[i] bit corresponding to the current channel when the
corresponding done instruction is executed.

7.2.7.3 Channel Stop/Channel Status (SDMABPx_STOP_STAT)

Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R DE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1238 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMABPx_STOP_STAT field descriptions

Field Description
DE This 32-bit register gives access to the BP (DSP) Enable bits, DE. There is one bit for every channel.
• This register is a "write-ones" register to the BP.
• When the BP writes 1 in bit i of this register, it clears the DE[i] and DSTART[i] bits.
• Reading this register yields the current state of the DE[i] bits.

7.2.7.4 Channel Start (SDMABPx_DSTART)

Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R DSTART_DE
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMABPx_DSTART field descriptions

Field Description
DSTART_DE The DSTART_DE registers are 32 bits wide with one bit for every channel.
• When a bit is written to 1, it enables the corresponding channel.
• Two physical registers are accessed with that address (DSTART and DE), which enables the BP to
trigger a channel a second time before the first trigger was processed.
• This register is a "write-ones" register to the BP. Neither DSTART[i] bit can be set while the
corresponding DE[i] bit is cleared.
• When the BP tries to set the DSTART[i] bit by writing a one (if the corresponding DE[i] bit is clear),
the bit in the DSTART[i] register will remain cleared and the DE[i] bit will be set. If the corresponding
DE[i] bit was already set, the DSTART[i] bit will be set.
• The next time the SDMA channel i attempts to clear the DE[i] bit by means of a done instruction, the
bit in the DSTART[i] register will be cleared and the DE[i] bit will take the old value of the DSTART[i]
bit.
• Reading this register yields the current state of the DSTART[i] bits. This mechanism enables the BP
to pipeline two DSTART commands per channel.

7.2.7.5 DMA Request Error Register (SDMABPx_EVTERR)

Address: Base address + 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CHNERR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMABPx_EVTERR field descriptions

Field Description
CHNERR This register is used by the SDMA to warn the BP when an incoming DMA request was detected; it then
triggers a channel that is already pending or being serviced, which may mean there is an overflow of data

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1239
Smart Direct Memory Access Controller (SDMA)

SDMABPx_EVTERR field descriptions (continued)

Field Description
for that channel. An interrupt is sent to the BP if the corresponding channel bit is set in the INTRMASK
register.
• This is a "write-ones" register for the scheduler. It is only able to set the flags. The flags are cleared
when the register is read by the BP or during an SDMA reset.
• The CHNERR[i] bit is set when a DMA request that triggers channel i is received through the
corresponding input pins and the EP[i] bit is already set. The EVTERR[i] bit is unaffected if the BP
tries to set the EP[i] bit when that EP[i] bit is already set.

7.2.7.6 Channel DSP Interrupt Mask (SDMABPx_INTRMASK)

Address: Base address + 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DIMASK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMABPx_INTRMASK field descriptions

Field Description
DIMASK The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit DIMASK[i] is set, the DI[i] bit
is set and an interrupt is sent to the BP when a DMA request error is detected on channel i (for example,
EVTERR[i] is set).

7.2.7.7 DMA Request Error Register (SDMABPx_EVTERRDBG)

Address: Base address + 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CHNERR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMABPx_EVTERRDBG field descriptions

Field Description
CHNERR This register is the same as EVTERR except reading it does not clear its contents. This address is meant
to be used in debug mode. The BP OnCE may check this register value without modifying it.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1240 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.8 SDMA Internal (Core) Memory Map and Internal Register

Definitions

The actual SDMA memory mapped registers are summarized in the following sections;
for peripherals' memory maps, refer to the respective chapters.
The following definitions serve as a key for the SDMA internal register summary.
SDMACORE memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.8.1/
302B_0000 Arm platform Channel 0 Pointer (SDMACORE3_MC0PTR) 32 R 0000_0000h
1244
7.2.8.2/
302B_0008 Current Channel Pointer (SDMACORE3_CCPTR) 32 R 0000_0000h
1244
7.2.8.3/
302B_000C Current Channel Register (SDMACORE3_CCR) 32 R 0000_0000h
1245
7.2.8.4/
302B_0010 Highest Pending Channel Register (SDMACORE3_NCR) 32 R 0000_0000h
1245
7.2.8.5/
302B_0014 External DMA Requests Mirror (SDMACORE3_EVENTS) 32 R 0000_0000h
1246
7.2.8.6/
302B_0018 Current Channel Priority (SDMACORE3_CCPRI) 32 R 0000_0000h
1247
7.2.8.7/
302B_001C Next Channel Priority (SDMACORE3_NCPRI) 32 R 0000_0000h
1247
7.2.8.8/
302B_0020 OnCE Event Cell Counter (SDMACORE3_ECOUNT) 32 R/W 0000_0000h
1248
7.2.8.9/
302B_0024 OnCE Event Cell Control Register (SDMACORE3_ECTL) 32 R/W 0000_0000h
1248
7.2.8.10/
302B_0028 OnCE Event Address Register A (SDMACORE3_EAA) 32 R/W 0000_0000h
1250
7.2.8.11/
302B_002C OnCE Event Cell Address Register B (SDMACORE3_EAB) 32 R/W 0000_0000h
1250
7.2.8.12/
302B_0030 OnCE Event Cell Address Mask (SDMACORE3_EAM) 32 R/W 0000_0000h
1250
7.2.8.13/
302B_0034 OnCE Event Cell Data Register (SDMACORE3_ED) 32 R/W 0000_0000h
1251
7.2.8.14/
302B_0038 OnCE Event Cell Data Mask (SDMACORE3_EDM) 32 R/W 0000_0000h
1251
7.2.8.15/
302B_003C OnCE Real-Time Buffer (SDMACORE3_RTB) 32 R/W 0000_0000h
1252
7.2.8.16/
302B_0040 OnCE Trace Buffer (SDMACORE3_TB) 32 R 0000_0000h
1252
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1241
Smart Direct Memory Access Controller (SDMA)

SDMACORE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.8.17/
302B_0044 OnCE Status (SDMACORE3_OSTAT) 32 R 0000_0000h
1253
7.2.8.18/
302B_0048 Channel 0 Boot Address (SDMACORE3_MCHN0ADDR) 32 R 0000_0000h
1255
7.2.8.19/
302B_004C ENDIAN Status Register (SDMACORE3_ENDIANNESS) 32 R 0000_0001h
1256
7.2.8.20/
302B_0054 Lock Status Register (SDMACORE3_SDMA_LOCK) 32 R 0000_0000h
1257
External DMA Requests Mirror #2 7.2.8.21/
302B_0058 32 R 0000_0000h
(SDMACORE3_EVENTS2) 1257
7.2.8.1/
302C_0000 Arm platform Channel 0 Pointer (SDMACORE2_MC0PTR) 32 R 0000_0000h
1244
7.2.8.2/
302C_0008 Current Channel Pointer (SDMACORE2_CCPTR) 32 R 0000_0000h
1244
7.2.8.3/
302C_000C Current Channel Register (SDMACORE2_CCR) 32 R 0000_0000h
1245
7.2.8.4/
302C_0010 Highest Pending Channel Register (SDMACORE2_NCR) 32 R 0000_0000h
1245
7.2.8.5/
302C_0014 External DMA Requests Mirror (SDMACORE2_EVENTS) 32 R 0000_0000h
1246
7.2.8.6/
302C_0018 Current Channel Priority (SDMACORE2_CCPRI) 32 R 0000_0000h
1247
7.2.8.7/
302C_001C Next Channel Priority (SDMACORE2_NCPRI) 32 R 0000_0000h
1247
7.2.8.8/
302C_0020 OnCE Event Cell Counter (SDMACORE2_ECOUNT) 32 R/W 0000_0000h
1248
7.2.8.9/
302C_0024 OnCE Event Cell Control Register (SDMACORE2_ECTL) 32 R/W 0000_0000h
1248
7.2.8.10/
302C_0028 OnCE Event Address Register A (SDMACORE2_EAA) 32 R/W 0000_0000h
1250
7.2.8.11/
302C_002C OnCE Event Cell Address Register B (SDMACORE2_EAB) 32 R/W 0000_0000h
1250
7.2.8.12/
302C_0030 OnCE Event Cell Address Mask (SDMACORE2_EAM) 32 R/W 0000_0000h
1250
7.2.8.13/
302C_0034 OnCE Event Cell Data Register (SDMACORE2_ED) 32 R/W 0000_0000h
1251
7.2.8.14/
302C_0038 OnCE Event Cell Data Mask (SDMACORE2_EDM) 32 R/W 0000_0000h
1251
7.2.8.15/
302C_003C OnCE Real-Time Buffer (SDMACORE2_RTB) 32 R/W 0000_0000h
1252
7.2.8.16/
302C_0040 OnCE Trace Buffer (SDMACORE2_TB) 32 R 0000_0000h
1252
7.2.8.17/
302C_0044 OnCE Status (SDMACORE2_OSTAT) 32 R 0000_0000h
1253
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1242 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMACORE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.8.18/
302C_0048 Channel 0 Boot Address (SDMACORE2_MCHN0ADDR) 32 R 0000_0000h
1255
7.2.8.19/
302C_004C ENDIAN Status Register (SDMACORE2_ENDIANNESS) 32 R 0000_0001h
1256
7.2.8.20/
302C_0054 Lock Status Register (SDMACORE2_SDMA_LOCK) 32 R 0000_0000h
1257
External DMA Requests Mirror #2 7.2.8.21/
302C_0058 32 R 0000_0000h
(SDMACORE2_EVENTS2) 1257
7.2.8.1/
30BD_0000 Arm platform Channel 0 Pointer (SDMACORE1_MC0PTR) 32 R 0000_0000h
1244
7.2.8.2/
30BD_0008 Current Channel Pointer (SDMACORE1_CCPTR) 32 R 0000_0000h
1244
7.2.8.3/
30BD_000C Current Channel Register (SDMACORE1_CCR) 32 R 0000_0000h
1245
7.2.8.4/
30BD_0010 Highest Pending Channel Register (SDMACORE1_NCR) 32 R 0000_0000h
1245
7.2.8.5/
30BD_0014 External DMA Requests Mirror (SDMACORE1_EVENTS) 32 R 0000_0000h
1246
7.2.8.6/
30BD_0018 Current Channel Priority (SDMACORE1_CCPRI) 32 R 0000_0000h
1247
7.2.8.7/
30BD_001C Next Channel Priority (SDMACORE1_NCPRI) 32 R 0000_0000h
1247
7.2.8.8/
30BD_0020 OnCE Event Cell Counter (SDMACORE1_ECOUNT) 32 R/W 0000_0000h
1248
7.2.8.9/
30BD_0024 OnCE Event Cell Control Register (SDMACORE1_ECTL) 32 R/W 0000_0000h
1248
7.2.8.10/
30BD_0028 OnCE Event Address Register A (SDMACORE1_EAA) 32 R/W 0000_0000h
1250
7.2.8.11/
30BD_002C OnCE Event Cell Address Register B (SDMACORE1_EAB) 32 R/W 0000_0000h
1250
7.2.8.12/
30BD_0030 OnCE Event Cell Address Mask (SDMACORE1_EAM) 32 R/W 0000_0000h
1250
7.2.8.13/
30BD_0034 OnCE Event Cell Data Register (SDMACORE1_ED) 32 R/W 0000_0000h
1251
7.2.8.14/
30BD_0038 OnCE Event Cell Data Mask (SDMACORE1_EDM) 32 R/W 0000_0000h
1251
7.2.8.15/
30BD_003C OnCE Real-Time Buffer (SDMACORE1_RTB) 32 R/W 0000_0000h
1252
7.2.8.16/
30BD_0040 OnCE Trace Buffer (SDMACORE1_TB) 32 R 0000_0000h
1252
7.2.8.17/
30BD_0044 OnCE Status (SDMACORE1_OSTAT) 32 R 0000_0000h
1253
7.2.8.18/
30BD_0048 Channel 0 Boot Address (SDMACORE1_MCHN0ADDR) 32 R 0000_0000h
1255
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1243
Smart Direct Memory Access Controller (SDMA)

SDMACORE memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.8.19/
30BD_004C ENDIAN Status Register (SDMACORE1_ENDIANNESS) 32 R 0000_0001h
1256
7.2.8.20/
30BD_0054 Lock Status Register (SDMACORE1_SDMA_LOCK) 32 R 0000_0000h
1257
External DMA Requests Mirror #2 7.2.8.21/
30BD_0058 32 R 0000_0000h
(SDMACORE1_EVENTS2) 1257

7.2.8.1 Arm platform Channel 0 Pointer (SDMACOREx_MC0PTR)

Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MC0PTR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_MC0PTR field descriptions

Field Description
MC0PTR Contains the address-in the Arm platform memory space-of the initial SDMA context and scripts that are
loaded by the SDMA boot script running on channel 0.

7.2.8.2 Current Channel Pointer (SDMACOREx_CCPTR)

Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 CCPTR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_CCPTR field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
CCPTR Contains the start address of the context data for the current channel: Its value is CONTEXT_BASE + 24*
CCR or CONTEXT_BASE + 32* CCR where CONTEXT_BASE = 0x0800. The value 24 or 32 is selected
according to the programmed channel scratch RAM size in the register shown in Channel 0 Boot Address
(SDMAARM_CHN0ADDR) .

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1244 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.8.3 Current Channel Register (SDMACOREx_CCR)

Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 CCR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_CCR field descriptions

Field Description
31–5 This read-only field is reserved and always has the value 0.
Reserved
CCR Contains the number of the current running channel whose context is installed. In the case that the SDMA
has finished running the channel and has entered sleep state, CCR will indicate the previous running
channel. The PST bits in the OSTAT register indicate when the SDMA is in sleep state.

7.2.8.4 Highest Pending Channel Register (SDMACOREx_NCR)

Address: Base address + 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 NCR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_NCR field descriptions

Field Description
31–5 This read-only field is reserved and always has the value 0.
Reserved
NCR Contains the number of the pending channel that the scheduler has selected to run next.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1245
Smart Direct Memory Access Controller (SDMA)

7.2.8.5 External DMA Requests Mirror (SDMACOREx_EVENTS)

NOTE
This register is very useful in the case of DMA requests that are
active when a peripheral FIFO level is above the programmed
watermark. The activation of the DMA request (rising edge) is
detected by the SDMA logic and it can enable one or several
channels. One of the channels accesses the peripheral and reads
or writes a number of data that matches the watermark level
(for example, if the watermark is four words, the channel reads
or writes four words).
If the channel is effectively executed long after the DMA
request was received, reading or writing the watermark number
of data may not be sufficient to reset the DMA request (for
example, if the FIFO watermark is four and at the channel
execution it already contains nine pieces of data). This means
no new rising edge may be detected by the SDMA, although
there still remains transfers to perform. Therefore, if the
channel were terminated at that time, it would not be restarted,
causing potential overrun or underrun of the peripheral.
The proposed mechanism is for the channel to check this
register after it has performed the "watermark" number of
accesses to the peripheral. If the bit for the DMA request that
triggers this channel is set, it means there is still another
watermark number of data to transfer. This goes on until the bit
is cleared. The same script can be used for multiple channels
that require this behavior. The script can determine its channel
number from the CCR register and infer the corresponding
DMA request bit to check. It needs a reference table that is
coherent with the request-channel matrix that the Arm platform
programmed.
Address: Base address + 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R EVENTS
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1246 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMACOREx_EVENTS field descriptions

Field Description
EVENTS Reflects the status of the SDMA's external DMA requests. It is meant to allow any channel to monitor the
states of these SDMA inputs.
This register displays EVENTS 0-31. The EVENTS2 register displays events 32-47.

7.2.8.6 Current Channel Priority (SDMACOREx_CCPRI)

Address: Base address + 18h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 CCPRI
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_CCPRI field descriptions

Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
CCPRI Contains the 3-bit priority of the channel whose context is installed. It is 0 when no channel is running.

NOTE: 1-7 current channel priority

0 no running channel

7.2.8.7 Next Channel Priority (SDMACOREx_NCPRI)

Address: Base address + 1Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 NCPRI
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_NCPRI field descriptions

Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
NCPRI Contains the 3-bit priority of the channel the scheduler has selected to run next. It is 0 when no other
channel is pending.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1247
Smart Direct Memory Access Controller (SDMA)

7.2.8.8 OnCE Event Cell Counter (SDMACOREx_ECOUNT)

Address: Base address + 20h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ECOUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_ECOUNT field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
ECOUNT The event cell counter contains the number of times minus one that an event detection must occur before
generating a debug request.
• This register should be written before any attempt to use the event detection counter during an
event detection process.
• The counter is cleared on a JTAG reset.

7.2.8.9 OnCE Event Cell Control Register (SDMACOREx_ECTL)

Address: Base address + 24h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EN CNT ECTC[1:0] DTC[1:0] ATC[1:0] ABTC[1:0] AATC[1:0] ATS[1:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_ECTL field descriptions

Field Description
31–14 This read-only field is reserved and always has the value 0.
Reserved
13 Event Cell Enable. If the EN bit is set, the event cell is allowed to generate debug requests (the cell is
EN awakened). If it is cleared, the event detection unit is disabled and no hardware breakpoint is generated,
but matching conditions are still reflected on the emulation pin.

0 Cell is disabled.
1 Cell is enabled.
12 Event Counter Enable. The event counter enable bit determines if the cell counter is used during the event
CNT detection. In order to use the event counter during an event detection process, the event cell counter
register should be loaded with a value equal to the number of times minus one that an event occurs before
a debug request is sent. After every event detection, the counter is decreased. When the counter reaches
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1248 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMACOREx_ECTL field descriptions (continued)

Field Description
the value 0, the event detection cell sends a debug request to the core. The event counter register should
be written and the EN bit should be set before each new event detection process uses the event counter.

0 Counter is disabled.
1 Counter is enabled.
11–10 The event cell trigger condition bits select the combination of address and data matching conditions that
ECTC[1:0] generate the final address/data condition. During program execution, if this event cell trigger condition
goes to 1, a debug request is sent to the SDMA. The EN bit must be set to enable the debug request
generation.

00 address ONLY
01 data ONLY
10 address AND data
11 address OR data
9–8 The data trigger condition bits define when data is considered matching after comparison with the data
DTC[1:0] register of the event detection unit. The operations are performed on unsigned values.

00 equal
01 not equal
10 greater than
11 less than
7–6 The address trigger condition bits select how the two address conditions (addressA and addressB) are
ATC[1:0] combined to define the global address matching condition. The supported combinations are described, as
follows.

00 addressA ONLY
01 addrA AND addrB
10 addrA OR addrB
11 reserved
5–4 The Address B Trigger Condition (ABTC) controls the operations performed by address comparator B. All
ABTC[1:0] operations are performed on unsigned values. This comparator B outputs the addressB condition.

00 equal
01 not equal
10 greater than
11 less than
3–2 The Address A Trigger Condition (AATC) controls the operations performed by address comparator A. All
AATC[1:0] operations are performed on unsigned values. This comparator A outputs the addressA condition.

00 equal
01 not equal
10 greater than
11 less than
ATS[1:0] The access type select bits define the memory access type required on the SDMA memory bus.

00 read ONLY
01 write ONLY
10 read or write
11 -

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1249
Smart Direct Memory Access Controller (SDMA)

7.2.8.10 OnCE Event Address Register A (SDMACOREx_EAA)

Address: Base address + 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EAA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_EAA field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EAA Event Cell Address Register A computes an address A condition. It is cleared on a JTAG reset.

7.2.8.11 OnCE Event Cell Address Register B (SDMACOREx_EAB)

Address: Base address + 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EAB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_EAB field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EAB Event Cell Address Register B computes an address B condition. It is cleared on a JTAG reset.

7.2.8.12 OnCE Event Cell Address Mask (SDMACOREx_EAM)

Address: Base address + 30h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EAM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_EAM field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1250 NXP Semiconductors
 Chapter 7 Interrupts and DMA

SDMACOREx_EAM field descriptions (continued)

Field Description
EAM The Event Cell Address Mask contains a user-defined address mask value. This mask is applied to the
address value latched from the memory address bus before performing the address comparison.

NOTE: There is a common address mask value for both address comparators. If bit i of this register is
set, then bit i of the address value latched from the memory bus does not influence the result of
the address comparison. The register is cleared on a JTAG reset.

7.2.8.13 OnCE Event Cell Data Register (SDMACOREx_ED)

Address: Base address + 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_ED field descriptions

Field Description
ED The event cell data register contains a user defined data value. This data value is an input for the data
comparator which generates the data condition. It is cleared on a JTAG reset.

7.2.8.14 OnCE Event Cell Data Mask (SDMACOREx_EDM)

Address: Base address + 38h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
EDM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_EDM field descriptions

Field Description
EDM The event cell data mask register contains the user-defined data mask value.
• This mask is applied to the data value latched from the memory bus before performing the data
comparison.
• Setting bit i of the event cell data mask register means that bit i of the data value latched from the
address bus does not influence the result of the data comparison.
• The data mask is cleared on a JTAG reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1251
Smart Direct Memory Access Controller (SDMA)

7.2.8.15 OnCE Real-Time Buffer (SDMACOREx_RTB)

Address: Base address + 3Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
RTB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_RTB field descriptions

Field Description
RTB The Real Time Buffer register stores and retrieves run time information without putting the SDMA in debug
mode. Writing to that register triggers a pulse on a specific real-time debug pin whose connection depends
on the chip implementation.
The RTB value can be accessed by the OnCE under Arm platform or JTAG control using the rbuffer
command.

7.2.8.16 OnCE Trace Buffer (SDMACOREx_TB)

Address: Base address + 40h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 TBF TADDR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R TADDR CHFADDR
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_TB field descriptions

Field Description
31–29 This read-only field is reserved and always has the value 0.
Reserved
28 The Trace Buffer Flag is set when the buffer contains the addresses of a valid change of flow. The
TBF contents of the buffer should be ignored otherwise.

0 Invalid information
1 Valid information
27–14 The target address is the address taken after the execution of the change of flow instruction.
TADDR
CHFADDR The change of flow address is the address where the change of flow is taken when executing a change of
flow instruction.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1252 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.8.17 OnCE Status (SDMACOREx_OSTAT)

Address: Base address + 44h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PST[3:0] RCV EDR ODR SWB MST 0 ECDR[2:0]

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_OSTAT field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
15–12 The Processor Status bits reflect the state of the SDMA RISC engine.
PST[3:0] • The "Program" state is the usual instruction execution cycle.
• The "Data" state is inserted when there are wait-states during a load or a store on the data bus (ld or
st).
• The "Change of Flow" state is the second cycle of any instruction that breaks the sequence of
instructions (jumps and channel-switching instructions).
• The "Change of Flow in Loop" state is used when an error causes a hardware loop exit.
• The "Debug" state means the SDMA is in debug mode.
• The "Functional Unit" state is inserted when there are wait-states during a load or a store on the
functional units bus (ldf or stf).
• In "Sleep" modes, no script is running (this is the RISC engine idle state). The "after Reset" is
slightly different because no context restoring phase will happen when a channel is triggered: The
script located at address 0 will be executed (boot operation).
• The "in Sleep" states are the same as above except they do not have any corresponding channel.
They are used when entering debug mode after reset; the reason is that it is necessary to return to
the "Sleep after Reset" state when leaving debug mode.

0 Program
1 Data
2 Change of Flow
3 Change of Flow in Loop
4 Debug
5 Functional Unit
6 Sleep
7 Save
8 Program in Sleep
9 Data in Sleep
10 Change of Flow in Sleep
11 Change Flow Loop Sleep
12 Debug in Sleep
13 Functional Unit in Sleep
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1253
Smart Direct Memory Access Controller (SDMA)

SDMACOREx_OSTAT field descriptions (continued)

Field Description
14 Sleep after Reset
15 Restore
11 After each write access to the real time buffer (RTB), the RCV bit is set. This bit is cleared after execution
RCV of an rbuffer command and on a JTAG reset.
10 This flag is raised when the SDMA has entered debug mode after an external debug request.
EDR
9 This flag is raised when the SDMA has entered debug mode after a OnCE debug request.
ODR
8 This flag is raised when the SDMA has entered debug mode after a software breakpoint.
SWB
7 This flag is raised when the OnCE is controlled from the Arm platform peripheral interface.
MST
0 JTAG interface controls the OnCE.
1 Arm platform peripheral interface controls the OnCE.
6–3 This read-only field is reserved and always has the value 0.
Reserved
ECDR[2:0] Event Cell Debug Request. If the debug request comes from the event cell, the reason for entering debug
mode is given by the EDR bits. The encoding of the EDR bits is useful to find out more precisely why the
debug request was generated. A debug request from an event cell is generated for a specific combination
of the addressA, addressB, and data conditions; the value of those fields is given by the EDR bits. If all
three bits of the EDR are reset, then it did not generate any debug request. If the cell did generate a
debug request, then at least one EDR bit is set; the meaning of the encoding is as follows:

0 1 matched addressA condition

1 1 matched addressB condition
2 1 matched data condition

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1254 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.8.18 Channel 0 Boot Address (SDMACOREx_MCHN0ADDR)

Address: Base address + 48h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMSZ

R 0 CHN0ADDR[13:0]

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_MCHN0ADDR field descriptions

Field Description
31–15 This read-only field is reserved and always has the value 0.
Reserved
14 The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel
SMSZ context. After reset, it is equal to 0, which defines a RAM space of 24 words for each channel. All of
this area stores the channel context. By setting this bit, 32 words are reserved for every channel
context, which gives eight additional words that can be used by the channel script to store any type of
data. Those words are never erased by the context switching mechanism.

0 24 words per context

1 32 words per context
CHN0ADDR[13:0] Contains the address of the channel 0 routine programmed by the Arm platform; it is loaded into a
general register at the very start of the boot and the SDMA jumps to the address it contains. By default,
it points to the standard boot routine in ROM.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1255
Smart Direct Memory Access Controller (SDMA)

7.2.8.19 ENDIAN Status Register (SDMACOREx_ENDIANNESS)

Address: Base address + 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

APEND
R 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

SDMACOREx_ENDIANNESS field descriptions

Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
2–1 This read-only field is reserved and always has the value 0.
Reserved
0 APEND indicates the endian mode of the Peripheral and Burst DMA interfaces. This bit is tied to logic '1'
APEND indicating little-endian mode.

0 - Arm platform is in big-endian mode

1 - Arm platform is in little-endian mode

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1256 NXP Semiconductors
 Chapter 7 Interrupts and DMA

7.2.8.20 Lock Status Register (SDMACOREx_SDMA_LOCK)

Address: Base address + 54h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LOCK
R 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDMACOREx_SDMA_LOCK field descriptions

Field Description
31–1 This read-only field is reserved and always has the value 0.
Reserved
0 The LOCK bit reports the value of the LOCK bit in the SDMA_LOCK status register. SDMA software may
LOCK use this value to determine if certain operations such as loading of new scripts is allowed.

0 - LOCK bit clear

1 - LOCK bit set

7.2.8.21 External DMA Requests Mirror #2 (SDMACOREx_EVENTS2)

Address: Base address + 58h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 EVENTS
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1257
Smart Direct Memory Access Controller (SDMA)

SDMACOREx_EVENTS2 field descriptions

Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EVENTS Reflects the status of the SDMA's external DMA requests. It is meant to allow any channel to monitor the
states of these SDMA inputs.
This register displays EVENTS 32-47. The separate EVENTS register displays events 0-31.

7.2.9 SDMA Peripheral Registers

Refer to the respective peripherals' chapters for more information.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1258 NXP Semiconductors
Chapter 8
Chip IO and Pinmux

8.1 External Signals and Pin Multiplexing

8.1.1 Overview
The chip contains a limited number of pins, most of which have multiple signal options.
These signal-to-pin and pin-to-signal options are selected by the input-output multiplexer
called IOMUX. The IOMUX is also used to configure other pin characteristics, such as
voltage level, drive strength, and hysteresis.
The muxing options table lists the external signals grouped by the module instance, the
muxing options for each signal, and the registers used to route the signal to the chosen
pad.

8.1.1.1 Muxing Options

Table 8-1. Muxing Options
Instance Port PAD MODE
ARM PLATFORM ARM_EVENTI SAI1_TXC ALT4
ARM_EVENTO SAI1_TXFS ALT4
CCM CCM_CLKO1 GPIO1_IO14 ALT6
CCM_CLKO2 GPIO1_IO15 ALT6
CCM_ENET_PHY_REF_CLK GPIO1_IO00 ALT1
_ROOT
CCM_EXT_CLK1 GPIO1_IO00 ALT6
CCM_EXT_CLK2 GPIO1_IO01 ALT6
CCM_EXT_CLK3 GPIO1_IO06 ALT6
CCM_EXT_CLK4 GPIO1_IO07 ALT6
CCM_PMIC_READY GPIO1_IO05 ALT5
CCM_PMIC_READY GPIO1_IO11 ALT5

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1259
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
CCM_PMIC_STBY_REQ PMIC_STBY_REQ ALT0
DRAM DRAM_DQS0_P DRAM_DQS0_P No muxing
DRAM_DQS0_N DRAM_DQS0_N No muxing
DRAM_DM0 DRAM_DM0 No muxing
DRAM_DQ00 DRAM_DQ00 No muxing
DRAM_DQ01 DRAM_DQ01 No muxing
DRAM_DQ02 DRAM_DQ02 No muxing
DRAM_DQ03 DRAM_DQ03 No muxing
DRAM_DQ04 DRAM_DQ04 No muxing
DRAM_DQ05 DRAM_DQ05 No muxing
DRAM_DQ06 DRAM_DQ06 No muxing
DRAM_DQ07 DRAM_DQ07 No muxing
DRAM_DQS1_P DRAM_DQS1_P No muxing
DRAM_DQS1_N DRAM_DQS1_N No muxing
DRAM_DM1 DRAM_DM1 No muxing
DRAM_DQ08 DRAM_DQ08 No muxing
DRAM_DQ09 DRAM_DQ09 No muxing
DRAM_DQ10 DRAM_DQ10 No muxing
DRAM_DQ11 DRAM_DQ11 No muxing
DRAM_DQ12 DRAM_DQ12 No muxing
DRAM_DQ13 DRAM_DQ13 No muxing
DRAM_DQ14 DRAM_DQ14 No muxing
DRAM_DQ15 DRAM_DQ15 No muxing
DRAM_DQS2_P DRAM_DQS2_P No muxing
DRAM_DQS2_N DRAM_DQS2_N No muxing
DRAM_DM2 DRAM_DM2 No muxing
DRAM_DQ16 DRAM_DQ16 No muxing
DRAM_DQ17 DRAM_DQ17 No muxing
DRAM_DQ18 DRAM_DQ18 No muxing
DRAM_DQ19 DRAM_DQ19 No muxing
DRAM_DQ20 DRAM_DQ20 No muxing
DRAM_DQ21 DRAM_DQ21 No muxing
DRAM_DQ22 DRAM_DQ22 No muxing
DRAM_DQ23 DRAM_DQ23 No muxing
DRAM_DQS3_P DRAM_DQS3_P No muxing
DRAM_DQS3_N DRAM_DQS3_N No muxing
DRAM_DM3 DRAM_DM3 No muxing
DRAM_DQ24 DRAM_DQ24 No muxing
DRAM_DQ25 DRAM_DQ25 No muxing

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1260 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
DRAM_DQ26 DRAM_DQ26 No muxing
DRAM_DQ27 DRAM_DQ27 No muxing
DRAM_DQ28 DRAM_DQ28 No muxing
DRAM_DQ29 DRAM_DQ29 No muxing
DRAM_DQ30 DRAM_DQ30 No muxing
DRAM_DQ31 DRAM_DQ31 No muxing
DRAM_RESET_N DRAM_RESET_N No muxing
DRAM_ALERT_N DRAM_ALERT_N No muxing
DRAM_AC00 DRAM_AC00 No muxing
DRAM_AC01 DRAM_AC01 No muxing
DRAM_AC02 DRAM_AC02 No muxing
DRAM_AC03 DRAM_AC03 No muxing
DRAM_AC04 DRAM_AC04 No muxing
DRAM_AC05 DRAM_AC05 No muxing
DRAM_AC06 DRAM_AC06 No muxing
DRAM_AC07 DRAM_AC07 No muxing
DRAM_AC08 DRAM_AC08 No muxing
DRAM_AC09 DRAM_AC09 No muxing
DRAM_AC10 DRAM_AC10 No muxing
DRAM_AC11 DRAM_AC11 No muxing
DRAM_AC12 DRAM_AC12 No muxing
DRAM_AC13 DRAM_AC13 No muxing
DRAM_AC14 DRAM_AC14 No muxing
DRAM_AC15 DRAM_AC15 No muxing
DRAM_AC16 DRAM_AC16 No muxing
DRAM_AC17 DRAM_AC17 No muxing
DRAM_AC19 DRAM_AC19 No muxing
DRAM_AC20 DRAM_AC20 No muxing
DRAM_AC21 DRAM_AC21 No muxing
DRAM_AC22 DRAM_AC22 No muxing
DRAM_AC23 DRAM_AC23 No muxing
DRAM_AC24 DRAM_AC24 No muxing
DRAM_AC25 DRAM_AC25 No muxing
DRAM_AC26 DRAM_AC26 No muxing
DRAM_AC27 DRAM_AC27 No muxing
DRAM_AC28 DRAM_AC28 No muxing
DRAM_AC29 DRAM_AC29 No muxing
DRAM_AC30 DRAM_AC30 No muxing
DRAM_AC31 DRAM_AC31 No muxing

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1261
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
DRAM_AC32 DRAM_AC32 No muxing
DRAM_AC33 DRAM_AC33 No muxing
DRAM_AC34 DRAM_AC34 No muxing
DRAM_AC35 DRAM_AC35 No muxing
DRAM_AC36 DRAM_AC36 No muxing
DRAM_AC37 DRAM_AC37 No muxing
DRAM_AC38 DRAM_AC38 No muxing
DRAM_ZN DRAM_ZN No muxing
DRAM_VREF DRAM_VREF No muxing
ECSPI1 ECSPI1_MISO ECSPI1_MISO ALT0
ECSPI1_MOSI ECSPI1_MOSI ALT0
ECSPI1_SCLK ECSPI1_SCLK ALT0
ECSPI1_SS0 ECSPI1_SS0 ALT0
ECSPI2 ECSPI2_MISO ECSPI2_MISO ALT0
ECSPI2_MOSI ECSPI2_MOSI ALT0
ECSPI2_SCLK ECSPI2_SCLK ALT0
ECSPI2_SS0 ECSPI2_SS0 ALT0
ECSPI3 ECSPI3_MISO UART2_RXD ALT1
ECSPI3_MOSI UART1_TXD ALT1
ECSPI3_SCLK UART1_RXD ALT1
ECSPI3_SS0 UART2_TXD ALT1
ENET11 ENET1_1588_EVENT0_IN GPIO1_IO08 ALT1
ENET1_1588_EVENT0_OUT GPIO1_IO09 ALT1
ENET1_1588_EVENT1_IN I2C2_SCL ALT1
ENET1_1588_EVENT1_OUT I2C2_SDA ALT1
ENET1_MDC ENET_MDC ALT0
ENET1_MDC GPIO1_IO06 ALT1
ENET1_MDC I2C1_SCL ALT1
ENET1_MDIO ENET_MDIO ALT0
ENET1_MDIO GPIO1_IO07 ALT1
ENET1_MDIO I2C1_SDA ALT1
ENET1_RGMII_RD0 ENET_RD0 ALT0
ENET1_RGMII_RD1 ENET_RD1 ALT0
ENET1_RGMII_RD2 ENET_RD2 ALT0
ENET1_RGMII_RD3 ENET_RD3 ALT0
ENET1_RGMII_RX_CTL ENET_RX_CTL ALT0
ENET1_RGMII_RXC ENET_RXC ALT0
ENET1_RGMII_TD0 ENET_TD0 ALT0
ENET1_RGMII_TD1 ENET_TD1 ALT0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1262 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
ENET1_RGMII_TD2 ENET_TD2 ALT0
ENET1_RGMII_TD3 ENET_TD3 ALT0
ENET1_RGMII_TX_CTL ENET_TX_CTL ALT0
ENET1_RGMII_TXC ENET_TXC ALT0
ENET1_RX_ER ENET_RXC ALT1
ENET1_TX_ER ENET_TXC ALT1
ENET1_TX_CLK ENET_TD2 ALT1
GPIO1 GPIO1_IO00 GPIO1_IO00 ALT0
GPIO1_IO01 GPIO1_IO01 ALT0
GPIO1_IO10 GPIO1_IO10 ALT0
GPIO1_IO11 GPIO1_IO11 ALT0
GPIO1_IO12 GPIO1_IO12 ALT0
GPIO1_IO13 GPIO1_IO13 ALT0
GPIO1_IO14 GPIO1_IO14 ALT0
GPIO1_IO15 GPIO1_IO15 ALT0
GPIO1_IO16 ENET_MDC ALT5
GPIO1_IO17 ENET_MDIO ALT5
GPIO1_IO18 ENET_TD3 ALT5
GPIO1_IO19 ENET_TD2 ALT5
GPIO1_IO02 GPIO1_IO02 ALT0
GPIO1_IO20 ENET_TD1 ALT5
GPIO1_IO21 ENET_TD0 ALT5
GPIO1_IO22 ENET_TX_CTL ALT5
GPIO1_IO23 ENET_TXC ALT5
GPIO1_IO24 ENET_RX_CTL ALT5
GPIO1_IO25 ENET_RXC ALT5
GPIO1_IO26 ENET_RD0 ALT5
GPIO1_IO27 ENET_RD1 ALT5
GPIO1_IO28 ENET_RD2 ALT5
GPIO1_IO29 ENET_RD3 ALT5
GPIO1_IO03 GPIO1_IO03 ALT0
GPIO1_IO04 GPIO1_IO04 ALT0
GPIO1_IO05 GPIO1_IO05 ALT0
GPIO1_IO06 GPIO1_IO06 ALT0
GPIO1_IO07 GPIO1_IO07 ALT0
GPIO1_IO08 GPIO1_IO08 ALT0
GPIO1_IO09 GPIO1_IO09 ALT0
GPIO2 GPIO2_IO00 SD1_CLK ALT5
GPIO2_IO01 SD1_CMD ALT5

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1263
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
GPIO2_IO10 SD1_RESET_B ALT5
GPIO2_IO11 SD1_STROBE ALT5
GPIO2_IO12 SD2_CD_B ALT5
GPIO2_IO13 SD2_CLK ALT5
GPIO2_IO14 SD2_CMD ALT5
GPIO2_IO15 SD2_DATA0 ALT5
GPIO2_IO16 SD2_DATA1 ALT5
GPIO2_IO17 SD2_DATA2 ALT5
GPIO2_IO18 SD2_DATA3 ALT5
GPIO2_IO19 SD2_RESET_B ALT5
GPIO2_IO02 SD1_DATA0 ALT5
GPIO2_IO20 SD2_WP ALT5
GPIO2_IO03 SD1_DATA1 ALT5
GPIO2_IO04 SD1_DATA2 ALT5
GPIO2_IO05 SD1_DATA3 ALT5
GPIO2_IO06 SD1_DATA4 ALT5
GPIO2_IO07 SD1_DATA5 ALT5
GPIO2_IO08 SD1_DATA6 ALT5
GPIO2_IO09 SD1_DATA7 ALT5
GPIO3 GPIO3_IO00 NAND_ALE ALT5
GPIO3_IO01 NAND_CE0_B ALT5
GPIO3_IO10 NAND_DATA04 ALT5
GPIO3_IO11 NAND_DATA05 ALT5
GPIO3_IO12 NAND_DATA06 ALT5
GPIO3_IO13 NAND_DATA07 ALT5
GPIO3_IO14 NAND_DQS ALT5
GPIO3_IO15 NAND_RE_B ALT5
GPIO3_IO16 NAND_READY_B ALT5
GPIO3_IO17 NAND_WE_B ALT5
GPIO3_IO18 NAND_WP_B ALT5
GPIO3_IO19 SAI5_RXFS ALT5
GPIO3_IO02 NAND_CE1_B ALT5
GPIO3_IO20 SAI5_RXC ALT5
GPIO3_IO21 SAI5_RXD0 ALT5
GPIO3_IO22 SAI5_RXD1 ALT5
GPIO3_IO23 SAI5_RXD2 ALT5
GPIO3_IO24 SAI5_RXD3 ALT5
GPIO3_IO25 SAI5_MCLK ALT5
GPIO3_IO03 NAND_CE2_B ALT5

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1264 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
GPIO3_IO04 NAND_CE3_B ALT5
GPIO3_IO05 NAND_CLE ALT5
GPIO3_IO06 NAND_DATA00 ALT5
GPIO3_IO07 NAND_DATA01 ALT5
GPIO3_IO08 NAND_DATA02 ALT5
GPIO3_IO09 NAND_DATA03 ALT5
GPIO4 GPIO4_IO00 SAI1_RXFS ALT5
GPIO4_IO01 SAI1_RXC ALT5
GPIO4_IO10 SAI1_TXFS ALT5
GPIO4_IO11 SAI1_TXC ALT5
GPIO4_IO12 SAI1_TXD0 ALT5
GPIO4_IO13 SAI1_TXD1 ALT5
GPIO4_IO14 SAI1_TXD2 ALT5
GPIO4_IO15 SAI1_TXD3 ALT5
GPIO4_IO16 SAI1_TXD4 ALT5
GPIO4_IO17 SAI1_TXD5 ALT5
GPIO4_IO18 SAI1_TXD6 ALT5
GPIO4_IO19 SAI1_TXD7 ALT5
GPIO4_IO02 SAI1_RXD0 ALT5
GPIO4_IO20 SAI1_MCLK ALT5
GPIO4_IO21 SAI2_RXFS ALT5
GPIO4_IO22 SAI2_RXC ALT5
GPIO4_IO23 SAI2_RXD0 ALT5
GPIO4_IO24 SAI2_TXFS ALT5
GPIO4_IO25 SAI2_TXC ALT5
GPIO4_IO26 SAI2_TXD0 ALT5
GPIO4_IO27 SAI2_MCLK ALT5
GPIO4_IO28 SAI3_RXFS ALT5
GPIO4_IO29 SAI3_RXC ALT5
GPIO4_IO03 SAI1_RXD1 ALT5
GPIO4_IO30 SAI3_RXD ALT5
GPIO4_IO31 SAI3_TXFS ALT5
GPIO4_IO04 SAI1_RXD2 ALT5
GPIO4_IO05 SAI1_RXD3 ALT5
GPIO4_IO06 SAI1_RXD4 ALT5
GPIO4_IO07 SAI1_RXD5 ALT5
GPIO4_IO08 SAI1_RXD6 ALT5
GPIO4_IO09 SAI1_RXD7 ALT5
GPIO5 GPIO5_IO00 SAI3_TXC ALT5

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1265
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
GPIO5_IO01 SAI3_TXD ALT5
GPIO5_IO10 ECSPI2_SCLK ALT5
GPIO5_IO11 ECSPI2_MOSI ALT5
GPIO5_IO12 ECSPI2_MISO ALT5
GPIO5_IO13 ECSPI2_SS0 ALT5
GPIO5_IO14 I2C1_SCL ALT5
GPIO5_IO15 I2C1_SDA ALT5
GPIO5_IO16 I2C2_SCL ALT5
GPIO5_IO17 I2C2_SDA ALT5
GPIO5_IO18 I2C3_SCL ALT5
GPIO5_IO19 I2C3_SDA ALT5
GPIO5_IO02 SAI3_MCLK ALT5
GPIO5_IO20 I2C4_SCL ALT5
GPIO5_IO21 I2C4_SDA ALT5
GPIO5_IO22 UART1_RXD ALT5
GPIO5_IO23 UART1_TXD ALT5
GPIO5_IO24 UART2_RXD ALT5
GPIO5_IO25 UART2_TXD ALT5
GPIO5_IO26 UART3_RXD ALT5
GPIO5_IO27 UART3_TXD ALT5
GPIO5_IO28 UART4_RXD ALT5
GPIO5_IO29 UART4_TXD ALT5
GPIO5_IO03 SPDIF_TX ALT5
GPIO5_IO04 SPDIF_RX ALT5
GPIO5_IO05 SPDIF_EXT_CLK ALT5
GPIO5_IO06 ECSPI1_SCLK ALT5
GPIO5_IO07 ECSPI1_MOSI ALT5
GPIO5_IO08 ECSPI1_MISO ALT5
GPIO5_IO09 ECSPI1_SS0 ALT5
GPT1 GPT1_CAPTURE1 SAI3_RXFS ALT1
GPT1_CAPTURE2 SAI3_TXFS ALT1
GPT1_CLK SAI3_RXC ALT1
GPT1_COMPARE1 SAI3_RXD ALT1
GPT1_COMPARE2 SAI3_TXC ALT1
GPT1_COMPARE3 SAI3_TXD ALT1
GPT2 GPT2_CLK I2C3_SCL ALT2
GPT3 GPT3_CLK I2C3_SDA ALT2
I2C1 I2C1_SCL I2C1_SCL ALT0
I2C1_SDA I2C1_SDA ALT0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1266 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
I2C2 I2C2_SCL I2C2_SCL ALT0
I2C2_SDA I2C2_SDA ALT0
I2C3 I2C3_SCL I2C3_SCL ALT0
I2C3_SDA I2C3_SDA ALT0
I2C4 I2C4_SCL I2C4_SCL ALT0
I2C4_SDA I2C4_SDA ALT0
CJTAG CJTAG_MODE JTAG_MOD ALT0
CJTAG_TCK JTAG_TCK ALT0
CJTAG_TDI JTAG_TDI ALT0
CJTAG_TDO JTAG_TDO ALT0
CJTAG_TMS JTAG_TMS ALT0
CJTAG_TRST_B JTAG_TRST_B ALT0
M4 M4_NMI GPIO1_IO05 ALT1
MIPI DSI MIPI_DSI_CLK_P MIPI_DSI_CLK_P No muxing
MIPI_DSI_CLK_N MIPI_DSI_CLK_N No muxing
MIPI_DSI_REXT MIPI_DSI_REXT No muxing
MIPI_DSI_D0_P MIPI_DSI_D0_P No muxing
MIPI_DSI_D0_N MIPI_DSI_D0_N No muxing
MIPI_DSI_D1_P MIPI_DSI_D1_P No muxing
MIPI_DSI_D1_N MIPI_DSI_D1_N No muxing
MIPI_DSI_D2_P MIPI_DSI_D2_P No muxing
MIPI_DSI_D2_N MIPI_DSI_D2_N No muxing
MIPI_DSI_D3_P MIPI_DSI_D3_P No muxing
MIPI_DSI_D3_N MIPI_DSI_D3_N No muxing
MIPI CSI MIPI_CSI_CLK_P MIPI_CSI_CLK_P No muxing
MIPI_CSI_CLK_N MIPI_CSI_CLK_N No muxing
MIPI_CSI_D0_P MIPI_CSI_D0_P No muxing
MIPI_CSI_D0_N MIPI_CSI_D0_N No muxing
MIPI_CSI_D1_P MIPI_CSI_D1_P No muxing
MIPI_CSI_D1_N MIPI_CSI_D1_N No muxing
MIPI_CSI_D2_P MIPI_CSI_D2_P No muxing
MIPI_CSI_D2_N MIPI_CSI_D2_N No muxing
MIPI_CSI_D3_P MIPI_CSI_D3_P No muxing
MIPI_CSI_D3_N MIPI_CSI_D3_N No muxing
PCIE1 PCIE1_CLKREQ_B I2C4_SCL ALT2
PCIE1_CLKREQ_B UART4_RXD ALT2
PCIE_REF_PAD_CLK_P PCIE_REF_PAD_CLK_P No muxing
PCIE_REF_PAD_CLK_N PCIE_REF_PAD_CLK_N No muxing
PCIE_RESREF PCIE_RESREF No muxing

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1267
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
PCIE_TXN_P PCIE_TXN_P No muxing
PCIE_TXN_N PCIE_TXN_N No muxing
PCIE_RXN_N PCIE_RXN_N No muxing
PCIE_RXN_P PCIE_RXN_P No muxing
PDM PDM_BIT_STREAM0 SAI1_RXD0 ALT3
PDM_BIT_STREAM0 SAI5_RXD0 ALT4
PDM_BIT_STREAM1 SAI1_RXD1 ALT3
PDM_BIT_STREAM1 SAI5_RXD1 ALT4
PDM_BIT_STREAM2 SAI1_RXD2 ALT3
PDM_BIT_STREAM2 SAI5_RXD2 ALT4
PDM_BIT_STREAM3 SAI1_RXD3 ALT3
PDM_BIT_STREAM3 SAI5_RXD3 ALT4
PDM_CLK SAI1_TXD7 ALT3
PDM_CLK SAI1_MCLK ALT3
PDM_CLK SAI5_RXC ALT4
PWM1 PWM1_OUT GPIO1_IO01 ALT1
PWM1_OUT SPDIF_EXT_CLK ALT1
PWM1_OUT I2C4_SDA ALT1
PWM2 PWM2_OUT SPDIF_RX ALT1
PWM2_OUT I2C4_SCL ALT1
PWM2_OUT GPIO1_IO13 ALT5
PWM3 PWM3_OUT SPDIF_TX ALT1
PWM3_OUT I2C3_SDA ALT1
PWM3_OUT GPIO1_IO14 ALT5
PWM4 PWM4_OUT SAI3_MCLK ALT1
PWM4_OUT I2C3_SCL ALT1
PWM4_OUT GPIO1_IO15 ALT5
QSPI QSPI_A_DATA0 NAND_DATA00 ALT1
QSPI_A_DATA1 NAND_DATA01 ALT1
QSPI_A_DATA2 NAND_DATA02 ALT1
QSPI_A_DATA3 NAND_DATA03 ALT1
QSPI_A_DQS NAND_DQS ALT1
QSPI_A_SCLK NAND_ALE ALT1
QSPI_A_SS0_B NAND_CE0_B ALT1
QSPI_A_SS1_B NAND_CE1_B ALT1
QSPI_B_DATA0 NAND_DATA04 ALT1
QSPI_B_DATA1 NAND_DATA05 ALT1
QSPI_B_DATA2 NAND_DATA06 ALT1
QSPI_B_DATA3 NAND_DATA07 ALT1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1268 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
QSPI_B_DQS NAND_RE_B ALT1
QSPI_B_SCLK NAND_CLE ALT1
QSPI_B_SS0_B NAND_CE2_B ALT1
QSPI_B_SS1_B NAND_CE3_B ALT1
RAWNAND RAWNAND_ALE NAND_ALE ALT0
RAWNAND_CE0_B NAND_CE0_B ALT0
RAWNAND_CE1_B NAND_CE1_B ALT0
RAWNAND_CE2_B NAND_CE2_B ALT0
RAWNAND_CE3_B NAND_CE3_B ALT0
RAWNAND_CLE NAND_CLE ALT0
RAWNAND_DATA00 NAND_DATA00 ALT0
RAWNAND_DATA01 NAND_DATA01 ALT0
RAWNAND_DATA02 NAND_DATA02 ALT0
RAWNAND_DATA03 NAND_DATA03 ALT0
RAWNAND_DATA04 NAND_DATA04 ALT0
RAWNAND_DATA05 NAND_DATA05 ALT0
RAWNAND_DATA06 NAND_DATA06 ALT0
RAWNAND_DATA07 NAND_DATA07 ALT0
RAWNAND_DQS NAND_DQS ALT0
RAWNAND_RE_B NAND_RE_B ALT0
RAWNAND_READY_B NAND_READY_B ALT0
RAWNAND_WE_B NAND_WE_B ALT0
RAWNAND_WP_B NAND_WP_B ALT0
SAI1 SAI1_MCLK SAI1_MCLK ALT0
SAI1_RX_BCLK SAI1_RXC ALT0
SAI1_RX_DATA0 SAI1_RXD0 ALT0
SAI1_RX_DATA1 SAI1_RXD1 ALT0
SAI1_RX_DATA2 SAI1_RXD2 ALT0
SAI1_RX_DATA3 SAI1_RXD3 ALT0
SAI1_RX_DATA4 SAI1_RXD4 ALT0
SAI1_RX_DATA5 SAI1_RXD5 ALT0
SAI1_RX_DATA6 SAI1_RXD6 ALT0
SAI1_RX_DATA7 SAI1_RXD7 ALT0
SAI1_RX_SYNC SAI1_RXFS ALT0
SAI1_RXD5 ALT3
SAI1_TX_BCLK SAI1_TXC ALT0
SAI5_MCLK ALT1
SAI1_MCLK ALT2
SAI1_TX_DATA0 SAI1_TXD0 ALT0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1269
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
SAI5_RXFS ALT1
SAI1_TX_DATA1 SAI1_TXD1 ALT0
SAI5_RXC ALT1
SAI1_RXD0 ALT2
SAI1_TX_DATA2 SAI1_TXD2 ALT0
SAI5_RXD0 ALT1
SAI1_TX_DATA3 SAI1_TXD3 ALT0
SAI5_RXD1 ALT1
SAI1_TX_DATA4 SAI1_TXD4 ALT0
SAI5_RXD2 ALT1
SAI1_RXD7 ALT3
SAI1_TX_DATA5 SAI1_TXD5 ALT0
SAI5_RXD3 ALT1
SAI1_TX_DATA6 SAI1_TXD6 ALT0
SAI1_TX_DATA7 SAI1_TXD7 ALT0
SAI1_TX_SYNC SAI1_TXFS ALT0
SAI5_RXD1 ALT2
SAI5_RXD2 ALT2
SAI5_RXD3 ALT2
SAI1_RXD7 ALT2
SAI2 SAI2_MCLK SAI2_MCLK ALT0
SAI2_RX_BCLK SAI2_RXC ALT0
SAI2_RX_DATA0 SAI2_RXD0 ALT0
SAI2_RX_DATA1 SAI2_RXFS ALT3
SAI2_RX_SYNC SAI2_RXFS ALT0
SAI2_TX_BCLK SAI2_TXC ALT0
SAI2_TX_DATA0 SAI2_TXD0 ALT0
SAI2_TX_DATA1 SAI2_TXFS ALT3
SAI2_TX_SYNC SAI2_TXFS ALT0
SAI3 SAI3_MCLK SAI3_MCLK ALT0
SAI3_RX_BCLK SAI3_RXC ALT0
SAI3_RX_DATA0 SAI3_RXD ALT0
SAI3_RX_DATA1 SAI3_RXFS ALT3
SAI3_RX_SYNC SAI3_RXFS ALT0
SAI3_TX_BCLK SAI3_TXC ALT0
SAI3_TX_DATA0 SAI3_TXD ALT0
SAI3_TX_DATA1 SAI3_TXFS ALT3
SAI3_TX_SYNC SAI3_TXFS ALT0
SAI5 SAI5_MCLK SAI5_MCLK ALT0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1270 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
SAI1_MCLK ALT1
SAI2_MCLK ALT1
SAI3_MCLK ALT2
SAI5_RX_BCLK SAI5_RXC ALT0
SAI1_RXC ALT1
SAI3_RXC ALT2
SAI5_RX_DATA0 SAI5_RXD0 ALT0
SAI1_RXD0 ALT1
SAI3_RXD ALT2
SAI5_RX_DATA1 SAI5_RXD1 ALT0
SAI1_RXD1 ALT1
SAI3_TXFS ALT2
SAI5_RX_DATA2 SAI5_RXD2 ALT0
SAI1_RXD2 ALT1
SAI3_TXC ALT2
SAI5_RX_DATA3 SAI5_RXD3 ALT0
SAI1_RXD3 ALT1
SAI3_TXD ALT2
SAI5_RX_SYNC SAI5_RXFS ALT0
SAI1_RXFS ALT1
SAI3_RXFS ALT2
SAI5_TX_BCLK SAI1_TXC ALT1
SAI2_RXC ALT1
SAI5_RXD2 ALT3
SAI5_TX_DATA0 SAI1_TXD0 ALT1
SAI2_RXD0 ALT1
SAI5_RXD3 ALT3
SAI5_TX_DATA1 SAI1_TXD1 ALT1
SAI2_TXFS ALT1
SAI2_RXFS ALT2
SAI5_TX_DATA2 SAI1_TXD2 ALT1
SAI2_TXC ALT1
SAI5_TX_DATA3 SAI1_TXD3 ALT1
SAI2_TXD0 ALT1
SAI5_TX_SYNC SAI1_TXFS ALT1
SAI2_RXFS ALT1
SAI5_RXD1 ALT3
SAI6 SAI6_MCLK SAI1_RXD7 ALT1
SAI1_TXD7 ALT1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1271
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
SAI6_RX_BCLK SAI1_TXD4 ALT1
SAI1_RXD4 ALT2
SAI6_RX_DATA0 SAI1_TXD5 ALT1
SAI1_RXD5 ALT2
SAI6_RX_SYNC SAI1_TXD6 ALT1
SAI1_RXD6 ALT2
SAI6_TX_BCLK SAI1_RXD4 ALT1
SAI1_TXD4 ALT2
SAI6_TX_DATA0 SAI1_RXD5 ALT1
SAI1_TXD5 ALT2
SAI6_TX_SYNC SAI1_RXD6 ALT1
SAI1_TXD6 ALT2
SDMA SDMA1_EXT_EVENT0 GPIO1_IO03 ALT5
SDMA1_EXT_EVENT1 GPIO1_IO04 ALT5
SDMA2_EXT_EVENT0 GPIO1_IO09 ALT5
SDMA2_EXT_EVENT1 GPIO1_IO12 ALT5
SNVS SNVS_ONOFF ONOFF ALT0
SNVS_PMIC_ON_REQ PMIC_ON_REQ ALT0
SNVS_POR_B POR_B ALT0
SNVS_RTC RTC_XTALI ALT0
SNVS_RTC_RESET_B RTC_RESET_B ALT0
SPDIF1 SPDIF1_EXT_CLK SPDIF_EXT_CLK ALT0
SPDIF1_IN SPDIF_RX ALT0
SPDIF1_OUT SPDIF_TX ALT0
SRC SRC_BOOT_CFG0 SAI1_RXD0 ALT6
SRC_BOOT_CFG1 SAI1_RXD1 ALT6
SRC_BOOT_CFG10 SAI1_TXD2 ALT6
SRC_BOOT_CFG11 SAI1_TXD3 ALT6
SRC_BOOT_CFG12 SAI1_TXD4 ALT6
SRC_BOOT_CFG13 SAI1_TXD5 ALT6
SRC_BOOT_CFG14 SAI1_TXD6 ALT6
SRC_BOOT_CFG15 SAI1_TXD7 ALT6
SRC_BOOT_CFG2 SAI1_RXD2 ALT6
SRC_BOOT_CFG3 SAI1_RXD3 ALT6
SRC_BOOT_CFG4 SAI1_RXD4 ALT6
SRC_BOOT_CFG5 SAI1_RXD5 ALT6
SRC_BOOT_CFG6 SAI1_RXD6 ALT6
SRC_BOOT_CFG7 SAI1_RXD7 ALT6
SRC_BOOT_CFG8 SAI1_TXD0 ALT6

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1272 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
SRC_BOOT_CFG9 SAI1_TXD1 ALT6
SRC_BOOT_MODE0 BOOT_MODE0 ALT0
SRC_BOOT_MODE1 BOOT_MODE1 ALT0
SRC_EARLY_RESET SD2_DATA3 ALT6
SRC_SYSTEM_RESET SD2_RESET_B ALT6
UART1 UART1_CTS_B UART3_RXD ALT1
SAI2_TXFS ALT4
UART1_RTS_B UART3_TXD ALT1
SAI2_RXD0 ALT4
UART1_RX UART1_RXD ALT0
SAI2_RXC ALT4
UART1_TX UART1_TXD ALT0
SAI2_RXFS ALT4
UART2 UART2_CTS_B UART4_RXD ALT1
SAI3_RXC ALT4
UART2_RTS_B UART4_TXD ALT1
SAI3_RXD ALT4
UART2_RX UART2_RXD ALT0
SAI3_TXFS ALT4
UART2_TX UART2_TXD ALT0
SAI3_TXC ALT4
UART3 UART3_CTS_B ECSPI1_MISO ALT1
UART3_RTS_B ECSPI1_SS0 ALT1
UART3_RX UART3_RXD ALT0
ECSPI1_SCLK ALT1
UART3_TX UART3_TXD ALT0
ECSPI1_MOSI ALT1
UART4 UART4_CTS_B ECSPI2_MISO ALT1
UART4_RTS_B ECSPI2_SS0 ALT1
UART4_RX UART4_RXD ALT0
ECSPI2_SCLK ALT1
UART4_TX UART4_TXD ALT0
ECSPI2_MOSI ALT1
USB1 USB1_OTG_ID GPIO1_IO10 ALT1
USB1_OTG_OC GPIO1_IO13 ALT1
USB1_OTG_PWR GPIO1_IO12 ALT1
USB1_P1_ID USB1_ID No muxing
USB1_P1_VBUS USB1_VBUS No muxing
USB1_P1_DP USB1_DP No muxing

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1273
External Signals and Pin Multiplexing

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
USB1_P1_DN USB1_DN No muxing
USB2 USB2_OTG_ID GPIO1_IO11 ALT1
USB2_OTG_OC GPIO1_IO15 ALT1
USB2_OTG_PWR GPIO1_IO14 ALT1
USB2_P2_ID USB2_ID No muxing
USB2_P2_VBUS USB2_VBUS No muxing
USB2_P2_DP USB2_DP No muxing
USB2_P2_DN USB2_DN No muxing
USDHC1 USDHC1_CD_B GPIO1_IO06 ALT5
USDHC1_CLK SD1_CLK ALT0
USDHC1_CMD SD1_CMD ALT0
USDHC1_DATA0 SD1_DATA0 ALT0
USDHC1_DATA1 SD1_DATA1 ALT0
USDHC1_DATA2 SD1_DATA2 ALT0
USDHC1_DATA3 SD1_DATA3 ALT0
USDHC1_DATA4 SD1_DATA4 ALT0
USDHC1_DATA5 SD1_DATA5 ALT0
USDHC1_DATA6 SD1_DATA6 ALT0
USDHC1_DATA7 SD1_DATA7 ALT0
USDHC1_RESET_B SD1_RESET_B ALT0
USDHC1_STROBE SD1_STROBE ALT0
USDHC1_VSELECT GPIO1_IO03 ALT1
USDHC1_WP GPIO1_IO07 ALT5
USDHC2 USDHC2_CD_B SD2_CD_B ALT0
USDHC2_CLK SD2_CLK ALT0
USDHC2_CMD SD2_CMD ALT0
USDHC2_DATA0 SD2_DATA0 ALT0
USDHC2_DATA1 SD2_DATA1 ALT0
USDHC2_DATA2 SD2_DATA2 ALT0
USDHC2_DATA3 SD2_DATA3 ALT0
USDHC2_RESET_B SD2_RESET_B ALT0
GPIO1_IO08 ALT5
USDHC2_VSELECT GPIO1_IO04 ALT1
USDHC2_WP SD2_WP ALT0
USDHC3 USDHC3_CD_B NAND_DATA02 ALT2
I2C2_SCL ALT2
GPIO1_IO14 ALT4
USDHC3_CLK NAND_WE_B ALT2
USDHC3_CMD NAND_WP_B ALT2

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1274 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

Table 8-1. Muxing Options (continued)

Instance Port PAD MODE
USDHC3_DATA0 NAND_DATA04 ALT2
USDHC3_DATA1 NAND_DATA05 ALT2
USDHC3_DATA2 NAND_DATA06 ALT2
USDHC3_DATA3 NAND_DATA07 ALT2
USDHC3_DATA4 NAND_RE_B ALT2
USDHC3_DATA5 NAND_CE2_B ALT2
USDHC3_DATA6 NAND_CE3_B ALT2
USDHC3_DATA7 NAND_CLE ALT2
USDHC3_RESET_B NAND_READY_B ALT2
UART3_RXD ALT2
GPIO1_IO09 ALT4
USDHC3_STROBE NAND_CE1_B ALT2
USDHC3_VSELECT UART3_TXD ALT2
GPIO1_IO11 ALT4
USDHC3_WP NAND_DATA03 ALT2
I2C2_SDA ALT2
GPIO1_IO15 ALT4
WDOG1 WDOG1_ANY GPIO1_IO02 ALT5
WDOG1_B GPIO1_IO02 ALT1
XTALOSC REF_CLK_24M GPIO1_IO01 ALT5
REF_CLK_32K GPIO1_IO00 ALT5
XTALI_24M XTALI_24M ALT0
XTALO_24M XTALO_24M No muxing

8.2 IOMUX Controller (IOMUXC)

8.2.1 Overview
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC to share
one pad to several functional blocks. This sharing is done by multiplexing the pad's input
and output signals.
Every module requires a specific pad setting (such as pull up or keeper), and for each
pad, there are up to 8 muxing options (called ALT modes). The pad settings parameters
are controlled by the IOMUXC.
The IOMUX consists only of combinatorial logic combined from several basic IOMUX
cells. Each basic IOMUX cell handles only one pad signal's muxing.
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
NXP Semiconductors 1275
IOMUX Controller (IOMUXC)

Figure 8-1 illustrates the IOMUX/IOMUXC connectivity in the system.

PAD Settings

PAD Settings
Registers

MUX Control
Registers

IOMUXC
. .
IOMUX IO Pad
Cells
. Cells
.
. .

IPMUX
HW
signal
moduleY

CFG
AIPS Reg
moduleX IOMUX IORING

Arm PLATFORM + AHBMAX module module module

#1 #2 #N

Figure 8-1. IOMUX SoC Level Block Diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1276 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.1.1 Features
The IOMUXC features are:
• 32-bit software mux control registers (IOMUXC_SW_MUX_CTL_PAD_<PAD
NAME> or IOMUXC_SW_MUX_CTL_GRP_<GROUP NAME>) to configure 1 of
8 alternate (ALT) MUX_MODE feilds of each pad or a predefined group of pads and
to enable the forcing of an input path of the pad(s) (SION bit).
• 32-bit software pad control registers
(IOMUXC_SW_PAD_CTL_PAD_<PAD_NAME> or
IOMUXC_SW_PAD_CTL_GRP_<GROUP NAME>) to configure specific pad
settings of each pad, or a predefined group of pads.
• 32-bit general purpose registers - several (GPR0 to GPRn) 32-bit registers according
to SoC requirements for any usage.
• 32-bit input select control registers to control the input path to a module when more
than one pad drives this module input.
Each SW MUX/PAD CTL IOMUXC register handles only one pad or one pad's group.
Only the minimum number of registers required by software are implemented by
hardware. For example, if only ALT0 and ALT1 modes are used on Pad x then only one
bit register will be generated as the MUX_MODE control field in the software mux
control register of Pad x.
The software mux control registers may allow the forcing of pads to become input (input
path enabled) regardless of the functional direction driven. This may be useful for
loopback and GPIO data capture.

8.2.2 Clocks
The table found here describes the clock sources for IOMUXC.
Please see Clock Controller Module (CCM) for clock setting, configuration and gating
information.
Table 8-2. IOMUXC Clocks
Clock name Clock Root Description
ipg_clk_s ipg_clk_root Peripheral access clock

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1277
IOMUX Controller (IOMUXC)

8.2.3 Functional description

This section provides a complete functional description of the block.
The IOMUXC consists of two sub-blocks:
• IOMUXC_REGISTERS includes all of the IOMUXC registers (see Features).
• IOMUXC_LOGIC includes all of the IOMUXC combinatorial logic (IP interface
controls, address decoder, observability muxes).

The IOMUX consists of a number (about the number of pads in the SoC) of basic
iomux_cell units. If only one functional mode is required for a specific pad, there is no
need for IOMUX and the signals can be connected directly from the module to the I/O.
The IOMUX cell is required whenever two or more functional modes are required for a
specific pad or when one functional mode and the one test mode are required.
The basic iomux_cell design, which allows two levels of HW signal control (in ALT6
and ALT7 modes - ALT7 gets highest priority) is shown in Figure 8-2.

IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]

SW_PAD_CTL

ALT0
ALT1
: PAD0
ALTn

ALT0
ALT1
<SOURCE>_SELECT_INPUT :
ALTn
Peripheral1 DATA_IN IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]
SW_PAD_CTL
ALT0
ALT1
:
PAD1
ALTn

ALT0
ALT1
:
ALTn

Figure 8-2. IOMUX Cell Block Diagram

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1278 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.3.1 GPIO pad features

The GPIO pad includes the following features:
• Wide-range voltage interface
• 1.8V ~ 3.3V I/O interface
• CMOS input / Schmitt trigger Input
• 3-state and open-drain output
• Two slew rate control levels
• Programmable feature support
• Controllable input enable
• Controllable CMOS/Schmitt trigger input
• Controllable pull-up/pull-down resistor
• Controllable output drive strength (x1 / x2 / x4 / x6)
• Controllable slew rate control (slow slew / fast slew)

8.2.3.1.1 Pull up/Pull down control

Pull up/Pull down function is controlled by the PE and PS pin.
Table 8-3. Pull up / Pull down control truth table
Mode State
PE PS
Disable 0 X
Pull-down enable 1 0
Pull-up enable 1 1

8.2.3.1.2 Input control

The IS pin selects CMOS and Schmitt trigger.
Table 8-4. Input control truth table
Mode State
IE IS
Disable 0 X
CMOS input 1 0
Schmitt trigger input 1 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1279
IOMUX Controller (IOMUXC)

8.2.3.1.3 Output driver control

Output drive strength is controlled by the DS0, DS1 pin.
Table 8-5. Drive strength control truth table
State Driver Strength
DS1 DS0
0 0 X1
1 0 X2
0 1 X4
1 1 X6

The SR pin controls slew-rate of output driver.

Table 8-6. Slew-rate of output driver
State Driver Slew
SR
0 Fast Slew
1 Slow Slew

8.2.3.2 ALT6 and ALT7 extended muxing modes

The ALT7 and ALT6 extended muxing modes allow any signal in the system (such as
fuse, pad input, JTAG, or software register) to override any software configuration and to
force the ALT6/ALT7 muxing mode.
It also allows an IOMUX software register to control a group of pads.

8.2.3.3 SW Loopback through SION bit

A limited option exists to override the default pad functionality and force the input path
to be active (ipp_ibe==1'b1) regardless of the value driven by the corresponding module.
This can be done by setting the SION (Software Input On) bit in the
IOMUXC_SW_MUX_CTL register (when available) to "1".
Uses include:
• LoopBack - Module x drives the pad and also receives pad value as an input.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1280 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.3.4 Daisy chain - multi pads driving same module input pin
In some cases, more than one pad may drive a single module input pin. Such cases
require the addition of one more level of IOMUXing; all of these input signals are
muxed, and a dedicated software controlled register controls the mux in order to select
the required input path.
A module port involved in "daisy chain" requires two software configuration commands,
one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers).
This means that a module port involved in "daisy chain" requires two software
configuration commands, one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers). The daisy chain is illustrated in the figure below.

IOMUX IORING
IOMUX Cells

To module D

To module F
A
To module X

ALT x select

To module G

To module X
Module X B
To module H

ALT x select

Daisy Chain
To module X
select
To module M
C
To module N

ALT x select

Figure 8-3. Daisy chain illustration

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1281
IOMUX Controller (IOMUXC)

8.2.4 IOMUXC GPR Memory Map/Register Definition

IOMUXC_GPR memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
8.2.4.1/
3034_0000 General Purpose Register 0 (IOMUXC_GPR_GPR0) 32 R/W 0000_0000h
1284
8.2.4.2/
3034_0004 General Purpose Register 1 (IOMUXC_GPR_GPR1) 32 R/W 0000_0000h
1285
8.2.4.3/
3034_0008 General Purpose Register 2 (IOMUXC_GPR_GPR2) 32 R/W 0000_0000h
1286
8.2.4.4/
3034_000C General Purpose Register 3 (IOMUXC_GPR_GPR3) 32 R/W See section
1289
8.2.4.5/
3034_0010 General Purpose Register 4 (IOMUXC_GPR_GPR4) 32 R/W 0000_0000h
1293
8.2.4.6/
3034_0014 General Purpose Register 5 (IOMUXC_GPR_GPR5) 32 R/W 0000_0000h
1296
8.2.4.7/
3034_0018 General Purpose Register 6 (IOMUXC_GPR_GPR6) 32 R/W 0000_0000h
1297
8.2.4.8/
3034_001C General Purpose Register 7 (IOMUXC_GPR_GPR7) 32 R/W 0000_0000h
1299
8.2.4.9/
3034_0020 General Purpose Register 8 (IOMUXC_GPR_GPR8) 32 R/W 0000_0000h
1300
8.2.4.10/
3034_0024 General Purpose Register 9 (IOMUXC_GPR_GPR9) 32 R/W 0000_0000h
1301
8.2.4.11/
3034_0028 General Purpose Register 10 (IOMUXC_GPR_GPR10) 32 R/W 0000_0008h
1302
8.2.4.12/
3034_002C General Purpose Register 11 (IOMUXC_GPR_GPR11) 32 R/W 0000_0000h
1304
8.2.4.13/
3034_0030 General Purpose Register 12 (IOMUXC_GPR_GPR12) 32 R/W 0000_4000h
1306
8.2.4.14/
3034_0034 General Purpose Register 13 (IOMUXC_GPR_GPR13) 32 R/W See section
1307
8.2.4.15/
3034_0038 General Purpose Register 14 (IOMUXC_GPR_GPR14) 32 R/W 4B49_9100h
1309
8.2.4.16/
3034_003C General Purpose Register 15 (IOMUXC_GPR_GPR15) 32 R/W 6188_FFFFh
1310
8.2.4.17/
3034_0040 General Purpose Register 16 (IOMUXC_GPR_GPR16) 32 R/W 4940_9100h
1311
8.2.4.18/
3034_0044 General Purpose Register 17 (IOMUXC_GPR_GPR17) 32 R/W 6188_FFFFh
1312
8.2.4.19/
3034_0048 General Purpose Register 18 (IOMUXC_GPR_GPR18) 32 R/W 0000_0000h
1313
8.2.4.20/
3034_004C General Purpose Register 19 (IOMUXC_GPR_GPR19) 32 R See section
1313
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1282 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
8.2.4.21/
3034_0050 General Purpose Register 20 (IOMUXC_GPR_GPR20) 32 R/W 0000_0000h
1313
8.2.4.22/
3034_0054 General Purpose Register 21 (IOMUXC_GPR_GPR21) 32 R/W 0000_0000h
1314
8.2.4.23/
3034_0058 General Purpose Register 22 (IOMUXC_GPR_GPR22) 32 R/W See section
1315
8.2.4.24/
3034_005C General Purpose Register (IOMUXC_GPR_GPR23) 32 R/W Undefined
1315
8.2.4.24/
3034_0060 General Purpose Register (IOMUXC_GPR_GPR24) 32 R/W Undefined
1315
8.2.4.24/
3034_0064 General Purpose Register (IOMUXC_GPR_GPR25) 32 R/W Undefined
1315
8.2.4.24/
3034_0068 General Purpose Register (IOMUXC_GPR_GPR26) 32 R/W Undefined
1315
8.2.4.24/
3034_006C General Purpose Register (IOMUXC_GPR_GPR27) 32 R/W Undefined
1315
8.2.4.24/
3034_0070 General Purpose Register (IOMUXC_GPR_GPR28) 32 R/W Undefined
1315
8.2.4.24/
3034_0074 General Purpose Register (IOMUXC_GPR_GPR29) 32 R/W Undefined
1315
8.2.4.24/
3034_0078 General Purpose Register (IOMUXC_GPR_GPR30) 32 R/W Undefined
1315
8.2.4.24/
3034_007C General Purpose Register (IOMUXC_GPR_GPR31) 32 R/W Undefined
1315
8.2.4.24/
3034_0080 General Purpose Register (IOMUXC_GPR_GPR32) 32 R/W Undefined
1315
8.2.4.24/
3034_0084 General Purpose Register (IOMUXC_GPR_GPR33) 32 R/W Undefined
1315
8.2.4.24/
3034_0088 General Purpose Register (IOMUXC_GPR_GPR34) 32 R/W Undefined
1315
8.2.4.24/
3034_008C General Purpose Register (IOMUXC_GPR_GPR35) 32 R/W Undefined
1315
8.2.4.24/
3034_0090 General Purpose Register (IOMUXC_GPR_GPR36) 32 R/W Undefined
1315
8.2.4.24/
3034_0094 General Purpose Register (IOMUXC_GPR_GPR37) 32 R/W Undefined
1315
8.2.4.24/
3034_0098 General Purpose Register (IOMUXC_GPR_GPR38) 32 R/W Undefined
1315
8.2.4.24/
3034_009C General Purpose Register (IOMUXC_GPR_GPR39) 32 R/W Undefined
1315
8.2.4.24/
3034_00A0 General Purpose Register (IOMUXC_GPR_GPR40) 32 R/W Undefined
1315
8.2.4.24/
3034_00A4 General Purpose Register (IOMUXC_GPR_GPR41) 32 R/W Undefined
1315
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1283
IOMUX Controller (IOMUXC)

IOMUXC_GPR memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
8.2.4.24/
3034_00A8 General Purpose Register (IOMUXC_GPR_GPR42) 32 R/W Undefined
1315
8.2.4.24/
3034_00AC General Purpose Register (IOMUXC_GPR_GPR43) 32 R/W Undefined
1315
8.2.4.24/
3034_00B0 General Purpose Register (IOMUXC_GPR_GPR44) 32 R/W Undefined
1315
8.2.4.24/
3034_00B4 General Purpose Register (IOMUXC_GPR_GPR45) 32 R/W Undefined
1315
8.2.4.24/
3034_00B8 General Purpose Register (IOMUXC_GPR_GPR46) 32 R/W Undefined
1315
8.2.4.24/
3034_00BC General Purpose Register (IOMUXC_GPR_GPR47) 32 R/W Undefined
1315

8.2.4.1 General Purpose Register 0 (IOMUXC_GPR_GPR0)

Address: 3034_0000h base + 0h offset = 3034_0000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR0 field descriptions

Field Description
- This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1284 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.2 General Purpose Register 1 (IOMUXC_GPR_GPR1)

Address: 3034_0000h base + 4h offset = 3034_0004h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GPR_TZASC1_SECURE_
R

BOOT_LOCK

Reserved

Reserved
GPR_DBG_ACK Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_ENET1_TX_CLK_

R
GPR_IRQ
Reserved

Reserved

SEL

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR1 field descriptions

Field Description
31–28 For CA53 cores.
GPR_DBG_ACK
27–24 This field is reserved.
-
23 TZASC-1 Secure Boot Lock.
GPR_TZASC1_
SECURE_
BOOT_LOCK
22 This field is reserved.
-
21–17 This field is reserved.
-
16 This field is reserved.
-
15 This field is reserved.
-
14 This field is reserved.
-

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1285
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR1 field descriptions (continued)

Field Description
13 1 ENET1 RMII clock comes from CCM->pad->loopback. SOI bit for the pad
GPR_ENET1_ (IOMUXC_SW_INPUT_ON_PAD_ENET_TD2) should be set also.
TX_CLK_SEL 0 ENET1 RMII clock comes from external PHY or OSC
12 Generate IRQ on IRQ0.
GPR_IRQ
- This field is reserved.

8.2.4.3 General Purpose Register 2 (IOMUXC_GPR_GPR2)

Address: 3034_0000h base + 8h offset = 3034_0008h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GPR_GPT6_EXT_CLK_
R

SEL
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_SAI6_EXT_MCLK_

GPR_SAI5_EXT_MCLK_

GPR_SAI3_EXT_MCLK_

GPR_SAI2_EXT_MCLK_

GPR_SAI1_EXT_MCLK_
GPR_GPT5_EXT_CLK_

GPR_GPT4_EXT_CLK_

R
Reserved
SEL

SEL

EN

EN

EN

EN

EN
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR2 field descriptions

Field Description
31–20 This field is reserved.
-
19–16 GPT6 IPP_IND_CLKIN source select.
GPR_GPT6_
EXT_CLK_SEL 4'h0 SAI1_TX_SYNC
4'h1 SAI2_TX_SYNC
4'h2 SAI3_TX_SYNC
4'h3 Reserved
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1286 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR_GPR2 field descriptions (continued)

Field Description
4'h4 SAI5_TX_SYNC
4'h5 SAI6_TX_SYNC
4'h6 SAI1_RX_SYNC
4'h7 SAI2_RX_SYNC
4'h8 SAI3_RX_SYNC
4'h9 Reserved
4'ha SAI5_RX_SYNC
4'hb SAI6_RX_SYNC
15–12 GPT5 IPP_IND_CLKIN source select.
GPR_GPT5_
EXT_CLK_SEL 4'h0 SAI1_TX_SYNC
4'h1 SAI2_TX_SYNC
4'h2 SAI3_TX_SYNC
4'h3 Reserved
4'h4 SAI5_TX_SYNC
4'h5 SAI6_TX_SYNC
4'h6 SAI1_RX_SYNC
4'h7 SAI2_RX_SYNC
4'h8 SAI3_RX_SYNC
4'h9 Reserved
4'ha SAI5_RX_SYNC
4'hb SAI6_RX_SYNC
11–8 GPT4 IPP_IND_CLKIN source select.
GPR_GPT4_
EXT_CLK_SEL 4'h0 SAI1_TX_SYNC
4'h1 SAI2_TX_SYNC
4'h2 SAI3_TX_SYNC
4'h3 Reserved
4'h4 SAI5_TX_SYNC
4'h5 SAI6_TX_SYNC
4'h6 SAI1_RX_SYNC
4'h7 SAI2_RX_SYNC
4'h8 SAI3_RX_SYNC
4'h9 Reserved
4'ha SAI5_RX_SYNC
4'hb SAI6_RX_SYNC
7–6 This field is reserved.
-
5
GPR_SAI6_
EXT_MCLK_EN
4
GPR_SAI5_
EXT_MCLK_EN
3 This field is reserved.
-

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1287
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR2 field descriptions (continued)

Field Description
2
GPR_SAI3_
EXT_MCLK_EN
1
GPR_SAI2_
EXT_MCLK_EN
0
GPR_SAI1_
EXT_MCLK_EN

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1288 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.4 General Purpose Register 3 (IOMUXC_GPR_GPR3)

Address: 3034_0000h base + Ch offset = 3034_000Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ocram_ctrl_s_write_addr_pipeline_en_pndg

ocram_ctrl_s_write_data_pipeline_en_pndg

ocram_ctrl_s_read_addr_pipeline_en_pndg

ocram_ctrl_write_addr_pipeline_en_pndg

ocram_ctrl_write_data_pipeline_en_pndg

ocram_ctrl_read_addr_pipeline_en_pndg
ocram_ctrl_s_read_data_wait_en_pndg

ocram_ctrl_read_data_wait_en_pndg
R

Reserved

Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1289
IOMUX Controller (IOMUXC)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN

OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN

OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN

OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN

OCRAM_CTRL_WRITE_DATA_PIPELINE_EN

OCRAM_CTRL_READ_ADDR_PIPELINE_EN
R

OCRAM_CTRL_S_READ_DATA_WAIT_EN

OCRAM_CTRL_READ_DATA_WAIT_EN
Reserved

Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

* Notes:
• For reset:
[31:16] - N/A
[15:0] - 16'b0000000011111111

IOMUXC_GPR_GPR3 field descriptions

Field Description
31–24 This field is reserved.
-
23 Write address pipeline enable update is pending.
ocram_ctrl_s_
write_addr_
pipeline_en_pndg
22 Write data pipeline enable update is pending.
ocram_ctrl_s_
write_data_
pipeline_en_pndg

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1290 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR_GPR3 field descriptions (continued)

Field Description
21 Read address pipeline enable update is pending.
ocram_ctrl_s_
read_addr_
pipeline_en_pndg
20 Read data wait state control update is pending.
ocram_ctrl_s_
read_data_wait_
en_pndg
19 Write address pipeline enable update is pending.
ocram_ctrl_write_
addr_pipeline_
en_pndg
18 Write data pipeline enable update is pending.
ocram_ctrl_write_
data_pipeline_
en_pndg
17 Read address pipeline enable update is pending.
ocram_ctrl_read_
addr_pipeline_
en_pndg
16 Read data wait state control update is pending.
ocram_ctrl_read_
data_wait_en_
pndg
15–8 This field is reserved.
-
7 Write address pipeline enable.
OCRAM_CTRL_
S_WRITE_
ADDR_
PIPELINE_EN
6 Write data pipeline enable.
OCRAM_CTRL_
S_WRITE_
DATA_
PIPELINE_EN
5 Read address pipeline enable.
OCRAM_CTRL_
S_READ_
ADDR_
PIPELINE_EN
4 Read data wait state control.
OCRAM_CTRL_
S_READ_DATA_
WAIT_EN
3 Write address pipeline enable.
OCRAM_CTRL_
WRITE_ADDR_
PIPELINE_EN

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1291
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR3 field descriptions (continued)

Field Description
2 Write data pipeline enable.
OCRAM_CTRL_
WRITE_DATA_
PIPELINE_EN
1 Read address pipeline enable.
OCRAM_CTRL_
READ_ADDR_
PIPELINE_EN
0 Read data wait state control.
OCRAM_CTRL_
READ_DATA_
WAIT_EN

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1292 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.5 General Purpose Register 4 (IOMUXC_GPR_GPR4)

Address: 3034_0000h base + 10h offset = 3034_0010h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDMA2_IPG_STOP_ACK

SDMA3_IPG_STOP_ACK

SDMA1_IPG_STOP_ACK
ENET1_IPG_STOP_ACK
PDM_IPG_STOP_ACK

SAI6_IPG_STOP_ACK

SAI5_IPG_STOP_ACK

SAI3_IPG_STOP_ACK

SAI2_IPG_STOP_ACK

SAI1_IPG_STOP_ACK
R

Reserved

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1293
IOMUX Controller (IOMUXC)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPR_SDMA3_IPG_STOP

GPR_SDMA2_IPG_STOP

GPR_SDMA1_IPG_STOP
GPR_ENET1_IPG_STOP

Reserved

Reserved
Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR4 field descriptions

Field Description
31–28 This field is reserved.
-
27 PDM stop acknowledge.
PDM_IPG_
STOP_ACK
26 SAI6 stop acknowledge.
SAI6_IPG_
STOP_ACK
25 SAI5 stop acknowledge.
SAI5_IPG_
STOP_ACK
24 This field is reserved.
-
23 SAI3 stop acknowledge.
SAI3_IPG_
STOP_ACK
22 SAI2 stop acknowledge.
SAI2_IPG_
STOP_ACK
21 SAI1 stop acknowledge.
SAI1_IPG_
STOP_ACK
20 SDMA2 stop acknowledge.
SDMA2_IPG_
STOP_ACK

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1294 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR_GPR4 field descriptions (continued)

Field Description
19 ENET1 stop acknowledge.
ENET1_IPG_
STOP_ACK
18 SDMA3 stop acknowledge.
SDMA3_IPG_
STOP_ACK
17 This field is reserved.
-
16 SDMA1 stop acknowledge.
SDMA1_IPG_
STOP_ACK
15–13 This field is reserved.
-
12 SDMA3 stop request.
GPR_SDMA3_
IPG_STOP
11–5 This field is reserved.
-
4 SDMA2 stop request.
GPR_SDMA2_
IPG_STOP
3 ENET1 stop request.
GPR_ENET1_
IPG_STOP
2 This field is reserved.
-
1 This field is reserved.
-
0 SDMA1 stop request.
GPR_SDMA1_
IPG_STOP

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1295
IOMUX Controller (IOMUXC)

8.2.4.6 General Purpose Register 5 (IOMUXC_GPR_GPR5)

Address: 3034_0000h base + 14h offset = 3034_0014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GPR_WDOG3_
R

MASK
RESERVED Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPR_WDOG2_

GPR_WDOG1_
R

MASK

MASK
Reserved Reserved
W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR5 field descriptions

Field Description
31–21 This field is reserved.
RESERVED
20 This bit is only used to mask the internal WDOG3 int signal for the output of GPIO1_IO02.ALT5_OUT,
GPR_WDOG3_ which is combined with WDOG1/2/3.
MASK
0 WDOG3 low will make the GPIO1_IO02.ALT5_OUT low
1 WDOG3 low will not impact the GPIO1_IO02.ALT5_OUT
19–8 This field is reserved.
-
7 This bit is only used to mask the internal WDOG2 int signal for the output of GPIO1_IO02.ALT5_OUT,
GPR_WDOG2_ which is combined with WDOG1/2/3.
MASK
0 WDOG2 low will make the GPIO1_IO02.ALT5_OUT low
1 WDOG2 low will not impact the GPIO1_IO02.ALT5_OUT
6 Normally, WDOG1 output is in GPIO1_IO02.ALT1_OUT. This bit is only used to mask the internal
GPR_WDOG1_ WDOG1 int signal for the output of GPIO1_IO02.ALT5_OUT, which is combined with WDOG1/2/3.
MASK
0 WDOG1 low will make the GPIO1_IO02.ALT5_OUT low
1 WDOG1 low will not impact the GPIO1_IO02.ALT5_OUT
- This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1296 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.7 General Purpose Register 6 (IOMUXC_GPR_GPR6)

Address: 3034_0000h base + 18h offset = 3034_0018h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GPR_SAI2_MCLK_

GPR_SAI2_SEL1
R OUT_SEL

Reserved GPR_SAI2_SEL2 Reserved GPR_SAI2_SEL3

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_SAI1_MCLK_

GPR_SAI1_SEL1
R
OUT_SEL

Reserved GPR_SAI1_SEL2 Reserved GPR_SAI1_SEL3

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR6 field descriptions

Field Description
31–30 This field is reserved.
-
29 Please refer to SAI1 control bit.
GPR_SAI2_
MCLK_OUT_SEL
28–24 Please refer to SAI1 control bit.
GPR_SAI2_SEL2
23–22 This field is reserved.
-
21 Please refer to SAI1 control bit.
GPR_SAI2_SEL1
20–16 Please refer to SAI1 control bit.
GPR_SAI2_SEL3
15–14 This field is reserved.
-
13 SAIn MCLK output select.
GPR_SAI1_
MCLK_OUT_SEL 1'd0 SAIn_CLK_ROOT
1'd1 IPP_DO_SAI_MCLK of SAIn
12–8 IPG_CLK_SAI_MCLK[2] of SAIn source select.
GPR_SAI1_SEL2
5'd0 SAI1_CLK_ROOT
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1297
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR6 field descriptions (continued)

Field Description
5'd1 SAI2_CLK_ROOT
5'd2 SAI3_CLK_ROOT
5'd3 Reserved
5'd4 SAI5_CLK_ROOT
5'd5 SAI6_CLK_ROOT
5'd6 SAI1.MCLK
5'd7 SAI2.MCLK
5'd8 SAI3.MCLK
5'd9 Reserved
5'd10 SAI5.MCLK
5'd11 SAI6.MCLK
5'd12 SPDIF1_CLK_ROOT
5'd13 Reserved
5'd14 SPDIF1.EXTCLK
5'd15 SPDIF1.SRCCLK
5'd16 SPDIF1.OUTCLK
5'd17 Reserved
7–6 This field is reserved.
-
5 IPG_CLK_SAI_MCLK of SAIn source select.
GPR_SAI1_SEL1
1'd0 SAIn_CLK_ROOT
1'd1 SAIn.MCLK
GPR_SAI1_SEL3 IPG_CLK_SAI_MCLK[3] of SAIn source select.

5'd0 SAI1_CLK_ROOT
5'd1 SAI2_CLK_ROOT
5'd2 SAI3_CLK_ROOT
5'd3 Reserved
5'd4 SAI5_CLK_ROOT
5'd5 SAI6_CLK_ROOT
5'd6 SAI1.MCLK
5'd7 SAI2.MCLK
5'd8 SAI3.MCLK
5'd9 Reserved
5'd10 SAI5.MCLK
5'd11 SAI6.MCLK
5'd12 SPDIF1_CLK_ROOT
5'd13 Reserved
5'd14 SPDIF1.EXTCLK
5'd15 SPDIF1.SRCCLK
5'd16 SPDIF1.OUTCLK
5'd17 Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1298 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.8 General Purpose Register 7 (IOMUXC_GPR_GPR7)

Address: 3034_0000h base + 1Ch offset = 3034_001Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R
Reserved

Reserved
Reserved Reserved Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_SAI3_MCLK_OUT_

GPR_SAI3_SEL1
R
SEL

Reserved GPR_SAI3_SEL2 Reserved GPR_SAI3_SEL3

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR7 field descriptions

Field Description
31–30 This field is reserved.
-
29 This field is reserved.
-
28–24 This field is reserved.
-
23–22 This field is reserved.
-
21 This field is reserved.
-
20–16 This field is reserved.
-
15–14 This field is reserved.
-
13 Please refer to SAI1 control bit.
GPR_SAI3_
MCLK_OUT_SEL
12–8 Please refer to SAI1 control bit.
GPR_SAI3_SEL2

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1299
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR7 field descriptions (continued)

Field Description
7–6 This field is reserved.
-
5 Please refer to SAI1 control bit.
GPR_SAI3_SEL1
GPR_SAI3_SEL3 Please refer to SAI1 control bit.

8.2.4.9 General Purpose Register 8 (IOMUXC_GPR_GPR8)

Address: 3034_0000h base + 20h offset = 3034_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR_SAI6_MCLK_

GPR_SAI6_SEL1
R
OUT_SEL

Reserved GPR_SAI6_SEL2 Reserved GPR_SAI6_SEL3

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_SAI5_MCLK_

GPR_SAI5_SEL1

R
OUT_SEL

Reserved GPR_SAI5_SEL2 Reserved GPR_SAI5_SEL3

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR8 field descriptions

Field Description
31–30 This field is reserved.
-
29 Please refer to SAI1 control bit.
GPR_SAI6_
MCLK_OUT_SEL
28–24 Please refer to SAI1 control bit.
GPR_SAI6_SEL2
23–22 This field is reserved.
-
21 Please refer to SAI1 control bit.
GPR_SAI6_SEL1

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1300 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR_GPR8 field descriptions (continued)

Field Description
20–16 Please refer to SAI1 control bit.
GPR_SAI6_SEL3
15–14 This field is reserved.
-
13 Please refer to SAI1 control bit.
GPR_SAI5_
MCLK_OUT_SEL
12–8 Please refer to SAI1 control bit.
GPR_SAI5_SEL2
7–6 This field is reserved.
-
5 Please refer to SAI1 control bit.
GPR_SAI5_SEL1
GPR_SAI5_SEL3 Please refer to SAI1 control bit.

8.2.4.10 General Purpose Register 9 (IOMUXC_GPR_GPR9)

Address: 3034_0000h base + 24h offset = 3034_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR9 field descriptions

Field Description
- This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1301
IOMUX Controller (IOMUXC)

8.2.4.11 General Purpose Register 10 (IOMUXC_GPR_GPR10)

NOTE
Set GPR10[1] to 1 when TZASC_EN is enabled.
Address: 3034_0000h base + 28h offset = 3034_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LOCK_GPR_EXC_ERR_

LOCK_GPR_SEC_ERR_

LOCK_GPR_TZASC_EN
R

RESP_EN

RESP_EN

Reserved
Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPR_EXC_ERR_RESP_

GPR_SEC_ERR_RESP_

GPR_TZASC_EN
R

EN

EN
Reserved

W 1

Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

IOMUXC_GPR_GPR10 field descriptions

Field Description
31–20 This field is reserved.
-
19 This is a "sticky" type bit.
LOCK_GPR_
Lock bit for GPR_EXC_ERR_RESP_EN.
EXC_ERR_
RESP_EN
18 This is a "sticky" type bit.
LOCK_GPR_
Lock bit for GPR_SEC_ERR_RESP_EN.
SEC_ERR_
RESP_EN
17 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1302 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR_GPR10 field descriptions (continued)

Field Description
16 This is a "sticky" type bit.
LOCK_GPR_
Lock bit for GPR_TZASC_EN.
TZASC_EN
15–4 This field is reserved.
-
3 This is a "lock" type bit.
GPR_EXC_
ERR_RESP_EN
2 This is a "lock" type bit.
GPR_SEC_
ERR_RESP_EN
1 Reserved. Set this bit to 1.
-
0 This is a "lock" type bit.
GPR_TZASC_EN Connect to TZASC_EN input on TZASC_ID_WRAP.

NOTE: Ensure GPR10[1] is set to 1 when TZASC_EN is enabled.

0 Do not use the TZASC module. All transactions are routed around the TZASC block.
1 Enable the TZASC module. All transactions are processed by this block as per the TZASC TRM
describes.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1303
IOMUX Controller (IOMUXC)

8.2.4.12 General Purpose Register 11 (IOMUXC_GPR_GPR11)

Address: 3034_0000h base + 2Ch offset = 3034_002Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OCRAM_TZ_SECURE_REGION0

OCRAM_TZ_SECURE_REGION0
LOCK_GPR_OCRAM_CTRL_S_

LOCK_GPR_OCRAM_CTRL_
R

LOCK_GPR_
OCRAM_CTRL_S_ LOCK_GPR_OCRAM_CTRL_
Reserved Reserved
OCRAM_TZ_ OCRAM_TZ_SECURE_REGION1
SECURE_REGION1

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_OCRAM_CTRL_S_OCRAM_

GPR_OCRAM_CTRL_OCRAM_
TZ_SECURE_REGION0

TZ_SECURE_REGION0
R

GPR_OCRAM_
CTRL_S_OCRAM_ GPR_OCRAM_CTRL_OCRAM_
Reserved Reserved
TZ_SECURE_ TZ_SECURE_REGION1
REGION1

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR11 field descriptions

Field Description
31–30 This field is reserved.
-
29–27 This is a "sticky" type bit.
LOCK_GPR_
Lock bit for GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1[13:11].
OCRAM_CTRL_
S_OCRAM_TZ_
SECURE_
REGION1
26 This is a "sticky" type bit.
LOCK_GPR_
Lock bit for GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0[10].
OCRAM_CTRL_
S_OCRAM_TZ_
SECURE_
REGION0

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1304 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR_GPR11 field descriptions (continued)

Field Description
25–22 This field is reserved.
-
21–17 This is a "sticky" type bit.
LOCK_GPR_
Lock bit for GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1[5:1].
OCRAM_CTRL_
OCRAM_TZ_
SECURE_
REGION1
16 This is a "sticky" type bit.
LOCK_GPR_
Lock bit for GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0[0].
OCRAM_CTRL_
OCRAM_TZ_
SECURE_
REGION0
15–14 This field is reserved.
-
13–11 This is a "lock" type bit.
GPR_OCRAM_
CTRL_S_
OCRAM_TZ_
SECURE_
REGION1
10 This is a "lock" type bit.
GPR_OCRAM_
CTRL_S_
OCRAM_TZ_
SECURE_
REGION0
9–6 This field is reserved.
-
5–1 This is a "lock" type bit.
GPR_OCRAM_
CTRL_OCRAM_
TZ_SECURE_
REGION1
0 This is a "lock" type bit.
GPR_OCRAM_
CTRL_OCRAM_
TZ_SECURE_
REGION0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1305
IOMUX Controller (IOMUXC)

8.2.4.13 General Purpose Register 12 (IOMUXC_GPR_GPR12)

Address: 3034_0000h base + 30h offset = 3034_0030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GPR_PCIE1_CTRL_
DIAG_CTRL_BUS
R

Reserved
GPR_PCIE1_CTRL_DIAG_
Reserved
STATUS_BUS_SELECT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPR_PCIE1_CTRL_
Reserved
DEVICE_TYPE

Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR12 field descriptions

Field Description
31–23 This field is reserved.
-
22–21 PCIe Diagnostic Control Bus.
GPR_PCIE1_
CTRL_DIAG_
CTRL_BUS
20–17 PCIe Diagnostic Status Bus Select.
GPR_PCIE1_
CTRL_DIAG_
STATUS_BUS_
SELECT
16 This field is reserved.
-
15–12 PCIe device/port type.
GPR_PCIE1_
CTRL_DEVICE_
TYPE
- This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1306 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.14 General Purpose Register 13 (IOMUXC_GPR_GPR13)

Address: 3034_0000h base + 34h offset = 3034_0034h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reserved

Reserved
Reserved

Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPR_AWCACHE_USDHC
GPR_AWCACHE_PCIE1_

GPR_ARCACHE_USDHC
GPR_ARCACHE_PCIE1_

GPR_AWCACHE_PCIE1

GPR_ARCACHE_PCIE1
GPR_AWCACHE_USB2

GPR_AWCACHE_USB1
GPR_ARCACHE_USB2

GPR_ARCACHE_USB1
R
Reserved

Reserved

Reserved

Reserved
EN

EN

Reserved

Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

* Notes:
• For reset:
[31:19] - N/A
[18:0] - 19'b0

IOMUXC_GPR_GPR13 field descriptions

Field Description
31–19 This field is reserved.
-
18 This field is reserved.
-
17 This field is reserved.
-
16 This field is reserved.
-
15 This field is reserved.
-

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1307
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR13 field descriptions (continued)

Field Description
14 Control the AWCACHE[1] of USB2 master transaction.
GPR_
AWCACHE_
USB2
13 Control the ARCACHE[1] of USB2 master transaction.
GPR_
ARCACHE_
USB2
12 This field is reserved.
-
11 Enable the GPR control of AWCACHE[1] of PCIE1 master transaction.
GPR_
AWCACHE_
PCIE1_EN
10 Enable the GPR control of ARCACHE[1] of PCIE1 master transaction.
GPR_
ARCACHE_
PCIE1_EN
9 This field is reserved.
-
8 Control the AWCACHE[1] of USB1 master transaction.
GPR_
AWCACHE_
USB1
7 Control the ARCACHE[1] of USB1 master transaction.
GPR_
ARCACHE_
USB1
6 This field is reserved.
-
5 Control the AWCACHE[1] of PCIE1 master transaction.
GPR_
AWCACHE_
PCIE1
4 Control the ARCACHE[1] of PCIE1 master transaction.
GPR_
ARCACHE_
PCIE1
3–2 This field is reserved.
-
1 Control the AWCACHE[1] of USDHC master transaction.
GPR_
AWCACHE_
USDHC
0 Control the ARCACHE[1] of USDHC master transaction.
GPR_
ARCACHE_
USDHC

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1308 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.15 General Purpose Register 14 (IOMUXC_GPR_GPR14)

Address: 3034_0000h base + 38h offset = 3034_0038h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FUNC_I_POWER_OFF
FUNC_I_CMN_RSTN
GPR_PCIE1_PHY_

GPR_PCIE1_PHY_

GPR_PCIE1_PHY_

GPR_PCIE1_PHY_
FUNC_I_AUX_EN

FUNC_I_SSC_EN
R
GPR_
PCIE1_PHY_
Reserved FUNC_I_ Reserved
PLL_REF_
W
CLK_SEL

Reset 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1

Bit 15 14 13 12 11 10 9
AUX_EN_OVERRIDE_EN 8 7 6 5 4 3 2 1 0

GPR_PCIE1_APP_CLK_
GPR_PCIE1_CLKREQ_

GPR_PCIE1_CLKREQ_

GPR_PCIE1_PHY_I_
B_OVERRIDE_EN

R
B_OVERRIDE
Reserved

PM_EN

Reserved Reserved Reserved

Reset 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR14 field descriptions

Field Description
31–26 This field is reserved.
-
25–24 00 N/A
GPR_PCIE1_ 01 Selects reference clock from XO (pll_refclk_from_xo)
PHY_FUNC_I_ 10 Selects reference clock from IO (ext_ref_clkp/n)
PLL_REF_CLK_
11 Selects reference clock from SOC PLL (pll_refclk_from_syspll)
SEL
23–20 This field is reserved.
-
19 External Reference Clock I/O (for PLL) Enable Signal.
GPR_PCIE1_ NOTE: Please see bit field 9 for more details.
PHY_FUNC_I_
AUX_EN 1 Enable
0 Disable
18 Resets the PCIe PHY Common Block Reset.
GPR_PCIE1_
This is an Active low reset for PCIe PHY Common Block.
PHY_FUNC_I_
CMN_RSTN

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1309
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR14 field descriptions (continued)

Field Description
17 PMA power down signal.
GPR_PCIE1_
PHY_FUNC_I_ 1 Power Down
POWER_OFF 0 Power Up
16 SSC enable signal.
GPR_PCIE1_
PHY_FUNC_I_ 1 Enable
SSC_EN 0 Disable
15–13 This field is reserved.
-
12 This field is reserved.
-
11 Control PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller.
GPR_PCIE1_
CLKREQ_B_
OVERRIDE
10 Control PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller.
GPR_PCIE1_
CLKREQ_B_
OVERRIDE_EN
9 {GPR_PCIE1_PHY_I_AUX_EN_OVERRIDE_EN, GPR_PCIE1_PHY_FUNC_I_AUX_EN}
GPR_PCIE1_
PHY_I_AUX_ 2'b00 External Reference Clock I/O (for PLL) Disable
EN_OVERRIDE_ 2'b01 External Reference Clock I/O (for PLL) Enable
EN 2'b10 External Reference Clock I/O (for PLL) Disable
2'b11 External Reference Clock I/O (for PLL) output is controlled by CLKREQ#
8 To PCIe CTRL.
GPR_PCIE1_
APP_CLK_PM_
EN
7–4 This field is reserved.
-
- This field is reserved.

8.2.4.16 General Purpose Register 15 (IOMUXC_GPR_GPR15)

Address: 3034_0000h base + 3Ch offset = 3034_003Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved Reserved Reserved Reserved
Reset 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1310 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_GPR_GPR15 field descriptions

Field Description
31–26 This field is reserved.
-
25–20 This field is reserved.
-
19–14 This field is reserved.
-
13–7 This field is reserved.
-
- This field is reserved.

8.2.4.17 General Purpose Register 16 (IOMUXC_GPR_GPR16)

Address: 3034_0000h base + 40h offset = 3034_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved Reserved Reserved Reserved

Reset 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved

Reserved

Reserved

Reserved

Reserved Reserved Reserved

Reset 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR16 field descriptions

Field Description
31–29 This field is reserved.
-
28–24 This field is reserved.
-
23–21 This field is reserved.
-

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1311
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPR16 field descriptions (continued)

Field Description
20–16 This field is reserved.
-
15–13 This field is reserved.
-
12 This field is reserved.
-
11 This field is reserved.
-
10 This field is reserved.
-
9 This field is reserved.
-
8 This field is reserved.
-
7–4 This field is reserved.
-
- This field is reserved.

8.2.4.18 General Purpose Register 17 (IOMUXC_GPR_GPR17)

Address: 3034_0000h base + 44h offset = 3034_0044h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Reserved Reserved Reserved Reserved
Reset 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IOMUXC_GPR_GPR17 field descriptions

Field Description
31–26 This field is reserved.
-
25–20 This field is reserved.
-
19–14 This field is reserved.
-
13–7 This field is reserved.
-
- This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1312 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.19 General Purpose Register 18 (IOMUXC_GPR_GPR18)

Address: 3034_0000h base + 48h offset = 3034_0048h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR18 field descriptions

Field Description
- This field is reserved.

8.2.4.20 General Purpose Register 19 (IOMUXC_GPR_GPR19)

Address: 3034_0000h base + 4Ch offset = 3034_004Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R PCIE_DIAG_STATUS
W

Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

* Notes:
• For reset:
[31:0] - N/A

IOMUXC_GPR_GPR19 field descriptions

Field Description
PCIE_DIAG_ From PCIE.
STATUS

8.2.4.21 General Purpose Register 20 (IOMUXC_GPR_GPR20)

Address: 3034_0000h base + 50h offset = 3034_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR20 field descriptions

Field Description
- This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1313
IOMUX Controller (IOMUXC)

8.2.4.22 General Purpose Register 21 (IOMUXC_GPR_GPR21)

Address: 3034_0000h base + 54h offset = 3034_0054h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reserved
Reserved Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_GPR_GPR21 field descriptions

Field Description
31–20 This field is reserved.
-
19 This field is reserved.
-
18 This field is reserved.
-
- This field is reserved.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1314 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.4.23 General Purpose Register 22 (IOMUXC_GPR_GPR22)

Address: 3034_0000h base + 58h offset = 3034_0058h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CPU_ CPU_
R STANDBYWF STANDBYWF
Reserved E I Reserved

Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

* Notes:
• For reset:
[31:16] - N/A
[15:0] - 16'b0

IOMUXC_GPR_GPR22 field descriptions

Field Description
31–24 This field is reserved.
-
23–20 From CA53.
CPU_
STANDBYWFE
19–16 From CA53.
CPU_
STANDBYWFI
- This field is reserved.

8.2.4.24 General Purpose Register (IOMUXC_GPR_GPRn)

Reserved.
Address: 3034_0000h base + 5Ch offset + (4d × i), where i=0d to 24d

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
-
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

* Notes:
• x = Undefined at reset.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1315
IOMUX Controller (IOMUXC)

IOMUXC_GPR_GPRn field descriptions

Field Description
- Reserved.

8.2.5 IOMUXC Memory Map/Register Definition

IOMUXC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Mux Register 8.2.5.1/
3033_0014 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ) 1331
Pad Mux Register 8.2.5.2/
3033_0018 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ) 1332
Pad Mux Register 8.2.5.3/
3033_001C 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_ONOFF) 1332
8.2.5.4/
3033_0020 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_POR_B) 32 R/W 0000_0000h
1333
Pad Mux Register 8.2.5.5/
3033_0024 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B) 1333
Pad Mux Register 8.2.5.6/
3033_0028 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00) 1334
Pad Mux Register 8.2.5.7/
3033_002C 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01) 1335
Pad Mux Register 8.2.5.8/
3033_0030 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02) 1336
Pad Mux Register 8.2.5.9/
3033_0034 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03) 1337
Pad Mux Register 8.2.5.10/
3033_0038 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04) 1338
Pad Mux Register 8.2.5.11/
3033_003C 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05) 1339
Pad Mux Register 8.2.5.12/
3033_0040 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06) 1340
Pad Mux Register 8.2.5.13/
3033_0044 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07) 1341
Pad Mux Register 8.2.5.14/
3033_0048 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08) 1342
Pad Mux Register 8.2.5.15/
3033_004C 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09) 1343
Pad Mux Register 8.2.5.16/
3033_0050 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10) 1344
Pad Mux Register 8.2.5.17/
3033_0054 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11) 1345
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1316 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Mux Register 8.2.5.18/
3033_0058 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12) 1346
Pad Mux Register 8.2.5.19/
3033_005C 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13) 1347
Pad Mux Register 8.2.5.20/
3033_0060 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14) 1348
Pad Mux Register 8.2.5.21/
3033_0064 32 R/W 0000_0000h
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15) 1349
Pad Mux Register 8.2.5.22/
3033_0068 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_MDC) 1350
Pad Mux Register 8.2.5.23/
3033_006C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO) 1351
Pad Mux Register 8.2.5.24/
3033_0070 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD3) 1352
Pad Mux Register 8.2.5.25/
3033_0074 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD2) 1353
Pad Mux Register 8.2.5.26/
3033_0078 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD1) 1354
Pad Mux Register 8.2.5.27/
3033_007C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD0) 1355
Pad Mux Register 8.2.5.28/
3033_0080 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL) 1356
Pad Mux Register 8.2.5.29/
3033_0084 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_TXC) 1357
Pad Mux Register 8.2.5.30/
3033_0088 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL) 1358
Pad Mux Register 8.2.5.31/
3033_008C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RXC) 1359
Pad Mux Register 8.2.5.32/
3033_0090 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD0) 1360
Pad Mux Register 8.2.5.33/
3033_0094 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD1) 1361
Pad Mux Register 8.2.5.34/
3033_0098 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD2) 1362
Pad Mux Register 8.2.5.35/
3033_009C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD3) 1363
Pad Mux Register 8.2.5.36/
3033_00A0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK) 1364
Pad Mux Register 8.2.5.37/
3033_00A4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_CMD) 1365
Pad Mux Register 8.2.5.38/
3033_00A8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0) 1366
Pad Mux Register 8.2.5.39/
3033_00AC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1) 1367
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1317
IOMUX Controller (IOMUXC)

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Mux Register 8.2.5.40/
3033_00B0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2) 1368
Pad Mux Register 8.2.5.41/
3033_00B4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3) 1369
Pad Mux Register 8.2.5.42/
3033_00B8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4) 1370
Pad Mux Register 8.2.5.43/
3033_00BC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5) 1371
Pad Mux Register 8.2.5.44/
3033_00C0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6) 1372
Pad Mux Register 8.2.5.45/
3033_00C4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7) 1373
Pad Mux Register 8.2.5.46/
3033_00C8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B) 1374
Pad Mux Register 8.2.5.47/
3033_00CC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_STROBE) 1375
Pad Mux Register 8.2.5.48/
3033_00D0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B) 1376
Pad Mux Register 8.2.5.49/
3033_00D4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_CLK) 1377
Pad Mux Register 8.2.5.50/
3033_00D8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_CMD) 1378
Pad Mux Register 8.2.5.51/
3033_00DC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0) 1379
Pad Mux Register 8.2.5.52/
3033_00E0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1) 1380
Pad Mux Register 8.2.5.53/
3033_00E4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2) 1381
Pad Mux Register 8.2.5.54/
3033_00E8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3) 1382
Pad Mux Register 8.2.5.55/
3033_00EC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B) 1383
Pad Mux Register 8.2.5.56/
3033_00F0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_WP) 1384
Pad Mux Register 8.2.5.57/
3033_00F4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE) 1385
Pad Mux Register 8.2.5.58/
3033_00F8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B) 1386
Pad Mux Register 8.2.5.59/
3033_00FC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B) 1387
Pad Mux Register 8.2.5.60/
3033_0100 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B) 1388
Pad Mux Register 8.2.5.61/
3033_0104 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B) 1389
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1318 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Mux Register 8.2.5.62/
3033_0108 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE) 1390
Pad Mux Register 8.2.5.63/
3033_010C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00) 1391
Pad Mux Register 8.2.5.64/
3033_0110 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01) 1392
Pad Mux Register 8.2.5.65/
3033_0114 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02) 1393
Pad Mux Register 8.2.5.66/
3033_0118 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03) 1394
Pad Mux Register 8.2.5.67/
3033_011C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04) 1395
Pad Mux Register 8.2.5.68/
3033_0120 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05) 1396
Pad Mux Register 8.2.5.69/
3033_0124 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06) 1397
Pad Mux Register 8.2.5.70/
3033_0128 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07) 1398
Pad Mux Register 8.2.5.71/
3033_012C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_DQS) 1399
Pad Mux Register 8.2.5.72/
3033_0130 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B) 1400
Pad Mux Register 8.2.5.73/
3033_0134 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B) 1401
Pad Mux Register 8.2.5.74/
3033_0138 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B) 1402
Pad Mux Register 8.2.5.75/
3033_013C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B) 1403
Pad Mux Register 8.2.5.76/
3033_0140 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS) 1404
Pad Mux Register 8.2.5.77/
3033_0144 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC) 1405
Pad Mux Register 8.2.5.78/
3033_0148 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0) 1406
Pad Mux Register 8.2.5.79/
3033_014C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1) 1408
Pad Mux Register 8.2.5.80/
3033_0150 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2) 1409
Pad Mux Register 8.2.5.81/
3033_0154 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3) 1410
Pad Mux Register 8.2.5.82/
3033_0158 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK) 1412
Pad Mux Register 8.2.5.83/
3033_015C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS) 1413
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1319
IOMUX Controller (IOMUXC)

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Mux Register 8.2.5.84/
3033_0160 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC) 1414
Pad Mux Register 8.2.5.85/
3033_0164 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0) 1415
Pad Mux Register 8.2.5.86/
3033_0168 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1) 1416
Pad Mux Register 8.2.5.87/
3033_016C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2) 1418
Pad Mux Register 8.2.5.88/
3033_0170 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3) 1419
Pad Mux Register 8.2.5.89/
3033_0174 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4) 1420
Pad Mux Register 8.2.5.90/
3033_0178 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5) 1422
Pad Mux Register 8.2.5.91/
3033_017C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6) 1423
Pad Mux Register 8.2.5.92/
3033_0180 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7) 1424
Pad Mux Register 8.2.5.93/
3033_0184 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS) 1426
Pad Mux Register 8.2.5.94/
3033_0188 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC) 1427
Pad Mux Register 8.2.5.95/
3033_018C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0) 1428
Pad Mux Register 8.2.5.96/
3033_0190 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1) 1429
Pad Mux Register 8.2.5.97/
3033_0194 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2) 1430
Pad Mux Register 8.2.5.98/
3033_0198 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3) 1431
Pad Mux Register 8.2.5.99/
3033_019C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4) 1432
Pad Mux Register 8.2.5.100/
3033_01A0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5) 1434
Pad Mux Register 8.2.5.101/
3033_01A4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6) 1435
Pad Mux Register 8.2.5.102/
3033_01A8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7) 1436
Pad Mux Register 8.2.5.103/
3033_01AC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK) 1437
Pad Mux Register 8.2.5.104/
3033_01B0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS) 1439
Pad Mux Register 8.2.5.105/
3033_01B4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC) 1440
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1320 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Mux Register 8.2.5.106/
3033_01B8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0) 1441
Pad Mux Register 8.2.5.107/
3033_01BC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS) 1442
Pad Mux Register 8.2.5.108/
3033_01C0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXC) 1443
Pad Mux Register 8.2.5.109/
3033_01C4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0) 1444
Pad Mux Register 8.2.5.110/
3033_01C8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK) 1445
Pad Mux Register 8.2.5.111/
3033_01CC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS) 1446
Pad Mux Register 8.2.5.112/
3033_01D0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC) 1448
Pad Mux Register 8.2.5.113/
3033_01D4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD) 1449
Pad Mux Register 8.2.5.114/
3033_01D8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS) 1450
Pad Mux Register 8.2.5.115/
3033_01DC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC) 1451
Pad Mux Register 8.2.5.116/
3033_01E0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXD) 1453
Pad Mux Register 8.2.5.117/
3033_01E4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK) 1454
Pad Mux Register 8.2.5.118/
3033_01E8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_TX) 1455
Pad Mux Register 8.2.5.119/
3033_01EC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_RX) 1456
Pad Mux Register 8.2.5.120/
3033_01F0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK) 1457
Pad Mux Register 8.2.5.121/
3033_01F4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK) 1458
Pad Mux Register 8.2.5.122/
3033_01F8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI) 1459
Pad Mux Register 8.2.5.123/
3033_01FC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO) 1460
Pad Mux Register 8.2.5.124/
3033_0200 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0) 1461
Pad Mux Register 8.2.5.125/
3033_0204 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK) 1462
Pad Mux Register 8.2.5.126/
3033_0208 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI) 1463
Pad Mux Register 8.2.5.127/
3033_020C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO) 1464
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1321
IOMUX Controller (IOMUXC)

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Mux Register 8.2.5.128/
3033_0210 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0) 1465
Pad Mux Register 8.2.5.129/
3033_0214 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL) 1466
Pad Mux Register 8.2.5.130/
3033_0218 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA) 1467
Pad Mux Register 8.2.5.131/
3033_021C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL) 1468
Pad Mux Register 8.2.5.132/
3033_0220 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA) 1469
Pad Mux Register 8.2.5.133/
3033_0224 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL) 1470
Pad Mux Register 8.2.5.134/
3033_0228 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA) 1471
Pad Mux Register 8.2.5.135/
3033_022C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL) 1472
Pad Mux Register 8.2.5.136/
3033_0230 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA) 1473
Pad Mux Register 8.2.5.137/
3033_0234 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART1_RXD) 1474
Pad Mux Register 8.2.5.138/
3033_0238 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART1_TXD) 1475
Pad Mux Register 8.2.5.139/
3033_023C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART2_RXD) 1476
Pad Mux Register 8.2.5.140/
3033_0240 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART2_TXD) 1477
Pad Mux Register 8.2.5.141/
3033_0244 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART3_RXD) 1478
Pad Mux Register 8.2.5.142/
3033_0248 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART3_TXD) 1479
Pad Mux Register 8.2.5.143/
3033_024C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART4_RXD) 1480
Pad Mux Register 8.2.5.144/
3033_0250 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_UART4_TXD) 1481
Pad Control Register 8.2.5.145/
3033_0254 32 R/W 0000_0101h
(IOMUXC_SW_PAD_CTL_PAD_TEST_MODE) 1482
Pad Control Register 8.2.5.146/
3033_0258 32 R/W 0000_0081h
(IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0) 1483
Pad Control Register 8.2.5.147/
3033_025C 32 R/W 0000_0181h
(IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1) 1484
Pad Control Register 8.2.5.148/
3033_0260 32 R/W 0000_1901h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD) 1485
Pad Control Register 8.2.5.149/
3033_0264 32 R/W 0000_0141h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B) 1486
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1322 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Control Register 8.2.5.150/
3033_0268 32 R/W 0000_0141h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI) 1486
Pad Control Register 8.2.5.151/
3033_026C 32 R/W 0000_0141h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS) 1487
Pad Control Register 8.2.5.152/
3033_0270 32 R/W 0000_0141h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK) 1488
Pad Control Register 8.2.5.153/
3033_0274 32 R/W 0000_0141h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO) 1489
8.2.5.154/
3033_0278 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RTC) 32 R/W 0000_0000h
1490
Pad Control Register 8.2.5.155/
3033_027C 32 R/W 0000_010Ch
(IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ) 1490
Pad Control Register 8.2.5.156/
3033_0280 32 R/W 0000_196Ch
(IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ) 1491
Pad Control Register 8.2.5.157/
3033_0284 32 R/W 0000_01CCh
(IOMUXC_SW_PAD_CTL_PAD_ONOFF) 1492
Pad Control Register 8.2.5.158/
3033_0288 32 R/W 0000_01CCh
(IOMUXC_SW_PAD_CTL_PAD_POR_B) 1493
Pad Control Register 8.2.5.159/
3033_028C 32 R/W 0000_01CCh
(IOMUXC_SW_PAD_CTL_PAD_RTC_RESET_B) 1494
Pad Control Register 8.2.5.160/
3033_0290 32 R/W 0000_0114h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00) 1495
Pad Control Register 8.2.5.161/
3033_0294 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01) 1496
Pad Control Register 8.2.5.162/
3033_0298 32 R/W 0000_0156h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02) 1497
Pad Control Register 8.2.5.163/
3033_029C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03) 1498
Pad Control Register 8.2.5.164/
3033_02A0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04) 1499
Pad Control Register 8.2.5.165/
3033_02A4 32 R/W 0000_0156h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05) 1500
Pad Control Register 8.2.5.166/
3033_02A8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06) 1502
Pad Control Register 8.2.5.167/
3033_02AC 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07) 1503
Pad Control Register 8.2.5.168/
3033_02B0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08) 1504
Pad Control Register 8.2.5.169/
3033_02B4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09) 1505
Pad Control Register 8.2.5.170/
3033_02B8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10) 1506
Pad Control Register 8.2.5.171/
3033_02BC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11) 1508
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1323
IOMUX Controller (IOMUXC)

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Control Register 8.2.5.172/
3033_02C0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12) 1509
Pad Control Register 8.2.5.173/
3033_02C4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13) 1510
Pad Control Register 8.2.5.174/
3033_02C8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14) 1511
Pad Control Register 8.2.5.175/
3033_02CC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15) 1512
Pad Control Register 8.2.5.176/
3033_02D0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_MDC) 1513
Pad Control Register 8.2.5.177/
3033_02D4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO) 1515
Pad Control Register 8.2.5.178/
3033_02D8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD3) 1516
Pad Control Register 8.2.5.179/
3033_02DC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD2) 1517
Pad Control Register 8.2.5.180/
3033_02E0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD1) 1518
Pad Control Register 8.2.5.181/
3033_02E4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD0) 1519
Pad Control Register 8.2.5.182/
3033_02E8 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL) 1520
Pad Control Register 8.2.5.183/
3033_02EC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TXC) 1522
Pad Control Register 8.2.5.184/
3033_02F0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL) 1523
Pad Control Register 8.2.5.185/
3033_02F4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RXC) 1524
Pad Control Register 8.2.5.186/
3033_02F8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD0) 1525
Pad Control Register 8.2.5.187/
3033_02FC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD1) 1526
Pad Control Register 8.2.5.188/
3033_0300 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD2) 1527
Pad Control Register 8.2.5.189/
3033_0304 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD3) 1529
Pad Control Register 8.2.5.190/
3033_0308 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_CLK) 1530
Pad Control Register 8.2.5.191/
3033_030C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_CMD) 1531
Pad Control Register 8.2.5.192/
3033_0310 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) 1532
Pad Control Register 8.2.5.193/
3033_0314 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1) 1533
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1324 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Control Register 8.2.5.194/
3033_0318 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2) 1534
Pad Control Register 8.2.5.195/
3033_031C 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3) 1536
Pad Control Register 8.2.5.196/
3033_0320 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA4) 1537
Pad Control Register 8.2.5.197/
3033_0324 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA5) 1538
Pad Control Register 8.2.5.198/
3033_0328 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA6) 1539
Pad Control Register 8.2.5.199/
3033_032C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA7) 1540
Pad Control Register 8.2.5.200/
3033_0330 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B) 1542
Pad Control Register 8.2.5.201/
3033_0334 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD1_STROBE) 1543
Pad Control Register 8.2.5.202/
3033_0338 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B) 1544
Pad Control Register 8.2.5.203/
3033_033C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_CLK) 1545
Pad Control Register 8.2.5.204/
3033_0340 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_CMD) 1546
Pad Control Register 8.2.5.205/
3033_0344 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0) 1547
Pad Control Register 8.2.5.206/
3033_0348 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1) 1549
Pad Control Register 8.2.5.207/
3033_034C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2) 1550
Pad Control Register 8.2.5.208/
3033_0350 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3) 1551
Pad Control Register 8.2.5.209/
3033_0354 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B) 1552
Pad Control Register 8.2.5.210/
3033_0358 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SD2_WP) 1553
Pad Control Register 8.2.5.211/
3033_035C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_ALE) 1554
Pad Control Register 8.2.5.212/
3033_0360 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B) 1556
Pad Control Register 8.2.5.213/
3033_0364 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B) 1557
Pad Control Register 8.2.5.214/
3033_0368 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B) 1558
Pad Control Register 8.2.5.215/
3033_036C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B) 1559
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1325
IOMUX Controller (IOMUXC)

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Control Register 8.2.5.216/
3033_0370 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE) 1560
Pad Control Register 8.2.5.217/
3033_0374 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00) 1561
Pad Control Register 8.2.5.218/
3033_0378 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01) 1563
Pad Control Register 8.2.5.219/
3033_037C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02) 1564
Pad Control Register 8.2.5.220/
3033_0380 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03) 1565
Pad Control Register 8.2.5.221/
3033_0384 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04) 1566
Pad Control Register 8.2.5.222/
3033_0388 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05) 1567
Pad Control Register 8.2.5.223/
3033_038C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06) 1569
Pad Control Register 8.2.5.224/
3033_0390 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07) 1570
Pad Control Register 8.2.5.225/
3033_0394 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_DQS) 1571
Pad Control Register 8.2.5.226/
3033_0398 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B) 1572
Pad Control Register 8.2.5.227/
3033_039C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B) 1573
Pad Control Register 8.2.5.228/
3033_03A0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B) 1574
Pad Control Register 8.2.5.229/
3033_03A4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B) 1576
Pad Control Register 8.2.5.230/
3033_03A8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS) 1577
Pad Control Register 8.2.5.231/
3033_03AC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_RXC) 1578
Pad Control Register 8.2.5.232/
3033_03B0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0) 1579
Pad Control Register 8.2.5.233/
3033_03B4 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1) 1580
Pad Control Register 8.2.5.234/
3033_03B8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2) 1582
Pad Control Register 8.2.5.235/
3033_03BC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3) 1583
Pad Control Register 8.2.5.236/
3033_03C0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK) 1584
Pad Control Register 8.2.5.237/
3033_03C4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS) 1585
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1326 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Control Register 8.2.5.238/
3033_03C8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXC) 1586
Pad Control Register 8.2.5.239/
3033_03CC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0) 1587
Pad Control Register 8.2.5.240/
3033_03D0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1) 1589
Pad Control Register 8.2.5.241/
3033_03D4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2) 1590
Pad Control Register 8.2.5.242/
3033_03D8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3) 1591
Pad Control Register 8.2.5.243/
3033_03DC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4) 1592
Pad Control Register 8.2.5.244/
3033_03E0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5) 1593
Pad Control Register 8.2.5.245/
3033_03E4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6) 1594
Pad Control Register 8.2.5.246/
3033_03E8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7) 1596
Pad Control Register 8.2.5.247/
3033_03EC 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS) 1597
Pad Control Register 8.2.5.248/
3033_03F0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXC) 1598
Pad Control Register 8.2.5.249/
3033_03F4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0) 1599
Pad Control Register 8.2.5.250/
3033_03F8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1) 1600
Pad Control Register 8.2.5.251/
3033_03FC 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2) 1602
Pad Control Register 8.2.5.252/
3033_0400 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3) 1603
Pad Control Register 8.2.5.253/
3033_0404 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4) 1604
Pad Control Register 8.2.5.254/
3033_0408 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5) 1605
Pad Control Register 8.2.5.255/
3033_040C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6) 1606
Pad Control Register 8.2.5.256/
3033_0410 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7) 1607
Pad Control Register 8.2.5.257/
3033_0414 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK) 1609
Pad Control Register 8.2.5.258/
3033_0418 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS) 1610
Pad Control Register 8.2.5.259/
3033_041C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_RXC) 1611
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1327
IOMUX Controller (IOMUXC)

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Control Register 8.2.5.260/
3033_0420 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0) 1612
Pad Control Register 8.2.5.261/
3033_0424 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS) 1613
Pad Control Register 8.2.5.262/
3033_0428 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_TXC) 1615
Pad Control Register 8.2.5.263/
3033_042C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0) 1616
Pad Control Register 8.2.5.264/
3033_0430 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK) 1617
Pad Control Register 8.2.5.265/
3033_0434 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS) 1618
Pad Control Register 8.2.5.266/
3033_0438 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_RXC) 1619
Pad Control Register 8.2.5.267/
3033_043C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_RXD) 1620
Pad Control Register 8.2.5.268/
3033_0440 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS) 1622
Pad Control Register 8.2.5.269/
3033_0444 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_TXC) 1623
Pad Control Register 8.2.5.270/
3033_0448 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_TXD) 1624
Pad Control Register 8.2.5.271/
3033_044C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK) 1625
Pad Control Register 8.2.5.272/
3033_0450 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SPDIF_TX) 1626
Pad Control Register 8.2.5.273/
3033_0454 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SPDIF_RX) 1628
Pad Control Register 8.2.5.274/
3033_0458 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK) 1629
Pad Control Register 8.2.5.275/
3033_045C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK) 1630
Pad Control Register 8.2.5.276/
3033_0460 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI) 1631
Pad Control Register 8.2.5.277/
3033_0464 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO) 1632
Pad Control Register 8.2.5.278/
3033_0468 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0) 1633
Pad Control Register 8.2.5.279/
3033_046C 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK) 1635
Pad Control Register 8.2.5.280/
3033_0470 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI) 1636
Pad Control Register 8.2.5.281/
3033_0474 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO) 1637
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1328 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Pad Control Register 8.2.5.282/
3033_0478 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0) 1638
Pad Control Register 8.2.5.283/
3033_047C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL) 1639
Pad Control Register 8.2.5.284/
3033_0480 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA) 1641
Pad Control Register 8.2.5.285/
3033_0484 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL) 1642
Pad Control Register 8.2.5.286/
3033_0488 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA) 1643
Pad Control Register 8.2.5.287/
3033_048C 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL) 1644
Pad Control Register 8.2.5.288/
3033_0490 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA) 1645
Pad Control Register 8.2.5.289/
3033_0494 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL) 1647
Pad Control Register 8.2.5.290/
3033_0498 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA) 1648
Pad Control Register 8.2.5.291/
3033_049C 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_UART1_RXD) 1649
Pad Control Register 8.2.5.292/
3033_04A0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_UART1_TXD) 1650
Pad Control Register 8.2.5.293/
3033_04A4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_UART2_RXD) 1651
Pad Control Register 8.2.5.294/
3033_04A8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_UART2_TXD) 1652
Pad Control Register 8.2.5.295/
3033_04AC 32 R/W 0000_1916h
(IOMUXC_SW_PAD_CTL_PAD_UART3_RXD) 1654
Pad Control Register 8.2.5.296/
3033_04B0 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_UART3_TXD) 1655
Pad Control Register 8.2.5.297/
3033_04B4 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_UART4_RXD) 1656
Pad Control Register 8.2.5.298/
3033_04B8 32 R/W 0000_0116h
(IOMUXC_SW_PAD_CTL_PAD_UART4_TXD) 1657
Select Input Register 8.2.5.299/
3033_04BC 32 R/W 0000_0000h
(IOMUXC_CCM_PMIC_READY_SELECT_INPUT) 1659
Select Input Register 8.2.5.300/
3033_04C0 32 R/W 0000_0000h
(IOMUXC_ENET1_MDIO_SELECT_INPUT) 1659
Select Input Register 8.2.5.301/
3033_04C4 32 R/W 0000_0000h
(IOMUXC_SAI1_RX_SYNC_SELECT_INPUT) 1660
Select Input Register 8.2.5.302/
3033_04C8 32 R/W 0000_0000h
(IOMUXC_SAI1_TX_BCLK_SELECT_INPUT) 1661
Select Input Register 8.2.5.303/
3033_04CC 32 R/W 0000_0000h
(IOMUXC_SAI1_TX_SYNC_SELECT_INPUT) 1661
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1329
IOMUX Controller (IOMUXC)

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Select Input Register 8.2.5.304/
3033_04D0 32 R/W 0000_0000h
(IOMUXC_SAI5_RX_BCLK_SELECT_INPUT) 1662
Select Input Register 8.2.5.305/
3033_04D4 32 R/W 0000_0000h
(IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0) 1663
Select Input Register 8.2.5.306/
3033_04D8 32 R/W 0000_0000h
(IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1) 1663
Select Input Register 8.2.5.307/
3033_04DC 32 R/W 0000_0000h
(IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2) 1664
Select Input Register 8.2.5.308/
3033_04E0 32 R/W 0000_0000h
(IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3) 1665
Select Input Register 8.2.5.309/
3033_04E4 32 R/W 0000_0000h
(IOMUXC_SAI5_RX_SYNC_SELECT_INPUT) 1665
Select Input Register 8.2.5.310/
3033_04E8 32 R/W 0000_0000h
(IOMUXC_SAI5_TX_BCLK_SELECT_INPUT) 1666
Select Input Register 8.2.5.311/
3033_04EC 32 R/W 0000_0000h
(IOMUXC_SAI5_TX_SYNC_SELECT_INPUT) 1667
Select Input Register 8.2.5.312/
3033_04F0 32 R/W 0000_0000h
(IOMUXC_UART1_RTS_B_SELECT_INPUT) 1667
Select Input Register 8.2.5.313/
3033_04F4 32 R/W 0000_0000h
(IOMUXC_UART1_RXD_SELECT_INPUT) 1668
Select Input Register 8.2.5.314/
3033_04F8 32 R/W 0000_0000h
(IOMUXC_UART2_RTS_B_SELECT_INPUT) 1669
Select Input Register 8.2.5.315/
3033_04FC 32 R/W 0000_0000h
(IOMUXC_UART2_RXD_SELECT_INPUT) 1669
Select Input Register 8.2.5.316/
3033_0500 32 R/W 0000_0000h
(IOMUXC_UART3_RTS_B_SELECT_INPUT) 1670
Select Input Register 8.2.5.317/
3033_0504 32 R/W 0000_0000h
(IOMUXC_UART3_RXD_SELECT_INPUT) 1671
Select Input Register 8.2.5.318/
3033_0508 32 R/W 0000_0000h
(IOMUXC_UART4_RTS_B_SELECT_INPUT) 1671
Select Input Register 8.2.5.319/
3033_050C 32 R/W 0000_0000h
(IOMUXC_UART4_RXD_SELECT_INPUT) 1672
Select Input Register 8.2.5.320/
3033_0510 32 R/W 0000_0000h
(IOMUXC_SAI6_RX_BCLK_SELECT_INPUT) 1673
Select Input Register 8.2.5.321/
3033_0514 32 R/W 0000_0000h
(IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0) 1674
Select Input Register 8.2.5.322/
3033_0518 32 R/W 0000_0000h
(IOMUXC_SAI6_RX_SYNC_SELECT_INPUT) 1675
Select Input Register 8.2.5.323/
3033_051C 32 R/W 0000_0000h
(IOMUXC_SAI6_TX_BCLK_SELECT_INPUT) 1676
Select Input Register 8.2.5.324/
3033_0520 32 R/W 0000_0000h
(IOMUXC_SAI6_TX_SYNC_SELECT_INPUT) 1677
Select Input Register 8.2.5.325/
3033_0524 32 R/W 0000_0000h
(IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT) 1678
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1330 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC memory map (continued)

Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Select Input Register 8.2.5.326/
3033_052C 32 R/W 0000_0000h
(IOMUXC_SAI5_MCLK_SELECT_INPUT) 1678
Select Input Register 8.2.5.327/
3033_0530 32 R/W 0000_0000h
(IOMUXC_SAI6_MCLK_SELECT_INPUT) 1679
Select Input Register 8.2.5.328/
3033_0534 32 R/W 0000_0000h
(IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0) 1680
Select Input Register 8.2.5.329/
3033_0538 32 R/W 0000_0000h
(IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1) 1681
Select Input Register 8.2.5.330/
3033_053C 32 R/W 0000_0000h
(IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2) 1682
Select Input Register 8.2.5.331/
3033_0540 32 R/W 0000_0000h
(IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3) 1683
Select Input Register 8.2.5.332/
3033_0544 32 R/W 0000_0000h
(IOMUXC_USDHC3_CD_B_SELECT_INPUT) 1683
Select Input Register 8.2.5.333/
3033_0548 32 R/W 0000_0000h
(IOMUXC_USDHC3_WP_SELECT_INPUT) 1684

8.2.5.1 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ)
Address: 3033_0000h base + 14h offset = 3033_0014h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved SION Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ field descriptions

Field Description
31–7 This field is reserved.
- Reserved
6 Not used for IO control, can be used by SW for general purpose
SION
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1331
IOMUX Controller (IOMUXC)

8.2.5.2 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ)
Address: 3033_0000h base + 18h offset = 3033_0018h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved SION Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ field descriptions

Field Description
31–7 This field is reserved.
- Reserved
6 Not used for IO control, can be used by SW for general purpose
SION
- This field is reserved.
Reserved

8.2.5.3 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ONOFF)

Address: 3033_0000h base + 1Ch offset = 3033_001Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved SION Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_ONOFF field descriptions

Field Description
31–7 This field is reserved.
- Reserved
6 Not used for IO control, can be used by SW for general purpose
SION
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1332 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.4 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_POR_B)

Address: 3033_0000h base + 20h offset = 3033_0020h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved SION Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_POR_B field descriptions

Field Description
31–7 This field is reserved.
- Reserved
6 Not used for IO control, can be used by SW for general purpose
SION
- This field is reserved.
Reserved

8.2.5.5 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B)
Address: 3033_0000h base + 24h offset = 3033_0024h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved SION Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B field descriptions

Field Description
31–7 This field is reserved.
- Reserved
6 Not used for IO control, can be used by SW for general purpose
SION
- This field is reserved.
Reserved

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1333
IOMUX Controller (IOMUXC)

8.2.5.6 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00)
Address: 3033_0000h base + 28h offset = 3033_0028h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO00

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO00.

000 ALT0 — Select signal GPIO1_IO00

001 ALT1 — Select signal CCM_ENET_PHY_REF_CLK_ROOT
101 ALT5 — Select signal CCM_REF_CLK_32K
110 ALT6 — Select signal CCM_EXT_CLK1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1334 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.7 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01)
Address: 3033_0000h base + 2Ch offset = 3033_002Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO01

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO01.

000 ALT0 — Select signal GPIO1_IO01

001 ALT1 — Select signal PWM1_OUT
101 ALT5 — Select signal CCM_REF_CLK_24M
110 ALT6 — Select signal CCM_EXT_CLK2

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1335
IOMUX Controller (IOMUXC)

8.2.5.8 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02)
Address: 3033_0000h base + 30h offset = 3033_0030h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO02

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO02.

000 ALT0 — Select signal GPIO1_IO02

001 ALT1 — Select signal WDOG1_WDOG_B
101 ALT5 — Select signal WDOG1_WDOG_ANY
111 ALT7 — Select signal SJC_DE_B

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1336 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.9 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03)
Address: 3033_0000h base + 34h offset = 3033_0034h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO03

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: GPIO1_IO03.

000 ALT0 — Select signal GPIO1_IO03

001 ALT1 — Select signal USDHC1_VSELECT
101 ALT5 — Select signal SDMA1_EXT_EVENT0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1337
IOMUX Controller (IOMUXC)

8.2.5.10 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04)
Address: 3033_0000h base + 38h offset = 3033_0038h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO04

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: GPIO1_IO04.

000 ALT0 — Select signal GPIO1_IO04

001 ALT1 — Select signal USDHC2_VSELECT
101 ALT5 — Select signal SDMA1_EXT_EVENT1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1338 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.11 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05)
Address: 3033_0000h base + 3Ch offset = 3033_003Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO05

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: GPIO1_IO05.

000 ALT0 — Select signal GPIO1_IO05

001 ALT1 — Select signal M4_NMI
101 ALT5 — Select signal CCM_PMIC_READY

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1339
IOMUX Controller (IOMUXC)

8.2.5.12 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06)
Address: 3033_0000h base + 40h offset = 3033_0040h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO06

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO06.

000 ALT0 — Select signal GPIO1_IO06

001 ALT1 — Select signal ENET1_MDC
101 ALT5 — Select signal USDHC1_CD_B
110 ALT6 — Select signal CCM_EXT_CLK3

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1340 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.13 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07)
Address: 3033_0000h base + 44h offset = 3033_0044h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO07

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO07.

NOTE: Pad GPIO1_IO07 is involved in Daisy Chain.

000 ALT0 — Select signal GPIO1_IO07

001 ALT1 — Select signal ENET1_MDIO
- Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1.
101 ALT5 — Select signal USDHC1_WP
110 ALT6 — Select signal CCM_EXT_CLK4

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1341
IOMUX Controller (IOMUXC)

8.2.5.14 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08)
Address: 3033_0000h base + 48h offset = 3033_0048h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO08

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: GPIO1_IO08.

000 ALT0 — Select signal GPIO1_IO08

001 ALT1 — Select signal ENET1_1588_EVENT0_IN
101 ALT5 — Select signal USDHC2_RESET_B

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1342 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.15 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09)
Address: 3033_0000h base + 4Ch offset = 3033_004Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO09

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO09.

000 ALT0 — Select signal GPIO1_IO09

001 ALT1 — Select signal ENET1_1588_EVENT0_OUT
100 ALT4 — Select signal USDHC3_RESET_B
101 ALT5 — Select signal SDMA2_EXT_EVENT0

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1343
IOMUX Controller (IOMUXC)

8.2.5.16 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10)
Address: 3033_0000h base + 50h offset = 3033_0050h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO10

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: GPIO1_IO10.

000 ALT0 — Select signal GPIO1_IO10

001 ALT1 — Select signal USB1_OTG_ID

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1344 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.17 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11)
Address: 3033_0000h base + 54h offset = 3033_0054h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO11

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO11.

000 ALT0 — Select signal GPIO1_IO11

001 ALT1 — Select signal USB2_OTG_ID
100 ALT4 — Select signal USDHC3_VSELECT
101 ALT5 — Select signal CCM_PMIC_READY

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1345
IOMUX Controller (IOMUXC)

8.2.5.18 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12)
Address: 3033_0000h base + 58h offset = 3033_0058h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO12

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: GPIO1_IO12.

000 ALT0 — Select signal GPIO1_IO12

001 ALT1 — Select signal USB1_OTG_PWR
101 ALT5 — Select signal SDMA2_EXT_EVENT1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1346 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.19 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13)
Address: 3033_0000h base + 5Ch offset = 3033_005Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO13

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: GPIO1_IO13.

000 ALT0 — Select signal GPIO1_IO13

001 ALT1 — Select signal USB1_OTG_OC
101 ALT5 — Select signal PWM2_OUT

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1347
IOMUX Controller (IOMUXC)

8.2.5.20 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14)
Address: 3033_0000h base + 60h offset = 3033_0060h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO14

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: GPIO1_IO14.

NOTE: Pad GPIO1_IO14 is involved in Daisy Chain.

000 ALT0 — Select signal GPIO1_IO14

001 ALT1 — Select signal USB2_OTG_PWR
100 ALT4 — Select signal USDHC3_CD_B
- Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1348 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 field descriptions (continued)

Field Description
101 ALT5 — Select signal PWM3_OUT
110 ALT6 — Select signal CCM_CLKO1

8.2.5.21 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15)
Address: 3033_0000h base + 64h offset = 3033_0064h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad GPIO1_IO15

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: GPIO1_IO15.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1349
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 field descriptions (continued)

Field Description
NOTE: Pad GPIO1_IO15 is involved in Daisy Chain.

000 ALT0 — Select signal GPIO1_IO15

001 ALT1 — Select signal USB2_OTG_OC
100 ALT4 — Select signal USDHC3_WP
- Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4.
101 ALT5 — Select signal PWM4_OUT
110 ALT6 — Select signal CCM_CLKO2

8.2.5.22 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_MDC)
Address: 3033_0000h base + 68h offset = 3033_0068h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ENET_MDC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1350 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_ENET_MDC field descriptions (continued)

Field Description
1 ENABLED — Force input path of pad ENET_MDC
0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_MDC.

000 ALT0 — Select signal ENET1_MDC

101 ALT5 — Select signal GPIO1_IO16

8.2.5.23 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO)
Address: 3033_0000h base + 6Ch offset = 3033_006Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1351
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO field descriptions (continued)

Field Description
1 ENABLED — Force input path of pad ENET_MDIO
0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_MDIO.

NOTE: Pad ENET_MDIO is involved in Daisy Chain.

000 ALT0 — Select signal ENET1_MDIO

- Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT0.
101 ALT5 — Select signal GPIO1_IO17

8.2.5.24 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_TD3)
Address: 3033_0000h base + 70h offset = 3033_0070h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ENET_TD3 field descriptions

Field Description
31–5 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1352 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_ENET_TD3 field descriptions (continued)

Field Description
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_TD3

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_TD3.

000 ALT0 — Select signal ENET1_RGMII_TD3

101 ALT5 — Select signal GPIO1_IO18

8.2.5.25 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_TD2)
Address: 3033_0000h base + 74h offset = 3033_0074h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ENET_TD2 field descriptions

Field Description
31–5 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1353
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_ENET_TD2 field descriptions (continued)

Field Description
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_TD2

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ENET_TD2.

000 ALT0 — Select signal ENET1_RGMII_TD2

001 ALT1 — Select signal INPUT=ENET1_TX_CLK, OUTPUT=CCM_ENET_REF_CLK_ROOT
101 ALT5 — Select signal GPIO1_IO19

8.2.5.26 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_TD1)
Address: 3033_0000h base + 78h offset = 3033_0078h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1354 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_ENET_TD1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_TD1

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_TD1.

000 ALT0 — Select signal ENET1_RGMII_TD1

101 ALT5 — Select signal GPIO1_IO20

8.2.5.27 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_TD0)
Address: 3033_0000h base + 7Ch offset = 3033_007Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1355
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_ENET_TD0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_TD0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_TD0.

000 ALT0 — Select signal ENET1_RGMII_TD0

101 ALT5 — Select signal GPIO1_IO21

8.2.5.28 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL)
Address: 3033_0000h base + 80h offset = 3033_0080h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1356 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_TX_CTL

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_TX_CTL.

000 ALT0 — Select signal ENET1_RGMII_TX_CTL

101 ALT5 — Select signal GPIO1_IO22

8.2.5.29 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_TXC)
Address: 3033_0000h base + 84h offset = 3033_0084h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1357
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_ENET_TXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_TXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ENET_TXC.

000 ALT0 — Select signal ENET1_RGMII_TXC

001 ALT1 — Select signal ENET1_TX_ER
101 ALT5 — Select signal GPIO1_IO23

8.2.5.30 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL)
Address: 3033_0000h base + 88h offset = 3033_0088h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1358 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_RX_CTL

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_RX_CTL.

000 ALT0 — Select signal ENET1_RGMII_RX_CTL

101 ALT5 — Select signal GPIO1_IO24

8.2.5.31 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_RXC)
Address: 3033_0000h base + 8Ch offset = 3033_008Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1359
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_ENET_RXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_RXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ENET_RXC.

000 ALT0 — Select signal ENET1_RGMII_RXC

001 ALT1 — Select signal ENET1_RX_ER
101 ALT5 — Select signal GPIO1_IO25

8.2.5.32 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_RD0)
Address: 3033_0000h base + 90h offset = 3033_0090h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1360 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_ENET_RD0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_RD0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_RD0.

000 ALT0 — Select signal ENET1_RGMII_RD0

101 ALT5 — Select signal GPIO1_IO26

8.2.5.33 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_RD1)
Address: 3033_0000h base + 94h offset = 3033_0094h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1361
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_ENET_RD1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_RD1

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_RD1.

000 ALT0 — Select signal ENET1_RGMII_RD1

101 ALT5 — Select signal GPIO1_IO27

8.2.5.34 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_RD2)
Address: 3033_0000h base + 98h offset = 3033_0098h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1362 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_ENET_RD2 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_RD2

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_RD2.

000 ALT0 — Select signal ENET1_RGMII_RD2

101 ALT5 — Select signal GPIO1_IO28

8.2.5.35 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ENET_RD3)
Address: 3033_0000h base + 9Ch offset = 3033_009Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1363
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_ENET_RD3 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ENET_RD3

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: ENET_RD3.

000 ALT0 — Select signal ENET1_RGMII_RD3

101 ALT5 — Select signal GPIO1_IO29

8.2.5.36 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CLK)

Address: 3033_0000h base + A0h offset = 3033_00A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1364 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD1_CLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_CLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_CLK.

000 ALT0 — Select signal USDHC1_CLK

101 ALT5 — Select signal GPIO2_IO00

8.2.5.37 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD)

Address: 3033_0000h base + A4h offset = 3033_00A4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1365
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD1_CMD field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_CMD

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_CMD.

000 ALT0 — Select signal USDHC1_CMD

101 ALT5 — Select signal GPIO2_IO01

8.2.5.38 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0)
Address: 3033_0000h base + A8h offset = 3033_00A8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1366 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA0.

000 ALT0 — Select signal USDHC1_DATA0

101 ALT5 — Select signal GPIO2_IO02

8.2.5.39 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1)
Address: 3033_0000h base + ACh offset = 3033_00ACh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1367
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA1

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA1.

000 ALT0 — Select signal USDHC1_DATA1

101 ALT5 — Select signal GPIO2_IO03

8.2.5.40 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2)
Address: 3033_0000h base + B0h offset = 3033_00B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1368 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA2

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA2.

000 ALT0 — Select signal USDHC1_DATA2

101 ALT5 — Select signal GPIO2_IO04

8.2.5.41 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3)
Address: 3033_0000h base + B4h offset = 3033_00B4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1369
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA3

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA3.

000 ALT0 — Select signal USDHC1_DATA3

101 ALT5 — Select signal GPIO2_IO05

8.2.5.42 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4)
Address: 3033_0000h base + B8h offset = 3033_00B8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1370 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA4

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA4.

000 ALT0 — Select signal USDHC1_DATA4

101 ALT5 — Select signal GPIO2_IO06

8.2.5.43 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5)
Address: 3033_0000h base + BCh offset = 3033_00BCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1371
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA5

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA5.

000 ALT0 — Select signal USDHC1_DATA5

101 ALT5 — Select signal GPIO2_IO07

8.2.5.44 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6)
Address: 3033_0000h base + C0h offset = 3033_00C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1372 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA6

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA6.

000 ALT0 — Select signal USDHC1_DATA6

101 ALT5 — Select signal GPIO2_IO08

8.2.5.45 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7)
Address: 3033_0000h base + C4h offset = 3033_00C4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1373
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_DATA7

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_DATA7.

000 ALT0 — Select signal USDHC1_DATA7

101 ALT5 — Select signal GPIO2_IO09

8.2.5.46 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B)
Address: 3033_0000h base + C8h offset = 3033_00C8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1374 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_RESET_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_RESET_B.

000 ALT0 — Select signal USDHC1_RESET_B

101 ALT5 — Select signal GPIO2_IO10

8.2.5.47 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD1_STROBE)
Address: 3033_0000h base + CCh offset = 3033_00CCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1375
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD1_STROBE field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD1_STROBE

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD1_STROBE.

000 ALT0 — Select signal USDHC1_STROBE

101 ALT5 — Select signal GPIO2_IO11

8.2.5.48 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B)
Address: 3033_0000h base + D0h offset = 3033_00D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1376 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_CD_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_CD_B.

000 ALT0 — Select signal USDHC2_CD_B

101 ALT5 — Select signal GPIO2_IO12

8.2.5.49 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CLK)

Address: 3033_0000h base + D4h offset = 3033_00D4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1377
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD2_CLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_CLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_CLK.

000 ALT0 — Select signal USDHC2_CLK

101 ALT5 — Select signal GPIO2_IO13

8.2.5.50 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CMD)

Address: 3033_0000h base + D8h offset = 3033_00D8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1378 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD2_CMD field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_CMD

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_CMD.

000 ALT0 — Select signal USDHC2_CMD

101 ALT5 — Select signal GPIO2_IO14

8.2.5.51 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0)
Address: 3033_0000h base + DCh offset = 3033_00DCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1379
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_DATA0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_DATA0.

000 ALT0 — Select signal USDHC2_DATA0

101 ALT5 — Select signal GPIO2_IO15

8.2.5.52 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1)
Address: 3033_0000h base + E0h offset = 3033_00E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1380 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_DATA1

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_DATA1.

000 ALT0 — Select signal USDHC2_DATA1

101 ALT5 — Select signal GPIO2_IO16

8.2.5.53 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2)
Address: 3033_0000h base + E4h offset = 3033_00E4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1381
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_DATA2

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_DATA2.

000 ALT0 — Select signal USDHC2_DATA2

101 ALT5 — Select signal GPIO2_IO17

8.2.5.54 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3)
Address: 3033_0000h base + E8h offset = 3033_00E8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1382 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_DATA3

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_DATA3.

000 ALT0 — Select signal USDHC2_DATA3

101 ALT5 — Select signal GPIO2_IO18

8.2.5.55 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B)
Address: 3033_0000h base + ECh offset = 3033_00ECh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1383
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_RESET_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_RESET_B.

000 ALT0 — Select signal USDHC2_RESET_B

101 ALT5 — Select signal GPIO2_IO19

8.2.5.56 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_WP)

Address: 3033_0000h base + F0h offset = 3033_00F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1384 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SD2_WP field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SD2_WP

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_WP.

000 ALT0 — Select signal USDHC2_WP

101 ALT5 — Select signal GPIO2_IO20

8.2.5.57 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE)
Address: 3033_0000h base + F4h offset = 3033_00F4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1385
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_ALE field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_ALE

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_ALE.

000 ALT0 — Select signal RAWNAND_ALE

001 ALT1 — Select signal QSPI_A_SCLK
101 ALT5 — Select signal GPIO3_IO00

8.2.5.58 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B)
Address: 3033_0000h base + F8h offset = 3033_00F8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1386 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_CE0_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_CE0_B.

000 ALT0 — Select signal RAWNAND_CE0_B

001 ALT1 — Select signal QSPI_A_SS0_B
101 ALT5 — Select signal GPIO3_IO01

8.2.5.59 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B)
Address: 3033_0000h base + FCh offset = 3033_00FCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1387
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_CE1_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_CE1_B.

000 ALT0 — Select signal RAWNAND_CE1_B

001 ALT1 — Select signal QSPI_A_SS1_B
010 ALT2 — Select signal USDHC3_STROBE
101 ALT5 — Select signal GPIO3_IO02

8.2.5.60 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B)
Address: 3033_0000h base + 100h offset = 3033_0100h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1388 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_CE2_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_CE2_B.

000 ALT0 — Select signal RAWNAND_CE2_B

001 ALT1 — Select signal QSPI_B_SS0_B
010 ALT2 — Select signal USDHC3_DATA5
101 ALT5 — Select signal GPIO3_IO03

8.2.5.61 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B)
Address: 3033_0000h base + 104h offset = 3033_0104h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1389
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_CE3_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_CE3_B.

000 ALT0 — Select signal RAWNAND_CE3_B

001 ALT1 — Select signal QSPI_B_SS1_B
010 ALT2 — Select signal USDHC3_DATA6
101 ALT5 — Select signal GPIO3_IO04

8.2.5.62 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE)
Address: 3033_0000h base + 108h offset = 3033_0108h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1390 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_CLE field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_CLE

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_CLE.

000 ALT0 — Select signal RAWNAND_CLE

001 ALT1 — Select signal QSPI_B_SCLK
010 ALT2 — Select signal USDHC3_DATA7
101 ALT5 — Select signal GPIO3_IO05

8.2.5.63 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00)
Address: 3033_0000h base + 10Ch offset = 3033_010Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1391
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA00

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_DATA00.

000 ALT0 — Select signal RAWNAND_DATA00

001 ALT1 — Select signal QSPI_A_DATA0
101 ALT5 — Select signal GPIO3_IO06

8.2.5.64 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01)
Address: 3033_0000h base + 110h offset = 3033_0110h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1392 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA01

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_DATA01.

000 ALT0 — Select signal RAWNAND_DATA01

001 ALT1 — Select signal QSPI_A_DATA1
101 ALT5 — Select signal GPIO3_IO07

8.2.5.65 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02)
Address: 3033_0000h base + 114h offset = 3033_0114h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1393
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA02

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_DATA02.

NOTE: Pad NAND_DATA02 is involved in Daisy Chain.

000 ALT0 — Select signal RAWNAND_DATA02

001 ALT1 — Select signal QSPI_A_DATA2
010 ALT2 — Select signal USDHC3_CD_B
- Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2.
101 ALT5 — Select signal GPIO3_IO08

8.2.5.66 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03)
Address: 3033_0000h base + 118h offset = 3033_0118h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1394 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA03

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_DATA03.

NOTE: Pad NAND_DATA03 is involved in Daisy Chain.

000 ALT0 — Select signal RAWNAND_DATA03

001 ALT1 — Select signal QSPI_A_DATA3
010 ALT2 — Select signal USDHC3_WP
- Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2.
101 ALT5 — Select signal GPIO3_IO09

8.2.5.67 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04)
Address: 3033_0000h base + 11Ch offset = 3033_011Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1395
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA04

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_DATA04.

000 ALT0 — Select signal RAWNAND_DATA04

001 ALT1 — Select signal QSPI_B_DATA0
010 ALT2 — Select signal USDHC3_DATA0
101 ALT5 — Select signal GPIO3_IO10

8.2.5.68 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05)
Address: 3033_0000h base + 120h offset = 3033_0120h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1396 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA05

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_DATA05.

000 ALT0 — Select signal RAWNAND_DATA05

001 ALT1 — Select signal QSPI_B_DATA1
010 ALT2 — Select signal USDHC3_DATA1
101 ALT5 — Select signal GPIO3_IO11

8.2.5.69 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06)
Address: 3033_0000h base + 124h offset = 3033_0124h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1397
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA06

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_DATA06.

000 ALT0 — Select signal RAWNAND_DATA06

001 ALT1 — Select signal QSPI_B_DATA2
010 ALT2 — Select signal USDHC3_DATA2
101 ALT5 — Select signal GPIO3_IO12

8.2.5.70 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07)
Address: 3033_0000h base + 128h offset = 3033_0128h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1398 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DATA07

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_DATA07.

000 ALT0 — Select signal RAWNAND_DATA07

001 ALT1 — Select signal QSPI_B_DATA3
010 ALT2 — Select signal USDHC3_DATA3
101 ALT5 — Select signal GPIO3_IO13

8.2.5.71 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_DQS)
Address: 3033_0000h base + 12Ch offset = 3033_012Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1399
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_DQS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_DQS

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_DQS.

000 ALT0 — Select signal RAWNAND_DQS

001 ALT1 — Select signal QSPI_A_DQS
101 ALT5 — Select signal GPIO3_IO14

8.2.5.72 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B)
Address: 3033_0000h base + 130h offset = 3033_0130h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1400 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_RE_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: NAND_RE_B.

000 ALT0 — Select signal RAWNAND_RE_B

001 ALT1 — Select signal QSPI_B_DQS
010 ALT2 — Select signal USDHC3_DATA4
101 ALT5 — Select signal GPIO3_IO15

8.2.5.73 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B)
Address: 3033_0000h base + 134h offset = 3033_0134h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1401
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_READY_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_READY_B.

000 ALT0 — Select signal RAWNAND_READY_B

010 ALT2 — Select signal USDHC3_RESET_B
101 ALT5 — Select signal GPIO3_IO16

8.2.5.74 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B)
Address: 3033_0000h base + 138h offset = 3033_0138h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1402 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_WE_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_WE_B.

000 ALT0 — Select signal RAWNAND_WE_B

010 ALT2 — Select signal USDHC3_CLK
101 ALT5 — Select signal GPIO3_IO17

8.2.5.75 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B)
Address: 3033_0000h base + 13Ch offset = 3033_013Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1403
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad NAND_WP_B

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: NAND_WP_B.

000 ALT0 — Select signal RAWNAND_WP_B

010 ALT2 — Select signal USDHC3_CMD
101 ALT5 — Select signal GPIO3_IO18

8.2.5.76 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS)
Address: 3033_0000h base + 140h offset = 3033_0140h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1404 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI5_RXFS

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI5_RXFS.

NOTE: Pad SAI5_RXFS is involved in Daisy Chain.

000 ALT0 — Select signal SAI5_RX_SYNC

- Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0.
001 ALT1 — Select signal SAI1_TX_DATA0
101 ALT5 — Select signal GPIO3_IO19

8.2.5.77 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC)

Address: 3033_0000h base + 144h offset = 3033_0144h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1405
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI5_RXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI5_RXC.

NOTE: Pad SAI5_RXC is involved in Daisy Chain.

000 ALT0 — Select signal SAI5_RX_BCLK

- Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0.
001 ALT1 — Select signal SAI1_TX_DATA1
100 ALT4 — Select signal PDM_CLK
101 ALT5 — Select signal GPIO3_IO20

8.2.5.78 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0)
Address: 3033_0000h base + 148h offset = 3033_0148h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1406 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI5_RXD0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI5_RXD0.

NOTE: Pad SAI5_RXD0 is involved in Daisy Chain.

000 ALT0 — Select signal SAI5_RX_DATA0

- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT0.
001 ALT1 — Select signal SAI1_TX_DATA2
100 ALT4 — Select signal PDM_BIT_STREAM0
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT4.
101 ALT5 — Select signal GPIO3_IO21

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1407
IOMUX Controller (IOMUXC)

8.2.5.79 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1)
Address: 3033_0000h base + 14Ch offset = 3033_014Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI5_RXD1

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI5_RXD1.

NOTE: Pad SAI5_RXD1 is involved in Daisy Chain.

000 ALT0 — Select signal SAI5_RX_DATA1

- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT0.
001 ALT1 — Select signal SAI1_TX_DATA3
010 ALT2 — Select signal SAI1_TX_SYNC
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1408 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 field descriptions (continued)

Field Description
- Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2.
011 ALT3 — Select signal SAI5_TX_SYNC
- Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT3.
100 ALT4 — Select signal PDM_BIT_STREAM1
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT4.
101 ALT5 — Select signal GPIO3_IO22

8.2.5.80 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2)
Address: 3033_0000h base + 150h offset = 3033_0150h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI5_RXD2

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1409
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 field descriptions (continued)

Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI5_RXD2.

NOTE: Pad SAI5_RXD2 is involved in Daisy Chain.

000 ALT0 — Select signal SAI5_RX_DATA2

- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0.
001 ALT1 — Select signal SAI1_TX_DATA4
010 ALT2 — Select signal SAI1_TX_SYNC
- Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2.
011 ALT3 — Select signal SAI5_TX_BCLK
- Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3.
100 ALT4 — Select signal PDM_BIT_STREAM2
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4.
101 ALT5 — Select signal GPIO3_IO23

8.2.5.81 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3)
Address: 3033_0000h base + 154h offset = 3033_0154h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1410 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI5_RXD3

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI5_RXD3.

NOTE: Pad SAI5_RXD3 is involved in Daisy Chain.

000 ALT0 — Select signal SAI5_RX_DATA3

- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0.
001 ALT1 — Select signal SAI1_TX_DATA5
010 ALT2 — Select signal SAI1_TX_SYNC
- Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2.
011 ALT3 — Select signal SAI5_TX_DATA0
100 ALT4 — Select signal PDM_BIT_STREAM3
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4.
101 ALT5 — Select signal GPIO3_IO24

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1411
IOMUX Controller (IOMUXC)

8.2.5.82 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK)
Address: 3033_0000h base + 158h offset = 3033_0158h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI5_MCLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI5_MCLK.

NOTE: Pad SAI5_MCLK is involved in Daisy Chain.

000 ALT0 — Select signal SAI5_MCLK

- Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0.
001 ALT1 — Select signal SAI1_TX_BCLK
- Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1.
101 ALT5 — Select signal GPIO3_IO25

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1412 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.83 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS)
Address: 3033_0000h base + 15Ch offset = 3033_015Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXFS

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_RXFS.

NOTE: Pad SAI1_RXFS is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_SYNC

- Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0.
001 ALT1 — Select signal SAI5_RX_SYNC
- Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1413
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS field descriptions (continued)

Field Description
100 ALT4 — Select signal CORESIGHT_TRACE_CLK
101 ALT5 — Select signal GPIO4_IO00

8.2.5.84 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC)

Address: 3033_0000h base + 160h offset = 3033_0160h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_RXC.

NOTE: Pad SAI1_RXC is involved in Daisy Chain.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1414 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC field descriptions (continued)

Field Description
000 ALT0 — Select signal SAI1_RX_BCLK
001 ALT1 — Select signal SAI5_RX_BCLK
- Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1.
100 ALT4 — Select signal CORESIGHT_TRACE_CTL
101 ALT5 — Select signal GPIO4_IO01

8.2.5.85 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0)
Address: 3033_0000h base + 164h offset = 3033_0164h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1415
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 field descriptions (continued)

Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI1_RXD0.

NOTE: Pad SAI1_RXD0 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA0

001 ALT1 — Select signal SAI5_RX_DATA0
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1.
010 ALT2 — Select signal SAI1_TX_DATA1
011 ALT3 — Select signal PDM_BIT_STREAM0
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3.
100 ALT4 — Select signal CORESIGHT_TRACE0
101 ALT5 — Select signal GPIO4_IO02
110 ALT6 — Select signal SRC_BOOT_CFG0

8.2.5.86 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1)
Address: 3033_0000h base + 168h offset = 3033_0168h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1416 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD1

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_RXD1.

NOTE: Pad SAI1_RXD1 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA1

001 ALT1 — Select signal SAI5_RX_DATA1
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1.
011 ALT3 — Select signal PDM_BIT_STREAM1
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3.
100 ALT4 — Select signal CORESIGHT_TRACE1
101 ALT5 — Select signal GPIO4_IO03
110 ALT6 — Select signal SRC_BOOT_CFG1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1417
IOMUX Controller (IOMUXC)

8.2.5.87 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2)
Address: 3033_0000h base + 16Ch offset = 3033_016Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD2

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_RXD2.

NOTE: Pad SAI1_RXD2 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA2

001 ALT1 — Select signal SAI5_RX_DATA2
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1.
011 ALT3 — Select signal PDM_BIT_STREAM2
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1418 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 field descriptions (continued)

Field Description
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3.
100 ALT4 — Select signal CORESIGHT_TRACE2
101 ALT5 — Select signal GPIO4_IO04
110 ALT6 — Select signal SRC_BOOT_CFG2

8.2.5.88 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3)
Address: 3033_0000h base + 170h offset = 3033_0170h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD3

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1419
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 field descriptions (continued)

Field Description
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_RXD3.

NOTE: Pad SAI1_RXD3 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA3

001 ALT1 — Select signal SAI5_RX_DATA3
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1.
011 ALT3 — Select signal PDM_BIT_STREAM3
- Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3.
100 ALT4 — Select signal CORESIGHT_TRACE3
101 ALT5 — Select signal GPIO4_IO05
110 ALT6 — Select signal SRC_BOOT_CFG3

8.2.5.89 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4)
Address: 3033_0000h base + 174h offset = 3033_0174h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1420 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD4

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_RXD4.

NOTE: Pad SAI1_RXD4 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA4

001 ALT1 — Select signal SAI6_TX_BCLK
- Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1.
010 ALT2 — Select signal SAI6_RX_BCLK
- Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2.
100 ALT4 — Select signal CORESIGHT_TRACE4
101 ALT5 — Select signal GPIO4_IO06
110 ALT6 — Select signal SRC_BOOT_CFG4

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1421
IOMUX Controller (IOMUXC)

8.2.5.90 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5)
Address: 3033_0000h base + 178h offset = 3033_0178h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD5

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI1_RXD5.

NOTE: Pad SAI1_RXD5 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA5

001 ALT1 — Select signal SAI6_TX_DATA0
010 ALT2 — Select signal SAI6_RX_DATA0
- Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1422 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 field descriptions (continued)

Field Description
011 ALT3 — Select signal SAI1_RX_SYNC
- Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3.
100 ALT4 — Select signal CORESIGHT_TRACE5
101 ALT5 — Select signal GPIO4_IO07
110 ALT6 — Select signal SRC_BOOT_CFG5

8.2.5.91 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6)
Address: 3033_0000h base + 17Ch offset = 3033_017Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD6

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1423
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 field descriptions (continued)

Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_RXD6.

NOTE: Pad SAI1_RXD6 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA6

001 ALT1 — Select signal SAI6_TX_SYNC
- Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1.
010 ALT2 — Select signal SAI6_RX_SYNC
- Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2.
100 ALT4 — Select signal CORESIGHT_TRACE6
101 ALT5 — Select signal GPIO4_IO08
110 ALT6 — Select signal SRC_BOOT_CFG6

8.2.5.92 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7)
Address: 3033_0000h base + 180h offset = 3033_0180h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1424 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_RXD7

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI1_RXD7.

NOTE: Pad SAI1_RXD7 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_RX_DATA7

001 ALT1 — Select signal SAI6_MCLK
- Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1.
010 ALT2 — Select signal SAI1_TX_SYNC
- Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2.
011 ALT3 — Select signal SAI1_TX_DATA4
100 ALT4 — Select signal CORESIGHT_TRACE7
101 ALT5 — Select signal GPIO4_IO09
110 ALT6 — Select signal SRC_BOOT_CFG7

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1425
IOMUX Controller (IOMUXC)

8.2.5.93 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS)
Address: 3033_0000h base + 184h offset = 3033_0184h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXFS

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_TXFS.

NOTE: Pad SAI1_TXFS is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_TX_SYNC

- Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0.
001 ALT1 — Select signal SAI5_TX_SYNC
- Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1426 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS field descriptions (continued)

Field Description
100 ALT4 — Select signal CORESIGHT_EVENTO
101 ALT5 — Select signal GPIO4_IO10

8.2.5.94 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC)

Address: 3033_0000h base + 188h offset = 3033_0188h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_TXC.

NOTE: Pad SAI1_TXC is involved in Daisy Chain.

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1427
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC field descriptions (continued)

Field Description
000 ALT0 — Select signal SAI1_TX_BCLK
- Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0.
001 ALT1 — Select signal SAI5_TX_BCLK
- Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1.
100 ALT4 — Select signal CORESIGHT_EVENTI
101 ALT5 — Select signal GPIO4_IO11

8.2.5.95 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0)
Address: 3033_0000h base + 18Ch offset = 3033_018Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1428 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 field descriptions (continued)

Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD0.

000 ALT0 — Select signal SAI1_TX_DATA0

001 ALT1 — Select signal SAI5_TX_DATA0
100 ALT4 — Select signal CORESIGHT_TRACE8
101 ALT5 — Select signal GPIO4_IO12
110 ALT6 — Select signal SRC_BOOT_CFG8

8.2.5.96 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1)
Address: 3033_0000h base + 190h offset = 3033_0190h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1429
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 field descriptions (continued)

Field Description
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD1

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD1.

000 ALT0 — Select signal SAI1_TX_DATA1

001 ALT1 — Select signal SAI5_TX_DATA1
100 ALT4 — Select signal CORESIGHT_TRACE9
101 ALT5 — Select signal GPIO4_IO13
110 ALT6 — Select signal SRC_BOOT_CFG9

8.2.5.97 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2)
Address: 3033_0000h base + 194h offset = 3033_0194h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1430 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD2

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD2.

000 ALT0 — Select signal SAI1_TX_DATA2

001 ALT1 — Select signal SAI5_TX_DATA2
100 ALT4 — Select signal CORESIGHT_TRACE10
101 ALT5 — Select signal GPIO4_IO14
110 ALT6 — Select signal SRC_BOOT_CFG10

8.2.5.98 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3)
Address: 3033_0000h base + 198h offset = 3033_0198h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1431
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD3

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD3.

000 ALT0 — Select signal SAI1_TX_DATA3

001 ALT1 — Select signal SAI5_TX_DATA3
100 ALT4 — Select signal CORESIGHT_TRACE11
101 ALT5 — Select signal GPIO4_IO15
110 ALT6 — Select signal SRC_BOOT_CFG11

8.2.5.99 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4)
Address: 3033_0000h base + 19Ch offset = 3033_019Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1432 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD4

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_TXD4.

NOTE: Pad SAI1_TXD4 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_TX_DATA4

001 ALT1 — Select signal SAI6_RX_BCLK
- Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1.
010 ALT2 — Select signal SAI6_TX_BCLK
- Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2.
100 ALT4 — Select signal CORESIGHT_TRACE12
101 ALT5 — Select signal GPIO4_IO16
110 ALT6 — Select signal SRC_BOOT_CFG12

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1433
IOMUX Controller (IOMUXC)

8.2.5.100 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5)
Address: 3033_0000h base + 1A0h offset = 3033_01A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD5

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_TXD5.

NOTE: Pad SAI1_TXD5 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_TX_DATA5

001 ALT1 — Select signal SAI6_RX_DATA0
- Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1.
010 ALT2 — Select signal SAI6_TX_DATA0
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1434 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 field descriptions (continued)

Field Description
100 ALT4 — Select signal CORESIGHT_TRACE13
101 ALT5 — Select signal GPIO4_IO17
110 ALT6 — Select signal SRC_BOOT_CFG13

8.2.5.101 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6)
Address: 3033_0000h base + 1A4h offset = 3033_01A4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD6

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1435
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 field descriptions (continued)

Field Description
Select 1 of 6 iomux modes to be used for pad: SAI1_TXD6.

NOTE: Pad SAI1_TXD6 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_TX_DATA6

001 ALT1 — Select signal SAI6_RX_SYNC
- Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1.
010 ALT2 — Select signal SAI6_TX_SYNC
- Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2.
100 ALT4 — Select signal CORESIGHT_TRACE14
101 ALT5 — Select signal GPIO4_IO18
110 ALT6 — Select signal SRC_BOOT_CFG14

8.2.5.102 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7)
Address: 3033_0000h base + 1A8h offset = 3033_01A8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 field descriptions

Field Description
31–5 This field is reserved.
- Reserved

Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1436 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 field descriptions (continued)

Field Description
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_TXD7

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_TXD7.

NOTE: Pad SAI1_TXD7 is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_TX_DATA7

001 ALT1 — Select signal SAI6_MCLK
- Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1.
011 ALT3 — Select signal PDM_CLK
100 ALT4 — Select signal CORESIGHT_TRACE15
101 ALT5 — Select signal GPIO4_IO19
110 ALT6 — Select signal SRC_BOOT_CFG15

8.2.5.103 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK)
Address: 3033_0000h base + 1ACh offset = 3033_01ACh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1437
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI1_MCLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_MCLK.

NOTE: Pad SAI1_MCLK is involved in Daisy Chain.

000 ALT0 — Select signal SAI1_MCLK

001 ALT1 — Select signal SAI5_MCLK
- Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1.
010 ALT2 — Select signal SAI1_TX_BCLK
- Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2.
011 ALT3 — Select signal PDM_CLK
101 ALT5 — Select signal GPIO4_IO20

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1438 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.104 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS)
Address: 3033_0000h base + 1B0h offset = 3033_01B0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI2_RXFS

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI2_RXFS.

NOTE: Pad SAI2_RXFS is involved in Daisy Chain.

000 ALT0 — Select signal SAI2_RX_SYNC

001 ALT1 — Select signal SAI5_TX_SYNC
- Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1.
010 ALT2 — Select signal SAI5_TX_DATA1
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1439
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS field descriptions (continued)

Field Description
011 ALT3 — Select signal SAI2_RX_DATA1
100 ALT4 — Select signal UART1_TX
101 ALT5 — Select signal GPIO4_IO21

8.2.5.105 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC)
Address: 3033_0000h base + 1B4h offset = 3033_01B4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI2_RXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1440 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC field descriptions (continued)

Field Description
Select 1 of 4 iomux modes to be used for pad: SAI2_RXC.

NOTE: Pad SAI2_RXC is involved in Daisy Chain.

000 ALT0 — Select signal SAI2_RX_BCLK

001 ALT1 — Select signal SAI5_TX_BCLK
- Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1.
100 ALT4 — Select signal UART1_RX
101 ALT5 — Select signal GPIO4_IO22

8.2.5.106 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0)
Address: 3033_0000h base + 1B8h offset = 3033_01B8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1441
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 field descriptions (continued)

Field Description
1 ENABLED — Force input path of pad SAI2_RXD0
0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI2_RXD0.

NOTE: Pad SAI2_RXD0 is involved in Daisy Chain.

000 ALT0 — Select signal SAI2_RX_DATA0

001 ALT1 — Select signal SAI5_TX_DATA0
100 ALT4 — Select signal UART1_RTS_B
- Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4.
101 ALT5 — Select signal GPIO4_IO23

8.2.5.107 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS)
Address: 3033_0000h base + 1BCh offset = 3033_01BCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1442 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI2_TXFS

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI2_TXFS.

000 ALT0 — Select signal SAI2_TX_SYNC

001 ALT1 — Select signal SAI5_TX_DATA1
011 ALT3 — Select signal SAI2_TX_DATA1
100 ALT4 — Select signal UART1_CTS_B
101 ALT5 — Select signal GPIO4_IO24

8.2.5.108 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXC)
Address: 3033_0000h base + 1C0h offset = 3033_01C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1443
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI2_TXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI2_TXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI2_TXC.

000 ALT0 — Select signal SAI2_TX_BCLK

001 ALT1 — Select signal SAI5_TX_DATA2
101 ALT5 — Select signal GPIO4_IO25

8.2.5.109 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0)
Address: 3033_0000h base + 1C4h offset = 3033_01C4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1444 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI2_TXD0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI2_TXD0.

000 ALT0 — Select signal SAI2_TX_DATA0

001 ALT1 — Select signal SAI5_TX_DATA3
101 ALT5 — Select signal GPIO4_IO26

8.2.5.110 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK)
Address: 3033_0000h base + 1C8h offset = 3033_01C8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1445
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI2_MCLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI2_MCLK.

NOTE: Pad SAI2_MCLK is involved in Daisy Chain.

000 ALT0 — Select signal SAI2_MCLK

001 ALT1 — Select signal SAI5_MCLK
- Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1.
101 ALT5 — Select signal GPIO4_IO27

8.2.5.111 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS)
Address: 3033_0000h base + 1CCh offset = 3033_01CCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1446 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI3_RXFS

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI3_RXFS.

NOTE: Pad SAI3_RXFS is involved in Daisy Chain.

000 ALT0 — Select signal SAI3_RX_SYNC

001 ALT1 — Select signal GPT1_CAPTURE1
010 ALT2 — Select signal SAI5_RX_SYNC
- Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2.
011 ALT3 — Select signal SAI3_RX_DATA1
101 ALT5 — Select signal GPIO4_IO28

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1447
IOMUX Controller (IOMUXC)

8.2.5.112 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC)
Address: 3033_0000h base + 1D0h offset = 3033_01D0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI3_RXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI3_RXC.

NOTE: Pad SAI3_RXC is involved in Daisy Chain.

000 ALT0 — Select signal SAI3_RX_BCLK

001 ALT1 — Select signal GPT1_CLK
010 ALT2 — Select signal SAI5_RX_BCLK
- Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1448 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC field descriptions (continued)

Field Description
100 ALT4 — Select signal UART2_CTS_B
101 ALT5 — Select signal GPIO4_IO29

8.2.5.113 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD)
Address: 3033_0000h base + 1D4h offset = 3033_01D4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI3_RXD

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI3_RXD.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1449
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD field descriptions (continued)

Field Description
NOTE: Pad SAI3_RXD is involved in Daisy Chain.

000 ALT0 — Select signal SAI3_RX_DATA0

001 ALT1 — Select signal GPT1_COMPARE1
010 ALT2 — Select signal SAI5_RX_DATA0
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2.
100 ALT4 — Select signal UART2_RTS_B
- Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4.
101 ALT5 — Select signal GPIO4_IO30

8.2.5.114 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS)
Address: 3033_0000h base + 1D8h offset = 3033_01D8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.
Table continues on the next page...

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1450 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS field descriptions (continued)

Field Description
1 ENABLED — Force input path of pad SAI3_TXFS
0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI3_TXFS.

NOTE: Pad SAI3_TXFS is involved in Daisy Chain.

000 ALT0 — Select signal SAI3_TX_SYNC

001 ALT1 — Select signal GPT1_CAPTURE2
010 ALT2 — Select signal SAI5_RX_DATA1
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2.
011 ALT3 — Select signal SAI3_TX_DATA1
100 ALT4 — Select signal UART2_RX
101 ALT5 — Select signal GPIO4_IO31

8.2.5.115 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC)
Address: 3033_0000h base + 1DCh offset = 3033_01DCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R
Reserved

Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1451
IOMUX Controller (IOMUXC)

IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI3_TXC

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI3_TXC.

NOTE: Pad SAI3_TXC is involved in Daisy Chain.

000 ALT0 — Select signal SAI3_TX_BCLK

001 ALT1 — Select signal GPT1_COMPARE2
010 ALT2 — Select signal SAI5_RX_DATA2
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2.
100 ALT4 — Select signal UART2_TX
101 ALT5 — Select signal GPIO5_IO00

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1452 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.116 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXD)
Address: 3033_0000h base + 1E0h offset = 3033_01E0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI3_TXD field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI3_TXD

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI3_TXD.

NOTE: Pad SAI3_TXD is involved in Daisy Chain.

000 ALT0 — Select signal SAI3_TX_DATA0

001 ALT1 — Select signal GPT1_COMPARE3
010 ALT2 — Select signal SAI5_RX_DATA3
- Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2.
101 ALT5 — Select signal GPIO5_IO01

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1453
IOMUX Controller (IOMUXC)

8.2.5.117 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK)
Address: 3033_0000h base + 1E4h offset = 3033_01E4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SAI3_MCLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI3_MCLK.

NOTE: Pad SAI3_MCLK is involved in Daisy Chain.

000 ALT0 — Select signal SAI3_MCLK

001 ALT1 — Select signal PWM4_OUT
010 ALT2 — Select signal SAI5_MCLK
- Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT2.
101 ALT5 — Select signal GPIO5_IO02

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1454 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.118 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SPDIF_TX)
Address: 3033_0000h base + 1E8h offset = 3033_01E8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SPDIF_TX field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SPDIF_TX

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SPDIF_TX.

000 ALT0 — Select signal SPDIF1_OUT

001 ALT1 — Select signal PWM3_OUT
101 ALT5 — Select signal GPIO5_IO03

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1455
IOMUX Controller (IOMUXC)

8.2.5.119 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SPDIF_RX)
Address: 3033_0000h base + 1ECh offset = 3033_01ECh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SPDIF_RX field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SPDIF_RX

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SPDIF_RX.

000 ALT0 — Select signal SPDIF1_IN

001 ALT1 — Select signal PWM2_OUT
101 ALT5 — Select signal GPIO5_IO04

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1456 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.120 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK)
Address: 3033_0000h base + 1F0h offset = 3033_01F0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad SPDIF_EXT_CLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SPDIF_EXT_CLK.

000 ALT0 — Select signal SPDIF1_EXT_CLK

001 ALT1 — Select signal PWM1_OUT
101 ALT5 — Select signal GPIO5_IO05

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1457
IOMUX Controller (IOMUXC)

8.2.5.121 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK)
Address: 3033_0000h base + 1F4h offset = 3033_01F4h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI1_SCLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI1_SCLK.

000 ALT0 — Select signal ECSPI1_SCLK

001 ALT1 — Select signal UART3_RX
101 ALT5 — Select signal GPIO5_IO06

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1458 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.122 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI)
Address: 3033_0000h base + 1F8h offset = 3033_01F8h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI1_MOSI

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI1_MOSI.

000 ALT0 — Select signal ECSPI1_MOSI

001 ALT1 — Select signal UART3_TX
101 ALT5 — Select signal GPIO5_IO07

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1459
IOMUX Controller (IOMUXC)

8.2.5.123 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO)
Address: 3033_0000h base + 1FCh offset = 3033_01FCh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI1_MISO

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI1_MISO.

000 ALT0 — Select signal ECSPI1_MISO

001 ALT1 — Select signal UART3_CTS_B
101 ALT5 — Select signal GPIO5_IO08

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1460 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.124 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0)
Address: 3033_0000h base + 200h offset = 3033_0200h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI1_SS0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI1_SS0.

NOTE: Pad ECSPI1_SS0 is involved in Daisy Chain.

000 ALT0 — Select signal ECSPI1_SS0

001 ALT1 — Select signal UART3_RTS_B
- Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1.
101 ALT5 — Select signal GPIO5_IO09

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1461
IOMUX Controller (IOMUXC)

8.2.5.125 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK)
Address: 3033_0000h base + 204h offset = 3033_0204h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI2_SCLK

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI2_SCLK.

000 ALT0 — Select signal ECSPI2_SCLK

001 ALT1 — Select signal UART4_RX
101 ALT5 — Select signal GPIO5_IO10

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1462 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.126 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI)
Address: 3033_0000h base + 208h offset = 3033_0208h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI2_MOSI

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI2_MOSI.

000 ALT0 — Select signal ECSPI2_MOSI

001 ALT1 — Select signal UART4_TX
101 ALT5 — Select signal GPIO5_IO11

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1463
IOMUX Controller (IOMUXC)

8.2.5.127 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO)
Address: 3033_0000h base + 20Ch offset = 3033_020Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI2_MISO

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI2_MISO.

000 ALT0 — Select signal ECSPI2_MISO

001 ALT1 — Select signal UART4_CTS_B
101 ALT5 — Select signal GPIO5_IO12

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1464 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.128 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0)
Address: 3033_0000h base + 210h offset = 3033_0210h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad ECSPI2_SS0

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: ECSPI2_SS0.

NOTE: Pad ECSPI2_SS0 is involved in Daisy Chain.

000 ALT0 — Select signal ECSPI2_SS0

001 ALT1 — Select signal UART4_RTS_B
- Configure register IOMUXC_UART4_RTS_B_SELECT_INPUT for mode ALT1.
101 ALT5 — Select signal GPIO5_IO13

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1465
IOMUX Controller (IOMUXC)

8.2.5.129 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL)
Address: 3033_0000h base + 214h offset = 3033_0214h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad I2C1_SCL

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: I2C1_SCL.

000 ALT0 — Select signal I2C1_SCL

001 ALT1 — Select signal ENET1_MDC
101 ALT5 — Select signal GPIO5_IO14

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1466 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.130 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA)
Address: 3033_0000h base + 218h offset = 3033_0218h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad I2C1_SDA

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: I2C1_SDA.

NOTE: Pad I2C1_SDA is involved in Daisy Chain.

000 ALT0 — Select signal I2C1_SDA

001 ALT1 — Select signal ENET1_MDIO
- Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1.
101 ALT5 — Select signal GPIO5_IO15

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1467
IOMUX Controller (IOMUXC)

8.2.5.131 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL)
Address: 3033_0000h base + 21Ch offset = 3033_021Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad I2C2_SCL

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: I2C2_SCL.

NOTE: Pad I2C2_SCL is involved in Daisy Chain.

000 ALT0 — Select signal I2C2_SCL

001 ALT1 — Select signal ENET1_1588_EVENT1_IN
010 ALT2 — Select signal USDHC3_CD_B
- Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2.
101 ALT5 — Select signal GPIO5_IO16

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

1468 NXP Semiconductors
 Chapter 8 Chip IO and Pinmux

8.2.5.132 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA)
Address: 3033_0000h base + 220h offset = 3033_0220h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad I2C2_SDA

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: I2C2_SDA.

NOTE: Pad I2C2_SDA is involved in Daisy Chain.

000 ALT0 — Select signal I2C2_SDA

001 ALT1 — Select signal ENET1_1588_EVENT1_OUT
010 ALT2 — Select signal USDHC3_WP
- Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2.
101 ALT5 — Select signal GPIO5_IO17

i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020

NXP Semiconductors 1469
IOMUX Controller (IOMUXC)

8.2.5.133 Pad Mux Register

(IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL)
Address: 3033_0000h base + 224h offset = 3033_0224h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved SION MUX_MODE

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL field descriptions

Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode input path no matter of MUX_MODE functionality.

1 ENABLED — Force input path of pad I2C3_SCL

0 DISABLED — Input Path is determined by functionality of the selected mux mode (regular).
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field