Computer Organization

CCE131
Lecture 3

I/O Hierarchy

Dr. Emad Badry

Lecturer at faculty of Engineering, Suez Canal University
[email protected]
 l/O Bus and Interface Modules

❑ The I/O bus consists of data lines, address lines, and control lines.
❑ Each peripheral device has associated with it an interface unit. Each interface decodes the address and control received
from the I/O bus, interprets them for the peripheral, and provides signals for the peripheral controller.
❑ Each peripheral has its own controller. The I/O bus from the processor is attached to all peripheral interfaces.
❑ The interface selected responds to the function code and proceeds to execute it.
 Isolated versus Memory-Mapped I/O

❑ In the isolated I/O configuration, the CPU has distinct input and output instructions, and each of these instructions is
associated with the address of an interface register.
❑ When the CPU fetches and decodes the operation code of an input or output instruction, it places the address
associated with the instruction into the common address lines. At the same time, it enables the I/O read (for input) or
I/O write (for output) control line.
❑ In memory-mapped configuration, the computer treats an interface register as being part of the memory system. The
assigned addresses for interface registers cannot be used for memory words, which reduces the memory address range
available.
❑ In a memory-mapped I/O organization there are no specific input or output instructions.

❑ Computers with memory-mapped I/O can use memory-type instructions to access I/O data.
 Example of I/O Interface

❑ The interface communicates with the CPU through the data bus.
❑ The chip select and register select inputs determine the address assigned to the interface.
❑ The I/O read and write are two control lines that specify an input or output, respectively.
❑ The four registers communicate directly with the
I/O device attached to the interface. The I/O data
to and from the device can be transferred into
either port A or port B.
❑ The control register receives control information from the CPU. By loading appropriate bits into the control register.
❑ The bits in the status register are used for status conditions and for recording errors that may occur during the data transfer.
The interface registers communicate with the CPU through the bidirectional data bus.
❑ The address bus selects the interface unit through the chip select and the two register select inputs. This circuit enables the
chip select (CS) input when the interface is selected by the address bus.
 Programmed I/O

❑ The CPU continually monitors (polls) a control register associated with each I/O port. When a byte arrives in the port, a bit
in the control register is also set. The CPU eventually polls the port and notices that the “data ready” control bit is set.

❑ The CPU resets the control bit, retrieves the byte, and processes it according to instructions programmed for that particular
port.

❑ When the processing is complete, the CPU resumes

polling the control registers as before. The CPU is in a
continual “busy wait” loop until it starts servicing an I/O
request. It doesn’t do any useful work until there is I/O to
process.
❑ Another problem is in deciding how frequently to poll;
some devices might need to be polled more frequently
than others. Because of these limitations, programmed
I/O is best suited for special-purpose systems such as
automated teller machines and embedded systems that
control or monitor environmental events.
 Priority Interrupt

❑ The first task of the interrupt system is to identify the source of the interrupt.
❑ A priority interrupt is a system that establishes a priority over the various sources to determine which condition is to
be serviced first when two or more requests arrive simultaneously.
❑ Higher-priority interrupt levels are assigned to requests which, if delayed or interrupted, could have serious
consequences.
❑ A hardware priority-interrupt unit functions as an overall manager in an interrupt system environment. It accepts
interrupt requests from many sources, determines which of the incoming requests has the highest priority, and issues
an interrupt request to the computer based on this determination.

❑ To speed up the operation, each interrupt source has its own interrupt vector to access its own service routine directly.
The hardware priority function can be established by either a serial or a parallel connection of interrupt lines. The serial
connection is also known as the daisy-chaining method.
Daisy-Chaining Priority

❑ Consists of a serial connection of all devices that request an interrupt.

❑ The device with the highest priority is placed in the first position, followed by lower-priority devices up to the device
with the lowest priority, which is placed last in the chain.
❑ If any device has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the
interrupt input in the CPU.

❑ When no interrupts are pending, the interrupt line stays in the high-level state and no interrupts are recognized by the
CPU.
❑ The CPU responds to an interrupt request by enabling the interrupt acknowledge line.

❑ The acknowledge signal passes on to the next device through the PO (priority out) output only if device 1 is not requesting
an interrupt.

❑ If device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by placing a 0 in the PO
output. It then proceeds to insert its own interrupt vector address (VAD) into the data bus for the CPU to use during the
interrupt cycle.
❑ A device with a 0 in its PI input generates a 0 in its PO output to inform the next-lower-priority device that the
acknowledge signal has been blocked.
1 Interrupt 0
request
1 Interrupt 0
request

2 CPU responds
to interrupt
3 Device 1
generates
PO=1
1

1 Interrupt 0
request

2 CPU responds
to interrupt
 4 Device 2
generates
PO=0
3 Device 1
generates
PO=1
1 0

1 Interrupt 0
request

2 CPU responds
to interrupt
 5 Device 2 puts its VAD ino data
4 Device 2 bus
generates
PO=0
3 Device 1
generates
PO=1
1 0

1 Interrupt 0
request

2 CPU responds
to interrupt
 5 Device 2 puts its VAD into data
4 Device 2 bus 6 Device 3 generates
generates PO=0
PO=0
3 Device 1
generates
PO=1
1 0 0

1 Interrupt 0
request

2 CPU responds
to interrupt
One stage of the daisy-chain priority arrangement
Parallel Priority Interrupt
 Direct Memory Access (DMA)

❑ These devices are designed specifically to transfer large amounts of data between system devices in a fraction of the
time that the system processor would require.
❑ Computer systems typically use DMA controllers to transfer data between memory and hardware peripherals, such as
when loading a program or data file from a hard drive to memory or when transferring a message from system memory
to the transmit buffer of an Ethernet controller.

❑ DMA speeds up data transfers between RAM and certain peripheral devices. Basically, DMA bypasses the CPU for
certain types of data transfers, thus eliminating the time consumed by normal fetch and execute cycles required for each
CPU read or write operation.
 Channel I/O

❑ With channel I/O, one or more I/O processors control various I/O pathways called channel paths.

❑ Channel paths for “slow” devices such as terminals and printers can be combined (multiplexed), allowing management
of several of these devices through only one controller.
❑ I/O channels are driven by small CPUs called I/O processors (IOPs), which are optimized for I/O. Unlike DMA circuits,
IOPs have the ability to execute programs that include arithmetic-logic and branching instructions.