SpyGlass® audits

Rules Reference Guide

Version L-2016.06, June 2016
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Contents

Preface..........................................................................................7
About This Book ...................................................................................... 7
Contents of This Book ............................................................................. 8
Typographical Conventions ..................................................................... 9

Using the Rules in the SpyGlass audits Product...........................11

SpyGlass area Rule Parameters............................................................. 12
audit_cell_details................................................................................. 12
checklib ............................................................................................. 13
report_all_cells ................................................................................... 13
report_rtl_name .................................................................................. 14
Product Reports .................................................................................... 15
SpyGlass audits RTL Report................................................................... 15

Rules in SpyGlass audits .............................................................19

Rule Grouping in SpyGlass audits.......................................................... 19
Audit2 : Evaluates the number of ports, instances, one-dimensional array
and two-dimensional array in a module .............................. 20
Audit3 : Evaluates the number of instances, gates, and memory consumed
in synthesis of each module .............................................. 21
Audit4 : Evaluates the information regarding number of flip-flops, latches,
and tristates in a module .................................................. 22
Verilog and VHDL Rules......................................................................... 23
Audit2FileNameDump : Dumps the information regarding which module is
defined in which file ......................................................... 24
Audit2ID : Gathers stats for design. Do not select this rule directly ....... 25
Audit2Stats : Evaluates the number of input, output, and inout ports in a
module........................................................................... 26
Audit2Stats3 : Evaluates the sum total of each of one-dimensional and
multi-dimensional buses used in a design on the RTL level .... 27
Audit2Stats8 : Evaluates the number of times each black box is
instantiated .................................................................... 29
Audit3ID : Gathers stats for design. Do not select this rule directly ....... 30

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 Audit3run : Evaluates the number of instances, gates and memory
consumed in synthesis of each module. Also dumps the area of
each module in terms of NAND gate count in a file sizer.log ...31
Audit4Count : Evaluates the number of flip-flops, latches, and tristates in
a module. This is done on a flat-level netlist ........................32
Audit4Dump : Dumps the information regarding number of flip-flops,
latches, and tristates (evaluated in the Audit4count rule) on
stdout ............................................................................33
Audit4ID : Gathers stats for design. Do not select this rule directly .......34
AuditReportCell : Dumps the information regarding library cells...........35
Verilog Rules ......................................................................................... 37
Audit2Stats4 : Dumps the parameters, macros, and files included in a
design file .......................................................................38
Audit2Stats5 : Dumps the data regarding line of codes, lines of comment,
per module .....................................................................39
Audit2Stats6 : Dumps the data regarding line of codes, lines of comment,
for entire design ..............................................................40
VHDL Rules............................................................................................ 41
Audit2Stats4 : Dumps the generic used per entity ..............................42
Audit2Stats5 : Dumps the data regarding line of codes, lines of comment,
per architecture ...............................................................43
Audit2Stats6 : Dumps the data regarding line of codes, lines of comment,
for entire design ..............................................................45
Audit2Stats7a : Gives the libraries that are declared but not used in the
design unit......................................................................47
Audit2Stats7b : Gives all the libraries declared for entity and architecture
48

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 Preface

About This Book

The SpyGlass® audits Rules Reference Guide describes the SpyGlass rules
designed for audits rule-checking requirements.

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Preface

Contents of This Book

Contents of This Book

The SpyGlass audits Rules Reference Guide consists of the following
sections:

Chapter Describes...
Using the Rules in the SpyGlass Describes the parameters and
audits Product reports in the SpyGlass audits
product
Rules in SpyGlass audits Describes the rules in the SpyGlass
audits product

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 Preface

Typographical Conventions

Typographical Conventions
This document uses the following typographical conventions:

To indicate Convention Used

Program code OUT <= IN;
Object names OUT
Variables representing <sig-name>
objects names
Message Active low signal name '<sig-name>' must end
with _X.
Message location OUT <= IN;
Reworked example OUT_X <= IN;
with message removed
Important Information NOTE: This rule...

The following table describes the syntax used in this document:

Syntax Description
[ ] (Square brackets) An optional entry
{ } (Curly braces) An entry that can be specified once or multiple
times
| (Vertical bar) A list of choices out of which you can choose
one
... (Horizontal Other options that you can specify
ellipsis)

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Preface

Typographical Conventions

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Using the Rules in the
SpyGlass audits Product

The SpyGlass® audits product has the following operating concepts:

 SpyGlass area Rule Parameters
 Product Reports

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Using the Rules in the SpyGlass audits Product

SpyGlass area Rule Parameters

SpyGlass area Rule Parameters

This section provides detailed information on the SpyGlass audits product
rule parameters.
You can set these parameters in both Atrenta Console and Tcl by using the
following syntax:
set_parameter <parameter_name> <parameter_value>
For more information on setting the parameters, refer to the SpyGlass Tcl
Interface User Guide and Atrenta Console User Guide.

audit_cell_details
Reads the cell types and their custom attribute combination from the
specified file.
By default, the value of this parameter is NULL.
You can specify the absolute or relative path of the file that contains the
cell details. The following specifies the format for the specified file:
<cell_type> <cell_celltype value>
<cell_blocktype value> <cell_blockgroup value>
You can use the audit_cell_details parameter only when the value
of the report_all_cells rule parameter is set to yes.
NOTE: To use the audit_cell_details parameter, you must have an sgm license
feature.

Used by AuditReportCell
Options are Absolute or relative path of a file
Default NULL
Example
Console/Tcl-based set_parameter audit_cell_details /home/users/
usage abcd.txt
Usage in goal/source -audit_cell_details=/home/users/abcd.txt
files

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 Using the Rules in the SpyGlass audits Product

SpyGlass area Rule Parameters

checklib
When the checklib rule parameter is set to yes, the Verilog rules
Audit2Stats5 and Audit2Stats6 dump data for library files.

Used by Audit2Stats5, Audit2Stats6

Options are yes, no
Default no
Example
Console/Tcl-based set_parameter checklib yes
usage
Usage in goal/source -checklib=yes
files

report_all_cells
Helps the user to extract information regarding flip-flops, latches, tristates,
funcIO, nonFuncIO, AMS (Analog Mixed Signal blocks), DRAM or fuse, and
memory cell used in the design.
By default, the value of the report_all_cells parameter is set to no
and the SpyGlass audits Structure Report does not displays information
regarding funcIO, nonFuncIO, AMS, DRAM or fuse, and memory cells in
Design Element Statistics section and in the Design Hierarchy Section.
You can set the value of this parameter to yes to enable the SpyGlass audits
Structure Report to print information regarding funcIO, nonFuncIO, AMS,
DRAM or fuse and memory cells in the Design Element Statistics section
and in the Design Hierarchy Section.
NOTE: To enable this feature user must have an sgm license feature.

Used by AuditReportCell
Options are yes, no
Default no
Example

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Using the Rules in the SpyGlass audits Product

SpyGlass area Rule Parameters

Console/Tcl-based set_parameter report_all_cells yes

usage
Usage in goal/source -report_all_cells=yes
files

report_rtl_name
Specifies if the RTL module name should be reported.
By default, the elaborated module name is reported in the Audit.rpt
report.
If the report_rtl_name parameter is set to yes, the RTL module name
is reported.

Used by Audit2ID, Audit2Stats, Audit2Stats3, Audit2Stats4,

Audit2Stats5, Audit2Stats6, Audit2Stats7a,
Audit2Stats7b, Audit2Stats8, Audit3ID, Audit3run,
Audit4ID, Audit4Count, Audit4Dump,
AuditReportCell, Audit2, Audit3, Audit4
Options are yes, no
Default no
Example
Console/Tcl-based set_parameter report_rtl_name yes
usage
Usage in goal/source -report_rtl_name=yes
files

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 Using the Rules in the SpyGlass audits Product

Product Reports

Product Reports
To view the reports generated by the rules in the SpyGlass audits product,
use the Tools -> Report menu option in Atrenta Console, or use the
set_option report <report-name> command in a project file.
The SpyGlass audits product report, Audit.rpt, is generated when the
block_profile goal is run. This goal is available at the following path:
./SPYGLASS_HOME/GuideWare/New_RTL/initial_rtl/audit/
block_profile-mixed.spq
This report provides summary information about the RTL, design inputs,
and structural data of the design.
You can generate the following reports, depending on the goal you are
using for running SpyGlass:

Report Name Description

Audit-RTL This report is generated when the rtl_audit goal
is run and provides information about the RTL of the
design.
Audit-Structure This report is generated when the
structure_audit goal is run and provides
information about the structural data of the design.

NOTE: These reports are generated with the same name, Audit.rpt.
NOTE: The 1D/2D column of the Audit report that lists the total of each One-dimensional
array and two-dimensional array, respectively, in a design currently works for
Verilog designs only. These columns are left blank for VHDL designs.

SpyGlass audits RTL Report

The SpyGlass audits RTL report is generated when the rtl_audit goal is
run. This goal is available at the following path:
./SPYGLASS_HOME/GuideWare/New_RTL/initial_rtl/audit/
rtl_audit-mixed.spq

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Using the Rules in the SpyGlass audits Product

Product Reports

The SpyGlass audits report for the Design RTL data consists of the
following sections:
 Basic Design Data
This section reports the basic information of the design, such as total
number of design units, file count, and so on.
 Top-Level Design Unit
This section reports all the top-level design units in a design.
 Black boxes
This section reports all black boxes and stopped design units found in
the design.
 Gray boxes
This section reports all gray boxes found in the design. In SpyGlass, a
gray box is a module that contains only port information.
 Unsynthesizable Design Units
This section reports all unsynthesizable design units found in the design.
 Parameters or Generics in Design Units
This section reports all parameters or generics declared in the design.
 Macros in Design Units
This section reports all the macros in a design (Verilog only). The
macros in the header files are reported, if the header files are included
in the design files by using the include syntax.
 Libraries in Design Units
This section reports the libraries that are declared, including both used
and unused libraries (VHDL only).
 Lines of Code per Design Unit and for Complete Design
This section reports the file statistics, such as lines of code, commented
lines, and blank lines preset in a file.
 Design Hierarchy
This section reports the hierarchical view of the complete design,
including the file name for each RTL module.
 Hierarchical Instance Count of Modules
This section reports the hierarchical view of the complete design,
including the instance count of each cell against its name.

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Product Reports

 Statistics by Design Unit

This section reports the basic information of all the modules or entities,
such as port count, memories, arrays, and instances inside the design
unit.

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Product Reports

SpyGlass audits Structure Report

The SpyGlass audits structure report is generated when the
structure_audit goal is run. This goal is available at the following
path:
./SPYGLASS_HOME/GuideWare/New_RTL/initial_rtl/audit/
structure_audit-mixed.spq
The SpyGlass audits report for the design structure consists of the
following sections:
 Design Size Statistics
This section reports design size summary, such as gate count. It also
reports the number of flip-flops, latches, and tristates inferred in the
complete design.
 Control Signals
This section reports the probable clocks and reset signals of the design.
 Design Element Statistics
This section generates a detailed structural report for every design unit.
This section consists of information, such as cumulative gate count,
percentage of total gate count, instance count, and the number of
flip-flops, latches, and tristates inferred in a design unit.
 Design Hierarchy
This section reports the hierarchical view of the complete design. It
shows the gate count along with the number of flip-flops, latches, and
tristates inferred for a design unit.
NOTE: The flip-flop, latch, or tristate count reported in this report is not actual, but based
on the SpyGlass internal synthesis engine. Therefore, results may vary with other
commercial synthesis tools. In SpyGlass, the flip-flop count could be slightly higher
than the actual implementation, because we retain all flip-flops to check for
hanging net and instances. Some of these flip-flops might be removed by the
production synthesis tools.

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 Rules in SpyGlass audits

Rule Grouping in SpyGlass audits

Some of the rules in the SpyGlass audits product are divided into the
following rule groups:
 Audit2
 Audit3
 Audit4
These are explained in the following sections.

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Rules in SpyGlass audits

Rule Grouping in SpyGlass audits

Audit2
Evaluates the number of ports, instances, one-dimensional array
and two-dimensional array in a module

Language
Verilog, VHDL

Rule Description
The Audit2 rule evaluates the number of input, inout, output ports, number
of instances, and the total bit count of each of the one-dimensional and
two-dimensional arrays used in the module.
The Audit2 rule runs the following rules:

Language Rules
Verilog and VHDL Audit2ID, Audit2Stats, Audit2Stats3, Audit2Stats8,
Audit2FileNameDump
Verilog Audit2Stats4, Audit2Stats5, Audit2Stats6
VHDL Audit2Stats4, Audit2Stats5, Audit2Stats6,
Audit2Stats7a, Audit2Stats7b

Parameters
report_rtl_name: Default value is
no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

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Rule Grouping in SpyGlass audits

Audit3
Evaluates the number of instances, gates, and memory consumed
in synthesis of each module

Language
Verilog, VHDL

Rule Description
The Audit3 rule evaluates the number of instances, gates, and memory
consumed in synthesis of each module. In addition, the rule generates the
area of each module in terms of NAND gate count in the sizer.log file.
The Audit3 rule runs the following rules:

Language Rules
Verilog and VHDL Audit3ID, Audit3run
Verilog -
VHDL -

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

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Rule Grouping in SpyGlass audits

Audit4
Evaluates the information regarding number of flip-flops, latches,
and tristates in a module

Language
Verilog, VHDL

Rule Description
The Audit4 rule evaluates the information regarding number of flip-flops,
latches, and tristates in a module. This is done on a flat-level netlist.
The Audit4 rule runs the following rules:

Language Rules
Verilog and VHDL Audit4ID, Audit4Count, Audit4Dump,
AuditReportCell
Verilog Audit2Stats4
VHDL Audit2Stats4

Parameters
report_rtl_name: Default value is
no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

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Verilog and VHDL Rules

Verilog and VHDL Rules

The following Verilog and VHDL rules in the SpyGlass audits product are
explained in this section.

Rule Description
Audit2FileNameD Dumps the information regarding which module is
ump defined in which file
Audit2ID Gathers stats for design. Do not select this rule
directly
Audit2Stats Evaluates the number of input, output, and inout
ports in a module
Audit2Stats3 Evaluates the sum total of each of one-
dimensional and multidimensional
buses used in a design on the RTL level
Audit2Stats8 Evaluates the number of times each black box is
instantiated
Audit3ID Gathers stats for design. Do not select this rule
directly
Audit3run Evaluates the number of instances, gates and
memory consumed in synthesis of each module.
Also dumps the area of each module in terms of
NAND gate count in a file sizer.log
Audit4Count Evaluates the number of flip-flops, latches, and
tristates in a module. This is done on a flat-level
netlist
Audit4Dump Dumps the information regarding number of flip-
flops, latches, and tristates (evaluated in the
Audit4count rule) on stdout
Audit4ID Gathers stats for design. Do not select this rule
directly
AuditReportCell Dumps the information regarding library cells

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Verilog and VHDL Rules

Audit2FileNameDump
Dumps the information regarding which module is defined in which
file

Language
Verilog, VHDL

Rule Description
The Audit2FileNameDump rule generates the information regarding which
module is defined in which file.
NOTE: This rule is for internal usage. Do not select this rule directly.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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Verilog and VHDL Rules

Audit2ID
Gathers stats for design. Do not select this rule directly

Language
Verilog, VHDL

Rule Description
The Audit2ID rule gathers statistics for a design.
NOTE: This rule is for internal usage. Do not select the rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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Verilog and VHDL Rules

Audit2Stats
Evaluates the number of input, output, and inout ports in a module

Language
Verilog, VHDL

Rule Description
The Audit2Stats rule gathers statistics for a design on the RTL level. The
rule evaluates the number of input, output, and inout ports in a module on
RTL level.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The following message appears:
Module <module-name> Ports <num1> <num2> <num3> Instances
<instance>
Where, <num1>, <num2>, and <num3> are the number of input, output,
and inout ports in a module. In addition, <instance> signifies the
number of instances in the module.

Rule Severity
Data

Examples
Consider the following example:
Module qae377 Ports 14 55 295 Instances 54

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Verilog and VHDL Rules

Audit2Stats3
Evaluates the sum total of each of one-dimensional and multi-
dimensional buses used in a design on the RTL level

Language
Verilog, VHDL

Rule Description
Verilog
The Audit2Stats3 rule gathers statistics for design on the RTL level. The
rule evaluates the sum total of each one-dimensional (packed or unpacked)
arrays and multi-dimensional memories, buses, and arrays used in a
design. The Audit2Stats3 rule does not consider the buses declared inside
functions, tasks, always blocks, or UDPs for such a calculation.
The size of a structure or an interface is one-dimensional and
multi-dimensional. The Audit2Stats3 rule calculates these sizes for both
the structure and the interface. However, the size of a union can be
one-dimensional or multi-dimensional, depending on the width of the
largest size union item.
If there is an array of a structure, a union, or an interface, then both
one-dimension and multi-dimension sizes of such constructs are multiplied
with respective array size to calculate the total one-dimension and
multi-dimension sizes.
The Audit2Stats3 rule considers integer, shortint, longint, and byte as
fixed-width one-dimensional vectors. These vectors are added to
one-dimensional widths of a module. If any arrays are formed from these
data types, then they are considered as multi-dimensional arrays.
VHDL
The Audit2Stats3 rule gathers statistics for a design on the RTL level. The
rule evaluates the sum total of each one-dimensional and
multi-dimensional buses used in a design.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is

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Rules in SpyGlass audits

Verilog and VHDL Rules

reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
Verilog
The following message appears:
1D and 2D: <num1> <num2>
Where,
<num1> is the sum total of each one-dimensional array (packed or
unpacked) in a design
<num2> is the sum total of each multi-dimensional array, memory, or bus
used in a design
VHDL
The following message appears:
1D and 2D: <num1> <num2>
Where,
<num1> is the sum total of each one-dimensional bus used in a design
<num2> is the sum total of each multi-dimensional bus used in a design

Rule Severity
Data

Examples
Consider the following example:
1D and 2D: 8 0

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Verilog and VHDL Rules

Audit2Stats8
Evaluates the number of times each black box is instantiated

Language
Verilog, VHDL

Rule Description
The Audit2Stats8 rule evaluates the number of times each black box is
instantiated.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The following message appears:
blackbox <bb-name> count <num>
Where,
<bb-name> is the name of the black box
<num> is the number of times a black box has been instantiated

Rule Severity
Data

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Verilog and VHDL Rules

Audit3ID
Gathers stats for design. Do not select this rule directly

Language
Verilog, VHDL

Rule Description
The Audit3ID rule gathers statistics for a design.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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Verilog and VHDL Rules

Audit3run
Evaluates the number of instances, gates and memory consumed in
synthesis of each module. Also dumps the area of each module in
terms of NAND gate count in a file sizer.log

Language
Verilog, VHDL

Rule Description
The Audit3run rule evaluates the number of instances, gates, and memory
consumed in synthesis of each module. In addition, the rule generates the
area of each module in terms of NAND gate count in the sizer.log file.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is
no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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Verilog and VHDL Rules

Audit4Count
Evaluates the number of flip-flops, latches, and tristates in a
module. This is done on a flat-level netlist

Language
Verilog, VHDL

Rule Description
The Audit4Count rule gathers statistics for a design. The rule evaluates the
number of flip-flops, latches, and tristates in a module. This is done on a
flat-level netlist.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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Verilog and VHDL Rules

Audit4Dump
Dumps the information regarding number of flip-flops, latches, and
tristates (evaluated in the Audit4count rule) on stdout

Language
Verilog, VHDL

Rule Description
The Audit4Dump rule generates information regarding the number of flip-
flops, latches, and tristates (evaluated in Audit4Count rule) on stdout.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The following message appears:
Mod <module-name> x Flops <num1> Latches <num2> Tristates
<num3>
Where,
<module-name> is the name of the module
<num1>, <num2>, and <num3> are the number of flip-flops, latches,
and tristates in a module

Rule Severity
Data

Examples
Consider the following example:
Mod exptop_dec 1 x Flops 0 Latches 0 Tristates 0

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Rules in SpyGlass audits

Verilog and VHDL Rules

Audit4ID
Gathers stats for design. Do not select this rule directly

Language
Verilog, VHDL

Rule Description
The Audit4ID rule gathers statistics for a design.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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 Rules in SpyGlass audits

Verilog and VHDL Rules

AuditReportCell
Dumps the information regarding library cells

Language
Verilog, VHDL

Rule Description
The AuditReportCell rule reports library cells, which are flip-flops, latches,
tristates, memory, funcIO, nonFuncIO, AMS (Analog Mixed Signal blocks)
and DRAM or fuse cells in a design unit.
By default, the value of the report_all_cells parameter is set to no and the
SpyGlass audits Structure Report does not displays information regarding
funcIO, nonFuncIO, AMS, DRAM or fuse, and memory cells in the Design
Element Statistics section and in the Design Hierarchy Section. You can set
the value of the report_all_cells parameter to yes to enable the
SpyGlass audits Structure Report to print such information.
In addition, you can set the value of the audit_cell_details parameter to read
the cell types and their custom attribute combination from the specified
file. By default, the value of the audit_cell_details parameter is
NULL.
NOTE: You can use the audit_cell_details parameter only when the value of the
report_all_cells parameter is set to yes.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The following message appears when the AuditReportCell rule generates
the information regarding library cells:
<Cell_Type> instance <instance_name> [MasterName:
'<master_name>'] found in module '<module_name>'

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Rules in SpyGlass audits

Verilog and VHDL Rules

Rule Severity
Data

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 Rules in SpyGlass audits

Verilog Rules

Verilog Rules
The following Verilog rules in the SpyGlass audits product are explained in
this section.

Rule Description
Audit2Stats4 Dumps the parameters, macros, and files
included in a design file
Audit2Stats5 Dumps the data regarding line of codes, lines of
comment, per module
Audit2Stats6 Dumps the data regarding line of codes, lines of
comment, for entire design

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Rules in SpyGlass audits

Verilog Rules

Audit2Stats4
Dumps the parameters, macros, and files included in a design file

Language
Verilog

Rule Description
The Audit2Stats4 rule generates the parameters in a module, and the
macros and files included in a file. The rule reports the macros in the
header files only if the header files are included in the design files using the
include syntax.
NOTE: This rule is for internal usage. Do not select this rule directly.

Message Details
The following message appears:
<name> parameter SIZE <num>
Where,
<name> is the name of the parameter
<num> is the size of the parameter

Rule Severity
Data

Examples
Consider the following example:
fanout parameter SIZE 8

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 Rules in SpyGlass audits

Verilog Rules

Audit2Stats5
Dumps the data regarding line of codes, lines of comment, per
module

Language
Verilog

Rule Description
The Audit2Stats5 rule generates the total lines of code, lines of comments,
lines with code and comments, and total blank lines in a module.
By default, this data will not be generated for the library files. To generate
the data for the library files, use the checklib rule parameter.
NOTE: This rule is for internal usage. Do not select this rule directly.

Message Details
The following message appears:
<module-name> total-line:<num1> codeline:<num2>
commentline:<num3> sameline:<num4> blankline:<num5>
Where,
<module-name> is the name of the module
<num1> is the total number of lines of code in a module
<num2> is the number of code lines in the module
<num3> is the number of commented lines
<num4> is the number of lines containing both code and comments
<num5> is the total number of blank lines

Rule Severity
Data

Examples
Consider the following example:
clcell total-line:19 codeline:15 commentline:0 sameline:0
blankline:4

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Rules in SpyGlass audits

Verilog Rules

Audit2Stats6
Dumps the data regarding line of codes, lines of comment, for
entire design

Language
Verilog

Rule Description
The Audit2Stats6 rule generates the total lines of code, lines of comments,
lines with code and comments, and total blank lines for the entire design.
By default, this data is not generated for the library files. To generate the
data for the library files, use the checklib rule parameter.
NOTE: This rule is for internal usage. Do not select this rule directly.

Message Details
The following message appears:
<du-name>: totalLine:<num1> totalCodeLine:<num2>
commentLine:<num3> sameLine:<num4> blankLine:<num5>
Where,
<du-name> is the name of the design unit
<num1> is the total number of lines in a design
<num2> is the total number of code lines
<num3> is the number of commented lines
<num4> is the number of lines containing both code and comments
<num5> is the total number of blank lines

Rule Severity
Data

Examples
Consider the following example:
CompleteDesign: totalLine:2404 totalCodeLine:1804
commentLine:189 sameLine:52 blankLine:463

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 Rules in SpyGlass audits

VHDL Rules

VHDL Rules
The following VHDL rules in the SpyGlass audits product are explained in
this section.

Rule Description
Audit2Stats4 Dumps the generic used per entity
Audit2Stats5 Dumps the data regarding line of codes, lines of
comment, per architecture
Audit2Stats6 Dumps the data regarding line of codes, lines of
comment, for entire design
Audit2Stats7a Gives the libraries that are declared but not used
in the design unit
Audit2Stats7b Gives all the libraries declared for entity and
architecture

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Rules in SpyGlass audits

VHDL Rules

Audit2Stats4
Dumps the generic used per entity

Language
VHDL

Rule Description
The Audit2Stats4 rule generates all the generics in an entity.
NOTE: Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The following message appears:
<name> parameter SIZE <num>
Where,
<name> is the name of the parameter
<num> is the size of the parameter

Rule Severity
Data

Examples
Consider the following example:
fanout parameter SIZE 8

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 Rules in SpyGlass audits

VHDL Rules

Audit2Stats5
Dumps the data regarding line of codes, lines of comment, per
architecture

Language
VHDL

Rule Description
The Audit2Stats5 rule generates the total lines of code, lines of comments,
lines with code and comments, and total blank lines in an architecture.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The following message appears:
<module-name> total-line:<num1> codeline:<num2>
commentline:<num3> sameline:<num4> blankline:<num5>
Where,
<module-name> is the name of the module
<num1> is the total number of lines of code in a module
<num2> is the number of code lines in the module
<num3> is the number of commented lines
<num4> is the number of lines containing both code and comments
<num5> is the total number of blank lines

Rule Severity
Data

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Rules in SpyGlass audits

VHDL Rules

Examples
Consider the following example:
clcell total-line:19 codeline:15 commentline:0 sameline:0
blankline:4

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 Rules in SpyGlass audits

VHDL Rules

Audit2Stats6
Dumps the data regarding line of codes, lines of comment, for
entire design

Language
VHDL

Rule Description
The Audit2Stats6 rule generates the total lines of code, lines of comments,
lines with code and comments, and total blank lines for the entire design.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The following message appears:
<du-name>: totalLine:<num1> totalCodeLine:<num2>
commentLine:<num3> sameLine:<num4> blankLine:<num5>
Where,
<du-name> is the name of the design unit
<num1> is the total number of lines in a design
<num2> is the total number of code lines
<num3> is the number of commented lines
<num4> is the number of lines containing both code and comments
<num5> is the total number of blank lines

Rule Severity
Data

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Rules in SpyGlass audits

VHDL Rules

Examples
Consider the following example:
CompleteDesign: totalLine:2404 totalCodeLine:1804
commentLine:189 sameLine:52 blankLine:463

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 Rules in SpyGlass audits

VHDL Rules

Audit2Stats7a
Gives the libraries that are declared but not used in the design unit

Language
VHDL

Rule Description
The Audit2Stats7a rule gives the libraries that are declared but are not
used in the design unit.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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Rules in SpyGlass audits

VHDL Rules

Audit2Stats7b
Gives all the libraries declared for entity and architecture

Language
VHDL

Rule Description
The Audit2Stats7b rule gives all the libraries declared for entity and
architecture.
NOTE: This rule is for internal usage. Do not select this rule directly.

Parameters
report_rtl_name: Default value is no and the elaborated module name is
reported in the Audit.rpt report. If the this parameter is set to yes, the
RTL module name is reported.

Message Details
The violation message of the rule is used to populate some internal data
structures and does not have much readability and significance.

Rule Severity
Data

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List of Topics

About This Book ............................................................................................. 7

audit_cell_details ......................................................................................... 12
checklib ...................................................................................................... 13
Contents of This Book ..................................................................................... 8
Product Reports ........................................................................................... 15
report_all_cells ............................................................................................ 13
report_rtl_name........................................................................................... 14
Rule Grouping in SpyGlass audits ................................................................... 19
SpyGlass area Rule Parameters ...................................................................... 12
SpyGlass audits RTL Report ........................................................................... 15
SpyGlass audits Structure Report ................................................................... 18
Typographical Conventions .............................................................................. 9
Verilog and VHDL Rules................................................................................. 23
Verilog Rules ............................................................................................... 37
VHDL Rules ................................................................................................. 41

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