SJCIT Question Bank

Estd: 1986

Department of Electronics and Communication Engineering

SUBJECT TYPE CORE

SUBJECT CODE 21EC71

ACADEMIC YEAR 2024-25 BATCH 2021

SCHEME 2021

SEMESTER VII- C
FACULTY NAME and
Dr. K.Ezhilarasan, Associate Professor
DESIGNATION

Module -1
Q. Bloom’s
Questions COs
No. LL
1. Classify ASIC based on manufacturing? L1 CO1
2. Show the steps used for ASIC design flow? L1 CO1
3. Explain the IC era in VLSI L2 CO1
Describe custom design, standard cell, compiled cell and macro cells L2 CO1
4.
approaches of Digital IC implementation
5. Describe with diagram the various stages of semiconductor design flow L2 CO1
6. Illustrate the ASIC design flow in detail. L2 CO1
7. Explain the different types of Programmable ASIC with neat diagram L2 CO1

8. Construct a n-bit ripple carry adder using full adders. What are the L3 CO1
advantages and limitations of this design in a datapath?
9. List and explain the primary datapath elements used in a processor L1 CO1
Explain the working principle of a4-bit conventional ripple carry adder. How L2
10. CO1
does the carry propagate and generate through the adder.
Explain the working principle of a carry save adder. How does it handle L2
11. CO1
carries compared to other types of adders?

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Design a 4-bit carry save adder to add three binary numbers. What is the sum L6
12. CO1
and carry results in each step?
13. Design a 4-bit pipeline-based carry save adder L6 CO1
Explain the working mechanism of a Carry Bypass Adder. How does it allow L2
14. CO1
the carry to skip over certain blocks?
Explain the working principle of a Carry Skip Adder. How does the carry- L2
15. CO1
skip mechanism function?
Design a 16-bit Carry Skip Adder using four 4-bit blocks. Explain how the L4
16. CO1
carry is processed within and between the blocks.
How does the Carry Lookahead Adder predict carry outputs for each bit L4
17. CO1
position? Describe the mathematical expressions involved.
How does a Carry Select Adder compute sums for both carry-in scenarios? L5
18. CO1
Explain the process.
How does a Conditional Sum Adder calculate multiple potential sums? L2
19. CO1
Describe the process in detail.

20. Write the verilog HDL Program for 4-bit conditional sum adder L2 CO1

What are the different types of arithmetic and logical operators commonly L1
21. CO1
used in data paths? How do they differ in functionality?
What are the components are required for Booth multiplier encoding and L2
22. CO1
explain in details with an example.
Explain the Three state bi-directional output buffer with a near diagram. L2
23. CO1

Module -2
Q. Bloom’s
Questions COs
No. LL
1. What are the key objectives to consider when placing functional blocks L1 CO2
on a chip?
2. How is wire (interconnect) delay estimated during the floor planning L1 CO2
stage?
3. What factors contribute to gate delay, and how is it measured in floor L1 CO2
planning?
4. What are the Floor Planning tools and explain L2 CO2
5. Can you explain the concept of seed cells and their role in guiding L2 CO2
placement?

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6. What are some common challenges faced in floor planning large and L2 CO2
complex designs?
7. How do floor planning tools utilize algorithms to optimize the placement L3 CO2
process?
8. Define chip allocation and explain the various channel allocation L2 CO2
methods.
9. Explain the Bonding Pad and Gate Array Pad with neat diagram L2 CO2
10. Explain the various levels of power distribution with the neat diagram L2 CO2
11. What are the key steps in Clock Tree Synthesis (CTS), and how does it L3 CO2
contribute to the overall timing closure process in ASIC design?
12. How does clock skew affect the performance of an ASIC, and what are L3 CO2
the key methods used to minimize skew?
13. Explain the following placement structure with the neat diagram L2
(i) Interconnect structure (ii) Multilevel routing (iii) Gate Array
CO2
interconnect
14. What are main goals and objective of placement is ASIC? L1 CO2
15. Explain the classification of placement algorithms in ASIC L2 CO2
16. Write down the procedure for min-cut placement algorithm L4 CO2
17. Explain the iterative improvement placement algorithm. L2 CO2
18. Explain the various approaches of time driven placement methods. L2 CO2
19. Explain the zero-slack algorithm with an example. L2 CO2
20. Illustrate the physical design flow cycle. L3 CO2
21. What are the goal and objectives of routing in ASIC? L1 CO2
22. Explain the various global routing method L2 CO2
23. Explain the global routing between blocks with neat diagram L2 CO2

Module -3
Q. Bloom’s
Questions COs
No. LL
1 Explain the verification process of system verilog L2 CO3
2 Draw the diagram of layered testbench of system verilog and describe the CO3
L2
functions of each block
3 Describe fixed array and dynamic array with and example L1 CO3
4 Describe the various array methods with a suitable Example L1 CO3
5 Describe typedef and enumerated data type with an example L1 CO3
6 Explain factors in randomizing the stimulus to a design L2 CO3
7 Write a note on user defined data types in system verilog L1 CO3
8 Explain constants and strings in system verilog with an example L2 CO3
9 Illustrate the test bench components L2 CO3
10 List the inbuilt data types of system verilog L1 CO3
11 What is a queue in SystemVerilog, and how does it differ from a regular CO3
L1
array and give the Example

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12 How do you choose the right storage type based on flexibility, CO3
L1
memory usage, speed, and sorting in System verilog

Module -4
Q. Bloom
Questions COs
No. ’s LL
1. Explain task, functions and void functions in system verilog L2 CO4
2. How time values are specified in system verilog and describe with an CO4
L1
example
3. Describe testbench-design race condition and write system verilog code CO4
L1
for race condition between testbench and design
4. Explain Automatic storage and variable initialization with system verilog CO4
L2
program example
5. Describe how to specify time values in system verilog L1 CO4
6. Write the difference between Tasks and functions in system verilog L3 CO4
7. Describe the communication between the test bench and DUT with CO4
L1
suitable diagram and system verilog program
8. Explain different types of system verilog assertions with example L2 CO4
9. Draw the diagram of Testbench-arbiter without interface and explain L2 CO4
10. Describe C-style routine arguments, argument direction, advanced CO4
argument types, and default argument values with system verilog L1
program example
11. Develop the system verilog code for the arbiter model using ports, CO4
L3
testbench using ports, top-level net list without interface

Module -5
Q. Bloom’s
Questions COs
No. LL
1. What is randomization? Explain randomization in system verilog L1 CO5
2. Describe conditional constraints and bidirectional constraints in system CO5
L2
verilog with example
3. Write any four random number functions with example L1 CO5
4. Interpret common randomization problems in system verilog L2 CO5
5. Write a note on Pseudo random number generators in system verilog L1 CO5
6. What is coverage? Explain coverage types in system verilog L2 CO5
7. Explain functional coverage inside class with program L2 CO5
8. Write a note on Data Sampling L1 CO5
9. What is cross coverage? Develop system verilog code for labeling cross CO5
L3
coverage Bins and give its summary report
10. Explain generic cover groups in system verilog L2 CO5

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11. Describe the operation of rand case statement with program L2 CO5
12. Infer various functional coverage strategies CO5
L2
13. Describe various coverage options with example L2 CO5

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