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ISO7730, ISO7731
SLLSES0G – SEPTEMBER 2016 – REVISED MARCH 2020

ISO773x High-Speed, Robust-EMC Reinforced and Basic Triple-Channel Digital Isolators

1 Features 3 Description
•
1 100 Mbps data rate The ISO773x devices are high-performance, triple-
channel digital isolators with 5000 VRMS (DW
• Robust isolation barrier: package) and 3000 VRMS (DBQ package) isolation
– >100-year projected lifetime at 1500 VRMS ratings per UL 1577.
working voltage
This family includes devices with reinforced insulation
– Up to 5000 VRMS isolation rating ratings according to VDE, CSA, TUV and CQC. The
– Up to 12.8 kV surge capability ISO7731B device is designed for applications that
– ±100 kV/μs typical CMTI require basic insulation ratings only.
• Wide supply range: 2.25 V to 5.5 V The ISO773x family of devices provides high
• 2.25-V to 5.5-V Level translation electromagnetic immunity and low emissions at low
power consumption, while isolating CMOS or
• Default output high (ISO773x) and low LVCMOS digital I/Os. Each isolation channel has a
(ISO773xF) options logic input and output buffer separated by a double
• Wide temperature range: –55°C to +125°C capacitive silicon dioxide (SiO2) insulation barrier.
• Low power consumption, typical 1.5 mA per This device comes with enable pins which can be
used to put the respective outputs in high impedance
channel at 1 Mbps
for multi-master driving applications and to reduce
• Low propagation delay: 11 ns Typical (5-V power consumption.
Supplies)
• Robust electromagnetic compatibility (EMC) Device Information(1)
– System-level ESD, EFT, and surge immunity PART NUMBER PACKAGE BODY SIZE (NOM)

– ±8 kV IEC 61000-4-2 contact discharge ISO7730 SOIC (DW) 10.30 mm × 7.50 mm

ISO7731 SSOP (DBQ) 4.90 mm × 3.90 mm
protection across isolation barrier
– Low emissions ISO7731B SOIC (DW) 10.30 mm × 7.50 mm

• Wide-SOIC (DW-16) and QSOP (DBQ-16) (1) For all available packages, see the orderable addendum at
the end of the datasheet.
package options
• Automotive version available: ISO773x-Q1 Simplified Schematic
• Safety-related certifications:
– DIN VDE V 0884-11:2017-01
– UL 1577 component recognition program VCCI VCCO

– CSA, CQC and TUV certifications Series Isolation

Capacitors

2 Applications INx OUTx

• Industrial automation ENx

• Motor control
GNDI GNDO
• Power supplies Copyright © 2016, Texas Instruments Incorporated

• Solar inverters
VCCI=Input supply, VCCO=Output supply
• Medical equipment
GNDI=Input ground, GNDO=Output ground

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.18 Insulation Characteristics Curves ......................... 16
2 Applications ........................................................... 1 7.19 Typical Characteristics .......................................... 17
3 Description ............................................................. 1 8 Parameter Measurement Information ................ 19
4 Revision History..................................................... 2 9 Detailed Description ............................................ 21
5 Description Continued .......................................... 5 9.1 Overview ................................................................. 21
9.2 Functional Block Diagram ....................................... 21
6 Pin Configuration and Functions ......................... 6
9.3 Feature Description................................................. 22
7 Specifications......................................................... 7
9.4 Device Functional Modes........................................ 23
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7 10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
7.3 Recommended Operating Conditions....................... 7
10.2 Typical Application ............................................... 24
7.4 Thermal Information .................................................. 8
7.5 Power Ratings........................................................... 8 11 Power Supply Recommendations ..................... 28
7.6 Insulation Specifications............................................ 9 12 Layout................................................................... 29
7.7 Safety-Related Certifications................................... 10 12.1 Layout Guidelines ................................................. 29
7.8 Safety Limiting Values ............................................ 10 12.2 Layout Example .................................................... 29
7.9 Electrical Characteristics—5-V Supply ................... 11 13 Device and Documentation Support ................. 30
7.10 Supply Current Characteristics—5-V Supply ........ 11 13.1 Documentation Support ........................................ 30
7.11 Electrical Characteristics—3.3-V Supply .............. 12 13.2 Related Links ........................................................ 30
7.12 Supply Current Characteristics—3.3-V Supply ..... 12 13.3 Receiving Notification of Documentation Updates 30
7.13 Electrical Characteristics—2.5-V Supply .............. 13 13.4 Community Resources.......................................... 30
7.14 Supply Current Characteristics—2.5-V Supply ..... 13 13.5 Trademarks ........................................................... 30
7.15 Switching Characteristics—5-V Supply................. 14 13.6 Electrostatic Discharge Caution ............................ 30
7.16 Switching Characteristics—3.3-V Supply.............. 15 13.7 Glossary ................................................................ 30
7.17 Switching Characteristics—2.5-V Supply.............. 15 14 Mechanical, Packaging, and Orderable
Information ........................................................... 31

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (May 2019) to Revision G Page

• Added ISO7731B device to this data sheet for applications that require basic insulation only. Previous data sheet
literature number for ISO7731B was SLLSF65A ................................................................................................................... 1
• Changed VDE standard name From: DIN V VDE V 0884-11:2017-01 To: DIN VDE V 0884-11:2017-01 throughout
the document ......................................................................................................................................................................... 1
• Changed UL certification bullet in Features From: '5000 VRMS (DW) and 3000 VRMS (DBQ) Isolation Rating per UL
1577' To: 'UL 1577 component recognition program' ............................................................................................................ 1
• Combined CSA, CQC, and TUV Features bullets into a single bullet ................................................................................... 1
• Deleted 'All certifications complete' bullet in Features ........................................................................................................... 1
• Updated certification information in Safety-Related Certifications table .............................................................................. 10

Changes from Revision E (January 2018) to Revision F Page

• Made editorial and cosmetic changes throughout the document .......................................................................................... 1

• Changed From: "Isolation Barrier Life: >40 Years" To: " >100-year projected lifetime at 1500 VRMS working voltage"
in Features.............................................................................................................................................................................. 1
• Added "Up to 5000 VRMS isolation rating" in Features............................................................................................................ 1
• Added "Up to 12.8 kV surge capability" in Features .............................................................................................................. 1
• Added "±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier" in Features ......................................... 1
• Added "Automotive version available: ISO773x-Q1" in Features........................................................................................... 1
• Fixed typo error in UL 1577 isolation rating for DBQ package From: 2500 VRMS To: 3000 VRMS in Features ....................... 1

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• Changed From: "All Certifications Complete except CQC Approval of DBQ-16 Package Devices" To: "All
certifications complete" in Features ....................................................................................................................................... 1
• Updated Simplified Schematic to show two isolation capacitors in series per channel instead of a single isolation
capacitor ................................................................................................................................................................................. 1
• Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in ESD Ratings table ............................................ 7
• Added the following table note to Data rate specification in Recommended Operating Conditions table: "100 Mbps is
the maximum specified data rate, although higher data rates are possible." ........................................................................ 7
• Changed VIORM value for DW-16 package From: "1414 VPK" To: "2121 VPK" in Insulation Specifications table.................... 9
• Changed VIOWM value for DW-16 package AC voltage From: "1000 VRMS" To: "1500 VRMS" and DC voltage From:
"1414 VDC" To: "2121 VDC" in Insulation Specifications table ................................................................................................. 9
• Added 'see Figure 27' to TEST CONDITIONS of VIOWM specification in Insulation Specifications ........................................ 9
• Changed VIOSM TEST CONDITIONS From: "Test method per IEC 60065" To: "Test method per IEC 62368-1" in
Insulation Specifications table ................................................................................................................................................ 9
• Updated certification information in Safety-Related Certifications table .............................................................................. 10
• Changed ground symbols for "Input (Devices with F suffix)" in Device I/O Schematics ..................................................... 23
• Added Insulation Lifetime sub-section under Application Curves section ............................................................................ 27
• Added 'How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems' application report to
Documentation Support section ........................................................................................................................................... 30

Changes from Revision D (May 2017) to Revision E Page

• Changed the DIN certification number and certification status throughout the document .................................................... 1
• Changed the isolation rating of the DBQ package from 2500 VRMS to 3000 VRMS ................................................................ 1
• Added VTEST to the conditions for the maximum transient isolation voltage parameter in the Insulation Specifications
table ........................................................................................................................................................................................ 9
• Changed the value for the DBQ package from 3600 VPK to 4242 VPK throughout the document........................................ 9
• Changed the method b1 Vini condition for apparent charge in the Insulation Specifications table ........................................ 9

Changes from Revision C (December 2016) to Revision D Page

• Updated the Safety-Related Certifications table................................................................................................................... 10

• Changed the minimum CMTI from 40 to 85 in all Electrical Characteristics tables ............................................................ 11

Changes from Revision B (October 2016) to Revision C Page

• Changed the Regulatory Information table to Safety-Related Certifications and updated content...................................... 10
• Changed the certifications from planned to certified in the Safety-Related Certifications table........................................... 10

Changes from Revision A (September 2016) to Revision B Page

• Changed Feature From: "VDE and UL Certifications..." To: "VDE, UL, and TUV Certifications..." ....................................... 1
• Changed the unit value of CLR and CPG From: µm To: mm in Insulation Specifications .................................................... 9
• Changed From: "according to VDE and UL;..." To: "according to VDE, UL, and TUV;..." in the conditions statement
of Safety-Related Certifications ............................................................................................................................................ 10
• Changed From: "Plan to certify" To: "Certified" in column TUV of Safety-Related Certifications ........................................ 10
• Changed From: "Certification Planned" To: "Client ID number: 77311" in column TUV of Safety-Related
Certifications ........................................................................................................................................................................ 10

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Changes from Original (September 2016) to Revision A Page

• Changed VI(HYS) MIN value From: 0.1 × VCCO To: 0.1 × VCCI in Electrical Characteristics—5-V Supply.............................. 11
• Changed VI(HYS) MIN value From: 0.1 × VCCO To: 0.1 × VCCI in Electrical Characteristics—3.3-V Supply........................... 12
• Changed VI(HYS) MIN value From: 0.1 × VCCO To: 0.1 × VCCI in Electrical Characteristics—2.5-V Supply........................... 13
• Changed CMTI MIN value From: 35 To: 40 in Electrical Characteristics—3.3-V Supply .................................................... 13
• Changed PWD MAX value From: 4.7 To: 4.9 in Switching Characteristics—5-V Supply.................................................... 14
• Changed tsk(o) MAX value From: 3.5 To: 4 in Switching Characteristics—5-V Supply......................................................... 14
• Changed tDO MAX value From: 9 To: 0.3 in Switching Characteristics—5-V Supply........................................................... 14
• Changed tDO MAX value From: 9 To: 0.3 in Switching Characteristics—3.3-V Supply........................................................ 15
• Changed tDO MAX value From: 9 To: 0.3 in Switching Characteristics—2.5-V Supply........................................................ 15
• Added Note B to Figure 15................................................................................................................................................... 20

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5 Description Continued
The ISO7730 device has all three channels in the same direction and the ISO7731 device has two forward and
one reverse-direction channel. If the input power or signal is lost, the default output is high for devices without
suffix F and low for devices with suffix F. See the Device Functional Modes section for further details.
Used in conjunction with isolated power supplies, this family of devices helps prevent noise currents on data
buses, such as RS-485, RS-232, and CAN, or other circuits from entering the local ground and interfering with or
damaging sensitive circuitry. Through innovative chip design and layout techniques, electromagnetic compatibility
of the ISO773x device has been significantly enhanced to ease system-level ESD, EFT, surge, and emissions
compliance. The ISO773x family of devices is available in 16-pin wide-SOIC and QSOP packages.

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6 Pin Configuration and Functions

ISO7730 DW and DBQ Packages ISO7731 DW and DBQ Packages

16-Pin SOIC-WB and QSOP 16-Pin SOIC-WB and QSOP
Top View Top View

VCC1 1 16 VCC2 VCC1 1 16 VCC2

GND1 2 15 GND2 GND1 2 15 GND2

INA 3 14 OUTA INA 3 14 OUTA

ISOLATION

ISOLATION
INB 4 13 OUTB INB 4 13 OUTB

INC 5 12 OUTC OUTC 5 12 INC

NC 6 11 NC NC 6 11 NC

NC 7 10 EN2 EN1 7 10 EN2

GND1 8 9 GND2 GND1 8 9 GND2

Pin Functions
PIN
NO. I/O DESCRIPTION
NAME
ISO7730 ISO7731
Output enable 1. Output pins on side 1 are enabled when EN1 is high or
EN1 — 7 I
open and in high-impedance state when EN1 is low.
Output enable 2. Output pins on side 2 are enabled when EN2 is high or
EN2 10 10 I
open and in high-impedance state when EN2 is low.
GND1 2, 8 2, 8 — Ground connection for VCC1
GND2 9, 15 9, 15 — Ground connection for VCC2
INA 3 3 I Input, channel A
INB 4 4 I Input, channel B
INC 5 12 I Input, channel C
NC 6, 7, 11 6, 11 — Not connected
OUTA 14 14 O Output, channel A
OUTB 13 13 O Output, channel B
OUTC 12 5 O Output, channel C
VCC1 1 1 — Power supply, VCC1
VCC2 16 16 — Power supply, VCC2

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7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN MAX UNIT
VCC1, VCC2 Supply voltage (2) –0.5 6 V
V Voltage at INx, OUTx, ENx –0.5 VCCX + 0.5 (3) V
IO Output current –15 15 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±6000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
V(ESD) Electrostatic discharge ±1500 V
pins (2)
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test (3) (4) ±8000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 2.25 5.5 V
VCC(UVLO+) UVLO threshold when supply voltage is rising 2 2.25 V
VCC(UVLO–) UVLO threshold when supply voltage is falling 1.7 1.8 V
VHYS(UVLO) Supply voltage UVLO hysteresis 100 200 mV
VCCO (1) = 5 V –4
IOH High-level output current VCCO = 3.3 V –2 mA
VCCO = 2.5 V –1
VCCO = 5 V 4
IOL Low-level output current VCCO = 3.3 V 2 mA
VCCO = 2.5 V 1
VIH High-level input voltage 0.7 × VCCI (1) VCCI V
VIL Low-level input voltage 0 0.3 × VCCI V
(2)
DR Data rate 0 100 Mbps
TA Ambient temperature –55 25 125 °C

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

(2) 100 Mbps is the maximum specified data rate, although higher data rates are possible.

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7.4 Thermal Information

ISO773x
THERMAL METRIC (1) DW (SOIC) DBQ (QSOP) UNIT
16 Pins 16 Pins
RθJA Junction-to-ambient thermal resistance 81.4 109 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 44.9 46.8 °C/W
RθJB Junction-to-board thermal resistance 45.9 60.6 °C/W
ψJT Junction-to-top characterization parameter 28.1 35.9 °C/W
ψJB Junction-to-board characterization parameter 45.5 60 °C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7730
PD Maximum power dissipation 150 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
PD1 Maximum power dissipation by side-1 25 mW
input a 50-MHz 50% duty cycle square wave
PD2 Maximum power dissipation by side-2 125 mW
ISO7731
PD Maximum power dissipation 150 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
PD1 Maximum power dissipation by side-1 50 mW
input a 50-MHz 50% duty cycle square wave
PD2 Maximum power dissipation by side-2 100 mW

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7.6 Insulation Specifications

SPECIFICATION
PARAMETER TEST CONDITIONS UNIT
DW-16 DBQ-16
(1)
CLR External clearance Shortest terminal-to-terminal distance through air >8 >3.7 mm
(1)
CPG External creepage Shortest terminal-to-terminal distance across the package surface >8 >3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A >600 >600 V
Material group According to IEC 60664-1 I I
Rated mains voltage ≤ 150 VRMS I–IV I–IV
Overvoltage category per IEC Rated mains voltage ≤ 300 VRMS I–IV I–III
60664-1 Rated mains voltage ≤ 600 VRMS I–IV n/a
Rated mains voltage ≤ 1000 VRMS I–III n/a
DIN VDE V 0884-11:2017-01 (2)
Maximum repetitive peak ISO773x 2121 566
VIORM AC voltage (bipolar) VPK
isolation voltage ISO7731B 1414 n/a
AC voltage; Time dependent dielectric ISO773x 1500 400
VRMS
breakdown (TDDB) Test; See Figure 27 ISO7731B 1000 n/a
Maximum working isolation
VIOWM
voltage ISO773x 2121 566
DC Voltage VDC
ISO7731B 1414 n/a
Maximum transient isolation VTEST = VIOTM, t = 60 s (qualification);
VIOTM 8000 4242 VPK
voltage VTEST = 1.2 × VIOTM, t = 1 s (100% production)
VTEST = 1.6 × VIOSM
8000 4000
Maximum surge isolation Test method per IEC 62368-1, 1.2/50 µs (ISO773x)
VIOSM VPK
voltage (3) waveform, VTEST = 1.3 × VIOSM
6000 n/a
(ISO7731B)
Method a, After Input/Output safety test subgroup 2/3,
≤5 ≤5
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s
Vpd(m) = 1.6 × VIORM,
Method a, After environmental tests ≤5 ≤5
tm = 10 s (ISO773x)
subgroup 1,
Vini = VIOTM, tini = 60 s Vpd(m) = 1.2 × VIORM,
qpd Apparent charge (4) ≤5 n/a pC
tm = 10 s (ISO7731B)
Method b1; At routine test (100% Vpd(m) = 1.875 × VIORM,
≤5 ≤5
production) and preconditioning (type test) tm = 1 s (ISO773x)
Vini = 1.2 × VIOTM, tini = 1 s Vpd(m) = 1.5 × VIORM,
≤5 n/a
tm = 1 s (ISO7731B)
Barrier capacitance, input to
CIO VIO = 0.4 x sin (2πft), f = 1 MHz ~0.7 ~0.7 pF
output (5)
VIO = 500 V, TA = 25°C >1012 >1012
(5) 11
RIO Isolation resistance VIO = 500 V, 100°C ≤ TA ≤ 125°C >10 >1011 Ω
9 9
VIO = 500 V at TS = 150°C >10 >10
Pollution degree 2 2
55/125/ 55/125/
Climatic category
21 21
UL 1577
VTEST = VISO , t = 60 s (qualification),
VISO Withstanding isolation voltage 5000 3000 VRMS
VTEST = 1.2 × VISO , t = 1 s (100% production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation (ISO773x) and basic electrical insulation (ISO7731B) only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.

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7.7 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to EN
Certified according to IEC Certified according to UL 1577
Certified according to DIN Certified according to GB 61010-1:2010/A1:2019, EN
60950-1, IEC 62368-1 and IEC Component Recognition
VDE V 0884-11:2017-01 4943.1-2011 60950-1:2006/A2:2013 and
60601-1 Program
EN 62368-1:2014
5000 VRMS (DW-16) and
Maximum transient 3000 VRMS (DBQ-16)
isolation voltage, 8000 VPK Reinforced insulation per CSA Reinforced insulation per EN
(DW-16) and 4242 VPK 60950-1-07+A1+A2 and IEC 61010-1:2010/A1:2019 up to
(DBQ-16); 60950-1 2nd Ed., DW-16: Reinforced Insulation, working voltage of 600 VRMS
Maximum repetitive peak 800 VRMS (DW-16) and 370 Altitude ≤ 5000 m, Tropical (DW-16) and 300 VRMS
isolation voltage, 2121 VPK VRMS (DBQ-16) max working DW-16: Single protection, 5000 Climate, 700 VRMS maximum (DBQ-16)
(DW-16, Reinforced), 1414 voltage (pollution degree 2, VRMS; working voltage;
VPK (DW-16, Basic) and material group I); DBQ-16: Single protection, DBQ-16: Basic Insulation, 5000 VRMS (DW-16) and
566 VPK (DBQ-16); 2 MOPP (Means of Patient 3000 VRMS Altitude ≤ 5000 m, Tropical 3000 VRMS (DBQ-16)
Maximum surge isolation Protection) per CSA 60601- Climate, 400 VRMS maximum Reinforced insulation per EN
voltage, 8000 VPK (DW-16, 1:14 and IEC 60601-1 Ed. 3.1, working voltage 60950-1:2006/A2:2013 and
Reinforced), 6000 VPK 250 VRMS (DW-16) max working EN 62368-1:2014 up to
(DW-16, Basic) and 4000 voltage working voltage of 800 VRMS
VPK (DBQ-16) (DW -16) and 370 VRMS
(DBQ-16)
Certificate numbers: Certificate numbers:
Master contract number:
40040142 (Reinforced) File number: E181974 CQC15001121716 (DW-16) Client ID number: 77311
220991
40047657 (Basic) CQC18001199097 (DBQ-16)

7.8 Safety Limiting Values

Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DW-16 PACKAGE
RθJA = 81.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1 279
Safety input, output, or
IS RθJA = 81.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1 427 mA
supply current
RθJA = 81.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1 558
Safety input, output, or total
PS RθJA = 81.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 3 1536 mW
power
Maximum safety
TS 150 °C
temperature
DBQ-16 PACKAGE
RθJA = 109.0°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2 209
Safety input, output, or
IS RθJA = 109.0 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2 319 mA
supply current
RθJA = 109.0°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2 417
Safety input, output, or total
PS RθJA = 109.0°C/W, TJ = 150°C, TA = 25°C, see Figure 4 1147 mW
power
Maximum safety
TS 150 °C
temperature

(1) The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-
air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-
air thermal resistance in the Thermal Information is that of a device installed on a High-K test board for leaded surface mount packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature
plus the power times the junction-to-air thermal resistance.

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7.9 Electrical Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 13 VCCO (1) – 0.4 4.8 V
VOL Low-level output voltage IOL = 4 mA; see Figure 13 0.2 0.4 V
VIT+(IN) Rising input voltage threshold 0.6 × VCCI 0.7 × VCCI V
VIT-(IN) Falling input voltage threshold 0.3 × VCCI 0.4 × VCCI V
Input threshold voltage
VI(HYS) 0.1 × VCCI 0.2 × VCCI V
hysteresis
IIH High-level input current VIH = VCCI (1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
Common-mode transient
CMTI VI = VCCI or 0 V, VCM = 1200 V; see Figure 16 85 100 kV/μs
immunity
CI Input Capacitance (2) VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V 2 pF

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

(2) Measured from input pin to ground.

7.10 Supply Current Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO7730

EN2 = 0 V; VI = VCC1 (ISO7730); ICC1 1 1.4 mA

VI = 0 V (ISO7730 with F suffix) ICC2 0.3 0.4 mA
Supply current - disable
EN2 = 0 V; VI = 0 V (ISO7730); ICC1 4.3 6 mA
VI = VCC1 (ISO7730 with F suffix) ICC2 0.3 0.4 mA

EN2 = VCC2; VI = VCC1 (ISO7730); ICC1 1 1.4 mA

VI = 0 V (ISO7730 with F suffix) ICC2 1.6 2.5 mA
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7730); ICC1 4.3 6 mA
VI = VCC1 (ISO7730 with F suffix) ICC2 1.8 2.7 mA
ICC1 2.6 3.7 mA
1 Mbps
ICC2 1.9 2.8 mA

EN2 = VCCI; All channels switching with ICC1 2.7 3.8 mA

Supply current - AC signal 10 Mbps
square wave clock input; CL = 15 pF ICC2 3.3 4.5 mA
ICC1 3.6 4.6 mA
100 Mbps
ICC2 17.5 21 mA
ISO7731

EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731); ICC1 0.8 1.2 mA

VI = 0 V (ISO7731 with F suffix) ICC2 0.7 1 mA
Supply current - disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7731); ICC1 3 4.3 mA
VI = VCCI (ISO7731 with F suffix) ICC2 1.8 2.6 mA

EN1 = EN2 = VCCI; VI = VCCI (ISO7731); ICC1 1.3 1.7 mA

VI = 0 V (ISO7731 with F suffix) ICC2 1.6 2.2 mA
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7731); ICC1 3.5 5 mA
VI = VCCI (ISO7731 with F suffix) ICC2 2.8 4.1 mA
ICC1 2.7 3.4 mA
1 Mbps
ICC2 2.3 3.3 mA

EN1 = EN2 = VCCI; All channels switching ICC1 3 4 mA

Supply current - AC signal 10 Mbps
with square wave clock input; CL = 15 pF ICC2 3.3 4.4 mA
ICC1 8.5 11 mA
100 Mbps
ICC2 13.1 16 mA

(1) VCCI = Input-side VCC

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7.11 Electrical Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA; see Figure 13 VCCO (1) – 0.3 3.2 V
VOL Low-level output voltage IOL = 2 mA; see Figure 13 0.1 0.3 V
VIT+(IN) Rising input voltage threshold 0.6 × VCCI 0.7 × VCCI V
VIT-(IN) Falling input voltage threshold 0.3 × VCCI 0.4 × VCCI V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI 0.2 × VCCI V
IIH High-level input current VIH = VCCI (1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
Common-mode transient
CMTI VI = VCCI or 0 V, VCM = 1200 V; see Figure 16 85 100 kV/μs
immunity

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

7.12 Supply Current Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO7730

EN2 = 0 V; VI = VCC1 (ISO7730); ICC1 1 1.4 mA

VI = 0 V (ISO7730 with F suffix) ICC2 0.3 0.4 mA
Supply current - disable
EN2 = 0 V; VI = 0 V (ISO7730); ICC1 4.3 6 mA
VI = VCC1 (ISO7730 with F suffix) ICC2 0.3 0.4 mA

EN2 = VCC2; VI = VCC1 (ISO7730); ICC1 1 1.4 mA

VI = 0 V (ISO7730 with F suffix) ICC2 1.6 2.5 mA
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7730); ICC1 4.3 6 mA
VI = VCC1 (ISO7730 with F suffix) ICC2 1.8 2.7 mA
ICC1 2.6 3.7 mA
1 Mbps
ICC2 1.8 2.8 mA

EN2 = VCCI; All channels switching with ICC1 2.7 3.8 mA

Supply current - AC signal 10 Mbps
square wave clock input; CL = 15 pF ICC2 2.8 3.9 mA
ICC1 3.3 4.3 mA
100 Mbps
ICC2 13 17 mA
ISO7731

EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731); ICC1 0.8 1.2 mA

VI = 0 V (ISO7731 with F suffix) ICC2 0.7 1 mA
Supply current - disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7731); ICC1 3 4.3 mA
VI = VCCI (ISO7731 with F suffix) ICC2 1.8 2.6 mA

EN1 = EN2 = VCCI; VI = VCCI (ISO7731); ICC1 1.3 1.7 mA

VI = 0 V (ISO7731 with F suffix) ICC2 1.6 2.2 mA
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7731); ICC1 3.5 5 mA
VI = VCCI (ISO7731 with F suffix) ICC2 2.8 4.1 mA
ICC1 2.4 3.4 mA
1 Mbps
ICC2 2.2 3.3 mA

EN1 = EN2 = VCCI; All channels switching ICC1 2.8 3.8 mA

Supply current - AC signal 10 Mbps
with square wave clock input; CL = 15 pF ICC2 2.9 4 mA
ICC1 6.7 8.5 mA
100 Mbps
ICC2 10 12.5 mA

(1) VCCI = Input-side VCC

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7.13 Electrical Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA; see Figure 13 VCCO (1) – 0.2 2.45 V
VOL Low-level output voltage IOL = 1 mA; see Figure 13 0.05 0.2 V
VIT+(IN) Rising input voltage threshold 0.6 × VCCI 0.7 × VCCI V
VIT-(IN) Falling input voltage threshold 0.3 × VCCI 0.4 × VCCI V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI 0.2 × VCCI V
IIH High-level input current VIH = VCCI (1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI = VCCI or 0 V, VCM = 1200 V; see Figure 16 85 100 kV/μs

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

7.14 Supply Current Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO7730

EN2 = 0 V; VI = VCC1 (ISO7730); ICC1 1 1.4 mA

VI = 0 V (ISO7730 with F suffix) ICC2 0.3 0.4 mA
Supply current - disable
EN2 = 0 V; VI = 0 V (ISO7730); ICC1 4.3 6 mA
VI = VCC1 (ISO7730 with F suffix) ICC2 0.3 0.4 mA

EN2 = VCC2; VI = VCC1 (ISO7730); ICC1 1 1.4 mA

VI = 0 V (ISO7730 with F suffix) ICC2 1.6 2.5 mA
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7730); ICC1 4.3 6 mA
VI = VCC1 (ISO7730 with F suffix) ICC2 1.8 2.7 mA
ICC1 2.6 3.7 mA
1 Mbps
ICC2 1.8 2.7 mA

EN2 = VCC2; All channels switching with ICC1 2.6 3.8 mA

Supply current - AC signal 10 Mbps
square wave clock input; CL = 15 pF ICC2 2.5 3.6 mA
ICC1 3.1 4.2 mA
100 Mbps
ICC2 10.2 14 mA
ISO7731

EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731); ICC1 0.8 1.2 mA

VI = 0 V (ISO7731 with F suffix) ICC2 0.7 1 mA
Supply current - disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7731); ICC1 3 4.3 mA
VI = VCCI (ISO7731 with F suffix) ICC2 1.8 2.6 mA

EN1 = EN2 = VCCI; VI = VCCI (ISO7731); ICC1 1.3 1.7 mA

VI = 0 V (ISO7731 with F suffix) ICC2 1.6 2.2 mA
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7731); ICC1 3.5 5 mA
VI = VCCI (ISO7731 with F suffix) ICC2 2.8 4.1 mA
ICC1 2.4 3.4 mA
1 Mbps
ICC2 2.2 3.2 mA

EN1 = EN2 = VCCI; All channels switching ICC1 2.7 3.7 mA

Supply current - AC signal 10 Mbps
with square wave clock input; CL = 15 pF ICC2 2.7 3.8 mA
ICC1 5.6 7 mA
100 Mbps
ICC2 8 10 mA

(1) VCCI = Input-side VCC

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7.15 Switching Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 6 11 16 ns
See Figure 13
PWD Pulse width distortion (1) |tPHL – tPLH| 0.6 4.9 ns
tsk(o) Channel-to-channel output skew time (2) Same-direction channels 4 ns
tsk(pp) Part-to-part skew time (3) 4.5 ns
tr Output signal rise time 1.3 3.9 ns
See Figure 13
tf Output signal fall time 1.4 3.9 ns
tPHZ Disable propagation delay, high-to-high impedance output 8 20 ns
tPLZ Disable propagation delay, low-to-high impedance output 8 20 ns
Enable propagation delay, high impedance-to-high output for
7 20 ns
ISO773x
tPZH
Enable propagation delay, high impedance-to-high output for See Figure 14
3 8.5 μs
ISO773x with F suffix
Enable propagation delay, high impedance-to-low output for ISO773x 3 8.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO773x
7 20 ns
with F suffix
Measured from the time VCC
tDO Default output delay time from input power loss 0.1 0.3 μs
goes below 1.7 V. See Figure 15
tie Time interval error 16 0.6 ns
2 – 1 PRBS data at 100 Mbps

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

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7.16 Switching Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 6 11 16 ns
See Figure 13
PWD Pulse width distortion (1) |tPHL – tPLH| 0.1 5 ns
tsk(o) Channel-to-channel output skew time (2) Same-direction channels 4.1 ns
tsk(pp) Part-to-part skew time (3) 4.5 ns
tr Output signal rise time 1.3 3 ns
See Figure 13
tf Output signal fall time 1.3 3 ns
tPHZ Disable propagation delay, high-to-high impedance output 17 30 ns
tPLZ Disable propagation delay, low-to-high impedance output 17 30 ns
Enable propagation delay, high impedance-to-high output for
17 30 ns
ISO773x
tPZH
Enable propagation delay, high impedance-to-high output for See Figure 14 3.2 8.5 μs
ISO773x with F suffix
Enable propagation delay, high impedance-to-low output for
3.2 8.5 μs
ISO773x
tPZL
Enable propagation delay, high impedance-to-low output for
17 30 ns
ISO773x with F suffix
Measured from the time VCC
tDO Default output delay time from input power loss 0.1 0.3 μs
goes below 1.7 V. See Figure 15
tie Time interval error 16 0.6 ns
2 – 1 PRBS data at 100 Mbps

(1) Also known as Pulse Skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

7.17 Switching Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 7.5 12 18.5 ns
See Figure 13
PWD Pulse width distortion (1) |tPHL – tPLH| 0.2 5.1 ns
tsk(o) Channel-to-channel output skew time (2) Same-direction Channels 4.1 ns
tsk(pp) Part-to-part skew time (3) 4.6 ns
tr Output signal rise time 1 3.5 ns
See Figure 13
tf Output signal fall time 1 3.5 ns
tPHZ Disable propagation delay, high-to-high impedance output 22 40 ns
tPLZ Disable propagation delay, low-to-high impedance output 22 40 ns
Enable propagation delay, high impedance-to-high output for
18 40 ns
ISO773x
tPZH
Enable propagation delay, high impedance-to-high output for See Figure 14 3.3 8.5 μs
ISO773x with F suffix
Enable propagation delay, high impedance-to-low output for
3.3 8.5 μs
ISO773x
tPZL
Enable propagation delay, high impedance-to-low output for
18 40 ns
ISO773x with F suffix
Measured from the time VCC goes
tDO Default output delay time from input power loss 0.1 0.3 μs
below 1.7 V. See Figure 15
tie Time interval error 16 0.6 ns
2 – 1 PRBS data at 100 Mbps

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

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7.18 Insulation Characteristics Curves

600 450
VCC1 = VCC2 = 2.75 V VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V 400 VCC1 = VCC2 = 3.6 V
500 VCC1 = VCC2 = 5.5 V VCC1 = VCC2 = 5.5 V

Safety Limiting Current (mA)

Safety Limiting Current (mA)

350

400 300

250
300
200

200 150

100
100
50

0 0
0 50 100 150 200 0 50 100 150 200
Ambient Temperature (qC) D001
Ambient Temperature (qC) D002

Figure 1. Thermal Derating Curve for Safety Limiting Figure 2. Thermal Derating Curve for Safety Limiting
Current per VDE for DW-16 Package Current per VDE for DBQ-16 Package
1800 1400

1600
1200
Safety Limiting Power (mW)

Safety Limiting Power (mW)

1400
1000
1200

1000 800

800 600
600
400
400
200
200

0 0
0 50 100 150 200 0 50 100 150 200
Ambient Temperature (qC) D003
Ambient Temperature (qC) D004

Figure 3. Thermal Derating Curve for Safety Limiting Power Figure 4. Thermal Derating Curve for Safety Limiting Power
per VDE for DW-16 Package per VDE for DBQ-16 Package

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7.19 Typical Characteristics

20 7
ICC1 at 2.5 V ICC1 at 2.5 V
18 ICC2 at 2.5 V ICC2 at 2.5 V
ICC1 at 3.3 V 6 ICC1 at 3.3 V
16
ICC2 at 3.3 V ICC2 at 3.3 V
Supply Current (mA)

Supply Current (mA)

14 ICC1 at 5 V ICC1 at 5 V
ICC2 at 5 V 5 ICC2 at 5 V
12
10 4
8
3
6
4
2
2
0 1
0 25 50 75 100 1 26 51 76 100
Data Rate (Mbps) D005
Data Rate (Mbps) D006
TA = 25°C CL = 15 pF TA = 25°C CL = No Load

Figure 5. ISO7730 Supply Current vs Data Rate Figure 6. ISO7730 Supply Current vs Data Rate
(With 15-pF Load) (With No Load)
14 6
ICC1 at 2.5 V
12 ICC2 at 2.5 V
ICC1 at 3.3 V 5
ICC2 at 3.3 V
Supply Current (mA)

Supply Current (mA)

10 ICC1 at 5 V
ICC2 at 5 V 4
8
3
6
2 ICC1 at 2.5 V
4 ICC2 at 2.5 V
ICC1 at 3.3 V
1 ICC2 at 3.3 V
2 ICC1 at 5 V
ICC2 at 5 V
0 0
0 25 50 75 100 0 25 50 75 100
Data Rate (Mbps) D007
Data Rate (Mbps) D008
TA = 25°C CL = 15 pF TA = 25°C CL = No Load

Figure 7. ISO7731 Supply Current vs Data Rate Figure 8. ISO7731 Supply Current vs Data Rate
(With 15-pF Load) (With No Load)
6 0.9

0.8
5
High-Level Output Voltage (V)

Low-Level Output Voltage (V)

0.7

4 0.6

0.5
3
0.4

2 0.3

0.2
1 VCC at 2.5 V VCC at 2.5 V
VCC at 3.3 V 0.1 VCC at 3.3 V
VCC at 5 V VCC at 5 V
0 0
-15 -10 -5 0 0 5 10 15
High-Level Output Current (mA) D011
Low-Level Output Current (mA) D012
TA = 25°C TA = 25°C

Figure 9. High-Level Output Voltage vs High-level Figure 10. Low-Level Output Voltage vs Low-Level
Output Current Output Current

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Typical Characteristics (continued)

2.10 14
2.05
Power Supply UVLO Threshold (V)

13

Propagation Delay Time (ns)

2.00
1.95
12
1.90
1.85 11
1.80
10
1.75
VCC1 Rising
1.70 VCC1 Falling 9
1.65 VCC2 Rising tPLH at 2.5 V tPLH at 3.3 V tPLH at 5 V
VCC2 Falling tPHL at 2.5 V tPHL at 3.3 V tPHL at 5 V
1.60 8
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 -55 -25 5 35 65 95 125
Free-Air Temperature (qC) D009 Free-Air Temperature (qC) D010

Figure 11. Power Supply Undervoltage Threshold vs Figure 12. Propagation Delay Time vs Free-Air Temperature
Free-Air Temperature

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8 Parameter Measurement Information

VCCI

Isolation Barrier
VI 50% 50%
IN OUT
0V
tPLH tPHL
Input Generator CL
(See Note A) VI 50 VO See Note B VOH
50% 90% 50%
VO
10%
VOL
tr tf

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 13. Switching Characteristics Test Circuit and Voltage Waveforms

VCCO

VCC
RL = 1 k ±1%
Isolation Barrier

VCC / 2
VCC / 2
VI
IN OUT
0V VO 0V
tPZL tPLZ
VOH
EN 0.5 V
VO 50%
CL
VOL
See Note B
Input
Generator VI
(See Note A) 50
Isolation Barrier

VCC
VO
IN OUT
3V VCC / 2 VCC / 2
VI
0V
EN tPZH
RL = 1 k ±1% VOH
CL
See Note B 50%
Input VO 0.5 V
Generator VI
50 tPHZ 0V
(See Note A)

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A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 14. Enable/Disable Propagation Delay Time Test Circuit and Waveform

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Parameter Measurement Information (continued)

VI See Note B

VCC VCC
VI 1.7 V

Isolation Barrier
0V
IN = 0 V (Devices without suffix F) IN OUT
VO tDO
IN = VCC (Devices with suffix F)
default high
VOH
CL
See Note A VO 50%
VOL
default low

A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

B. Power Supply Ramp Rate = 10 mV/ns

Figure 15. Default Output Delay Time Test Circuit and Voltage Waveforms

VCCI VCCO

C = 0.1 µF ±1% C = 0.1 µF ±1%

Pass-fail criteria:
The output must
Isolation Barrier

remain stable.
IN OUT
S1
+

CL VOH or VOL
See Note A
±

GNDO
GNDI + VCM ±

A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 16. Common-Mode Transient Immunity Test Circuit

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9 Detailed Description

9.1 Overview
The ISO773x family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is
low then the output goes to high impedance. The ISO773x family of devices also incorporates advanced circuit
techniques to maximize the CMTI performance and minimize the radiated emissions due the high frequency
carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 17, shows a
functional block diagram of a typical channel.

9.2 Functional Block Diagram

Transmitter Receiver
EN

OOK
Modulation
TX IN SiO2 based
TX Signal Capacitive RX Signal Envelope RX OUT
Conditioning Isolation Conditioning Detection
Barrier

Emissions
Oscillator Reduction
Techniques

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Figure 17. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 18 shows a conceptual detail of how the ON-OFF keying scheme works.

TX IN

Carrier signal through

isolation barrier

RX OUT

Figure 18. On-Off Keying (OOK) Based Modulation Scheme

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9.3 Feature Description

Table 1 provides an overview of the device features.

Table 1. Device Features

MAXIMUM DATA
PART NUMBER CHANNEL DIRECTION DEFAULT OUTPUT PACKAGE RATED ISOLATION (1)
RATE
3 Forward, DW-16 5000 VRMS / 8000 VPK
ISO7730 100 Mbps High
0 Reverse DBQ-16 3000 VRMS / 4242 VPK
ISO7730 with F 3 Forward, DW-16 5000 VRMS / 8000 VPK
100 Mbps Low
suffix 0 Reverse DBQ-16 3000 VRMS / 4242 VPK
2 Forward, DW-16 5000 VRMS / 8000 VPK
ISO7731 100 Mbps High
1 Reverse DBQ-16 3000 VRMS / 4242 VPK
ISO7731 with F 2 Forward, DW-16 5000 VRMS / 8000 VPK
100 Mbps Low
suffix 1 Reverse DBQ-16 3000 VRMS / 4242 VPK
2 Forward,
ISO7731B 100 Mbps High DW-16 5000 VRMS / 8000 VPK
1 Reverse
ISO7731B with F 2 Forward,
100 Mbps Low DW-16 5000 VRMS / 8000 VPK
suffix 1 Reverse

(1) See Safety-Related Certifications for detailed isolation ratings.

9.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO773x
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

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9.4 Device Functional Modes

Table 2 lists the functional modes for the ISO773x devices.

Table 2. Function Table (1)

OUTPUT
INPUT OUTPUT
VCCI VCCO ENABLE COMMENTS
(INx) (2) (OUTx)
(ENx)
H H or open H Normal Operation:
L H or open L A channel output assumes the logic state of its input.
PU PU
Default mode: When INx is open, the corresponding channel output goes
Open H or open Default to its default logic state. Default is High for ISO773x and Low for ISO773x
with F suffix.
X PU X L Z A low value of Output Enable causes the outputs to be high-impedance
Default mode: When VCCI is unpowered, a channel output assumes the
logic state based on the selected default option. Default is High for
ISO773x and Low for ISO773x with F suffix.
PD PU X H or open Default When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined (3).
X PD X X Undetermined When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input

(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.

9.4.1 Device I/O Schematics

Input (Devices without F suffix) Input (Devices with F suffix)

VCCI VCCI VCCI VCCI VCCI VCCI VCCI

1.5 M

985 985
INx INx

1.5 M

Output Enable
VCCO
VCCO VCCO VCCO VCCO

2M
~20 1970
OUTx ENx

Copyright © 2016, Texas Instruments Incorporated

Figure 19. Device I/O Schematics

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ISO773x devices are high-performance, triple-channel digital isolators. These devices come with enable pins
on each side which can be used to put the respective outputs in high impedance for multi-master driving
applications and reduce power consumption. The ISO773x family of devices use single-ended CMOS-logic
switching technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When
designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators
do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL
digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data
converter or a line transceiver, regardless of the interface type or standard.

10.2 Typical Application

The ISO7731 device, combined with Texas Instruments' mixed-signal microcontroller, RS-485 transceiver,
transformer driver, and voltage regulator, can create an isolated RS-485 system as shown in Figure 20.
VIN

3.3V 0.1 F
2 1:2.2 MBR0520L
1 5VISO
Vcc D2 3 IN OUT
5

TPS76350
SN6501 10 F 0.1 F 3 2 10 F
1 EN GND
GND D1
10 F MBR0520L
4,5

ISO-BARRIER

0.1 F 0.1 F
0.1 F
0.1 F
1 16
2
VCC1 VCC2
DVcc 11 3 14 VCC
5 P3.0 INA OUTA RE 10 MELF
XOUT ISO7731 13 2 B
MSP430 UCA0TXD 15 4
INB OUTB DE
6 F2132 3 SN65HVD 10 MELF
XIN 16 5 12 D 3082E A
UCA0RXD OUTC INC 4
DVss 7 EN1 EN2 10 R GND
1 SM712
4 GND1 GND2
2,8 9,15

4.7nF/
2kV

Copyright © 2016, Texas Instruments Incorporated

Figure 20. Isolated RS-485 Interface Circuit

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Typical Application (continued)

10.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.

Table 3. Design Parameters

PARAMETER VALUE
Supply voltage, VCC1 and VCC2 2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1 0.1 µF
Decoupling capacitor from VCC2 and GND2 0.1 µF

10.2.2 Detailed Design Procedure

Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO773x family of devices only requires two external bypass capacitors to operate. Figure 21 and Figure 22
show the typical circuit hook-up for the devices.
2 mm maximum 2 mm maximum
from VCC1 from VCC2

0.1 µF 0.1 µF
VCC1 VCC2
1 16

GND1 GND2
2 15

INA 3 14 OUTA

INB 4 13 OUTB

INC 5 12 OUTC

NC NC
6 11

NC EN
7 10

GND1 GND2
8 9

Figure 21. Typical ISO7730 Circuit Hook-Up

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2 mm maximum 2 mm maximum
from VCC1 from VCC2

0.1 µF 0.1 µF
VCC1 VCC2
1 16

GND1 GND2
2 15

INA 3 14 OUTA

INB 4 13 OUTB

OUTC 5 12 INC

NC NC
6 11

EN1 EN2
7 10

GND1 GND2
8 9

Figure 22. Typical ISO7731 Circuit Hook-Up

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10.2.3 Application Curves

The following typical eye diagrams of the ISO773x family of devices indicate low jitter and wide open eye at the
maximum data rate of 100 Mbps.

Ch4 = 1 V / div
Ch4 = 1 V / div

Time = 2.5 ns / div Time = 2.5 ns / div

Figure 23. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and Figure 24. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V
25°C and 25°C
Ch4 = 500 mV / div

Time = 2.5 ns / div

Figure 25. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C

10.2.3.1 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 26 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 27 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 135 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1500 VRMS and DBQ-16 package up to 400
VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 135 years.

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A
Vcc 1 Vcc 2

Time Counter

DUT > 1 mA

GND 1 GND 2
VS

Oven at 150 °C

Figure 26. Test Setup for Insulation Lifetime Measurement

Figure 27. Insulation Lifetime Projection Data

11 Power Supply Recommendations

To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505A. For such applications, detailed power supply design and transformer selection recommendations are
available in the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505A Low-Noise 1-A
Transformer Drivers for Isolated Power Supplies (SLLSEP9).

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12 Layout

12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 28). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.

12.1.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.

12.2 Layout Example

High-speed traces
10 mils
Ground plane
Keep this
space free FR-4
40 mils from planes, 0r ~ 4.5
traces, pads,
and vias
Power plane
10 mils
Low-speed traces
Figure 28. Layout Example Schematic

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SNx5HVD308xE Low-Power RS-485 Transceivers, Available in a Small MSOP-8
Package data sheet
• Texas Instruments, TPS76350 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
• Texas Instruments, MSP430F2132 Mixed Signal Microcontroller data sheet

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 4. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
ISO7730 Click here Click here Click here Click here Click here
ISO7731 Click here Click here Click here Click here Click here

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

13.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [ 0.11 -0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

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EXAMPLE BOARD LAYOUT

DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
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EXAMPLE STENCIL DESIGN

DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO7730DBQ ACTIVE SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7730

ISO7730DBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7730

ISO7730DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7730

ISO7730DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7730

ISO7730FDBQ ACTIVE SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7730F

ISO7730FDBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7730F

ISO7730FDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7730F

ISO7730FDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7730F

ISO7731BDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731B

ISO7731BDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731B

ISO7731DBQ ACTIVE SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7731

ISO7731DBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7731

ISO7731DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731

ISO7731DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731

ISO7731FBDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731FB

ISO7731FBDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731FB

ISO7731FDBQ ACTIVE SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7731F

ISO7731FDBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7731F

ISO7731FDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731F

ISO7731FDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7731F

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ISO7730, ISO7731 :

• Automotive: ISO7730-Q1, ISO7731-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7730DBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7730DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7730DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7730DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7730FDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7730FDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7730FDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7730FDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731BDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731BDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731BDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731DBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7731DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731FBDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2022

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7731FBDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731FBDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731FDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7731FDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731FDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7731FDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7730DBQR SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7730DWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7730DWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7730DWR SOIC DW 16 2000 350.0 350.0 43.0
ISO7730FDBQR SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7730FDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7730FDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7730FDWR SOIC DW 16 2000 350.0 350.0 43.0
ISO7731BDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7731BDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7731BDWR SOIC DW 16 2000 350.0 350.0 43.0
ISO7731DBQR SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7731DWR SOIC DW 16 2000 356.0 356.0 35.0
ISO7731DWR SOIC DW 16 2000 356.0 356.0 35.0
ISO7731DWR SOIC DW 16 2000 350.0 350.0 43.0
ISO7731FBDWR SOIC DW 16 2000 350.0 350.0 43.0
ISO7731FBDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7731FBDWR SOIC DW 16 2000 367.0 367.0 38.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2022

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7731FDBQR SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7731FDWR SOIC DW 16 2000 350.0 350.0 43.0
ISO7731FDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7731FDWR SOIC DW 16 2000 367.0 367.0 38.0

Pack Materials-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ISO7730DBQ DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7730DW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7730DW DW SOIC 16 40 507 12.83 5080 6.6
ISO7730FDBQ DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7730FDW DW SOIC 16 40 507 12.83 5080 6.6
ISO7730FDW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7731BDW DW SOIC 16 40 507 12.83 5080 6.6
ISO7731BDW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7731DBQ DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7731DW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7731DW DW SOIC 16 40 507 12.83 5080 6.6
ISO7731FBDW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7731FBDW DW SOIC 16 40 507 12.83 5080 6.6
ISO7731FDBQ DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7731FDW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7731FDW DW SOIC 16 40 507 12.83 5080 6.6

Pack Materials-Page 5
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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