Finite State Machine

Mr. Shridhar S. Dudam

FPGA Tech Solutions

[email protected]
7745024542
 Introduction
• A state machine is a representation of a digital system
that transverse through a predefined sequences of states
in an orderly fashion.
• State machine takes decisions depending on the history
of inputs.
– A memory element is required to remember the past inputs,
– In hardware the memory element is generally a flip-flop.
• Also called as FSM: Because it is a sequential circuit,
Which transit through a set of well defined states finite
in number in response to finite number of inputs, in
synchronous or asynchronous manner and generates
finite number of outputs.
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 Mealy Machines
• Output is function of both inputs and present states.
• The output function is very complex, but there is more
flexibility to design.

I/Ps A Memory O/Ps Y

Next State S Output
Function  Function 
Next Present
State State

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 Example : Mealy FSM
• Detect 3 or more consecutive 1’s

0/0 1/0
S0 S1
0/0

0/0 1/0
0/0

S3 S2
1/1 1/0
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 Moore Machines
• Output is function of present state only. This makes
output function very simple.
• Since in Moore machine output is depends on present
state, every output combination will require a
corresponding state.
• The Moore machine might require more number of
states as compared to Mealy machine.

I/Ps A Memory O/Ps Y

Next State Output
S
Function  Function 
Next Present
State State

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 Example : Moore FSM
• Detect 3 or more consecutive 1’s x = 0 0 1 1 1 0 1 1 1 1.....
y = 0 0 0 0 1 0 0 0 1 1 (ove
y = 0 0 0 0 1 0 0 0 1 0 (No
0 1
S0 / 0 S1 / 0
0

0 1
0

S3 / 1 S2 / 0
1 1
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 Building Blocks of FSM (1)
• Combinational Next State Logic:
– An FSM can only be in one state at any given
time, and each active transition of the clock
causes it to change from its current state to the
next state, as defined by the next state logic.
– The next state is a function of the FSM’s inputs
and its current state.

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 Building Blocks of FSM (2)
• Sequential Current State Register:
– The register, a set of n-bit flip-flops (state vector flip-
flops) clocked by a single clock signal is used to hold
the state vector (current state or simply state) of the
FSM.
– A state vector with a length of n-bit has 2^n possible
binary patterns, known as state encoding. Often, not
all 2^n patterns are needed, so the unused ones should
be designed not to occur during normal operation.
– Alternatively, an FSM with m-state requires at least
log2 (m) state vector flip-flops.
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 Building Blocks of FSM (3)
• Combinational Output Logic:
– Outputs are normally a function of the current
state and possibly the FSM’s primary inputs (in
the case of a Mealy FSM).
– Often in a Moore FSM, you may want to
derive the outputs from the next state instead of
the current state, when the outputs are
registered for faster clock-to-out timings.

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 Encoding styles in FSM
• State assignment is a process of assigning binary values to
states in such a way, so as to reduce the combinational circuit
that drives the flip-flops.
• It does not affect the function of state machine, hence can be
selected by synthesis tool.
• But the way you encode the state can have a major effect on
the amount of hardware you need to implement machine.
• A poor choice of codes results in a state machine that uses
too much logic, or is too slow, or both.
• There are three most common encoding styles for FSM.
– Binary encoding
– Gray encoding
– One hot encoding 11
 Binary encoding style
• For m states it requires log 2 m flip-flops are required.
• It keeps number of registers to minimum but increases
amount of combinational logic as more logic is required
to decode each state.
• Normally used for gate rich logic i.e. CPLD’s.

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 Gray encoding style
• Only one bit in state vector changes value when the state
machine changes state.
• This is essential when outputs are combinational &
outputs drive asynchronous control signals.
• Since more than one bit can be ‘hot’ the value must be
decoded to determine the state.

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 One-Hot encoding style
• One flip-flop for every state.
• N bit state vector is used for N states. Only one bit of
state vector is ‘hot’ for any given state.
• Efficient for FPGA application.
• Minimum combinational logic is required.
• One hot state machine is typically faster. Speed is
independent of the number of state, and only depend on
only transition in particular state.
• Critical path are easy to find out.
• Also Easy to debug.

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 Guidelines for writing FSM in HDL
• Only one state machine per module:
– This will keep you in applying specialized techniques for FSM
optimization.
• Keep minimum extraneous logic:
– This helps in optimization of the state machine.
• Separate out any structured logic:
– e.g. muxes, counters etc. from the state machine. Ideally only random logic
should be included.
• Make your state machine completely synchronous:
– Asynchronous FSM need extra care when they are designed.
• Choose an optimum encoding for the state vector.
• To improve design performance, Divide large state machines into
several small state machines and use the appropriate encoding
style for each.
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 Mathematical Representation
• A FSM is defined as quintuple:
M = (A, S, Y, , )
• Where,
– A : Finite, non empty set of input symbols a1, a2, ….an
– S : Finite, non empty set of states S1, S2, …Sn
– Y : Finite, non empty set of output symbols Y1, Y2, …. Yn
–  : Next state function :  function of S & A
–  : Output function :  depends of only on S or both S & A

I/Ps A Memory O/Ps Z

Next State Output
Function  S Function 
Next Present
State State

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 Specifying FSM in Verilog
• To specify a FSM fully we have to completely define the
quintuple: M = (A, S, Y, , )
• Specification of A and Y is with the Module declaration
• The set of states is generally defined as the parameter
– parameter S0 = 0, S1 = 1, S2 = 2;
• A state vector is created to take the state values:
– reg present_state, next_state;
• The Next state function and Output function are specified in the
architecture in different ways.
• There are three primary methods of writing architecture for FSM
coding
– Single Block coding (Single always procedural block)
– Two Block coding (Two always procedural block)
– Three Block coding (Three always procedural block)
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 Parameters
• Declare runtime constant.
– parameter p1 = 8, real_constant = 2.309 ;
• Parameters are local to a module.
• Used to configure design values
• defparam : override parameter value
– Specify the complete hierarchy
• New value within module instance using #.
– Multiple parameter order same as declared in module
– Not necessary to assign new values to all parameters
– cannot skip over a parameter

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 Example
module adder (cout, sum, a, b, cin);
parameter width = 8 ;
output cout ;
output [width-1:0] sum ;
input cin ;
input [width-1:0] a,b ;
assign {cout, sum} = a + b + cin ;
endmodule

module top ();

adder #(16) adder_16bit(.cout(cout), .sum(sum), .a(a), .b(b), .cin(cin)) ;
defparam top.A1.width = 16 ;
adder A1(.cout(cout), .sum(sum), .a(a), .b(b), .cin(cin)) ;
endmodule

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 Single Block coding
• In this style, only one always block is used, and both the
outputs and next state decoder are specified in it.
• This is the easiest way of writing FSM. This description
is very close to the way we think.
• Advantages
– The outputs are registered.
– As next state and the outputs are described in the same process,
understanding and debugging easy.
– Output is glitch free.
• Disadvantages
– This method generates more hardware as compared to other
two coding styles.
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 Two Block coding (1)
• One always block to generate the output function and
next state function.
• The other always block to synchronize next state
assignments with the clock.
• In this coding style every output has to be specified
under every condition.
• If there is a case where a particular signal is not
specified, the circuit tries to remember the previous
value, which results in latch inference. This makes it
difficult for coding, debugging and understanding.

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 Two Block coding (2)
• Advantages
– The amount of logic is less compared to the previous case.
– The tool vendors recommend this method because
combinational logic is available together for optimization.

• Disadvantages
– Outputs are combinational.
– The output logic will add to delays in the input circuit of the
next stage that uses these outputs.

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 Three Block Coding
• In this coding style three Always Blocks are used
– For FSM registers.
– For combinational block (next state decoder).
– For output decoder.
• Advantages
– Code is very readable
– Generates less hardware as compare to other coding styles.
• Disadvantages
– Output is combinational.
– Output is not glitch free.

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 Example : Moore FSM
• To detect a pair of 1's or 0's in the single bit input
– Input will be a series of one's and zero's. If two one's or two
zero's comes one after another, output should go high.
Otherwise output should be low.

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 Example : Mealy FSM
• To detect a pair of 1's or 0's in the single bit input
– Input will be a series of one's and zero's. If two one's or two
zero's comes one after another, output should go high.
Otherwise output should be low.

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 Assignments
• Implement Simple Traffic Light Controller
• Implement Gray counter which has out as follows
– 000 001 011 010 110 111 101 100
• Implement FSM to detect “101” overlapping sequence.

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THANKS