ts5a3154
ts5a3154
1FEATURES APPLICATIONS
•
2 Specified Make-Before-Break Switching • Cell Phones
• Low ON-State Resistance (0.9 Ω) • PDAs
• Control Inputs Are 5.5-V Tolerant • Portable Instrumentation
• Low Charge Injection • Audio and Video Signal Routing
• Excellent ON-State Resistance Matching • Low-Voltage Data-Acquisition Systems
• Low Total Harmonic Distortion (THD) • Communication Circuits
• 1.65-V to 5.5-V Single-Supply Operation • Modems
• Latch-Up Performance Exceeds 100 mA Per • Hard Drives
JESD 78, Class II • Computer Peripherals
• ESD Performance Tested Per JESD 22 • Wireless Terminals and Peripherals
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Logic
COM 1 8 V+ GND D1 4 5 D2 IN
Control
EN 2 7 NC GND C1 3 6 C2 NO
GND 3 6 NO EN B1 2 7 B2 NC
Logic
GND 4 5 IN COM A1 1 8 A2 V+
Control
DESCRIPTION/ORDERING INFORMATION
The TS5A3154 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 1.65 V to
5.5 V. The device offers a low ON-state resistance and an excellent channel-to-channel ON-state resistance
matching. The device has excellent total harmonic distortion (THD) performance and consumes very low power.
These features make this device suitable for portable audio applications.
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TS5A3154
(1) V+ = 5 V, TA = 25°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
(4) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(5) This value is limited to 5.5 V maximum.
(6) Pulse at 1-ms duration < 10% duty cycle.
(7) The package thermal impedance is calculated in accordance with JESD 51-7.
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
TYPICAL PERFORMANCE
TA = 25°C
ron (Ω)
ron (Ω)
TA = 85°C
TA = 25°C
TA = –40°C
TA = 85°C
TA = 25°C
TA = –40°C
TA (°C)
Figure 3. ron vs VCOM (V+ = 5 V) Figure 4. Leakage Current vs Temperature
(V+ = 5.5 V)
Figure 5. Charge Injection (QC) vs VCOM Figure 6. tON and tOFF vs Supply Voltage
TA (°C)
Figure 7. tON and tOFF vs Temperature (V+ = 5 V) Figure 8. Logic-Level Threshold vs V+
Figure 9. Bandwidth (V+ = 5 V) Figure 10. OFF Isolation and Crosstalk (V+ = 5 V)
TA (ºC)
Figure 11. Total Harmonic Distortion (THD) Figure 12. Power Supply Current vs Temperature
vs Frequency (V+ = 5 V)
PIN DESCRIPTION
PIN NO. NAME DESCRIPTION
1 COM Common
2 EN Enable control input
3 GND Digital ground
4 GND Digital ground
5 IN Digital control to connect the COM to NO or NC
6 NO Normally open
7 NC Normally closed
8 V+ Power supply
PARAMETER DESCRIPTION
SYMBOL DESCRIPTION
VCOM Voltage at COM
VNC Voltage at NC
VNO Voltage at NO
ron Resistance between COM and NC or COM and NO ports when the channel is ON
Δron Difference of ron between channels in a specific device
ron(flat) Difference between the maximum and minimum value of ron in a channel over the specified range of conditions
INC(OFF) Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the OFF state
INO(OFF) Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the OFF state
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the ON state and the output
INC(ON)
(COM) open
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the ON state and the output
INO(ON)
(COM) open
Leakage current measured at the COM port, with the corresponding channel (COM to NO or COM to NC) in the ON state and
ICOM(ON)
the output (NC or NO) open
VIH Minimum input voltage for logic high for the control input (IN)
VIL Maximum input voltage for logic low for the control input (IN)
VI Voltage at the control input (IN)
IIH, IIL Leakage current measured at the control input (IN)
Turn-on time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay
tON
between the digital control (IN) signal and analog output (COM, NC, or NO) signal when the switch is turning ON.
Turn-off time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay
tOFF
between the digital control (IN) signal and analog output (COM, NC, or NO) signal when the switch is turning OFF.
Break-before-make time. This parameter is measured under the specified range of conditions and by the propagation delay
tBBM
between the output of two adjacent analog channels (NC and NO) when the control signal changes state.
Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (NC, NO, or COM)
QC output. This is measured in coulomb (C) and measured by the total charge induced due to switching of the control input.
Charge injection, QC = CL × ΔVCOM, CL is the load capacitance and ΔVCOM is the change in analog output voltage.
CNC(OFF) Capacitance at the NC port when the corresponding channel (NC to COM) is OFF
CNO(OFF) Capacitance at the NO port when the corresponding channel (NO to COM) is OFF
CNC(ON) Capacitance at the NC port when the corresponding channel (NC to COM) is ON
CNO(ON) Capacitance at the NO port when the corresponding channel (NO to COM) is ON
CCOM(ON) Capacitance at the COM port when the corresponding channel (COM to NC or COM to NO) is ON
CI Capacitance of control input (IN)
OFF isolation of the switch is a measurement of OFF-state switch impedance. This is measured in dB in a specific frequency,
OISO
with the corresponding channel (NC to COM or NO to COM) in the OFF state.
Crosstalk is a measurement of unwanted signal coupling from an ON channel to an OFF channel (NC to NO or NO to NC).
XTALK
This is measured in a specific frequency and in dB.
BW Bandwidth of the switch. This is the frequency where the gain of an ON channel is –3 dB below the DC gain.
Total harmonic distortion describes the signal distortion caused by the analog switch. This is defined as the ratio of root mean
THD
square (RMS) value of the second, third, and higher harmonic to the absolute magnitude of fundamental harmonic.
V+
VNC NC
COM VCOM
+
VNO NO Channel ON
VCOM * VNO or VNC
r on + W
IN or EN I COM
VI ICOM
VI = VIH or VIL
+
GND
V+
VNC NC
COM VCOM
+
VNO NO + OFF-State Leakage Current
Channel OFF
VI = VIH or VIL
IN or EN
VI
+
GND
VNC NC
COM
+ VCOM
VNO NO
ON-State Leakage Current
Channel ON
IN or EN VI = VIH or VIL
VI
+
GND
V+
VNC NC
Capacitance
Meter VBIAS = V+ or GND
VNO NO
VI = VIH or VIL
VCOM COM
VBIAS Capacitance is measured at NC,
VI NO, COM, and IN inputs during
ON and OFF conditions.
IN or EN
GND
Figure 16. Capacitance (CI, CCOM(OFF), CCOM(ON), CNC(OFF), CNO(OFF), CNC(ON), CNO(ON))
V+
TEST RL CL VCOM
VCOM COM
NC or NO CL(2) RL tOFF 50 Ω 35 pF V+
IN or EN
Logic V+
VI
Input 50% 50%
Logic (VI) 0
GND
Input(1) tON tOFF
Switch
Output 90% 90%
(VNC or VNO)
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
(2) CL includes probe and jig capacitance.
Logic V+
NC VNC Input 50%
(VI) 0
VCOM COM
NO VNO CL(2) RL
VNC
0.8 VOUT
Switch
IN or EN
Output 0.8 VOUT
VI
CL(2) RL VNO
Logic
GND
Input(1) VCOM = V+ tMBB
RL = 50 Ω
CL = 35 pF
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
(2) CL includes probe and jig capacitance.
V+
Network Analyzer
V+
Network Analyzer
V+
Network Analyzer
Channel ON: NC to COM
50 W VNC NC Channel OFF: NO to COM
VCOM VI = V+ or GND
Source
VNO NO
Signal
IN or EN 50 W Network Analyzer Setup
VI
50 W + Source Power = 0 dBm
GND (632-mV P-P at 50-W load)
DC Bias = 350 mV
V+ Logic VIH
Input
OFF ON OFF V
(VI) IL
RGEN
NC or NO
COM VCOM
+ VCOM ∆VCOM
VGEN NC or NO
CL(2)
IN or EN VGEN = 0 to V+
VI
RGEN = 0
CL = 0.1 nF
Logic
Input(1) GND QC = CL × ∆VCOM
VI = VIH or VIL
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
(2) CL includes probe and jig capacitance.
REVISION HISTORY
www.ti.com 30-Aug-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TS5A3154DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (CF, JCFQ, JCFR)
JZ
TS5A3154DCURE6 PREVIEW VSSOP DCU 8 3000 TBD Call TI Call TI -40 to 85
TS5A3154DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 JCFR
TS5A3154YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 JXN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 30-Aug-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
DCU0008A SCALE 6.000
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
3.2
TYP C
3.0
A
0.1 C
PIN 1 INDEX AREA SEATING
6X 0.5 PLANE
8
1
2X
2.1
1.5
1.9
NOTE 3
4
5
0.25
8X
0.17
2.4
B 0.08 C A B
2.2
NOTE 3
SEE DETAIL A
0.12 0.9
GAGE PLANE 0.6
0.1
0 -6 0.35 0.0
(0.13) TYP
0.20
DETAIL A
A 30
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
www.ti.com
EXAMPLE BOARD LAYOUT
DCU0008A VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
(R0.05) TYP
8X (0.3) 1 8
SYMM
6X (0.5)
4 5
(3.1)
4225266/A 09/2014
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DCU0008A VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
(R0.05) TYP
8X (0.3) 1 8
SYMM
6X (0.5)
4 5
(3.1)
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0008 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
C
0.5 MAX
SEATING PLANE
0.19
0.15 0.05 C
BALL TYP
0.5 TYP
C
SYMM
1.5
TYP
D: Max = 1.918 mm, Min =1.858 mm
B
E: Max = 0.918 mm, Min =0.858 mm
0.5
TYP
A
0.25
8X 1 2
0.21
0.015 C A B
SYMM
4223082/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0008 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.23)
1 2
(0.5) TYP
B
SYMM
SYMM
( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
4223082/A 07/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0008 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.25)
(R0.05) TYP
1 2
(0.5)
TYP
B
SYMM
METAL
TYP
SYMM
4223082/A 07/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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