IJSRD - International Journal for Scientific Research & Development| Vol.

2, Issue 08, 2014 | ISSN (online): 2321-0613

Study of Low Voltage Cascode Current Mirror with Enhance Dynamic

Range
Viswas Giri1
1
M. Tech Student
1
Department of Electronics and Communication Engineering
1
Takshshila Institute of Engineering & Technology, Jabalpur
Abstract— The current mirror is one of most common
building blocks both in analog and mixed mode VLSI II. LOW VOLTAGE CURRENT MIRROR
circuits and the performance of analog structures largely The Low Voltage current mirror is the basic building block
depends on their characteristics. The current mirror can be of analog integrated circuit. Current mirror enables a single
used as an active element and as a biasing circuit. In this current source to supply mirrors are output impedance and
paper we study about the current mirror, cascode current voltage headroom. The output impedance determines the
mirror and different low voltage current mirror topology and variation of the mirrored current when the applied voltage
study the literature survey. After that we study, analysis and varies. Higher output impedance implies less current
design of convention Level shifted low voltage current variation with applied voltage and hence a more stable
mirror and TSPICE simulation technology. Presented current source Voltage headroom specifies how much
analysis low voltage current mirror input –output voltage drop across the current mirror is required ton operate
characteristic, high output swing capability and wide input - the current mirror reliably. This is important for low voltage
output swing capabilities, suitable for low voltage operation circuit design [2].
and minimum power dissipation.
Key words: simple current mirror, Low voltage current
mirror, level shifted Current mirror, Level shifted low
voltage current mirror, Dynamic range.

I. INTRODUCTION
Now a day, microelectronics (VLSI) is dominant in every
sphere of electronics and communications forming the
backbone of modern electronics industry in mobile
communications, computers, state-of-art processors etc. So
the portable electronics has made low power circuit design
extremely desirable. All efforts eventually converge on
Fig. 1: Low Voltage Current Mirror
decreasing the power consumption entailed by ever Low voltage cascode current shown in Figure 1.
compacted size of the circuits enabling the portable gadgets. We assume that the current mirror transistors (M1)
Reducing the power supply voltage is a straightforward
and (M2) have identical. Accept ratio, Where
method to achieve low power consumption. The low power
and low voltage CMOS techniques were applied extensively ‘W1’ and ‘W2’ are showing the transistor channel width and
in analog and mixed mode circuits for the compatibility with L1 and L2 are the transistor length. Similarly the transistor
(M3) and (M4) are assumed the same aspect ratio
the present IC technologies. Designing high – performance
analog circuits is becoming increasingly challenging with
the persistent trend towards reduced supply voltages. The
The aspect ratio Am may be different from the
current mirror (CM) is one of the most basic building blocks
aspect ratio Ac. The partition of the dynamic range the same
both in analog and mixed mode VLSI circuits especially for
aspect ratio of Am and Ac and we use standard Schman –
active elements like op-amps, current conveyors, current Hodges transistor model for the transistor in the saturation
feedback amplifiers etc. At large supply voltages, there is an region and we neglected the bulk effect and assume that all
exchange speed, power and gain. The main characteristics the NMOS transistors have the identical. Low voltage
under consideration are power, voltage, dynamic range, current mirror input current Iin we find the gate- source
bandwidth, low offset voltage, high output voltage swing. voltages and drain -source voltages [3]
The desire for portability of the electronic equipment
generated a need for low power systems in battery operated √ .................. (1)
products like hearing aids and implantable cardiac Gate to source voltage of transistor (M3).
pacemakers and cell phones and hand held multimedia
√ ........................ ( 2)
terminals. Low power dissipation is attractive, and perhaps
even essential in these applications to have reasonable Drain to source voltage of transistor ((M1)) is
battery life and weight. The main objective of design is
√ ........................(3)
close to having battery- less systems, because the battery
contributes greatly to volume and weight. Drain to source voltage of transistor ((M3) )is

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 Study of Low Voltage Cascode Current Mirror with Enhance Dynamic Range
(IJSRD/Vol. 2/Issue 08/2014/034)

have as large an effective gate-source voltage as possible in

√ ...................... (4) order to minimize the effect of threshold voltage
√ √
Where, (Vtn) is the transistor threshold voltage, dissimilarity. This obvious that the effective gate source
(VBC) is the bias or gate voltage of transistor (M3), (M4) and voltage VGs1 -Vtn can be increase the value of above given
K is the transconductance parameter. Requiring by equation (15) if Ac is increased, i.e. a larger aspect ratio
for both (M1) and (M3) result in : is used for the cascade transistor. This case the( cascode
transistor) requires a smaller effective gate-source voltage
√ ( ) .......... (5) for a given value of input current and leaving more
√ √
headroom for the drain source voltage of the mirror
Biasing voltage √ ------------- (6) transistor. Introducing
In Figure 1 low voltage current mirror, biasing N= AC /AM we find
voltage VB is fixed when Iin increases, voltage of the gate – .......... (14) And
source voltage VGS3 of transistor (M3) and Vin will increase,
and voltage level at the drain terminal of (M1) decrease. √ ............ (15)
There by (M1) enter the triode region which determine the The (small signal) output resistance of the mirror is
upper limit of Iin.below equation (7) ensure the saturation given by:-
(M1) and determine the maximum value of Iin for given
value of the cascade bias voltage VB we find ( )
√ As is inversely proportional to the square
root of (AC) .we find that the output resistance is inversely
√ proportional to (N). Thus, the higher effective gate-source
Equations (7) ensure the saturation of (M3) and voltage of the mirror transistors is achieved at the expense
determine the minimum value of Iin we find of a reduced output resistance

III. LEVEL SHIFTED CURRENT MIRROR

the value of AC and AM which determined the saturation of Shown in figure 2 level shifted current mirror, the simple
(M1) and the maximum value of input current . The current mirror topology [10] requires input voltage (Vin) at
Saturation operation of transistors (M1) and (M3) the input least one Vtn and unsuitable for low voltage application.
current range determined by Level shifted current mirror operates at low voltage with the
advantage of low input output voltage requirement,
incorporates a level shifter PMOS transistor (M5) (biased
through a current Ibias1) at input port. For this structure, we
√
have
................ (17)
√
In a practical design procedure equation(8) can be
used to determine the maximum value of the bias voltage
which will ensure saturation of (M3) even at the minimum
value of input current, and equation (6) can then be used to
determine values of AC and AM which will ensure saturation
of (M1), even at the maximum value of input current. In the
important special case of Iin,minim= 0 we find from (8) VB ≤
2Vtn .From equation (7) we then find the following design
Fig. 2: Level Shifted Current Mirror
constraint on AC and AM
Where VDS1 drain to source and VGS1 gate to source
√
voltage of (M1), VGS5 is the gate to source voltage of (M5).
.......... (10)
√ A level shifted current mirror circuit structure is shown in
Figure 2 (M3) is used to shift the voltage level at the drain
Assuming as a typical case W1 = W3 and L1 = L3
terminal of (M1). Vin is a characteristics parameter of a low
i.e. identical aspect ratios for the mirror transistors and the
voltage current mirror and decides the range of input
cascode transistors, we find that
voltage swing in such circuits. The bias current (Ibias1)
.............. (11) decide the operation region of (M1). For example, low value
In this case of effective gate source voltage of the of( Ibias1) forces (M3) to operate in sub threshold region,
mirror transistors (M1), (M2) is (Ibias) high (Ibias1) ensures transistor (M5) operates the triode
region. For high value, transistor (M2) operates in saturation
√ √ ............ (12) region. Gate voltage of transistor (M1) is high
In this case the minimum output voltage of the correspondingly input current is also high. Hence Vin can be
current mirror is and is independent of the input calculated for this circuit structure if we must idea about
the values of (VGS1) and (VGS5) since (Vtp ≥ Vtn) , there is a
In a high precision current mirror one would like to main difficulty to keep the condition (

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 Study of Low Voltage Cascode Current Mirror with Enhance Dynamic Range
(IJSRD/Vol. 2/Issue 08/2014/034)

valid in a level shifter based circuit over a wide range of

(Iin1 ) . One solution of this is to use a lateral p-n-p transistor
(bjt) for level shifting, and now )
approximates as ( 0.7V) and is always more than(0.8v)
(if we assume Vtn =0.8v). As the device sizes are reducing
and ( Vt ) is also reducing and there will be a situation where
will not be valid and hence we can not be
able to use p-n-p transistor. Therefore , there is a need to
must have an alternative a p-n-p transistor and the use of a
PMOS transistor is the most obvious choice..
Fig. 3:- Proposed Level Shifted Low Voltage Cascode
IV. PROPOSED LOW VOLTAGE LEVEL SHIFTED CURRENT
Current Mirror
MIRROR
The Sub threshold operation of transistor (M5),
The Fig 3 is shows the level shifted low voltage cascode when the input current (Iin2) increases the input voltage
current mirror, It is the mainly combination of low voltage (Vin2) is also increases, transistor (M5) shifts the voltage
and level shifted current mirror and The combined the low level at gate terminal of transistor( M3), there for this
voltage and level shifted current mirror present a result , current mirror must be improved the upper limit of the input
level shifted low voltage current mirror. In this topology current, compared to low voltage cascode current mirror.
mainly achieve larger dynamic range for low voltage The current through transistor( M5) should be small enough
operation. The operation of transistor (M5) and transistor to keep in transistor (M5) in sub-threshold region.
(M3) are similar shown in the Figure 2 of transistor( M 5) Correspondingly the channel width and length ratio of the
and transistor (M1), we adopt the same assumptions as transistor (M5) should also be large. The current through
above in low voltage in this current mirror. We assume transistor (M1) and M3 should be large to keep it in
figure 3.5 the threshold voltage of (M5) is (V tp )when the saturation region. Level shifted low voltage cascode current
level shifted current mirror transistor (M5) and transistor mirror input current (Iin2) is low, The transistor (M1) and
(M1) on must be conditions satisfied( VGS3 > Vtn ) and (M3) are operate in sub-threshold region. When input
(VGS5 > Vtp) , but when (Vtp > Vtn) there is a little difficulty current (i.e. Iin2) is low, transistor (M3) and (M1) will
to the condition satisfy (VDS3 >0) wide range of input operate in sub- threshold region. If only transistor (M5)
current (Iin2.). we can find the most suitable operation mode operates in sub-threshold region and transistor ( M1)-(M4)
of (M5) is in sub threshold region because here is low input are restricted to operate in saturation region, this current
current and in the saturation region high input current of mirror will possesses better frequency response and the
(M1) and( M3). The assumption under the (V SD5 > 3Vt) ,the lower limit of the input current is slightly higher And the
sub-threshold drain current of transistor (M5) can be minimum output voltage of the level shifted low voltage
expressed as following:- cascode current mirror is equal to following :-
)................ (18)
In the above equation (18), (W5) and (L5) √ √ ..... (23)
represent the channel width and length of transistor (M5)
respectively, and Vt (approximately ≈26mv at room
temperature), equation [2] is thermal voltage. The Constant V. CONCLUSION
‘n’ and (Ido5 ) are process parameters. Typically value of( For the proposed Low Voltage Cascode Current Mirror, the
IDO5 ≈20nA) and ‘n’ lie between 1.2 and 2.0 . For the sub- dynamic range and bandwidth has been improved. Power
threshold operation of (transistor) M5 (V SGS ≈|Vtp|) and dissipation has been also reduced for proposed Low Voltage
saturation operation of transistor (M1) and transistor (M3), Cascode Current Mirror. So, from this study paper it is
find clearly concluded that a Low Voltage Cascode Current
. .................. (19) Mirror can be used to improve the dynamic range,
bandwidth and to reduce the power dissipation.

√ √ ACKNOWLEDGEMENTS
The author (Mr. Viswas Giri) is thankful to Mr. Shobhit
When transistors (M1), (M3), (M5) respectively
Verma, Asstt. Prof. ,ECE department, Takshshila Institute of
are in sub-threshold region and the gate to source voltage of
Engineering & Technology, Jabalpur for providing the
transtitor (M1), (M3) and (M5) are almost near to their
environment for research work & their motivation, kind
threshold voltages, we can find
cooperation, and suggestions.
................ (21)
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 Study of Low Voltage Cascode Current Mirror with Enhance Dynamic Range
(IJSRD/Vol. 2/Issue 08/2014/034)

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