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782019 791 BCS302 DDCO Most Important Questions With

Answers
Business Management HL (PES Public School)

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

MODULE – 1
INTRODUCTION TO DIGITAL DESIGN

1] All solved examples/ problems/ Verilog implementations of Class notes

2] Mention the different Theorems and Postulates of Boolean Algebra and Prove each of them
[CO1: L2: P6-P7]
3] Demonstrate the non-associativity of the NOR Gate [CO1: L2: P14]
4] Demonstrate the positive and negative logic signal [CO1: L2: P16-P17]
5] Reduce the following Boolean expressions to the minimum number of literals:
(i) x (x’ + y) (ii) x + x’y (iii) (x +y) (x + y’)
(iv) xy + x’z + yz (v) (x + y) (x’ + z) (y + z) [CO1: L3: P9]
6] Simplify the Boolean function using a Karnaugh Map:
(i) F (w, x, y, z) = ∑m (1, 3, 7, 11, 15) + ∑d (0, 2, 5) [CO1: L3: P26]
(ii) F (a, b, c) = M0 + M2 + M5 + M6 (iii) F (d, e, f) = ∑m (0, 1, 2, 4)

𝑏̅𝑐̅ 𝑏̅𝑐 bc 𝑏𝑐̅ 00 01 11 10

F F

𝑎̅ 1 1 0 1 1 1

a 1 1 1
1

F (a, b, c) = F (d, e, f) =
(iv) F (r, s, t) = rt’ + r’s’ + r’s

𝑠̅𝑡̅ 𝑠̅𝑡 st 𝑠𝑡̅

F

𝑟̅ 1 1 1 1

r 1 1

F (r, s, t) =

7] Determine the minimum SOP form from using Karnaugh Map:

(i) F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’
(ii) F (w, x, y, z) = x' z' + wyz + w’y’z’ + x’y + w’xyx + wxy’z’ [CO1: L3: P24]

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

CD 00 01 11 10 yz 00 01 11 10
AB 1 1 1 wx
00 00 1 1 1
1 1 1
01 01
1 1
11 11
1 1 1 1 1 1
10 10

8] Identify the prime implicants and essential prime implicants of the following functions
(i) F (A, B, C, D) = ∑m (1, 3, 4, 5, 10, 11, 12, 13, 14, 15)
(ii) F (W, X, Y, Z) = ∑m (0, 1, 2, 5, 7, 8, 10, 15) [CO1: L3: P22]

CD 00 01 11 10 YZ 00 01 11 10
AB 1 1 WX
00 00 1 1 1
1 1 1 1
01 01
1 1 1 1 1
11 11
1 1 1 1
10 10

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

9] Design a car safety alarm circuit diagram. The system considers four inputs: door (D), key (K), seat
pressure (P) and seat belt (B). The input is considered HIGH (1) if the door is closed, the key is in, the
driver is on the seat, or the seat belt is fastened. The alarm (A) should sound with two conditions as stated
below: The door is not closed, and the key is in. The door is closed, the key is in, the driver in the seat, and
the seat belt is not closed.
(i) Construct a truth table for the system based on input arrangement D, K, P, B with A as an output
(ii)Design a Karnaugh Map to verify the simplified expression
(iii) Draw the simplified circuit using
(a) Basic gates (b) NAND gates only (c) NOR gates only
[CO1: L3]
D = 1: door is closed D = 0: door is not closed
K = 1: key is in K = 0: key is not in
P = 1: driver in the seat P = 0: driver not in the seat
B = 1: seat belt is fastened B = 0: seat belt is not fastened
The alarm (A) should sound with two conditions as stated below:
1. The door is not closed, and the key is in; i.e., DKPB = 01XX
2. The door is closed, the key is in the driver's seat, and the seat belt is not closed; i.e., DKPB = 1110
D K P B Alarm, A
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

0 1 0 0 1
0 1 0 1 1 Boolean expression in SOP form: Y=Σm (4,5,6,7,14)

0 1 1 0 1
PB 00 01 11 10
0 1 1 1 1
DK
1 0 0 0 0 00
1 0 0 1 0
1 1 1 1
01
1 0 1 0 0
1
1 0 1 1 0 11
1 1 0 0 0
10
1 1 0 1 0
1 1 1 0 1 A (D, K, P, B) = D’K + KPB’
1 1 1 1 0

10] A digital system is to be designed in which the months of the year is given as input in four-bit form. The
month January is represented as ‘0000’, February as ‘0001’, and so on. The output of the system should be
‘1’ corresponding to the input of the month containing 31 days or otherwise it is ‘0’. Consider the excess
numbers in the input beyond ‘1011’ as don’t care conditions. Consider the excess numbers in the inputs
beyond ‘1011’ as don’t care conditions
i) Write the truth table
ii) Boolean expression in ∑m and ΠM form
iii) Using K-map, simplify the Boolean expression for SOP
iv) Implement the simplified equation using
(a) Basic gates (b) NAND gates only (c) NOR gates only
[CO1: L3]
Month A B C D Output, Y
January 0 0 0 0 1
February 0 0 0 1 0
March 0 0 1 0 1
April 0 0 1 1 0
May 0 1 0 0 1
June 0 1 0 1 0
July 0 1 1 0 1
August 0 1 1 1 1

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

September 1 0 0 0 0
October 1 0 0 1 1 Boolean expression in SOP form: Y=Σm
November 1 0 1 0 0 (0,2,4,6,7,9,11) + d (12,13,14,15)
December 1 0 1 1 1 Boolean expression in POS form: Y=πM
- 1 1 0 0 x (1,3,5,8,10) + d (12,13,14,15)
- 1 1 0 1 x
- 1 1 1 0 x
- 1 1 1 1 x

11] Simplify and implement the following Boolean function using NAND Gates:
(i) F (x, y, z) = ∑m (1, 2, 3, 4, 5, 7) [CO1: L3: P29]

𝑦̅𝑧̅ 𝑦̅𝑧 yz 𝑦𝑧̅

F

𝑥̅ 1 1 1

x 1 1 1

12] With an example, explain the working of Test Bench in Verilog [CO1: L2: P36-P37]
13] Write a Verilog code for the expression using dataflow and behavioral model:
Y = (AB’ + A’B) (CB + AD) (AB’C + AC) [CO1: L2]

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

module Q13_dataflow (Y, A, B, C, D);

input A, B, C, D;
output Y;
assign Y = ((A & ~B) | (~A & B)) & ((C & B) | (A & D)) & ((A & B & ~C) | (A & C));
endmodule
module Q13_behav (Y, A, B, C, D);
input A, B, C, D;
output Y;
always @ (A or B or C or D)
if ((A == 1’b1 & B == 1b’0) | (A == 1b’0 & B == 1b’1)) & ((C == 1b’1 & B == 1b’1) | (A ==
1b’1 & D == 1b’1)) & ((A == 1b’1 & B == 1b’0 & C == 1b’1) | (A == 1b’1 & C == 1b’1)) begin
Y = 1b’1;
end
else Y = 1b’0;
endmodule

14] Write a Verilog code and time diagram for the given circuit (Y = (AB’ + A’B) (C + D)) with propagation
delay of 30 ns and 10 ns respectively for AND and OR gates respectively [CO1: L2]
module Q14_gatelevel (Y, A, A_bar, B, B_bar, C, D);
input A, A_bar, B, B_bar, C, D;
output Y;
wire w1, w2, w3, w4;
and #(30) G1 (w1, A, B_bar);
and #(30) G2 (w2, A_bar, B);
or #(10) G3 (w3, w1, w2);
or #(10) G4 (w4, C, D);
and #(30) G5 (Y, w3, w4);
endmodule
// Time diagram

15] What is User-Defined Primitives in Verilog? What are the general rules for UDP? Explain with an
example HDL for user defined primitive. Draw the Schematic for the Circuit with UDP_02467
[CO1: L2: P41]

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

MODULE – 2
COMBINATIONAL AND SEQUENTIAL LOGIC

1] All solved examples/ problems/ Verilog implementations of Class notes

2] Implement the design of combinational circuit BCD to Excess-3 Code Converter
[CO2: L2: P2-P4]
3] With truth table and K-Map, implement the full adder with basic gates and by using two half adders &
an OR Gate [CO2: L2: P6-P8]
4] Design and explain four-bit adder with carry look ahead [CO2: L3: P9]
5] What is multiplexer? Design 9:1 MUX using 2:1 MUX. [CO2: L3: P12]

6] Realize the following Boolean function using 16:1 multiplexer and 8:1 multiplexer:
(i) F (A, B, C, D) = ∑m (1, 3, 4, 11, 12, 13, 14, 15)
(ii) Y (A, B, C, D) = ∑m (0, 1, 6, 7, 8, 9, 10, 11, 12, 14) [CO2: L2: Refer P16]
7] Realize the following Boolean functions using 8:1 MUX with A, B, C as Select lines and 4:1 MUX with
A, B as Select lines:
(i) Y (A, B, C, D) = ∑m (0, 1, 5, 6, 7, 10, 15)
(ii) Y (A, B, C, D) = ∑m (0, 1, 5, 6, 10, 12, 14, 15) [CO2: L3: Refer P17]

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

8] Implement full adder circuit using 3:8 decoders [CO2: L2: P22]
9] Define decoder. Describe the working principle of a 3:8 decoder. Draw the logic diagram of the 3:8
decoder with enable input. Realize the following Boolean expressions using a 3:8 decoder and multi-input
OR gates: F1 (A, B, C) = ∑m (1, 3, 7) F2 (A, B, C) = ∑m (2, 3, 5)
[CO2; L3: P18-P19 & Refer P22]
10] What is priority encoder? Design 4:2 priority encoder with necessary diagrams
[CO2: L3: P23-P25]
11] Explain different modeling styles used to write the code in Verilog with an example
[CO2: L2: P28-29]
12] What is a Latch? With neat diagram, explain SR latch using NOR Gate. Derive characteristic equation
[CO2: L3: P38-P39 & Refer P46]
13] Differentiate Latches and Flip-flops [CO2: L2: P38]
14] Explain SR, D, JK and T flip-flops with characteristics tables and characteristic equations
[CO2: L2: P46]

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

MODULE – 3
BASIC STRUCTURE OF COMPUTERS & INSTRUCTIONS AND PROGRAMS

1] All solved examples/ problems/ of Class notes

2] With neat diagram, discuss the basic functional units of a computer [CO3: L2: P1-P3]
3] With neat diagram, explain the basic operational concepts between processor and memory
[CO3: L2: P3-P5]
4] Explain Bus structure with diagram. Explain how different peripherals connect to the bus
[CO3: L2: P5-P6]
5] Explain the following:
(i) Measure of performance (ii) Processor time & Processor cache
(iii) Processor clock & Clock rate (iv) Basic performance equation
(v) Performance measurement & Overall SPEC rating of the computer [CO3: L2: P6-P9]
6] Explain in details about the word alignment of a microprocessor-based machine. What is the consecutive
address of aligned words for 16-, 32- and 64-bit word length of the machine? [CO3: L2: P6-P9]
7] Explain the following:
(i) Byte Addressability (ii) Word addressability
(iii) Big-endian assignment (iv) Little-endian assignment
[CO3: L2: P10-P12]
8] Explain the four types of operations performed (four types of instructions capable of performing) by the
computer with example [CO3: L2: P14 & P1-P3]
9] Write a note on:
(i) Register Transfer Notation (ii) Assembly Language Notation
[CO3: L2: P14-P15]
10] Show how the below expression will be executed in three address, two address, one address and zero
address processor in an accumulator organization X = (A * B) + (C * D) [CO3: L3: P18-P19]
11] Write one address, two address and three address instructions to carry out C ← [A] + [B]
[CO3: L3: P19]
12] Describe the concept of branching with an example program of instruction execution
[CO3: L2: P20-P22]
13] What is addressing mode? Explain different types of addressing modes with examples
[CO3: L2: P23-P30]
14] Write ALP of adding a list of N numbers using indirect addressing mode [CO3: L3: P24-P25]
15] Illustrate an indexed addressing mode with an ALP to find the sum of the Test 1, Test 2 and Test 3
scores of the N number of students [CO3: L2: P26-P29]
Dr. MAHESH PRASANNA K., VCET, PUTTUR

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BCS302
DIGITAL DESIGN AND COMPUTER ORGANIZATION
– MOST IMPORTANT QUESTIONS & ANSWERS

16] Consider a computer that has a byte addressable memory organized in 32 words, according to Little -
Endian scheme. A program reads ASCII characters entered at a keyboard and store them in successive byte
location starting at 2000. Show how the contents of the three memory words at locations 2000, 2004 and
2008 after the string "VTU BELAGAVI" has been entered. (ASCII codes: V = 56H, T = 54H, U = 55H, " "
= 20H, B = 42H, E = 45H, L = 4CH, A = 41H, G = 47H, I = 49H) [CO3: L3: P13]

By: DR. Mahesh Prasanna K.,

Dept. of CSE, VCET.
____________*********____________
*********

Dr. MAHESH PRASANNA K., VCET, PUTTUR

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