Lecture 5:

DC &
Transient
Response
 Outline
❑ Pass Transistors
❑ DC Response
❑ Logic Levels and Noise Margins
❑ Transient Response
❑ RC Delay Models
❑ Delay Estimation

5: DC and Transient Response CMOS VLSI Design 4th Ed. 2

 DC Response
❑ DC Response: Vout vs. Vin for a gate
❑ Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

5: DC and Transient Response CMOS VLSI Design 4th Ed. 3

 Transistor Operation
❑ Current depends on region of transistor behavior
❑ For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

5: DC and Transient Response CMOS VLSI Design 4th Ed. 4

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

5: DC and Transient Response CMOS VLSI Design 4th Ed. 5

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

5: DC and Transient Response CMOS VLSI Design 4th Ed. 6

 I-V Characteristics
❑ Make pMOS is wider than nMOS such that bn = bp
Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

5: DC and Transient Response CMOS VLSI Design 4th Ed. 7

 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

5: DC and Transient Response CMOS VLSI Design 4th Ed. 8

 Load Line Analysis
❑ For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

5: DC and Transient Response CMOS VLSI Design 4th Ed. 9

 Load Line Analysis
❑ Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD

Vin0 Vin5
in5

Vin1 Vin4
dsn, |Idsp
Idsn dsp
|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
Vout
out
DD

5: DC and Transient Response CMOS VLSI Design 4th Ed. 10

 DC Transfer Curve
❑ Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 11

 Operating Regions
❑ Revisit transistor operating regions VDD

Vin Vout

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 12

 Beta Ratio
❑ If bp / bn  1, switching point will move from VDD/2
❑ Called skewed gate
❑ Other gates: collapse into equivalent inverter
VDD
bp
= 10
bn
Vout 2
1
0.5
bp
= 0.1
bn

0
VDD
Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 13

 Noise Margins
❑ How much noise can a gate input see before it does
not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

5: DC and Transient Response CMOS VLSI Design 4th Ed. 14

 Logic Levels
❑ To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

b p/b n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

5: DC and Transient Response CMOS VLSI Design 4th Ed. 15

 Transient Response
❑ DC analysis tells us Vout if Vin is constant
❑ Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
❑ Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa

5: DC and Transient Response CMOS VLSI Design 4th Ed. 16

 Inverter Step Response
❑ Ex: find step response of inverter driving load cap
Vin (t ) = u(t − t0 )VDD
Vin(t)
Vout (t  t0 ) = VDD Vout(t)
Cload
dVout (t ) I dsn (t )
=− Idsn(t)
dt Cload
Vin(t)

 0 t  t0

( )
b 2
I dsn (t ) =  2
VDD − V t Vout  VDD − Vt Vout(t)
 t
 b  VDD − Vt − Vout (t ) V (t ) V  V − V
 out t0
  2 
out DD t

5: DC and Transient Response CMOS VLSI Design 4th Ed. 17

 Delay Definitions
❑ tpdr: rising propagation delay
(worse case)
– From input to rising output
crossing VDD/2
❑ tpdf: falling propagation delay
(worse case)
– From input to falling output
crossing VDD/2
❑ tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
❑ tr: rise time
– From output crossing 0.2
VDD to 0.8 VDD
❑ tf: fall time
– From output crossing 0.8
5: DC and V DD to 0.2
Transient VDD
Response CMOS VLSI Design 4th Ed. 18
 Delay Definitions
❑ tcdr: rising contamination delay (best_case)
– From input to rising output crossing VDD/2
❑ tcdf: falling contamination delay (best_case)
– From input to falling output crossing VDD/2
❑ tcd: average contamination delay
– tpd = (tcdr + tcdf)/2

5: DC and Transient Response CMOS VLSI Design 4th Ed. 19

Simulated Inverter Delay
❑ Solving differential equations by hand is too hard
❑ SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
❑ But simulations take time to write, may hide insight
2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)

5: DC and Transient Response CMOS VLSI Design 4th Ed. 20

 Delay Estimation
❑ We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
❑ The step response usually looks like a 1st order RC
response with a decaying exponential.
❑ Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
❑ Characterize transistors by finding their effective R
– Depends on average current as gate switches

5: DC and Transient Response CMOS VLSI Design 4th Ed. 21

 Effective Resistance
❑ Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
❑ Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
❑ Too inaccurate to predict current at any given time
– But good enough to predict RC delay

5: DC and Transient Response CMOS VLSI Design 4th Ed. 22

 RC Delay Model
❑ Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
❑ Capacitance proportional to width
❑ Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

5: DC and Transient Response CMOS VLSI Design 4th Ed. 23

 RC Values
❑ Capacitance
– C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
– Gradually decline to 1 fF/mm in 65 nm
❑ Resistance
– R  10 KW•mm in 0.6 mm process
– Improves with shorter channel lengths
– 1.25 KW•mm in 65 nm process
❑ Unit transistors
– May refer to minimum contacted device (4/2 l)
– Or maybe 1 mm wide device
– Doesn’t matter as long as you are consistent

5: DC and Transient Response CMOS VLSI Design 4th Ed. 24

 Inverter Delay Estimate
❑ Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC

5: DC and Transient Response CMOS VLSI Design 4th Ed. 25

 Delay Model Comparison

5: DC and Transient Response CMOS VLSI Design 4th Ed. 26

 Example: 3-input NAND
❑ Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

2 2 2

3
3

5: DC and Transient Response CMOS VLSI Design 4th Ed. 27

 3-input NAND Caps
❑ Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
9C
3 3C
5C 3C
3C
3
5C 3C
3C
3
5C 3C
3C

5: DC and Transient Response CMOS VLSI Design 4th Ed. 28

 Elmore Delay
❑ ON transistors look like resistors
❑ Pullup or pulldown network modeled as RC ladder
❑ Elmore delay of RC ladder
t pd  R
nodes i
i −to − source Ci

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) CN

R1 R2 R3 RN

C1 C2 C3 CN

5: DC and Transient Response CMOS VLSI Design 4th Ed. 29

 Example: 3-input NAND
❑ Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2 2 2 Y
3 9C 5hC
n2
3 n1 3C
h copies
3 3C

t pdf = ( 3C ) ( R3 ) + ( 3C ) ( R3 + R3 ) + ( 9 + 5h ) C  ( R3 + R3 + R3 )
t pdr = ( 9 + 5h ) RC
= (12 + 5h ) RC

5: DC and Transient Response CMOS VLSI Design 4th Ed. 30

 Delay Components
❑ Delay has two parts
– Parasitic delay
• 9 or 12 RC
• Independent of load
– Effort delay
• 5h RC
• Proportional to load capacitance

5: DC and Transient Response CMOS VLSI Design 4th Ed. 31

 Contamination Delay
❑ Best-case (contamination) delay can be substantially less than
propagation delay.
❑ Ex: If all three inputs fall simultaneously

2 2 2 Y
3 9C 5hC
n2
3 n1 3C

3 3C

R  5 
tcdr = ( 9 + 5h ) C    =  3 + h  RC
3  3 

5: DC and Transient Response CMOS VLSI Design 4th Ed. 32

 Diffusion Capacitance
❑ We assumed contacted diffusion on every s / d.
❑ Good layout minimizes diffusion area
❑ Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C

3C 3C 3C 3 3C

5: DC and Transient Response CMOS VLSI Design 4th Ed. 33