Received: 11 October 2019 Revised: 2 April 2020 Accepted: 3 April 2020

DOI: 10.1002/cta.2799

RESEARCH ARTICLE

A reversible ALU using HNG and Ferdkin gates in QCA

nanotechnology

Maliheh Norouzi1 | Saeed Rasouli Heikalabad2 | Fereshteh Salimzadeh3

1
Department of Electrical Engineering,
Kermanshah University of Technology,
Summary
Kermanshah, Iran Quantum dot cellular automata (QCA) with the characteristics such as low
2
Industrial Nanotechnology Research energy dissipation and high density is a suitable alternative technology to
Center, Tabriz Branch, Islamic Azad
CMOS technology. Arithmetic logic unit (ALU) is one of the most important
University, Tabriz, Iran
3
Department of Computer Engineering,
critical components of a microprocessor, and it is the core component of cen-
Urmia Branch, Islamic Azad University, tral processing unit (CPU). In this work, a novel reversible ALU in QCA nano-
Urmia, Iran technology is proposed. The reversible ALU contains three Ferdkin gates and
Correspondence one HNG gate. The proposed structure needs one constant input and generates
Saeed Rasouli Heikalabad, Industrial only one garbage output. The proposed circuit does not need any rotated cells
Nanotechnology Research Center, Tabriz
and only uses one layer that improves the manufacturability of the design
Branch, Islamic Azad University, Tabriz,
Iran. interestingly. This circuit can perform 20 operations such as AND, OR, XOR,
Email: [email protected] XNOR, COPY, addition, and increment. Our design contains only 480 cells
and 12 majority voters and requires 15 clock phases. The proposed structures
are simulated using QCADesigner version 2.0.3. The reversible ALU, despite a
25% increase in operations, has a 28% improvement in cell numbers and a 6%
improvement in delay.

KEYWORDS
arithmetic and logical unit, nanotechnology, quantum-dot cellular automata, reversible logic

1 | INTRODUCTION

Today, ICs are designed using COMS technology. When CMOS technology enters the scope of nanometer, lots of
problems such as short channel effects, high power density, and high lithography cost occur.1–3 Thus, a number
of technologies have been proposed for replacing it. Among these new devices, quantum-dot cellular automata
(QCA) with the many advantages such as high speed, low power consumption, and high density is a suitable
alternative for COMS technology.4–6 QCA designs digital logic circuits using nano-scale cells to perform various
operations. In irreversible logic computations some of input information is lost, and it cannot be recovered from
output information. Landauer has shown that each bit of information lost generates KTLn2 joules of heat energy
where K is Boltzmann's constant and T is absolute temperature of operation.7 Benett showed that in order to
avoid this energy dissipation in a circuit, it must be composed of reversible gates.8 Reversible logic generates one
to one correspondence between input and output vectors, which reduces energy dissipation. The main limitations
in reversible computing are as follows: minimization of garbage outputs, using the minimum input constants,
using the minimum number of gates, and quantum cost to be a minimum.9 ALU is an important section of any
processor and CPU which can perform arithmetic operations like add, subtract, and comparison and logic

Int J Circ Theor Appl. 2020;1–13. wileyonlinelibrary.com/journal/cta © 2020 John Wiley & Sons, Ltd. 1
2 NOROUZI ET AL.

operation like AND, OR, and XOR. This paper presents an optimized reversible ALU using the Ferdkin and HNG
gates.
The rest of the paper is organized as follows: Section 2 describes the background of QCA technology and a review
on the previous works. In Section 3, we present the QCA implementation of Fredkin gate and HNG gate and design a
new reversible ALU using these gates. Simulation results and comparison with the other available designs are offered
in Section 4. Finally, this paper will be concluded in Section 5.

2 | B A C K G R O U N D A N D RE L A T E D W O R K

2.1 | Fundamentals of QCA

The basic building block of QCA devices is QCA cell shown in Figure 1A. A QCA cell consists of four quantum dots
located at the four corners of a square and two extra mobile electrons.11,12 Due to coulomb interactions, the electrons
will only be located on the opposite corners of quantum cell.13,14
Three-input majority gate is the key logic gate in QCA-based designs.15,16 The QCA structure and truth table of this
gate are shown in Figure 1B. Majority gate is implemented by five QCA cells. The logic function of the majority gate can
be used as a 2-input AND gate or a 2-input OR gate by fixing one of the three input cells to P = −1 or P = +1,
respectively.10
In QCA technology, the clock signal is used to provide the power to run the circuit and control the information flow
direction from the input to the output cell.17–23 There are four clock zones with a 90
phase shift from one clocking
zone to the next. As shown in Figure 2, each clock zone uses four phases, namely, switch, hold, release, and relax,
respectively.24,25 During the switch phase, the interdot barriers are slowly raised and push the electrons into the corner
dots and electrons in the cell become localized according to the state of the input cell. In the hold phase, the interdot
barriers are kept high, the locations of electrons remain constant, and the cell can be used as an input for the cells of
next clock zone. During the release phase, the interdot barriers start to reduce. In the relax phase, the barriers are kept
low, and cells have no polarization.26,27
In QCA technology, there are three crossover methods including (a) coplanar (rotated cells), (b) multilayer crossing
wire, and (c) coplanar (clocking based). Figure 3 shows different types of wire-crossing. The first method uses two type
of QCA cells in the same layer which the first wire has direct cells and the second wire has rotating cells. In the second
method, the crossing will be done in another layer, and it requires at least three layers. The last method uses only one
type of cells which depend on overlapping clock phases.21

F I G U R E 1 (A) Schematics of the basic QCA cells and (B) the QCA
majority gate and its truth table10 [Colour figure can be viewed at
wileyonlinelibrary.com]
NOROUZI ET AL. 3

F I G U R E 2 QCA clocking with

four phases24 [Colour figure can be
viewed at wileyonlinelibrary.com]

F I G U R E 3 Wire crossing methods (A) coplanar crossing (rotated cells), (B) multilayer crossing, and (C) coplanar crossing (clocking
phase)28 [Colour figure can be viewed at wileyonlinelibrary.com]

F I G U R E 4 (A) Schematic diagram and

truth table of Fredkin gate and (B) quantum
equivalent of Fredkin gate29
4 NOROUZI ET AL.

2.2 | Related work

Several reversible ALU have been presented based on QCA.29–34 Sen et al29 have presented a testable reversible ALU
using reversible multiplexer (RM). The presented ALU has two parts: reversible arithmetic unit (RAU) and reversible
logic unit (RLU). These parts have been presented separately, but the QCA structure of the proposed ALU has not been
presented. This design is implemented using one layer and rotated cells which include nine constant inputs and 15 gar-
bage outputs. This design is able to perform 17 different logic and arithmetic operations. Chaves et al30 proposed a

F I G U R E 5 (A) Schematic diagram

and truth table of HNG gate and
(B) quantum equivalent of HNG gate30

F I G U R E 6 The proposed QCA layout of

Frekin gate [Colour figure can be viewed at
wileyonlinelibrary.com]
NOROUZI ET AL. 5

F I G U R E 7 The proposed QCA layout

of HNG gate [Colour figure can be viewed
at wileyonlinelibrary.com]

F I G U R E 8 Schematic diagram of
the proposed reversible ALU

TABLE 1 Arithmetic functionalities of proposed ALU

C0 C1 C2 F1 Operation
0 0 0 B Transfer
0 0 1 B+1 Increment
0 1 0 B + Ac Subtract with borrow
0 1 1 B + Ac + 1 Subtraction
1 0 0 A+B Addition
1 0 1 A+B+1 Add with carry
1 1 0 B+1 Increment
1 1 1 B–1 Decrement
6 NOROUZI ET AL.

design of single-bit ALU by four Fredkin gates and two Toffoli gates in QCA. This design is implemented using multi-
layer crossing which includes four garbage outputs. This design is only able to perform six logic operations. In previous
studies,31,32 the authors used RUG (Reversible Universal Gate) to design a reversible arithmetic unit and a reversible
logic unit separate, but the QCA structure of the proposed ALU has not been presented. The circuits in these papers
have the same schematic, but the QCA layouts of these structures are different. The QCA layout in Sasamal et al31 is
implemented using one layer and rotated cells, and the QCA layout in Sasamal et al32 does not use any rotated cells
and cross wiring is based on Coplanar wire crossing (clocking based). These structures carry out 16 arithmetic and logi-
cal operations and include 6 constant inputs and 11 garbage outputs. Naghibzadeh and Houshmand33 designed a new
4 × 4 reversible gate called NHG (Naghibzadeh–Hoshmand Gate) and used it as the basic building block of proposed
ALU. This design is implemented using multilayer crossing which include one constant input and two garbage outputs.

TABLE 2 Logical functionalities of proposed ALU

C0 C1 C2 C3 F2 F3
0 0 0 1 A AND Bc A AND B
0 0 1 0 A NOR B Ac AND B
0 0 1 1 Bc B
0 1 0 0 A AND B A AND Bc
0 1 0 1 A A
0 1 1 0 A XNOR B A XOR B
0 1 1 1 A OR Bc A OR B
1 0 0 0 Ac AND B A NOR B
1 0 0 1 A XOR B A XNOR B
1 0 1 0 Ac Ac
1 0 1 1 A NAND B Ac OR B
1 1 0 0 B Bc
1 1 0 1 A OR B A OR Bc
1 1 1 0 Ac OR B A NAND B

FIGURE 9 The QCA layout of the proposed reversible ALU [Colour figure can be viewed at wileyonlinelibrary.com]
NOROUZI ET AL. 7

This design can carry out 16 arithmetic and logic operations. Oskouei and Ghaffari34 designed an ALU using a revers-
ible gate called double Feynman gate an AND gate, OR gate, and a full adder, then the output is selected by a multi-
plexer. This design is only able to perform four operations (AND, OR, XOR, and ADD). This design is implemented
using three layers. Kamaraj and Marichamy35 introduced four reversible gates named as KMD Gate1, KMD Gate2,
KMD Gate3, and KMD Gate4. This study introduced two different approaches to design reversible ALU. The first
approach is implemented using only KMD gates. KMD, Toffoli, and Fredkin gates are used to design the second
approach. The QCA layout of first approach is implemented using multilayer crossing, but the QCA layout of second
structure has not been presented. These designs can carry out 18 arithmetic and logic operations.

TABLE 3 The simulation parameters

Parameters Values
Cell width, nm 18
Cell height, nm 18
Number of samples (Fredkin and HNG gates) 12 800
Number of samples (ALU) 164 000
Convergence tolerance 0.001
Radius of effect, nm 65
Relative permittivity 12.9
Clock high 9.8e-022
Clock low 3.8e-023
Clock amplitude factor 2
Layer separation 11.5
Maximum iterations per sample 100

TABLE 4 Comparison between the proposed design and previous works

Number of Number of
Number of Number of Constant Garbage Quantum Wire
Reference Operations Cells Delay Input Output Cost Crossing
22
17 2370 28 9 14 - Coplanar
(rotate cell)
23
6 1097 60 0 4 14 Multiple
layers
24
18 - 32 6 11 - Coplanar
(rotate cell)
25
18 - 21 6 11 - Coplanar
(clock
phase)
26
16 670 16 1 2 19 Multiple
layers
27
4 332 12 - - - Multiple
layers
28
Approach1 18 - - 6 21 118 Multiple
layers
28
Approach2 18 - - 7 22 99 Multiple
layers
Proposed 20 480 15 1 1 20 Coplanar
(clock
phase)
8 NOROUZI ET AL.

2.3 | Fredkin gate

The Fredkin gate is a 3 × 3 universal gate which maps inputs (A, B, and C) to outputs (P = A, Q = Ac B + AC,
R = AB + Ac C). The schematic diagram and truth table of this gate are presented in Figure 4A. As shown Figure 4B, it
has36 quantum cost 5.

FIGURE 10 The simulation results of Fredkin gate [Colour figure can be viewed at wileyonlinelibrary.com]

FIGURE 11 The simulation results of HNG gate [Colour figure can be viewed at wileyonlinelibrary.com]
NOROUZI ET AL. 9

2.4 | HNG gate

HNG gate is a 4 × 4 reversible gate which is described by the following equations:

P = A,

Q = B,

R = ABC,

S = ðABÞCABD:

FIGURE 12 The simulation results of proposed ALU [Colour figure can be viewed at wileyonlinelibrary.com]
10 NOROUZI ET AL.

One of the prominent functionalities of the HNG gate is that if Iv = (A, B, Cin, 0), it can work singly as a reversible full
adder, and the output vector becomes Ov = (P = A, Q = Cin, R = Sum, S = Cout). The implementation of HNG gate
involves quantum37 cost of 6. The block diagram, truth table, and the quantum cost of this gate are illustrated in
Figure 5.

3 | P R O P O S ED D E S I G N

Arithmetic and logical unit (ALU) is a fundamental building block of many types of computing circuits. An ALU must
be able to produce a variety of possible arithmetic and logic functions. We can design more significant ALU using
reversible gates. The reversible gates should maximize the operations of arithmetic and logical unit, but the cost of the
circuit, select lines used for designing the circuit, garbage outputs of the circuit and circuit delays must be reduced. We
use Fredkin gate and HNG gate to design an ALU with this characteristic.
The proposed cellular representation of Fredkin gate is shown in Figure 6. It consists of 100 cells and occupies an
area of 0.12 μm2; the latency is one clock cycle (four clock phases) and requires four three-input majority gate.
The proposed cellular representation of HNG gate is shown in Figure 7. It consists of 80 cells, which has a 0.12-μm2
area, and the latency is 0.75 clock cycle (three clock phases) and requires two three-input majority gate.
A novel design for reversible ALU has been presented in this section. As shown in Figure 8, the proposed reversible
ALU includes one HNG gate and three Fredkin gates. The proposed ALU architecture has seven inputs and seven out-
puts. The number of garbage outputs used here is 1, and the number of constant inputs employed is 1. This circuit can
perform the operations shown in Tables 1 and 2. Its corresponding quantum cost is 20. The cellular representation of
the proposed ALU is shown Figure 9. It consists of 480 cells and occupies an area of 0.75 μm2, and the latency is 15 clock
phases.

4 | S I MULATION RESULTS A ND C OM PARISONS

In our design, we used QCADesigner Ver. 2.0.3. The QCADesigner tool facilitates rapid design, layout, and simulation
of QCA circuits by providing powerful CAD features available in more complex circuit design tools. There are two types
of simulation engines in QCADesigner: bistable approximation and coherence vector. The bistable approximation is
used in our designs because it is faster than coherence vector.38 The utilized parameters in the bistable approximation
simulation mode were summarized in Table 3.

F I G U R E 1 3 The percentage of
improvement compared with Sasamal
et al25 [Colour figure can be viewed at
wileyonlinelibrary.com]
NOROUZI ET AL. 11

F I G U R E 1 4 The percentage of
improvement compared with
Naghibzadeh and Houshmand26 [Colour
figure can be viewed at
wileyonlinelibrary.com]

4.1 | Fredkin gate

The simulation result of the reversible Fredkin gate is presented in Figure 10. In this figure, the inputs are labeled as A,
S0, and S1, and the outputs are labeled as P, Q, and R. These simulation results confirm that the outputs are correctly
achieved. For example, S0 will appear at Q when A = 0, and Q will become S1 when A = 1.

4.2 | HNG gate

The simulation result of the reversible HNG gate is presented in Figure 11. In this figure, the inputs are labeled as A,
B, C, and D, and the outputs are labeled as P, Q, R, and S. These simulation results confirm that the outputs are cor-
rectly achieved after three clock zones delay.

4.3 | Proposed reversible ALU

The simulation result of the proposed reversible ALU is presented in Figure 12. Six waveforms with different frequen-
cies are applied at the inputs C0, C1, C2, C3, A, and B. The outputs are shown by A, B, G1, F1, Carry, F2, and F3. The
arithmetic operations like transfer, increment, subtract with borrow, addition, and decrement are obtained at F1 and
Carry shows carry out. The logical operations include AND, OR, NOR, XOR, XNOR, and COPY are obtained at F1 and
F2. G1 is garbage output.
Table compares the number of operations, number of cells, delay, number of constant inputs, and number of gar-
bage outputs in the proposed reversible ALU with previous studies. The summary of the comparison between our
design and other works25,26 is illustrated in Figures 13 and 14. It can be seen that our design is more efficient in terms
of operation, cell, delay, constant input, and garbage output compared with proposed circuits in previous studies.25,26
The presented ALU in Oskouei and Ghaffari27 needs less number of cells and delay in comparison our design, but our
design has 80% improvement in number of operations and we use one layer to design the our circuits. So we can say
that our proposed ALU is more efficient.

5 | C ON C L U S I ON

Reversible logic presents a method for constructing digital circuits that produces low power dissipation and low heat
dissipation, and it is widely used in nano-based systems. In this work, we proposed and implemented a reversible ALU
12 NOROUZI ET AL.

using reversible Fredkin gate and HNG gate in QCA nanotechnology. The proposed ALU shows improvement in the
design parameters of reversible logic includes number of constant inputs and number of garbage outputs and parame-
ters of QCA structure like QCA cells and delay. Therefore, these structures can be simply used in the designing of
reversible QCA-based circuits. As future work, the number of gates can be reduced by introducing a new
reversible gate.

ORCID
Saeed Rasouli Heikalabad https://orcid.org/0000-0001-9926-5153

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How to cite this article: Norouzi M, Heikalabad SR, Salimzadeh F. A reversible ALU using HNG and Ferdkin
gates in QCA nanotechnology. Int J Circ Theor Appl. 2020;1–13. https://doi.org/10.1002/cta.2799