2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S)

Design and Analysis of Binary to Gray and Gray to

Binary code converter using QCA technology
2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S) | 979-8-3503-6408-8/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICIC3S61846.2024.10603366

Shubham Gupta Ashwani Kumar Rana

ECE Department ECE Department
National Institute of Technology Hamirpur National Institute of Technology Hamirpur
[email protected] [email protected]

Abstract—This study delves into the exploration of Quantum- computing applications where space and power consumption
dot Cellular Automata (QCA) technology as a promising avenue are critical concerns.
for the advancement of computing in upcoming generations. QCA In the realm of code conversion circuits, significant progress
stands poised to revolutionize the landscape of computing with
its array of advantages, including reduced power consumption, has been made in using QCA for designing efficient converters.
heightened operational speeds, and the potential to transcend For instance, papers [1] and [2] discuss the design of a Binary
the limitations of conventional CMOS technology. Our research to Gray code converter. Paper [1] describes a circuit utilizing
focuses on the design and analysis of binary-to-Gray and Gray- an XOR gate to achieve a 2-bit converter with a minimal cell
to-binary code converters spanning a range of bit sizes from 2 to count of 17, and by replicating the circuit they obtained a 4-
4 bits. By examining factors such as temperature sensitivity, area
utilization, and cell count as compared to previous designs, we bit circuit using 45 cells covering an area of 0.07 µm2 . On
aim to highlight the unique strengths of QCA in comparison other hand, paper [2] adopts a different approach by employing
to CMOS technology, while also considering previous QCA 9 majority gates of QCA to construct a 4-bit circuit with a
converter designs. Additionally, we conduct a comprehensive significantly higher cell count of 126 and an area of 0.15 µm2 .
evaluation of power consumption disparities between QCA and Similarly, papers [3] and [4] explore the design of Gray to
CMOS implementations, offering insights into their respective
energy efficiencies. Through this research endeavor, we endeavor Binary code converters. Paper [3] uses a compact XOR gate
to provide valuable insights into the opportunities and challenges comprising 18 cells, culminating in a converter that utilizes
presented by QCA technology in the realm of practical circuit de- 69 cells and spans an area of 0.1 µm2 . Meanwhile, paper
sign, paving the way for its integration and potentially reshaping [4] demonstrates a more cell-efficient method by arranging
the future landscape of computing. majority gates to mimic the functionality of XOR gates using
Index Terms—QCA Designer 2.0.3, Quantum Dot Cellular
Automata(QCA), Code Converters AND, OR, and NAND gates. This approach results in a 4-
bit converter design that uses 76 cells, maintaining the same
area footprint as the design in paper [3]. The research in [5],
I. I NTRODUCTION
[6], and [7], has focused on diverse designs of XOR gates
The landscape of modern computing is experiencing a and various other digital circuits by which prior studies have
profound shift towards innovative technologies to meet the made substantial progress in understanding QCA’s potential
increasing demand for faster, energy-efficient systems. QCA for logic circuits and code converters.
emerges as a compelling substitute for conventional CMOS Our approach takes a step further by introducing novel
technology, operating at the nanoscale level and exploiting strategies to optimize performance metrics. Specifically, we
quantum effects to process information. Its unique approach, utilize an 8-cell XOR gate design which designed without
based on electron charge manipulation rather than current any cross-wire technique and gives result based on columbic
flow as in CMOS, offers numerous advantages. QCA boasts interaction of charges among QCA cells and utilizes the 4-
minimal power requirements, potential for exceedingly high phase clocking scheme in QCA to reduce cell count and area
operational speed, and scalability beyond CMOS constraints, utilization while improving overall performance. Our circuits
making it a promising candidate for next-generation comput- reduce the cell count and area consumption by ∼ 20-30% as
ing. This paper investigates QCA’s potential through the design compare to previous studies. Additionally, we conduct a thor-
and analysis of digital code converters, showcasing its role in ough temperature analysis which shows our circuits can works
advancing computational capabilities. efficiently till 7-10K while standard operating temperature for
Previous studies have laid the groundwork for understanding QCA circuits are 1K and the energy dissipation of proposed
QCA’s potential in implementing basic and complex logic circuits are less than 0.02 eV which is quite less than previous
circuits. Notably, research outlined in previous papers pro- studies. Through these innovative techniques, our research
vides valuable insights into the performance of QCA de- aims to enhance the efficiency and practical applicability of
signs compared to CMOS, particularly in terms of energy QCA technology in digital circuit design.
dissipation, temperature stability, and area efficiency. These This research aims to further these studies by systematically
studies demonstrate QCA’s suitability for high-performance designing, analyzing, and simulating Binary to Gray and Gray

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 2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S)

to Binary code converters. The goal is to optimize cell count in a complementary output. electron repulsion achieves logic
and area while enhancing the converters’ performance and inversion as demonstrated in Figure 2.
stability across various temperatures, and understanding their
performance against counterparts realized in CMOS through
Verilog and Xilinx Vivado tool. By integrating the advanced
capabilities of QCA with effective design strategies, this paper
seeks to underscore the feasibility of replacing traditional
CMOS circuits in specific applications, and understand the
potential of QCA circuits in achieving reduced area utilization Fig. 2: QCA wire and inverter
and lower energy consumption in digital systems potentially
leading to significant advancements in digital computing tech- C. Building Block of QCA- Majority Gate
nology. Majority Gate in QCA highlights its pivotal role as the
II. QCA TECHNOLOGY BACKGROUND universal gate in QCA Logic. By polarising one input to +1
or -1, it can operate as an AND or OR gate, making it an
QCA utilizes the principles of quantum mechanics and nan- adaptable gate as given in [9]. accordingly, as seen in Fig. 3.
otechnology to perform computational tasks. Unlike traditional The function, MG(x,y,z) = xy+yz+zx is implemented in this.
transistor-based technologies like CMOS, which rely on the Here the centre cell gets the signal from 3 surrounding cells
flow of electrical current, QCA operates based on the charge and based on majority and columbic repulsion it generates the
and position of electrons in arrays of quantum dots. output result.
A. QCA cell and Logic propagation
QCA harnesses the physical arrangement of four quantum
dots within a cell, as shown in Fig 1 are interconnected
by tunnel barriers to facilitate digital logic operations at
the nanoscale. Electrons within the cell can tunnel between
these dots, constrained within the structure due to barriers
that prevent their exit as given in [8]. When two excess
electrons occupy the cell, their coulombic repulsion results in
positioning at opposite corners, establishing the fundamental Fig. 3: Gates using Majority Gate
polarization defining the QCA cell’s logic state. Logic propa-
gation occurs through controlled electron tunneling, represent- D. Clocking in QCA
ing ”0” or ”1” based on their configurations within the dots. Clocking in QCA is fundamental to orchestrate synchro-
This movement and redistribution of electrons within the cell nized operations within circuits. Unlike traditional clocking
underpin QCA’s logic operations, enabling rapid information in CMOS, QCA’s clocking mechanism revolves around signal
transfer and processing. polarization. The clocking signal controls the timely manip-
ulation of QCA cells, enabling precise execution of logic
operations. Clock in QCA is multi-phase which has 4 phases
as, Switch, hold, Release, Relax depicted in Fig 4. Initially in
switch phase of the clocking scheme in QCA, the tunneling
barrier starts with low potential, leaving cells in an unpolarized
state. As tunneling barriers gradually rise, neighboring cell
influence polarizes extra electrons, assigning specific binary
values to cells. Then subsequent hold phase elevates barriers,
maintaining electron polarity and preventing switching. In the
release phase, lowered barriers cause depolarization, while the
relax phase, characterized by barrier absence, retains cells in
an unpolarized state. With this clocking system, a sub-array
Fig. 1: QCA cell and polarization state can execute a specific calculation, and then make its state
frozen by raising the interdot barriers, and have its output
B. QCA wire and inverter serve as the input for a subsequent array.
QCA wires consist of a linear array of QCA cells aligned III. B INARY TO G RAY CODE CONVERTER PROPOSED
to facilitate signal transmission. The signal in a QCA wire CIRCUITS
is transferred through a series of cell-to-cell interactions, By utilising the XOR gate proposed in [10] 2,3,4 bit Binary
where polarization states change based on the signal received. to Gray code converter circuits are designed by reducing the
For inverter input wires control cell polarization, resulting cell count and area utilization.

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 2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S)

Fig. 4: Interdot barriers in clocking zone (a) 2 Bit (b) 3 Bit

A. 2-Bit
As for the two bit code converter we used one XOR gate
which utilizes 12 cells shown in Fig 5(a) which follows the
following Boolean expression:
A0 = A (1)

B0 = A ⊕ B (2)

B. 3-Bit
As for the three bit code converter we used two XOR gates
which utilizes 22 cells shown in Fig 5(b) which follows the
following Boolean expression:
A0 = A (3)

B0 = A ⊕ B (4)

C0 = B ⊕ C (5)
C. 4-Bit
(c) 4 Bit
As for the four bit code converter we used three XOR gates
which all are working in same clock zone as each output is Fig. 5: Binary to Gray code conveter circuits
independent of previous output and depends only on current
input so this input cells are in switch phase and the XOR
decision making cell is in Hold phase for all 4 bits. This design A. 2-Bit
utilizes 31 cells shown in Fig 5(c) which follows the following As for the two bit code converter we used one XOR gate
Boolean expression: which utilizes 9 cells shown in Fig 6(a) which follows the
A0 = A (6) following Boolean expression:
B0 = A ⊕ B (7) B1 = G1 (10)
C0 = B ⊕ C (8)
B2 = G1 ⊕ G2 (11)
D0 = C ⊕ D (9)
B. 3-Bit
IV. G RAY TO B INARY CODE CONVERTER PROPOSED As for the three bit code converter we used two XOR gates
CIRCUITS
which utilizes 20 cells shown in Fig 6(b). In this we have to
By utilising the XOR gate proposed in [10] 2,3,4 bit Gray wait for the signal B2 which is generated by G1 and G2 so
to Binary code converter circuits are designed by reducing the we changed the clock phase by raising the barrier potential
cell count and area utilization. and after the result generated it goes into switch stage to take

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 2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S)

V. S IMULATION R ESULTS
The proposed designs of Binary to Gray code converters for
multiple bits are compared on the basis of cell count and area
occupied with the previous designs in [1] and [2] as shown in
Fig 7 and Fig 8. The designs are simulated on QCA Designer
2.0.3 which gives the cell count and the area consumption
by the circuit and shows that there is significant change in
(a) 2 Bit number of cells which leads to efficient area utilization. Our 4
bit converter proposed design uses 31 cells with area of 0.05
µm2 while the prior study circuit [1] uses 45 cells and area
(b) 3 Bit
of 0.07 µm2 . Similar analysis is preformed with the Gray to
Binary code converter with the previous designs proposed in
[3], [4] as shown in Fig 9. As compared with previous designs
our 4 bit converter uses 31 cells and area of 0.08 µm2 while
the prior study circuit [3] uses 69 cells and area of 0.1 µm2 .
Our study delved deeper into temperature analysis using the

(c) 4 Bit
Fig. 6: Gray to Binary code converter circuits

input and operate accordingly Following Boolean expression Fig. 7: Number of cells comparison
are designed in this:
B1 = G1 (12)

B2 = G1 ⊕ G2 (13)

B3 = G3 ⊕ B2 (14)

C. 4-Bit
As for four bit code converter we used three XOR gates. As
same in 3 Bit we have to further wait for B3 signal to generate
the B4 signal so by changing the clock stages we achieved the
required results. This design utilizes 31 cells shown in Fig 6(c)
which follows the following Boolean expression:

B1 = G1 (15) Fig. 8: Area occupied comparison

B2 = G1 ⊕ G2 (16) QCA Designer E Tool. Simulations of QCA circuits across

various temperatures provided valuable insights into energy
consumption per cycle, as visually represented in Fig. 10 and
B3 = B2 ⊕ G3 (17) Fig. 11. These figures illustrate that our proposed circuits
exhibit lower energy dissipation over a range of tempera-
B4 = B3 ⊕ G4 (18) tures compared to previous studies. Specifically, the proposed

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 2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S)

circuit’s energy dissipation remains below 0.02 eV, whereas

previous works [1], [2], [3], [4] observed dissipation ranging
from 0.02 to 0.05 eV. Additionally, our analysis revealed that
the circuits maintained temperature stability. The observed
abrupt shifts in energy levels in previous works resulted
in distorted waveforms, highlighting our circuits’ improved
response to thermal conditions. The waveforms of the 4-bit
QCA converters simulated using the QCA Designer 2.0.3 are
depicted in Fig. 12 and Fig. 13.
Furthermore, to enhance our study, we engaged Verilog-
HDL and the Xilinx Vivado tool to design and simulate CMOS
counterparts. This approach facilitated a comprehensive com-
parative analysis, enabling us to contrast the power consump-
tion between circuits designed using QCA and conventional
CMOS technology which is depicted in Fig 14.
Fig. 9: Gray to Binary code converter comparison

Fig. 12: Simulation waveform for 4 bit Binary code converter

Fig. 10: Temperature analysis of Binary to Gray converters

Fig. 13: Simulation waveform for 4 bit Gray code converter

VI. C ONCLUSION
In conclusion, our study showed significant advancements in
the QCA framework’s Binary to Gray and Gray to Binary code
converters. In comparison to earlier iterations, the suggested
designs for 2, 3, and 4-bit converters demonstrated improved
efficiency with fewer cells and better use of available space,
indicating the possibility of more compact digital systems.
A QCA circuit consist of arrays of nanoscale quantum dots
arranged in a specific pattern to perform logic operations.
Fig. 11: Temperature analysis of Gray to Binary converters While the individual quantum dots are nanometers in size,
the entire array, along with its wiring and interconnects, might
span micrometers which give the area of circuit in micrometre.

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 2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S)

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ACKNOWLEDGMENT
We would like to start by expressing our sincerest gratitude
to VLSI Lab of Electronics and Communication Engineering
Department at the National Institute of Technology, Hamirpur,
for their invaluable support and resources, which greatly
enriched the experience. Their expertise and facilities played
a pivotal role in the successful completion of this research
paper.
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