EECE – 457

VLSI II (Logical Effort)

Md. Tawfiq Amin, PhD

Department of EECE, MIST
[email protected]

Slides based on the initial set from David Harris & Deming Chen
 Unit

1
Logical Effort
Ref: Ch. 4 – CMOS VLSI DESIGN- A Circuits and Systems Perspective – 4th edition-Weste & Harris

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 References

Text book:
1. Weste & Harris, CMOS VLSI DESIGN- A Circuits and Systems
Perspective – 4th edition., Pearson- Hill, 2011.

References:
1. Basic VLSI Design by Douglas A. Pucknell and Kamran
Eshraghian; 3rd Edition.

2. CMOS digital Integrated circuits: Analysis and design: Sung-Mo

Kang and Yusuf Leblebici.

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 Course Contents
➢ Logical Effort ➢ Wire
• Delay in a Logic Gate • Interconnect Modeling
• Multistage Logic Networks • Wire Resistance, Wire Capacitance
• Choosing the Best Number of Stages • Wire RC Delay, Crosstalk
• Wire Engineering, Repeaters
➢ Cascode and Current Mirror
• Cascode Basics & Cascode Amplifier ➢ Scaling & Packaging
• Practical Cascode • Scaling, Transistors
• Current Mirror Basics • Interconnect, Future Challenges
• CMOS Current Mirror • Economics, Packaging

➢ CMOS Manufacturing Process ➢ Application Specific IC

• Layout Design Rules • VCO Design, PLL Design
• Process Enhancements • Filter Design, I/O Pad Design
• Manufacturing Issues • Low Power IC Design

➢ Testing ➢ Implementations Strategies

• Logic Verification, Silicon Debug • Full Custom IC Design
• Manufacturing Test, Fault Models • Semi-Custom IC Design
• Observability and Controllability • Standard Cell Design and Cell Libraries
• Design for Test, Scan • FPGA Building Block Architectures
• Global, Detailed, Special Routing
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 Delay (VLSI-I Course)
The two most common metrics for a good chip are speed and power,
respectively. Delay and power are influenced as much by the wires as
by the transistors. A chip is of no value if it cannot reliably accomplish
its function.

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 Delay Estimation (VLSI-I Course)
The most fundamental way to compute delay is to develop a physical model of the
circuit of interest, write a differential equation describing the output voltage as a
function of input voltage and time, and solve the equation. The solution of the
differential equation is called the transient response, and the delay is the time when
the output reaches VDD/2.

➢ Use RC delay models to estimate delay * A unit nMOS transistor is defined to have
effective resistance R.
▪ C = total capacitance on output
* An nMOS transistor of k times unit width has
node resistance R/k because it delivers k times as
▪ Use effective resistance R much current.
▪ So that tpd = RC * A unit pMOS transistor has greater resistance,
generally in the range of 2R–3R, because of its
➢ Characterize transistors by finding lower mobility. R is typically on the order of 10
their effective R kΩ for a unit transistor.

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 Delay Estimation (VLSI-I Course)

Total Capacitance on the output node

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 Delay Estimation (VLSI-I Course)

Figure shows equivalent RC circuit

models for nMOS and pMOS
transistors of width k with
contacted diffusion on both source
and drain. The pMOS transistor has
approximately twice the resistance
of the nMOS transistor because
holes have lower mobility than
electrons.

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 Delay Estimation (FO1) (VLSI-I Course)

Figure (a) shows the equivalent circuit for a fanout-of-1 inverter with negligible wire
capacitance. Figure (b) gives an equivalent circuit, showing the first inverter driving the
second inverter’s gate. Figure (c) illustrates this case with the switches removed. The
capacitors shorted between two constant supplies are also removed because they are not
charged or discharged. The total capacitance on the output Y is 6C.

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Delay Estimation (3-input NAND) (VLSI-I Course)

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 Logical Effort (Introduction)

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 Example

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 Delay in a Logic Gate

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 Computing Logical Effort

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 Delay Plots

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 Catalog of Gates

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 Catalog of Gates

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 Example: Ring Oscillator

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 Example: FO4 Inverter

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 Example:
Example: A four-input nor gate drives 10 identical gates, as shown in Figure.What is the delay
in the driving nor gate?

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 Example:
Example: Design inverter, 2-input NAND, and 2-input NOR, each with input capacitance equal
to 60-unit sized transistors.

Solution:
inverter: (1:2)

2-input NAND: (2:2)

2-input NOR: (1:4)

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 Multistage Logic Networks

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 Multistage Logic Networks

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 Paths that Branch

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 Branching Effort

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 Multistage Delays
Delay of a multi‐stage network = sum of stage delays

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 Designing Fast Circuits

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 Gate Sizes

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 Example: 3-stage path

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 Example: 3-stage path

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 Example: 3-stage path

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 Example:
Consider the path from A to B involving three two-input NAND gates shown in Figure. The
input capacitance of the first gate is C, and the load capacitance is also C. What is the least
delay of this path, and how should the transistors be sized to achieve least delay? Draw the
schematic for the resultant 2-input NAND by showing its transistor size.

The path logical effort is the product of the

logical efforts of the three nand gates, G =
g0g1g2 = 4/3 × 4/3 × 4/3 = (4/3)3 = 2.37.
F = GBH = 2.37
D = 3(2.37)1/3 + 3(2pinv) = 10.0 delay units.

z =C ×(4/3)/(4/3)=C. Similarly,
y = z × (4/3)/(4/3) = z = C.
Hence we find that all three nand gates
should have the same input capacitance, C.

Using the network as in Figure, find the least delay achievable along the path from A to B
when the output capacitance is 8C.
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 Example:
Optimize the circuit in Figure to obtain the least delay along the path from A to B when the
electrical effort of the path is 4.5

z = 4.5C × (4/3)/4 = 1.5C

y = 3z × (4/3)/4 = z = 1.5C

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 Example: 3-stage path
Consider a process in which pMOS transistors have three times the effective resistance as
nMOS transistors. Calculate the logical efforts of a 2-input NAND gate and a 2-input NOR
gate if they are designed with equal rising and falling delays. Using calculated logical efforts,
select gate sizes X and Y for the least delay for the path A to B.

NAND2: g = 5/4; NOR2: g = 7/4.

The inverter has a 3:1 P/N ratio and 4
units of capacitance. The NAND has
a 3:2 ratio and 5 units of capacitance,
while the NOR has a 6:1 ratio and 7
units of capacitance.

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 Choosing the Best Number of Stages

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 Choosing the Best Number of Stages
Consider three alternative circuits for driving a load 25 times the input capacitance of the circuit.
The first design uses one inverter, the second uses three inverters in series, and the third uses
five in series. All three designs compute the same logic function. Which is best, and what is the
minimum delay?

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 Choosing the Best Number of Stages
A string of inverters in a 0.6μ process drives a signal that goes off-chip through a pad. The
capacitance of the pad and its load is 40 pF, which is equivalent to about 20,000 microns of gate
capacitance. Assuming the load on the input should be that of an inverter with 7.2 microns of
input capacitance, what is the fastest inverter string?

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Derivation of the Best Number of Stages

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 Best Number of Stages

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 Example

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 Example: Number of Stages

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 Example: Gate Sizes & Delay

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 Asymmetric Gates

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 Compound Gates

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 Review of Definitions

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 Limitations of Logical Effort
Logical Effort is based on the linear delay model and the simple premise that making
the effort delays of each stage equal minimizes path delay. This simplicity is the
method’s greatest strength, but also results in a number of limitations:
1. Logical Effort does not account for interconnect. Logical Effort is most applicable
to high-speed circuits with regular layouts where routing delay does not dominate.
Such structures include adders, multipliers, memories, and other datapaths and
arrays.
2. Logical Effort explains how to design a critical path for maximum speed, but not
how to design an entire circuit for minimum area or power given a fixed speed
constraint.
3. Paths with nonuniform branching or reconvergent fanout are difficult to analyze
by hand.
4. The linear delay model fails to capture the effect of input slope. Fortunately, edge
rates tend to be about equal in well-designed circuits with equal effort delay per
stage.

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