Data converters- Unit 5

By,
Sanjana T
Syllabus
• Digital-to-Analog Converter specifications: DNL, INL, Offset, Gain error, Latency, SNR,
Dynamic Range.
• Analog-to-Digital Converter specifications: Quantization error, DNL, INL, Missing
codes, Offset, Gain error, Aliasing, SNR, Aperture error, Mixed-Signal layout issues.
• DAC Architectures: R-2R ladder DAC, Current Steering DACs, Charge Scaling DACs,
Pipeline DAC.
• ADC Architectures: Pipeline ADC, Integrating ADCs, Successive Approximation ADC,
Oversampling ADCs.
Introduction
• Data converters are circuits that changes analog signals to digital representations or
vice-versa
• Analog-to-digital converters, also known as A/Ds or ADCs, convert analog signals to
discrete time or digital signals. Digital-to-analog converters (D/As or DACs) perform the
reverse operation.
Digital-to-Analog Converter (DAC)
• Block diagram of DAC

• vOUT is the analog voltage output, VREF is the reference voltage, and F is
the fraction defined by the input word, D, that is N bits wide.
• The Maximum analog output voltage for any DAC is limited by the
value of VREF.

• Eg. if a 3-bit DAC is being used, the input, D, is 100 = 410, and FÄ£F is 5
V, then F=4/8, Vout=2.5V

• Maximum analog output that can be generated by the 3-bit DAC is

Digital-to-Analog Converter (DAC)
• This maximum analog output voltage that can be generated is
known as full-scale voltage, VFS, and can be generalized to any
N-bit DAC as

• The LSB defines the smallest possible change in the analog

output voltage.

• For a 3-bit DAC, 1 LSB = 5/8 V, or 0.625 V

• Change in MSB causes the output to change by 1/2 VREF
• Resolution describes the smallest change in the
analog output with respect to the value of the
reference voltage VREF. It is specified as number
of bits.
• Accuracy =1/(2^N)
1. Find the resolution for a DAC if the output voltage is desired to
change in 1 mV increments while using a reference voltage of 5 V.

• 1LSB=1mV

• Accuracy

• Resolution
2. Find the number of input combinations, values for 1 LSB, the percentage
accuracy, and the full-scale voltage generated for a 3-bit, 8-bit, and 16-bit DAC,
assuming that VREF= 5 V.
DAC specifications
1. Differential Nonlinearity
2. Integral Nonlinearity
3. Offset
4. Gain Error
5. Latency
6. Signal-to-Noise Ratio (SNR)
7. Dynamic Range
Differential Nonlinearity (DNL)
• Nonideal components cause the analog increments to differ from their ideal values.
The difference between the ideal and nonideal values is known as differential
nonlinearity, or DNL and is defined as
DNLn = Actual increment height of transition n - Ideal increment height
• where n is the number corresponding to the digital input transition. The DNL
specification measures how well a DAC can generate uniform analog LSB multiples at
its output.
Determine the DNL for the 3-bit nonideal DAC whose transfer
curve is shown in Fig. Assume that VREF = 5 V.
DNL1= DNL2=0

• Overall error of the DAC is defined by its worst-case DNL.

DAC will have less than ±1/2 LSB of DNL if it is to be N-bit
accurate
• A 5-bit DAC with 0.75 LSBs of DNL actually has the
resolution of a 4-bit DAC.
• If the DNL for a DAC is less than -1 LSBs, then the DAC is
said to be non-monotonic, which means that the analog
output voltage does not always increase as the digital input
code is incremented.
• A DAC should always exhibit monotonicity if it is to function
without error.
Integral Nonlinearity (INL)
• Defined as the difference between the data converter output
values and a reference straight line drawn through the first
and last output values, INL defines the linearity of the overall
transfer curve and can be described as
• INLn = Output value for input code n -Output value of the
reference line at that point
• A converter with N-bit resolution will have less than ±1/2 LSB
of DNL and INL.
• ±1/2 LSB is a common term that typically denotes the
maximum error of a data converter (both DACs and ADCs).
• Eg. 13-bit DAC having greater than ±1/2 LSB of DNL or INL
actually has the resolution of a 12-bit DAC.
Determine the INL for the non-ideal 3-bit DAC shown in Fig. Assume
that VREF=5V

• Reference line method

• Best fit method
Offset, Gain Error and Latency
• Offset
• The analog output should be 0 V for D = 0.
• However, an offset exists if the analog output voltage is
not equal to zero.
• Gain Error
• A gain error exists if the slope of the best-fit line through
the transfer curve is different from the slope of the best-
fit line for the ideal case.
• Gain error = Ideal slope - Actual slope
• Latency
• Total time from the moment that the input digital word
changes to the time the analog output value has settled
to within a specified tolerance.
• latency includes the delay required to map the digital
word to an analog value plus the settling time.
Signal-to-Noise Ratio (SNR) and Dynamic
Range
• SNR:
• Ratio of the signal power to the noise at the analog output.
• The SNR can reveal the true resolution of a data converter as the effective number of bits
can be quantified mathematically.
• Dynamic Range:
• Ratio of the largest output signal over the smallest output signal
• N-bit DAC can produce a maximum output of 2N-1 multiples of LSBs and a minimum value
of 1 LSB.

• A 16-bit data converter has a dynamic range of 96.33 dB.

Analog-to-Digital Converter (ADC)
• Input is an analog signal with an infinite number of values, which
then has to be quantized into an N-bit digital word

• The y-axis of the transfer characteristics is the digital output, and

the x-axis has been normalized to VREF, Since the input signal is a
continuous signal and the output is discrete, the transfer curve of
the ADC resembles that of a staircase
• 2N quantization levels correspond to the digital output codes 0 to
7. Thus, the maximum output of the ADC will be 111 (2N - 1),
corresponding to the value for which Vin/VREF>=7/8.
Quantization Error
• Since the analog input is an infinite valued
quantity and the output is a discrete value, an
error will be produced as a result of the
quantization. This error, known as quantization
error, Qe

• the magnitude of Qe will be no greater than one

LSB and no less than 0.
• It would be advantageous if the quantization
error were centered about zero so that the error
would be at most ±1/2 LSBs
• Entire transfer curve is shifted to the left by 1/2
LSB, thus making the codes centered around the
LSB increments on the x-axis.
Observations from the transfer curve
• First code transition occurs when Vin/VREF>=1/16.
• First step width=0.5LSB
• Last code transition occurs when Vin/VREF>=13/16.
• Last step width=1.5LSB, rest of them 1 LSB
• converter would be considered to be out of range once Vin/VREF>=15/16
Analog-to-Digital Converter (ADC)
Specifications
1. Differential Nonlinearity
2. Missing Codes
3. Integral Nonlinearity
4. Offset and Gain Error
5. Aliasing
6. Signal-to-Noise Ratio
7. Aperture Error
Differential Nonlinearity (DNL)
• DNL is the difference between the actual code
width of a nonideal converter and the ideal
case.

• DNL0=DNL1=DNL4=0

• quantization error is directly related to the

DNL.
Missing codes
• The total width of the step corresponding to
101 is completely missing
• The value of DNL5 is -1 LSB.
• Step width corresponding to 010 is 2 LSBs and
that the value for DNL2 is +1 LSB.
• ADC having a DNL greater than +1 LSB is not
guaranteed to have a missing code, though in
all probability a missing code will occur.
Integral Nonlinearity (INL)
• A "best-fit“ straight line is drawn through the
end points of the first and last code transition
• INL is difference between the data converter
code transition points and the straight line with
all other errors set to zero.

INL6= -0.5 LSB

Offset and Gain Error
• Offset error:
• occurs when there is a difference
between the value of the first
code transition and the ideal
value of 1/2 LSBs
• offset error is a constant value.
• Note that the quantization error
becomes ideal after the initial
offset voltage is overcome.
• Gain Error:
• Gain error or scale factor error is
the difference in the slope of a
straight line drawn through the
transfer characteristic and the
slope of 1 of an ideal ADC.
Dynamic errors- Aliasing
• Nyquist Criterion requires that a signal be sampled at least
two times the highest frequency contained in the signal
• Aliasing would occur if the sampling rate is less than Nyquist
rate, then totally different signal will be sampled
• The different frequency signal is an "alias" of the original
signal, and its frequency can be calculated using

• Aliasing can be eliminated by

• both sampling at higher frequencies
• by filtering the analog signal before sampling and removing
any frequencies that are greater than one-half the sampling
frequency.
Aliasing- frequency domain analysis

• The analog signal is represented as a simple band-

limited signal with center frequency, f0.
• multiplication in the time domain is equivalent to
convolution in the frequency domain
• Frequency domain representation of the sampled signal
reveals that the overall signal consists of multiple
versions of the band-limited signal at multiples of the
sampling frequency.
• As the sampling time increases, the sampling frequency
decreases and the impulses in the frequency domain
become more closely spaced
• This results in aliasing as the multiple versions of the
band-limited signal begin to overlap.
• The point at which the spectra overlap is called the
folding frequency.
• Solution to aliasing are higher sampling frequency and
filtering (combination of both s efficient).
Signal-to-Noise Ratio
• Ratio of value of the largest RMS input signal into the converter over the RMS value of
the noise.

• Input signal is a sinewave with a peak-to-peak value equal to the full-scale reference
voltage of the converter

• The value of the noise (if the data converter is considered to be ideal) will be equivalent
to the RMS value of the error signal
Aperture Error
• Maximum sampling error associated with the
aperture uncertainty can be no larger than 1/2
LSB.
• A transient effect that introduces error occurs
between the sample and the hold modes in a
S/H circuit.
• The aperture time actually varies slightly as a
result of noise on the hold-control signal and the
value of the input signal. This effect is called
aperture uncertainty or aperture jitter.
• As a result, if a periodic signal were being
sampled repeatedly at the same points, slight
variations in the hold value would result, thus
creating sampling error.
Find the maximum resolution of an ADC which can use the S/H given
aperture uncertainty of 0.628 mV, while maintaining a sampling error
less than 1/2 LSB

Resolution N= 11 bits
Mixed-Signal Layout Issues
• Analog ICs are more sensitive to noise than digital Ics
• Sensitive analog nodes must be protected and
shielded from any potential noise sources.
• Grounding and power supply routing must also be
considered when using digital and analog circuitry on
the same substrate.
• Since a majority of ADCs use switches controlled by
digital signals, separate routing channels must be
provided for each type of signal.
• Strategies regarding the systemwide minimization of
noise should always be considered foremost.
• The lowest issues are foundational and must be
considered before each succeeding step.
• The successful mixed-signal design will always
minimize the effect of the digital switching on the
analog circuits.
Floor-planning
• The analog circuitry should be categorized by the sensitivity of
the analog signal to noise. For example, low-level signals or
high-impedance nodes typically associated with input signals
are considered to be sensitive nodes.
• High-swing analog circuits such as comparators and output
buffer amplifiers should be placed between the sensitive analog
and the digital circuitry.
• The digital circuitry should also be categorized by speed and
function.
• Digital output buffers are usually designed to drive capacitive
loads at very high rates, they should be kept farthest from the
sensitive analog signals.
• High and lower speed digital should be placed between the
insensitive analog and the output buffers.
• sensitive analog is as far away as possible from the digital
output buffers and that the least sensitive analog circuitry is
next to the least offensive digital circuitry.
Power Supply and Grounding Issues
• When analog and digital circuits exist together on the same die, danger exists of injecting
noise from the digital system to the sensitive analog circuitry through the power supply and
ground connections
• Resistors represent the small, nonnegligible resistance of the interconnect to the pad.
• The inductors represent the inductance of the bonding wire which connects the pads to the
pin on the lead frame.
• Since digital circuitry is typified by high amounts of transient currents due to switching, a
small amount of resistance associated with the interconnect can result in significant voltage
spikes.
• Low-level analog signals are very sensitive to such interference, thus resulting in a
contaminated analog system.
• Another significant voltage spike can occur due to the inductance of the bonding wire.
• By using separate pads and pins, the analog and the digital circuits are completely decoupled.
The current through the analog interconnect is much less abrupt than the digital; thus, the
analog circuitry now has a "quiet" power and ground.
• It is not wise to use two separate power supplies because if both types of circuits are
not powered up simultaneously, latch-up could easily result
• The resistance associated with the analog connection to ground or supply can be
reduced by making the power supply and ground bus as wide as feasible.
• The effect of the wire inductance by reserving pins closest to the die for sensitive
connections such as analog supply and ground.
Fully Differential Design
• The noise sources represent the noise from digital circuitry coupled through the parasitic stray
capacitors.
• If equal amounts of noise are injected into the differential amplifiers, then the common-mode
rejection inherent in the amplifiers will eliminate most or all of the noise.
• This depends on the symmetry of the amplifiers, meaning that matching the transistors in the
amplifier becomes crucial.
• In a mixed-signal environment, layout techniques should be used to improve matching such as
common-centroid and interdigitated techniques.
Guard Rings
• Circuits that process sensitive signals should be placed in a separate well (if possible) with
guard rings attached to the analog VDD supply.
• In the case of an n-well (only) process, the n-type devices outside the well should have
guard rings attached to analog ground placed around them.
• Digital circuits should be placed in their own well with guard rings attached to digital VDD.
• Guard rings placed around the n-channel digital devices also help minimize the amount of
noise transmitted from the digital devices.
Shielding
• A shield can take the form of a layer tied to analog ground placed between two other layers,
or it can be a barrier between two signals running in parallel.
• Avoid crossing sensitive analog signals, such as low-level analog input signals, with any digital
signals
• Digital signal carried using the top layer of metal (such as metal2), analog signal is carried by
poly layer, A strip of metal 1 can be placed between the two layers and connected to analog
ground
• Another situation that should be avoided is running an interconnect containing sensitive
analog signals parallel and adjacent to any interconnect carrying digital signals.
• Coupling occurs due to the parasitic capacitance between the lines.
• n-well can be used as a bottom-plate shield to protect analog signals from substrate noise.
Other Interconnect Considerations
• When routing the analog circuitry, minimize the lengths of current carrying paths. This will
simply reduce the amount of voltage drop across the path due to the metal 1 or metal2
resistance.
• Vias and contacts should also be used very liberally whenever changing layers. Not only does this
minimize resistance in the path, but it also improves fabrication reliablity.
• Avoid using poly to route current carrying signal paths.
• Not only is the poly higher in resistance value, but also the additional contact resistance required
to change layers will not be insignificant.
• If the poly is made wider to lower the resistance, additional parasitic capacitance will be added
to the node.
• Use poly to route only high-impedance gate nodes that carry virtually no current.