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4 views3 pages

SolB

Uploaded by

MUDIT JAIN
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CS F342 Computer Architecture

First Semester 2024-2025


Comprehensive Exam PART-B (SOLUTION KEY)
Q.1 Solution
Marking Scheme: For the first 8 correct rows [1 Mark for each row], The last 2 rows [2 marks for each row]
No marks have been awarded for any rows following an incorrect one. All entries of a row should be
correct.

Instruction Issue Begin Ex End Ex CDB Commit


LD.D 1 2 4 5 6
MUL 2 6 10 11 12
LD.D 6 7 9 10 13
MUL 7 11 15 16 17
DIV.D 13 17 22 23 24
SUB 14 15 17 18 25
ADD 18 19 21 22 26
MUL 25 26 30 31 32
ADD 26 32 34 35 36
SD.D 27 32 34 36 37

Q.2 Solution
Marking Scheme: 3 marks for each correct column. All entries of a column should be correct.
No marks have been awarded for any column following an incorrect one.

R1  6 3 8 2
b1 prediction T(GP) T(LP) T(LP) NT(GP)
b1 actual T NT T T
b2 prediction T(GP) T(GP) NT(GP) NT(LP)
b2 actual NT NT NT NT
b3 prediction T(GP) T(GP) T(LP) NT(GP)
b3 actual NT T NT NT
Q.3 Solution
a) Address division: LI: Tag=6 bits, Offset: 6 bits (1 Mark) L2: Tag=4 bits, Line=2 bits, offset=6 bits (1 Mark)
b) 1 Mark for each memory access with correct values of Tag and Data in L1 and L2 both.
L1 Cache L2 Cache
Tag Data Tag Data
101101 M[101101]

MISS

Tag Data Tag Data


101101 M[101101]

HIT L1
Tag Data Tag Data
101101 M[101101]
101100 M[101100]
MISS

Tag Data Tag Data


101010 M[101010]
101100 M[101100] 1011 M[101101]
MISS

Tag Data Tag Data


101010 M[101010] 1011 M[101100]
101101 M[101101]
HIT L2

Tag Data Tag Data


101111 M[101111] 1011 M[101100]
101101 M[101101]
MISS 1010 M[101010]

Tag Data Tag Data


101111 M[101111] 1011 M[101100]
100000 M[100000] 1011 M[101101]
MISS 1010 M[101010]

Tag Data Tag Data


101110 M[101110] 1000 M[100000]
100010 M[100010] 1011 M[101101]
MISS 1010 M[101010]
1011 M[101111]
Tag Data Tag Data
100000 M[10000]
100010 M[100010] 1011 M[101101]
HIT L2 1011 M[101110]
1011 M[101111]
Q.4 Solution

Dispatch ROM 1: 2 Marks


Table name is must to get credit.
Opcode Name Label
101010 Store 2 word S2D

Main Table:

Label ALU SRC1 SRC2 Register Memory PC Write Seq.


Control Control control
S2D Read rd Seq
B R[rd]
ADD B 4 Read rt Write B SW2
BR[rt] M[R[rd]] A
*SW2 Write ALU Fetch
M[ALUout]B

After decode stage R[rs] value is present in A and R[rt] value is present in B.
The SW2 is already present in the main table. NO need to write explicitly.

Marking Scheme: 3 Marks for the row with S2D label and 4 Marks for the next row.
Total 5 cycles are required.
Solution with 6 cycles and additional entry in the main table attracts penalty.
Solution with more than 6 cycles and/or with Dispatch ROM 2 are awarded 0 marks.

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