DIGITAL LOGIC DESIGN 1

Dr. Eng. Alaa Rabie

THE IMPORTANCE OF DIGITAL LOGIC
THE IMPORTANCE OF DIGITAL LOGIC
COURSE OBJECTIVES
 Understand the theory of operation for most of digital electronic
devices.
 Analyze how a digital computer performs complex operations, based
on simply manipulating bits (0s and 1s).
 learn how to realize a logic function with different numbers of inputs
and outputs.
 Optimize the function realization.
 Design digital logic systems
TEXT AND REFERENCE BOOKS
STUDENT ASSESSMENT METHOD
Item percentage

Assignments 10%
Quizzes &Project 10%
Midterm Exam 20%
Practical Exam 20%

Final Exam 40%

COURSE OUTLINE

CHAP I. COMBINATIONAL LOGIC CIRCUITS

CHAP II COMBINATIONAL MODULES AND SUBSYSTEMS.
CHAP III SEQUENTIAL CIRCUITS.

CHAP IV REGISTERS & MEMORY ELEMENTS.

 DIGITAL LOGIC LEVELS

• Digital logic circuits are hardware components that manipulate binary

information (we call these gates)
• A digital system is basically a black box with a minimum of one input and
one output
• Inside this box, are millions of switches called transistors
• Transistors perform different functions according to inputs
• In binary logic circuits there are only two levels: 0 and 1
DIGITAL LOGIC LEVELS
What is the physical meaning of logic 0 and logic 1?

Electrical signals (voltages or currents) that exist in a digital system are in

either of two recognizable values (logic 1 or logic 0)
DIGITAL LOGIC GATES
There are three fundamental logical operations, from which all
other functions, no matter how complex, can be derived. These
Basic functions are named:

 AND
 OR
 NOT (INVERTER)

Each of these has a specific symbol and a clearly-

defined behavior
AND Gate (Logic Product)

 Represented by any of the following

notations:
 X AND Y
 X.Y
 XY
 Function definition:
Z=1 only if X=Y=1
0 otherwise
 OR Gate(Logic Sum)

 Represented by any of the following

notations:
 X OR Y
 X+Y
 XvY
 Function definition:

1 if X=1 or Y =1 or both X=Y=1

Z=
0 if X=Y=0
NOT (Inverter) Gate

 Represented by a bar over the variable X’

Function definition:
Z is what X is not

It is also called the complement operation,

as it changes 1s into 0s and 0s into 1s.
HOW TO DESCRIBE A LOGIC SYSTEM?

By using one of the following two methods:

• A Truth Table

• A Boolean Expression
 TRUTH TABLES
A Truth Table is a table of combinations of the binary variables showing
the relationship between the different values that the (input) variables take
and the result of the operation (output).

The number of rows in the Truth Table is 2n , where n = number of input

variables in the function.

The binary combinations are obtained from the binary number by counting
from 0 to (2n – 1)
TRUTH TABLES
Example: AND gate with 2 inputs n=2

The truth table has 22 rows = 4

The binary combinations are from

0 to (22-1=(3)) {00,01,10,11}
BOOLEAN EXPRESSIONS
We can use these basic operations to form more complex
expressions:
f(x,y,z) = (x + y’)z + x’
Some terminology and notation:
f is the name of the function
(x,y,z) are the input variables, each representing 1 or 0. Listing
the inputs is optional, but sometimes helpful
A literal is any occurrence of an input variable or its complement.
The function above has four literals: x, y’, z, and x’
BOOLEAN EXPRESSIONS
Precedencies are important, but not too difficult

NOT has the highest precedence, followed by AND, and then OR

Fully parenthesized, the function above would be kind of messy:

f(x,y,z) = (((x +(y’))z) + x’)

BOOLEAN EXPRESSIONS FROM TRUTH TABLES
Each 1 in the output of a truth table specifies one term in the
corresponding Boolean expression
The expression can be read off by inspection…

F is true when:
A is false AND B is true AND C is false
OR
A is true AND B is true AND C is true

F = A’BC’ + ABC
F=?

F = A’B’C +
A’BC’ +
AB’C’ +
ABC
LAWS & RULES OF BOOLEAN ALGEBRA
The basic laws of Boolean algebra
The commutative law
The associative law
The distributive law
COMMUTATIVE LAW
The commutative law of addition for two variables is

A+B = B+A

The commutative law of multiplication for two variables is

AB = BA
ASSOCIATIVE LAW
The associative law of addition for 3 variables is
A+(B+C) = (A+B)+C

The associative law of multiplication for 3 variables is

A(BC) = (AB)C
DISTRIBUTIVE LAW
The distributive law for multiplication is
A(B+C) = AB + AC

The distributive law for addition is

A+(B.C) = (A+B)(A+C)
BASIC THEOREMS OF BOOLEAN ALGEBRA
DEMORGAN’S LAW
(AB)’ =A’+B’

(A+B)’ = A’ B’

(ABCD)’=A’ + B’+ C’ + D’
(AB+CD)’=(AB)’ (CD)’= (A’+B’) (C’+D’)
EXAMPLE
Get the logic function from the following truth table and implement it
using basic logic gates (AND, OR, NOT) State X0 X1 X2 Y
0 0 0 0 1
Y=F(X0,X1,X2)=∑(0,2,5,7) X0’.X1’.X2’

1 0 0 1 0

2 0 1 0 1 X0’.X1.X2’

3 0 1 1 0

4 1 0 0 0

5 1 0 1 1 X0.X1’.X2

6 1 1 0 0

7 1 1 1 1 X0.X1.X2
Y = X0’.X1’.X2’ + X0’.X1.X2’
+X0.X1’.X2 + X0.X1.X2
DERIVED GATES
DIGITAL LOGIC DESIGN 1
Lecture 2

Dr. Eng. Alaa Rabie

SIMPLIFICATION OF THE LOGIC FUNCTION
F(A,B)=A’B’ + A’B + AB’

By using simplification rules, we can optimize the design, so that it is implemented

with a minimum number of gates.
BASIC THEOREMS OF BOOLEAN ALGEBRA
F(A,B)=A’B’ + A’B + AB’
= A’ * (B’ + B) + A * B’ (Distributivity)
= A’ * (B + B’) + A * B’ (Commutativity)

= A’ * 1 + A * B’ (A+A’= 1)

= A’ + (A * B’) (A+A’B)=(A+B) (11)

= (A’ + B’) (De Morgan’s)

= (A B)’
1 GATE (NAND) ONLY
STANDARD FORMS OF REPRESENTING BOOLEAN FUNCTIONS
•Sum of Products (SOP)

•Product of Sums (POS)

SUM OF PRODUCTS (SOP)
SUMMING (ORing) PRODUCT (ANDed) terms, Product terms are known as minterms.

Example:
Example:
PRODUCT OF SUMS (POS)
PRODUCT (ANDing) of SUM (ORed) terms, Sum terms are known as Maxterms.

Example:
Example:
Example:
SOP AND POS REPRESENT THE SAME FUNCTION GATES

F=m(1,3,5,6,7) F=M(0,2,4)
POS VERSUS SOP
• Any expression can be written either way
• We can convert from one form to the other using theorems

• Sometimes SOP looks simpler

AB + CD = ( A + C )( B + C )( A + D )( B + D )

• Other times POS looks simpler

(A + B)(C + D) = BD + AD + BC + AC

• However, SOP is most commonly used

 TASK(1)

• Realize the logic Function

y=F(A,B,C)=∑(2,5,7) Using SOP, POS
which is better?
• Realize the logic Function
g=F(X,Y,Z)=∑(0,1,2,5,7) Using POS, SOP
which is better?
MINIMIZATION OF LOGIC FUNCTIONS
We have chips with millions of gates
Why care about minimizing a function?
What do a few gates matter?
Basic logic functions are replicated thousands of times
Saving one gate for a memory cell pays off
What is the criterion for minimization?
Should we minimize the…
Number of product terms?
Number of logic operations?
Number of variables (literals)?
Number of wires?
…?
For implementation: minimize the number of gates!
HOW TO MINIMIZE THE GATE COUNT?
Example: F=A’BC’+AB’C’+AB’C+ABC’= Σm(2,4,5,6)
How many gates do we need for implementation?
If AND gates have 3 inputs and OR gates have 4 inputs?
If all gates are binary (2 inputs)?
Are there any tricks we can use?
Combine minterms:
A’BC’+ABC’=BC’
AB’C’+AB’C=AB’
F = BC’+AB’
How many gates does F need now?
This mainly depends on your experience but we need a systematic approach to minimize
Boolean expressions Answer: Karnaugh maps (K-maps)
KARNAUGH MAPS (STATES MAP)
• Karnaugh maps (K-maps) are graphical representations of Boolean functions
• One map cell corresponds to a row in the truth table
• Also, one map cell corresponds to a minterm or a maxterm in the Boolean expression
• Multiple-cell areas of the map correspond to standard terms
•The ordering of variables is important for 𝑓(𝑥,𝑦), 𝑥 is the row, 𝑦 is the
The two-variable map
column
•For the K map on the left, cell 0 represents 𝑥′𝑦′; cell 1 represents 𝑥′𝑦,
etc…
Example:
F = x’y + xy’ + xy
The1s and 0s represent a function in a K-map
A 1 represents the On-set (F=1), while a 0 represents the Off-set (F=0)
Similar to the truth table

1 1
 Any two adjacent cells in the map
differ by ONLY one variable
y
1

1 1
X

F = x’y + xy’ + xy = x+y

Example:
𝐹(𝑥1,𝑥2)=𝑥1′𝑥2′+ 𝑥1′ 𝑥2+ 𝑥1 𝑥2′
=𝑚0+𝑚1+ 𝑚2

𝑥1′
1 1 𝐹(𝑥1,𝑥2)= 𝑥1′+𝑥2′
𝑥2′
1
Three-variable map

Note that the minterms are arranged, not in a binary sequence, but in a
sequence similar to the Gray code
The characteristic of this sequence is that only one bit changes in value
from one adjacent column to the next.
NOTES ON A 3-VARIABLE MAP

• The number of adjacent cells that may be combined must always represent
a number that is a power of two, such as 1, 2, 4 and 8
• As more adjacent cells are combined, we obtain a product term with fewer
literals
• One cell represents one minterm, giving a term with 3 literals
• Two adjacent cell represent a term with 2 literals
• Four adjacent cells represent a term with 1 literal
• Eight adjacent cells encompass the entire map and produce a function that
is always equal to logic 1
Example: Simplify the Boolean expression: F𝑥,𝑦,𝑧=Σ(2,3,4,5)

𝑥′𝑦
1 1

1 1

𝑥𝑦′
F(𝑥,𝑦,𝑧)=𝑥𝑦′+𝑥′𝑦
Example: Simplify the Boolean expression: F𝑥,𝑦,𝑧=Σ(3,4,6,7)

1 1 1

𝑥𝑧′ 𝑦z
F(𝑥,𝑦,𝑧)=𝑦𝑧+𝑥𝑧′
Example: Simplify the Boolean expression: F(𝑥,𝑦,𝑧)=Σ(0,2,4,5,6)

1 1

1 1 1

𝑧′ 𝑥𝑦′

F(𝑥,𝑦,𝑧)=𝑧′+𝑥𝑦′
Example:
Let the Boolean function 𝐹(𝐴,𝐵,𝐶)=𝐴′𝐶+𝐴′𝐵+𝐴𝐵′𝐶+𝐵𝐶
(a) Express this function as a sum of minterms
(b) Find the minimal SOP expression

𝐹(𝐴,𝐵,𝐶)=𝛴(1,2,3,5,7) 1 1 1

1 1 A’B

F = C + A’B
c
 FOUR-VARIABL E K-MAP
The map for Boolean
functions of four binary

• Remember that the cells in the top row are adjacent to the cells in the bottom row
• Remember that cells in the most left column are adjacent to cells in the most right column
• Remember that cells in the four corners
are adjacent to each other
NOTES ON A 4-VARIABLE MAP
• The number of adjacent squares that may be combined must always
represent a number that is a power of two, such as 1, 2, 4, 8 and 16
• As more adjacent squares are combined, we obtain a product term with
fewer literals
• One square represents one minterm, giving a term with 4 literals
• Two adjacent squares represent a term with 3 literals
• Four adjacent squares represent a term with 2 literals
• Eight adjacent squares represent a term with 1 literal
• Sixteen adjacent squares encompass the entire map and produce a function
that is always equal to logic 1
Example: Simplify the Boolean function
F (w, x, y, z) = Σ (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

𝑤′𝑧′
1 1 1

𝐹(𝑤,𝑥,𝑦,𝑧)=𝑦′+𝑤′𝑧′+𝑥𝑧′ 1 1 1

𝑥𝑧′ 1
1 1

𝑦′ 1 1
Example: Simplify the Boolean function
F (A,B,C,D) = A’B’C’ + B’CD’ + A’BCD’ + AB’C’
A’CD’

1 1 1
B’C’ B’D’
1

1 1 1
F = B’D’ + B’C’ + A’CD’
Thank you
DIGITAL LOGIC DESIGN 1
Lecture 3

Dr. Eng. Alaa Rabie

 FOUR-VARIABL E K-MAP
The map for Boolean
functions of four binary

• Remember that the cells in the top row are adjacent to the cells in the bottom row
• Remember that cells in the most left column are adjacent to cells in the most right column
• Remember that cells in the four corners
are adjacent to each other
NOTES ON A 4-VARIABLE MAP
• The number of adjacent squares that may be combined must always
represent a number that is a power of two, such as 1, 2, 4, 8 and 16
• As more adjacent squares are combined, we obtain a product term with
fewer literals
• One square represents one minterm, giving a term with 4 literals
• Two adjacent squares represent a term with 3 literals
• Four adjacent squares represent a term with 2 literals
• Eight adjacent squares represent a term with 1 literal
• Sixteen adjacent squares encompass the entire map and produce a function
that is always equal to logic 1
Example: Simplify the Boolean function

F (w, x, y, z) = Σ (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

𝑤′𝑧′
1 1 1

𝐹(𝑤,𝑥,𝑦,𝑧)=𝑦′+𝑤′𝑧′+𝑥𝑧′ 1 1 1

𝑥𝑧′ 1
1 1

𝑦′ 1 1
Example: Simplify the Boolean function
F (A,B,C,D) = A’B’C’ + B’CD’ + A’BCD’ + AB’C’
A’CD’

1 1 1
B’C’ B’D’
1

1 1 1
F = B’D’ + B’C’ + A’CD’
DON’ T-CARE CONDITIONS
In practice, in some applications the function is not specified for certain combinations
of the variables.

These don’t-care conditions can be used on a map to provide further simplification

of the Boolean expression

To distinguish the don’t-care condition from 1’s and 0’s, an X is used. Thus, an X
inside a square in the map indicates that we don’t care whether the value of 0 or 1 is
assigned.
Example: Simplify the Boolean function
F (w, x, y, z) = Σ (1, 3, 7, 11,15)
which has the don’t-care conditions: d (w, x, y, z) = Σ(0, 2, 5)

X 1 1 X
𝑤′x′ X 1
𝑤′z
1

1
𝑦z 𝑦z
PRODUCT OF SUMS SIMPLIFICATION USING K-MAPS
• Use the SOP simplification on the zeros of the function in the K-map to get 𝐹’
• Find the complement of 𝐹’, i.e. 𝐹’′=𝐹
• Recall that the complement of a Boolean function can be obtained by using
De Morgan’s theorem

How to generate a POS from a K-map?

• Use duality of Boolean algebra (De Morgan’s law)

• Look at the 0s in map instead of the 1s
• Generate blocks around the 0s
This gives the inverse of 𝐹
Use duality to generate POS
Example: 𝐹= (0,1,2,5,8,9,10)

𝐹′=𝐴𝐵+𝐶𝐷+𝐵𝐷′

𝐹=(𝐴′+𝐵′)(𝐶′+𝐷′)(𝐵′+𝐷)
GATE IMPLEMENTATION
Example: Given the K-map below, produce the 𝐹′ from the zeros in the map and
then obtain 𝐹 from it

𝐹′=AB′+AC′+A′BCD ′
𝐹=(AB′)’(AC′)’(A′BCD′ )’
𝐹=(𝐴′+𝐵)(𝐴′+𝐶)(𝐴+𝐵′+𝐶′+𝐷)
NAND AND NOR IMP L EMENTAT ION
Digital circuits are frequently constructed with NAND or NOR gates rather
than with AND and OR gates. NAND and NOR gates are easier to fabricate
with electronic components and are the basic gates used in all IC digital
logic families

Because of the prominence of NAND and NOR gates in the design of digital
circuits, rules and procedures have been developed for the conversion from
Boolean functions given in terms of AND, OR, and NOT into equivalent
NAND and NOR logic diagrams.
NAND Circuits
The NAND gate is said to be a universal gate because any logic circuit
can be implemented with it.
To show that any Boolean function can be implemented with NAND
gates, we need only show that the logical operations of AND, OR, and
complement can be obtained with NAND gates alone.
The implementation of Boolean functions with NAND gates requires that the functions
be in sum-of-products form.

1.Inverter
2. AND gate

3. OR gate
Example: Implement the Boolean expression. F = AB + CD
(a) with AND and OR gates (b) NAND gate only

(b) Applying De Morgan two times we can get NAND expressions as:

F =F’’= (AB + CD)’’

=((AB)’ . (CD)’)’

= (AB)’’ +(CD)’’= AB + CD
Example: Implement the following Boolean function with NAND gates:
F (x, y, z) = (1, 2, 3, 4, 5, 7)

𝑥′𝑦
F = xy’ + x’y + z 1 1 1

1 1 1
𝑥𝑦′ z
F =F’’= (xy’ + x’y + z)’’

F =F’’= ((xy’)’ . (x’y)’ . (z)’)’

NOR Implementation
The NOR gate is another universal gate that can be used to implement any
Boolean function. The implementation of the complement, OR, and AND
operations with NOR gates is shown in Figures
1.Inverter

2. AND gate
3. OR gate

4. NAND gate
Example: Implement the Boolean expression using NOR gates only.
X = (A+B ) (C+D)
Applying De Morgan two times we can get Nor expressions as:
• Consider the expression Y= BC+ A’ B D’ + A B’ D’.
Applying De Morgan two times we can get NAND expressions as:

Y= ((BC)’( A’ B D’ )’( A B’ D’)’ )’ = ( U V W)’.

And the resulting electronic circuit will be as shown.

Y= BC+ A’ B D’ + A B’ D’= ( (BC)’ ( A’ B D’ )’ ( A B’ D’ )’ )’

ABCD A’ B’ D’
• Consider the expression Y= BC+ A’ B D’ + A B’ D’.
Applying De Morgan two times we can get NOR expressions as:

Y= BC+ A’ B D’ + A B’ D’
= ( (BC)’ ( A’ B D’ )’ ( A B’ D’ )’ )’ ABCD A’ B’ C’

= ( (B’+C’) ( A+B’+ D ) ( A’+B+D ) )’

= (B’+C’)’+ ( A+B’+ D)’+ ( A’+B+D)’

And the resulting electronic circuit will be as shown.

Thank you
DIGITAL LOGIC DESIGN 1
Lecture 4

Dr. Eng. Alaa Rabie

 COMBINATIONAL LOGIC

• Combinational logic circuits can have any number of inputs and outputs
• The logic states of the inputs at any given instant
determine the state of the output

• Sequential circuits, which we will discuss later in this course, will feature
circuits in which the outputs are not determined solely by the inputs at the
same time
HOW TO DESIGN A COMBINATIONAL LOGIC CIRCUIT?

1.From the specifications of the circuit, determine the required number

of inputs and outputs and assign a letter (symbol) to each

2.Derive the truth table that defines the required relationship between
the inputs and outputs

3.Obtain the simplified Boolean functions for each output as a function

of the input variables (using a K-map)

4.Sketch the logic diagram

DESIGN PROBLEM

Design a digital system whose output is defined as logically low

if the 4-bit input binary number is a multiple of 3; Otherwise, the
output will be logically high. The output is defined if and only if
the input binary number is greater than 2
A B C D Decimal Y
0 0 0 0 0 X
0 0 0 1 1 X
0 0 1 0 2 X
0 0 1 1 3 0
0 1 0 0 4 1
0 1 0 1 5 1
0 1 1 0 6 0
0 1 1 1 7 1
1 0 0 0 8 1
1 0 0 1 9 0
1 0 1 0 10 1
1 0 1 1 11 1
1 1 0 0 12 0
1 1 0 1 13 1
1 1 1 0 14 1
1 1 1 1 15 0
𝑌𝑆𝑂𝑃=𝐵′𝐷′+𝐴′𝐶′+𝐴′𝐵𝐷+𝐵𝐶′𝐷+𝐴𝐵′𝐶+𝐴𝐶′
𝑌𝑃𝑂𝑆=(𝐴+𝐵)(𝐵+𝐶+𝐷′)(𝐴+𝐶′+𝐷)(𝐴′+𝐵′+𝐶+𝐷)(𝐴′+𝐵′+𝐶′+𝐷′)
ARITHMETIC CIRCUITS
• We will continue with the design of digital logic circuits, One of the
famous digital logic circuits is the calculator, How to design it?
• An arithmetic circuit is a combinational circuit that performs arithmetic
operations such as:
• Addition
• Subtraction
• Multiplication
• Division
• A combinational circuit that performs the addition of two bits is
called a Half Adder

So, we need two binary outputs to represent the addition block

(carry & sum)
HALF ADDER
It is required to design a combinational circuit that adds two binary numbers
and produces the output in the form of two bits, sum and carry

Solution:
1.We need to determine the inputs and output of the system and give
letters for all of them: Our system has two inputs (x, y) and two outputs
(S, C)
2.Derive the truth table according to the given relation
between inputs and outputs

3.Obtain the simplified Boolean functions for each output as a function of the input
variables using a K-map

𝑆=𝑥𝑦′+𝑥′𝑦 =𝑥⊕𝑦 𝐶=𝑥𝑦

4.Sketch the logic diagram
FULL ADDER
It is required to design a combinational circuit that adds three binary
numbers and produces the output in the form of two bits, sum and carry
Solution:
1.We need to determine the inputs and outputs of the system and give letters
for all of them: Our system has three inputs (x, y, z) and two outputs (S, C)
2.Derive the truth table according to the given relation between the inputs
and outputs
3.Obtain the simplified Boolean functions for each output as a function of the
input variables using a K-map

𝑆=𝑥′𝑦′𝑧+𝑥′𝑦𝑧′+𝑥𝑦′𝑧′+𝑥𝑦𝑧

=𝑧(𝑥′𝑦′+𝑥𝑦)+𝑧′(𝑥′𝑦+𝑥𝑦′)
3.Obtain the simplified Boolean functions for each output as a function of the
input variables using a K-map

𝐶=𝑥𝑦+𝑥𝑧+𝑦𝑧
4.Sketch the logic diagram

𝑆=𝑥′𝑦′𝑧+𝑥′𝑦𝑧′+𝑥𝑦′𝑧′+𝑥𝑦𝑧 𝐶=𝑥𝑦+𝑥𝑧+𝑦𝑧
𝑆= 𝑥⊕𝑦⊕𝑧
• The logic circuit for the full adder could also be sketched using two half
adders and a single OR gate
 4-BIT BINARY RIPPLE CARRY ADDER
• Connecting n full adders in cascade allows us to add n-bit binary numbers together
Example: Connecting 4 full adders in cascade allows us to add 1011 to 0011.
 BINARY SUBTRACTOR
• The subtraction of binary numbers can be easily done using complements
• The subtraction 𝐴−𝐵 is done by taking the 2’s complement of 𝐵 and
adding it to 𝐴

• The 2’s complement can be obtained by taking the 1’s complement and
adding 1 to the least significant bit (LSB)

• The 1’s complement can be implemented easily with an inverter gate

• We can add 1 to the sum by making the initial input carry of the parallel
adder equal to 1
SUBTRACTION EXAMPLE

1’s Complement 2’s Complement

BINARY ADDER/SUBTRACTOR

• Subtractor

• Adder/Subtractor

If 𝐶𝑖𝑛=0, circuit acts as an Adder

If 𝐶𝑖𝑛=1, circuit acts as a Subtractor
BINARY MULTIPLIER
2 bits × 2 bits = max 4 bits
It is required to design a circuit to multiply 2 binary
numbers 𝐴={𝐴2𝐴1𝐴0} and 𝐵={𝐵3𝐵2𝐵1𝐵0}.
 DECODERS
• A Decoder is a combinational circuit that converts binary
information from 𝑛 input lines to a maximum of 2𝑛 unique
output lines.

• Consider a vending machine that takes 3 bits as input

and releases a single product, out of the available 8
product sorts
• It is required to design a combinational circuit with two inputs (𝑎,𝑏) and
four outputs (𝐷0,𝐷1,𝐷2,𝐷3), such that:

• 𝐷0=1 when 𝑎=0 and 𝑏=0

• 𝐷1=1 when 𝑎=0 and 𝑏=1
• 𝐷2=1 when 𝑎=1 and 𝑏=0
• 𝐷3=1 when 𝑎=1 and 𝑏=1
Solution

1.From the specifications of the circuit, determine the

required number of inputs and outputs and assign a
letter (symbol) to each
2.Derive the truth table that defines the required relationship between the
inputs and outputs

3.Obtain the simplified Boolean functions for

each output as a function of the input
variables
𝐷0=𝑎′𝑏′
𝐷1=𝑎′𝑏
𝐷2=𝑎𝑏′
𝐷3=𝑎𝑏
4.Sketch the logic diagram
3×8 DECODER
• A 3×8 line decoder decodes 3 input
bits into one of 8 possible outputs
• Each output represents one of the
minterms of the 3 input variables
IMPLEMENTING FUNCTIONS USING DECODERS
• Any combinational circuit can be constructed using decoders and OR
gates (the decoder generates the minterms and the OR gate performs
the summation)
• Example: Implement a full adder circuit with a decoder and two OR gates

• Full adder equations:

𝑆(𝑥,𝑦,𝑧)=Σ𝑚(1,2,4,7) and
𝐶(𝑥,𝑦,𝑧)=Σ𝑚(3,5,6,7)
• Since there are 3 inputs, we need a 3×8 decoder
DECODER EXPANSIONS
• Larger decoders can be constructed using a number of smaller ones
• For example, a 3×8 decoder
can be built using a couple of
2×4 decoders and a 4×16
decoder can be built using a
couple of 3×8 decoders
• Can you sketch a 4×16 decoder using a number of 2×4 decoders
Make use a (3—8) and (2—4) decoders to make a (5—32 decoder).
c
3 to 8
d decoder
e
c’d’e’ c’d’e c’de’ c’de cd’e’ cd’e cde’ cde 5-32
DECODER
a’b’
y0 y7
y1

a a’b
y15
b y14

2 to 4
decoder
ab’
y16 y23

ab y30
y31
 ENCODERS
• An encoder is a digital circuit that performs the inverse operation of
a decoder
• An encoder has 2𝑛 input lines and 𝑛 output lines
• The output lines generate the binary equivalent of the input line
whose value is 1 a b c d X Y
X
a X= c + d
b
X
1 0 0
c Encoder Y 1 0 1 Y= b + d Y

d
1 1 0
a b c d
1 1 1
8×3 OCTAL-TO-BINARY ENCODER

𝑥=𝐷4+𝐷5+𝐷6+𝐷7
𝑧=𝐷1+𝐷3+𝐷5+𝐷7
𝑦=𝐷2+𝐷3+𝐷6+𝐷7
ENCODER BY DIODE MATRIX
a
X= c+ d , Y= b + d
b

X Y

5-10 5-10
KΩ KΩ
ROM (read only memory) code conversion system
• ROM=DECODER+ENCODER
m
K=2 lines

X0 Y0
X1 Y1
m to K K to n
Decoder Encoder

Xm-1
Yn-1

n >= m
 EXAMPLE FOR ROM
a b W0 W1 W2 W3 Y0 Y1 Y2 Y3 Y4
0 0 1 0 1 0 1 0
0 1 1 0 0 1 0 1
1 0 1 1 0 1 1 0
1 1 1 1 1 0 0 1

W0=a b ;w1=a b ;w2 =a b; w3=a b AND gates

Y0=w2+w3 ;y1=w0+ w3;y2=w1+w2; y3=w0+w2;y4=w1+w3 OR gates

 EXAMPLE FOR ROM (CONT.1)

W0=a b ;w1=a b ;w2 =a b; w3=a b AND gates

Y0=w2+w3 ;y1=w0+ w3;y2=w1+w2; y3=w0+w2;y4=w1+w3 OR gates

ab a b
W0

W1

W2

W3
 EXAMPLE FOR ROM (CONT.1)
W0=a b ;w1=a b ;w2 =a b; w3=a b AND gates

Y0=w2+w3 ;y1=w0+ w3;y2=w1+w2; y3=w0+w2;y4=w1+w3 OR gates

ab a b
W0

W1

W2

W3

Y0 y1 y2 y3 y4
 EXAMPLE FOR ROM (CONT.2)
Using Diode Matrix

Y0=w2+w3 ;y1=w0+ w3;y2=w1+w2; y3=w0+w2;y4=w1+w3 OR gates

ab a b
W0

W1

W2

W3

Y0 y1 y2 y3 y4
 ASSIGNMENT ON ROM
• Design and implement a ROM which converts from BCD to a
seven segment display
Thank you
DIGITAL LOGIC DESIGN 1
Lecture 5

Dr. Eng. Alaa Rabie

MAGNITUDE COMPARATOR
Two bit comparator
It is required to design a circuit to compare between two binary bits
A B G E L
G 0 0 0 1 0
A 2bit
E 0 1 0 0 1
comparator
B 1 0 1 0 0
L
1 1 0 1 0
A B

< G
G =AB’
E =A’B’ + AB =A . B = E

L =A’B > L
 MAGNITUDE COMPARATOR
• It is required to design a circuit to compare between two inputs 𝑨={𝑨𝟎,𝑨𝟏}
and 𝑩={𝑩𝟎,𝑩𝟏}. Both inputs consist of two binary bits and the circuit has
three outputs:
Greater than, Less than or Equal
Solution:
1.We need to determine the inputs and outputs of the system and give
letters for all of them: Our system has four inputs (𝐴0,𝐴1, 𝐵0, 𝐵1) and
three outputs (𝐺,𝐿,𝐸)
2.Derive the truth table that defines the required relationship between
the inputs and outputs
3.Obtain the simplified Boolean functions for each output as a function of the input
variables using a K-map

Greater than Function

3.Obtain the simplified Boolean functions for each output as a function of the input
variables using a K-map

Equal Function
3.Obtain the simplified Boolean functions for each output as a function of the input
variables using a K-map

Less than Function

4.Sketch the logic diagram for the output 𝐺
Greater than Circuit
4.Sketch the logic diagram for the output E Equal Circuit
4.Sketch the logic diagram for the output L
Less than Circuit
MAGNITUDE COMPARATOR
• The previous example compared two 2-bit numbers, resulting in a truth
table with 16 rows
• Clearly, if we are interested in comparing two numbers that are larger,
the design complexity increases rapidly
• Thus, we need a way to design magnitude comparators and at the same
time does not follow the usual 4 steps of combinational logic design
• The following slides outline the design procedure for a magnitude
comparator that takes as input two 4-bit numbers
• Such an example can be easily extended to deal with larger numbers
4-BIT MAGNITUDE COMPARATOR EXAMPLES
MAGNITUDE COMPARATOR
• Consider two numbers with 4-bits each: 𝐴=𝐴3𝐴2𝐴1𝐴0 and 𝐵=𝐵3𝐵2𝐵1𝐵0

• These two numbers would be equal if all pairs of their significant digits
are equal: 𝐴3=𝐵3,𝐴2=𝐵2,𝐴1=𝐵1 and 𝐴0=𝐵0
• Since the numbers are binary, the digits are either 1
or 0, and the equality of each pair of bits can be
expressed logically with an XNOR function as

𝒙𝒊=𝑨𝒊𝑩𝒊+𝑨′𝒊 𝑩′𝒊 𝑓𝑜𝑟 𝑖=0,1,2,3

Such that 𝑥𝑖=1 only if the pair of bits in position 𝑖 are equal (i.e. if both are
1 or both are 0)
MAGNITUDE COMPARATOR
• To determine whether 𝐴 is greater or less than 𝐵, we inspect the relative
magnitudes of pairs of significant digits
• We do so starting from the most significant position (𝐴3 and 𝐵3)
• If the 2 digits of a pair are equal, we compare the next lower significant
pair of digits
• This comparison continues until a pair of unequal digits is reached
• If the corresponding digit of 𝐴 is 1 and that of 𝐵 is 0, we conclude that
𝐴>𝐵, otherwise 𝐴<𝐵
A0 <
=
B0 > < G

A1 <
=
B1 >
= E

A2 <
=
>
B2

A3 <
= > L
>
B3
A0 <
=
B0 > < G

A1 <
=
B1 >
= E

A2 <
=
>
B2

A3 <
= > L
>
B3
 ASSIGNMENT
• Find from the data sheet the IC which makes a 4 bit
comparison.
• Keep by heart its number and its pin assignment
• Design an 8 bit comparator.
 MULTIPLEXERS

MAKING CONNECTIONS
• Direct point-to-point connections between gates are made up of wires

• Routing one of many inputs to a single output is carried out using a multiplexer

• Routing a single input to one of many outputs is carried out using a demultiplexer
MULTIPLEXERS
• A multiplexer is used to connect 2𝑛 points to a single point
• The control signal pattern forms the binary index of the input to be
connected to the output
I0
I1
I2
Z Z=only one of the inputs
n to 1
MUX depending on k control inputs :
2k =n
In-1

C0 C1…...Ck-1
2×1 LINE MULTIPLEXER
4×1 LINE MULTIPLEXER

Z= S0 S1 I0 + S0 S1 I1 + S0 S1 I2+ + S0 S1 I3
8×1 LINE MULTIPLEXER
MULTIPLEXERS AS GENERAL-PURPOSE LOGIC
• A 2𝑛−1:1 multiplexer can implement any function of 𝑛 variables

•Steps:
1.The Boolean function is listed in a truth table
2.The first 𝑛−1 variables in the table are applied to the selection
inputs of the MUX
3.For each combination of the selection variables, evaluate the
output as a function of the last variable
4.The values are then applied to the data inputs in the proper order
EXAMPLE
𝐹(𝑥,𝑦,𝑧)=Σ(1,2,6,7)
EXAMPLE II 𝐹(𝐴,𝐵,𝐶,𝐷)=Σ(1,3,4,11,12,13,14,15)

𝐷
𝐷

𝐷’
0
0

1
1
DE-MULTIPLEXER
Y0
x Y1
1 to n Y2 According to the control signals;
DEMUX ONE ONLY of the outputs = X
Yn-1

C0 C1…...Ck-1

Example C0 C1 Y0 Y1 Y2 Y3
Y0 0 0 x 0 0 0
x 1 to 4 0 1 0 x 0 0
Y1
DEMUX Y2 1 0 0 0 x 0
Y3
1 1 0 0 0 x
C0 C1
Y0=C0. C1. X; Y1=C0. C1. X; Y2 = C0. C1. X ;Y3=C0. C1. X
Y0=C0. C1. X; Y1=C0. C1. X;Y2 = C0. C1. X ;Y3=C0. C1. X

C0 C1 C0’ C1’ X

Y0

Y1

Y2

Y3
PARITY BITS
• XOR functions are very useful in systems requiring error detection and
correction (e.g. communication systems)
• A parity bit is used to detect errors that occur during the transmission of
binary information
• A parity bit is an extra bit included with a binary message to make the
number of 1s either even or odd

• The message, including the parity bit, is transmitted and then checked for
errors at the receiver
Simplest Error Detection: Parity Checks
Even Parity : Sum of 1s is even
Odd Parity : Sum of 1s is odd
• An error is detected if the checked parity does not correspond with the
one transmitted

• The circuit that generates the parity bit in the transmitter is called a
parity generator

• The circuit that checks the parity bit in the receiver is called a parity
checker

• The purpose of generating a parity checker to generate a number of

bits to be added to the required to send word bits then we can get a
fixed new output capable to verify the correctness of the sent word
AN EXAMPLE OF EVEN PARITY
• Consider a three-bit message to be
transmitted together with an even-parity
bit
• For even parity, the bit P must be
generated to make the total number of
1s even
• P is an odd function, thus we can
express it using the XOR operator as

𝑃=𝑥⊕𝑦⊕𝑧
PARITY GENERATOR AND CHECKER CIRCUITS
• A parity generator/checker circuit
can be implemented in a single circuit
• This is done if the input P is
connected to logic 0 and the output
is marked with P
• This is done if the input P is connected 0 Parity Generator
to logic 0 and the output is marked
with P P Parity Checker
𝑧⊕0=𝑧
EXAMPLE: CONSIDER WE NEED TO SEND 4 BIT a b c d Zodd Ycheck
WORD (ABCD) 0 0 0 0 0 0
Then we find Zodd ; So the new word is (abcdZodd) ; 0 0 0 1 1 0
so when receiving the new word the check bit Ycheck 0 0 1 0 1 0
will be 0 for correct word 0 0 1 1 0 0
d 0 1 0 0 1 0
Zodd
0 1 0 1 0 0
0 1 0 1
0 1 1 0 0 0
1 0 1 0
0 1 1 1 1 0
0 1 0 1 b 1 0 0 0 1 0
a 1 0 1 0 1 0 0 1 0 0
1 0 1 0 0 0
c
1 0 1 1 1 0
1 1 0 0 0 0
Zodd = (a b) (c d) 1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 0
HOW WE CAN GENERATE ZOUT IN A TREE SHAPE?
a

b
Zodd

n=4 bits Level 1 level 2

Number of levels = log2 (n)= 2 levels

Number of XOR gates =n-1 =3
EXAMPLE DESIGN AN ODD VARIABLE AS A BIT TO
BE ADDED TO 8 BIT WORD

d Zodd

f
We have 3 levels
g And (8-1)=7 XOR gates
h
 ASSIGNMENT
1.A ROM has to be designed to find the solution of the equation
• y = x2+1, for (0 ≤ x ≤ 9) ;
2. Design a single bit comparator. Then design a 6 bit comparator.
3. Implement the logic function y=Σ (0, 2, 4, 6, 9, 11, 13, 15). Once
by zeros and another by ones. Verify the result on the two solutions for
a single state.
4. Implement y= Σ (1, 3, 5, 7, 8, 10,12,14) using NAND gates ONLY
and NOR gates ONLY.
5. Design a parity checker for 32 bit word, and the receiver checker.
Thank you
DIGITAL LOGIC DESIGN 1
Lecture 6

Dr. Eng. Alaa Rabie

SEQUENTIAL CIRCUITS
COMBINATIONAL LOGIC CIRCUITS
These are circuits that use logic gates, where the output depends only
on the current inputs.
 SEQUENTIAL LOGIC CIRCUITS
5

• These are circuits where the outputs depend on the sequence of past outputs

• As a result, such a circuit must remember something about the past

Example: In a football game

• The current score = the previous goals (state) + new goal (input)

• For example, if you have a previous goal score of 5 and there is a new
goal, then the updated score will be 6
SEQUENTIAL LOGIC CIRCUITS
5

• A circuit with memory, whose outputs depend on the current input and the
sequence of past outputs, is called a sequential circuit

• The behavior of such a circuit may be described by a state table that

specifies its output and next state as functions of its current state and input
TYPES OF SEQUENTIAL LOGIC CIRCUITS

1.Synchronous, where the behavior of the circuit depends on the input

signal at discrete instances of time (also called clocked)

2.Asynchronous, where the behavior of the circuit depends on the input

signals at any instance of time and the order of the inputs change
•A combinational logic circuit with feedback
STORAGE ELEMENTS

What is required from a storage element?

• Store data (hold)

• Accept writing new data (write)

• Read the stored data

TYPES OF STORAGE ELEMENTS

• Latches • Flip-flops
• SR • Master-slave
•D • Edge-triggered
•D
• JK
•T

Before going in detail regarding storage elements, we must understand

what a clock signal is…
DEFINING THE CLOCK
• A clock signal is a particular type of signal that oscillates between a high
and a low state and is utilized to coordinate actions of circuits
• A clock signal is produced by a clock generator
• While other more complex arrangements are also in use, the most common
clock signal takes the form of a square wave, with 50% duty cycle, usually
with a fixed, constant frequency
• Circuits using a clock signal for synchronization may become active
at either the rising or the falling edge of a clock cycle
CLOCK PULSES

• A clock pulse can be positive or negative

BASIC MEMORY ELEMENTS
• A basic memory element consists of two cascaded inverters and the
output of the last inverter is fed back into the input of the first inverter
• 𝑄 and 𝑄′ are the outputs of the memory element
• Such a memory element will always store a single bit
• Such a memory element is called a Latch
• But how to write a new value in this latch?
• We need a special technique that enables us to do this writing action
S R flip-flop

S R Qn+1
0 0 Qn No change
0 1 0 Reset
1 0 1 Set
1 1 Φ Un defined

R
Qn+1
States Map 0 0 φ 1

Qn 1 0 φ 1
Qn+1 = S+ R’ Qn
S
Qn+1’ = R +S’ Qn’
❑Now try to draw the circuits of these functions using :

NAND gates only and NOR gates ONLY

Carry out one of these circuits and test it using LEDs in the inputs and outputs

S’ 5V S
Q Pull
down

Q’
R’ R
IT IS CLEAR THAT FROM SEQUENTIAL EFFECT THAT WE GET THE OUTPUT

(NEXT STATE) …………( QN+1)

TAKING INTO ACCOUNT THE (PRESENT STATE)……. (QN)

AND THIS HAPPENS IN 4 TRANSITIONS AS FOLLOWS

States Map Qn Qn+1 Transition

R
0 0 u0
0 0 φ 1
0 1 e
Qn 1 0 φ 1 1 0 d
S
1 1 u1
IT IS CLEAR THAT FROM SEQUENTIAL EFFECT THAT WE GET THE OUTPUT

(NEXT STATE) …………( QN+1)

TAKING INTO ACCOUNT THE (PRESENT STATE)……. (QN)

AND THIS HAPPENS IN 4 TRANSITIONS AS FOLLOWS

States Map
R Qn Qn+1 Transition S R
0 0 φ 1 0 0 u0
0 1 e
Qn 1 0 φ 1
1 0 d
S 1 1 u1
Transition Map
R
u0 u0 φ e
Qn u1 d φ u1

S
IT IS CLEAR THAT FROM SEQUENTIAL EFFECT THAT WE GET THE OUTPUT

(NEXT STATE) …………( QN+1)

TAKING INTO ACCOUNT THE (PRESENT STATE)……. (QN)

AND THIS HAPPENS IN 4 TRANSITIONS AS FOLLOWS

States Map
R
0 0 φ 1 Qn Qn+1 Transition S R
0 0 u0 0 φ
Qn 1 0 φ 1
0 1 e 1 0
S 1 0 d 0 1
Transition Map
R 1 1 u1 φ 0
u0 u0 φ e
This table is called
Qn u1 d φ u1 EXCITATION TABLE
of SR flip flop
S
J K flip-flop

J K Qn+1
0 0 Qn No change
0 1 0 Reset
1 0 1 Set
1 1 Q’n Toggle

K
Qn+1
States Map 0 0 1 1

Qn 1 0 0 1

J
We can from states map deduce the transition map and then deduce the
excitation table

States Map
K Qn Qn+1 Transition J K
0 0 1 1 0 0 u0
Qn 1 0 1
0 1 e
0
1 0 d
J 1 1 u1
Transition Map
K

Qn

J
We can from states map deduce the transition map and then deduce the
excitation table

States Map
K Qn Qn+1 Transition J K
0 0 1 1 0 0 u0 0 φ

Qn 1 0 1
0 1 e 1 φ
0
1 0 d φ 1
J 1 1 u1 φ 0

Transition Map
K
This table is called
u0 u0 e e
EXCITATION TABLE
Qn u1 d d u1 of JK flip flop

J
By this way we can deduce a JK flip flop from an SR flip flop using excitation table
 SR TO JK
Transition Map
K
u0 u0 e e
J
Qn u1 d d u1
S Q
J
R Q’
K
BY THIS WAY WE CAN DEDUCE A JK FLIP FLOP
FROM AN SR FLIP FLOP USING EXCITATION TABLE
EXCITATION TABLE of SR flip flop
Transition Map
K Transition S R
u0 u0 e e 0 φ
u0
Qn u1 d d u1 e 1 0
J d 0 1
u1 φ 0
S R
K K
0 0 1 1 φ φ 0
0
Qn φ 0 0 φ Qn 0 1 1 0
J J

S=J Qn’ R=K Qn

THEN WE DRAW THE ELECTRONIC CIRCUIT

S=J Qn’
J S Q

R Q’
K
R=K Qn
 ASSIGNMENT

• By the same way deduce an SR flip flop from JK flip flop

D FLIP FLOP (DATA)

Truth Table

D Q D Qn+1
0 0
Q’ 1 1
D FLIP FLOP (DATA)
Truth Table Transition Map

D Q D Qn+1 Qn+1 u0 e
0 0
Q’ 1 1
Qn d u1

D
States Map Excitation Table

Tr D
Qn+1 0 1 u0 0
e 1
Qn 0 1
d 0
D u1 1
HOW CAN YOU CONVERT SR FLIP FLOP TO D FLIP FLOP?
States Map Transition Map Excitation Table

Tr S R
Qn+1 0 1 Qn+1 u0 e u0 0 φ
e 1 0
Qn 0 1
Qn d u1
d 0 1
D D u1 Φ 0

S 0 1 R φ 0 S
D Q

Qn 0 φ Qn 1 0
R Q’
S=D D D
R= D’
• By the same way Convert D flip flop to SR flip flop
Transition Map Excitation Table
R Tr D
u0 u0 φ e u0 0
Qn u1 d φ u1 e 1
S d 0
u1 1

R S D Q
0 0 φ 1
Qn 1 0 φ 1
D=S +R’ Qn
Q’

S R
T FLIP FLOP (TOGGLE)
Truth Table Transition Map
T Q T Qn+1 Qn+1 u0 e
Q’ 0 Qn

1 Qn’
Qn u1 d

T
States Map Excitation Table

Qn+1 0
Tr T
1
u0 0
e
Qn 1 0 1
d 1
T
u1 0
HOW CAN YOU CONVERT SR FLIP FLOP TO T FLIP FLOP?
Excitation Table
States Map Transition Map
Tr SR
Qn+1 0 1 Qn+1 u0 u0 0 φ
e
e 1 0
Qn 1 0
Qn u1 d
d 0 1
T T u1 Φ 0

S 0 1
R φ 0 S Q
T
Qn φ 0
Qn 0 1
T R Q’
T
S=T Qn’ R= T Qn
After you have known the main memory elements SR, JK, D, and T flip
flops; you can convert any type to another one or create a new one:

1. Truth table of the required FF.

2. States Map of the required FF.
3. Transition Map of the required FF.
4. Excitation table of the existing FF.
5. States maps of the inputs of the existing FF.
6. Algebraic expression of these inputs.
7. Draw the electronic circuits.
CLASSIFICATION OF THE FF

1. TWO INP FF
S Q J Q

R Q’ K Q’

2. ONE INP FF

D Q T Q

Q’ Q’
 CLASSIFICATION OF THE FF

1. Asynchronous FF.
2. Synchronous FF.
The main difference between these two types is that the synchronous ones
carry out the prescribed transitions ONLY with the pulse of the clock. The
transition occurs in the front edge, the rear edge, or during the pulse.
ASYNCHRONOUS FF

S Q J Q D Q T Q

R Q’ K Q’ Q’ Q’

SYNCHRONOUS FF

S Q J Q D Q T Q
CLK CLK CLK CLK
R Q’ K Q’ Q’ Q’
MASTER SLAVE
Due to the racing problem generated from delay variation and fluctuation
even for similar modules; so it is recommended to verify the delivery of
certain information and retransmit it to the output during another time
duration. this is done by the following scenario:

CP

Master Slave

S Q S Q

R Q’ R Q’

CP
Thank you
DIGITAL LOGIC DESIGN 1
Lecture 7

Dr. Eng. Alaa Rabie

REGISTERS
• A register is a memory element that can be used to store more than a single
bit of information
• A register is made up of several flip-flops with common control signals that
control the movement of data to and from the registers
• An 𝑛-bit register consists of 𝑛 flip-flops and is capable of storing an 𝑛-bit
word
• The main operations on a register are the same as for any storage element,
namely:
• load or store: input new data into the register
• Read: retrieve the stored data in the register
SERIAL I/P AND O/P REGISTERS 5
 PARALLEL I/P AND O/P REGISTERS
5

• With every positive edge of the clock,

new data is loaded into the register, in a
parallel fashion

I0 Out 0 I1 Out 1 I2 Out 2

I3 Out3

D Q D Q D Q D Q
Q’ Q’ Q’ Q’

CP
UNIVERSAL SHIFT REGISTER
This is the most general case of a register and has the following capabilities:
1.A clear control to clear the register to 0
2.A Clk input to synchronize the operations
3.A shift-right control to enable the shift-right operation and the serial
input and output lines associated with the shift right
4.A shift-left control to enable the shift-left operation and the serial input
and output lines associated with the shift left
5.A parallel-load control to enable a parallel transfer and the n input lines
associated with the parallel transfer
6.n parallel output lines
7.A control state that leaves the information in the register unchanged
UNIVERSAL SHIFT REGISTER
UNIVERSAL SHIFT REGISTER
Parallel
load I0 I1 I2 I3

Serial
data Out 0 Out 1 Out 2 Out3
input

D Q D Q D Q D Q
Q’ Q’ Q’ Q’
CP

Cl
 BIDIRECTIONAL SHIFT REGISTER
Left/Right

data
input D Q D Q D Q D Q
(Right)

CP

data input(Left)
 COUNTERS:
• A register that goes through a prescribed sequence of states upon the
application of input pulses is called a counter
• A counter that follows the binary number sequence is called a binary counter
• An 𝑛−bit binary counter consists of 𝑛 FFs and can count from 0 through 2𝑛−1
• The counters are classified into:
1. Up counter( i.e. 0-1-2-3…)
2. Down counter(i.e. 8-7-6….)
3. Random counter they generate arbitrary sequence of numbers (5-8-3-7-0-2)
4. Modulo counters : they generate (i.e. 5-8-3-7-0-2- 5-8-3-7-0-2 - 5-8-3-7-0-2)

Definition: the modulo of a counter: is the number of states in repeated group.

COUNTERS:
Example: Design a counter using JK FF to carry out the sequence:
5-3-7-0-1 where the initial state (IS) is 5, and the state 1 returns to 5
IS
5 3 7 0 1

Step 1 find the number of FF, by converting the greatest number 7

to binary= 111, so we need 3FF
Step 2 construct the truth table of present states and the next states
IS
St An Bn Cn An+1 Bn+1 Cn+1 5 3 7 0 1
1 0 1 0 1 1
5
0 1 1 1 1 1
3
1 1 1 0 0 0
7
0 0 0 0 0 1
0
0 0 1 1 0 1
1
0 1 0 φ φ φ
2
1 0 0 φ φ φ
4
1 1 0 φ φ φ
6
 Step 3 we construct states maps of An+1,Bn+1, Cn+1
States maps St An Bn Cn An+1 Bn+1 Cn+1
1 0 1 0 1 1
An+1 5
Bn+1 0 1 1 1 1 1
Cn 3
Cn 1 1 1 0 0 0
7
0 1 1 φ 0 0 1 φ 0 0 0 0 0 1
0
0 0 1 1 0 1
φ 0 0 φ 1
An An φ 1 0 φ 0 1 0 φ φ φ
2
Bn 1 0 0 φ φ φ
4
Bn 1 1 0 φ φ φ
6

Cn+1
Cn

1 1 1 φ

An φ 1 0 φ

Bn
Step 4: convert states maps to transition maps Transition maps
States maps Cn
An+1 Cn
u0 e e φ
0 1 1 φ
EXCITATION TABLE of JK flip flop An φ d d φ
An φ 0 0 φ
Qn Qn+1 Transition J K Bn
Bn 0 0 u0 0 φ Cn
Bn+1 Cn
0 1 e 1 φ
u0 u0 u1 φ
0 0 1 φ 1 0 d φ 1
1 1 An φ e d φ
An φ 1 0 φ u1 φ 0
Bn
Bn
Cn+1 Cn Cn

1 1 1 φ e u1 u1 φ

An φ 1 0 φ An φ u1 d φ

Bn Bn
Step 5: convert each transition map into J states map and K states map For
this we need JK excitation table
Cn
Ja Ka
u0 e e φ 0 1 1 φ φ φ φ φ
φ φ φ φ φ 1 1 φ
An φ d d φ J K
Tr
Bn u0 0 φ
Cn
e 1 φ Jb Kb
u0 u0 u1 φ
d φ 1 0 0 φ φ φ φ 0 φ
An φ e d φ u1 φ 0 φ 1 φ φ φ φ 1 φ
Bn
Cn
Jc Kc
e u1 u1 φ
1 φ φ φ φ 0 0 φ
An φ u1 d φ φ φ φ φ φ 0 1 φ

Bn
Step 5: convert each transition map into J states map and K states map For
this we need JK excitation table
Cn Cn
0 1 1 φ φ φ φ φ
Ja= Cn Ka= 1
An φ φ φ φ An φ 1 1 φ
Bn Bn
Cn Cn
0 0 φ φ Φ φ 0 φ

An φ 1 φ φ Jb=An Kb=An An φ φ 1 φ
Bn Bn
Cn Cn
1 φ φ φ φ 0 0 φ
Jc= 1 Kc=An Bn
An φ φ φ φ An φ 0 1 φ

Bn Bn
Step 6: to find a function for unused states Fu=∑(2,4,6)

Cn

0 0 0 1

An 1 0 0 1

Bn

Fu = An Cn’+ Bn Cn’
=(An + Bn) Cn’

Fu=(An + Bn) Cn’

 Step 7: Carry out the electronic drawing.
To reset to initial state at any time suppose the green/blue drawing

Ja= Cn Ka= 1 A B C
Jb=An Kb=An
Jc= 1 Kc=An Bn Fu
Fu=(An + Bn) Cn’

1
Ja Qa Jb Qb Jc Qc

Ka Qa’ Kb Qb’ Kc Qc’

1

1
CP
UNUSED STATES
• What happens if we are interested in a counter design that does not
include all states (counts)?
• What should we write in the table for the couple of unused states?
•To reach the simplest possible circuit, we can fill in don’t cares for the
next states
•This will also result in don’t cares for the FF inputs, which might
simplify the hardware
•If the circuit somehow ends up in one of the unused states, its behavior
will depend on exactly what the don’t cares were filled in with
•To reach the safest possible circuit, we can explicitly fill in next states for the
unused states
•This guarantees that even if the circuit somehow enters an unused state, it
will eventually end up into one of the valid states
•This is called a self-starting counter
 3 7
Example: Apply self starting counter for the 2
previous counter IS
0
5
Step 1 find the number of FF, by converting the 4
1
greatest number 7 to binary= 111, so we need 3FF
6

Step 2 construct the truth table of present states and the next states
St An Bn Cn An+1 Bn+1 Cn+1
1 0 1 0 1 1
5
3 0 1 1 1 1 1
7 1 1 1 0 0 0
0 0 0 0 0 1
0
0 0 1 1 0 1
1
0 1 0 1 0 1
2
1 0 0 1 0 1
4
1 1 0 1 0 1
6
 Step 3 we construct states maps Step 4: convert states maps to
of An+1,Bn+1, Cn+1 transition maps
Cn
An+1 Cn
u0 e e e
0 1 1 1
An u1 d d u1
An 1 0 0 1
Bn
Bn Cn
Bn+1 Cn
u0 u0 u1 u0
States maps 0 0 1 0
An d e d d
An 0 1 0 0
Bn
Bn
Cn+1 Cn Cn

1 1 1 1 e u1 u1 e

An 1 1 0 1 An u1 u1 d u1

Bn Bn
Step 5: convert each transition map into J states map and K states map For this we need JK excitation table
Cn
0 1 1 1 φ φ φ φ
u0 e e e
φ φ φ φ 0 1 1 0
An u1 d d u1
Ja=Cn+Bn Ka=Cn
Bn Tr J K
Cn u0 0 φ
0 0 φ 0 φ φ 0 φ
u0 u0 u1 u0 e 1 φ
d φ 1 φ 1 φ φ 1 φ 1 1
An d e d d
u1 φ 0
Bn Jb=An Kb=An
Cn
1 φ φ 1 φ 0 0 φ
e u1 u1 e φ φ φ φ
0 0 1 0
An u1 u1 d u1

Bn Jc=1 Kc=AnBnCn
Step 6 to carry out the electronic drawing.
To reset to initial state at any time suppose the green/blue drawing
Ja=Cn+Bn Ka=Cn Jb=An Kb=An Jc=1 Kc=AnBnCn

A B C

1
Ja Qa Jb Qb Jc Qc

Ka Qa’ Kb Qb’ Kc Qc’

CP
Thank you
DIGITAL LOGIC DESIGN 1
Lecture 8

Dr. Eng. Alaa Rabie

 Quiz
Example: Design a counter using JK FF to carry out the sequence:
7-5-3-2-1 where the initial state (IS) is 7, and the state 1 returns to 7
Random Access Memory (RAM)

TO STORE DATA A BINARY CELL (BC) IS REQUIRED

ENABLE

INPUT OUTPUT

BC

READ/WRITE
Random Access Memory (RAM)
THIS CELL COULD BE REALIZED USING ANY TYPE OF FF

ENABLE

INPUT
S Q

R Q’

READ/WRITE
Random Access Memory (RAM)

The RAM could be configured as follows

Data lines (n) to be written
0 1 2 n-1

address lines (k)

0
1 Decoder
2 k K
2 addresses n. 2 Binary Cells

k-1

Data lines (n) read out

 Random Access Memory (RAM) Data lines (n=3) to be written
Example n=3, k=2,

R/W

address lines (k=2)

a

Decoder
b

Data lines (n=3) read out

RAM capacity = 2^k .n = 2^2 x 3 = 4 x 3 = 12 bit
• The capacity of a RAM= n.2k

10
If the value= 2 bits = 1Kbit

10
If the value=8x 2 bits = 1KByte

20
If the value=8x 2 bits = 1MByte

30
If the value=8x 2 bits = 1GByte
 ASSIGNMENT

• Design an up counter 0-1-2-3-4-5-6-7, it stops at 7, manual reset to 0.

• Design a down counter 7-6-5-4-3-2-1-0, it stops at 0, manual reset to 7.
• Design the modulu counter 10-13-7-0-3-1.
• Design a RAM of 5GB using 1GB chips.
 Example of final exam 4 Questions
QUESTION 1 [10 points]
a)Derive the excitation table of SR flipflop. Derive a D flip flop from SR flip flop.
b) Design RAM binary cells (BC) using D flip flop and clarify different modes of operations.
c)A chip has a RAM of 32 data lines and 30 address lines? How many Bytes in this RAM?
d)Using this chip and modular logic circuits, design a 16GByte RAM.

QUESTION 2 [10 points]

a)A ROM has to be designed to get fixed output data to drive a 7 segment display from
binary input. Write down the truth table of inputs and outputs in binary. Design the decoder
and encoder. Use diode matrix.
b)Design a single bit comparator. Then design a 4 bit comparator.
QUESTION 3 [10 points]
a)Design a DOWN counter which counts 13 -11-9-7 where 13 is the initial
state (IS), using D flip flops. The final state automatically goes to IS.
b)Design a circuit to reset the counter to IS. Draw this circuit and use it to
avoid unused states.

QUESTION 4 [10 points]

a)Simplify the logic function y=Σ (0, 2, 4, 6, 8, 10, 12, 14).
b)Design a full adder. Then design an 8 bit adder.
c)Design a parity generator of 8 bit word. Try to design the checker at the
receiver.
• Solution of Question
S A B C 2
D w w w w w w w w w w w w w w w w y y y y y y y z Z z z z z z
t 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 0 1 2 3 4 5 6 0 1 2 3 4 5 6
0 1 2 3 4 5
0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0

2 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 1

3 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1

4 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 1

5 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1

6 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 1 0 1

7 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0

8 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1

1 1 0 1 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0
0
1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0
1
1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 1
2
1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1
3
1 1 1 1 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 1
4
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1
5
THE DECODER
W0= A’B’C’D’,W1=A’B’C’D,
W2=A’B’CD’,W3=A’B’CD,W4=A’BC’D’,W5=A’BC’D,W6=A’BCD’,W7=A’BCD,W8=AB’C’D’,W9=AB’C’D,
W10=AB’CD’,W11=AB’CD,W12=ABC’D’,W13=ABC’D,W14=ABCD’,W15ABCD

• THE ENCODER

• Y0= W10+W11+W12+W13+W14+W15

• Y1= W10+W11+W12+W13+W14+W15

• Y2=Y3=Y4=Y5=Y6=0

• Z0=W0+W1+W2+W3+W4+W6+W7+W8+W9+W10+W11+W12 +W13+W14

• Z1=W0+W1+W3+W4+W5+W6+W7+W8+W9+W10+W11+W13 +W14+W15

• Z2=

• Z3=

• Z4=

• Z5=

• Z6=
Thank you