5 4 3 2 1

D D

DW70 CALPELLA N11P-GE1 Schematics

uFCPGA Mobile Arrandale/Clarksfield

C
Intel Ibex Peak-M C

2009-09-03

REV : SA
B B

DY : Nopop Component
UMA : Pop when schematic is UMA
DIS : Pop when schematic is DIS
A
ARD : Pop when schematic is Arrandale UMA
A

CFD : Pop when schematic is Clarksfield Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
Custom
Vostro Calpella SA
Date: Thursday, September 03, 2009 Sheet 1 of 90
5 4 3 2 1
 5 4 3 2 1

CPU DC/DC

PCB LAYER
Winery CALPELLA Block Diagram INPUTS
ISL62883
OUTPUTS
47,48

L1: Top Project code : 91.4RU01.001 +PWR_SRC +VCC_CORE

L2: VCC Part Number : 48.4RU06.0SA

L3: Signal SYSTEM DC/DC
46
TPS51125
D
L4: Signal PCB P/N : 09290 D

L5: GND INPUTS OUTPUTS

L6: Bottom Clock Generator
Revision : SA +15V_ALW
+3.3V_RTC_LDO
+PWR_SRC +5V_ALW
SLG8SP585 7 +3.3V_ALW

DDRIII DM1 18 SYSTEM DC/DC

DDRIII Channel A TPS51116 50
100MHz/ Intel CPU Arrandale 1066MHz
INPUTS OUTPUTS
2.5Gbps Arrandale 800/1066MHz Clarksfield 1333MHz
Nvidia Clarksfield 1066/1333MHz +PWR_SRC
+1.5V_SUS
+0.75V_DDR_VTT
VRAM(gDDR3) +V_DDR_REF
64Mbx16x8 (1GB) 4
VRAM
N11P-GE1(40nm) PCIe x 16
Arrandale 19
84,85,89,90 DDRIII DM2
Bandwidth
:8GB
Clarksfield DDRIII Channel B
Arrandale 1066MHz SYSTEM DC/DC
53
80,81,82,83 Arrandale 800/1066MHz Clarksfield 1333MHz ADP3211
HDMI Clarksfield 1066/1333MHz
HDMI INPUTS OUTPUTS
LVDS

RGB CRT
57
HDMI

(Dual 8,9,10,11,12,13,14 +PWR_SRC +CPU_GFXCORE

RGB CRT
Channel)
PCIE x 1 10/100/1000LOM RJ45
CRT 55 RGB CRT RTL8111DL CONN
(On LAN board) SYSTEM DC/DC
C

LVDS
Switchable LVDS
TPS51218 86
C

LCD 54 DMIx4 FDI

Power SW INPUTS OUTPUTS
TPS2231R
+PWR_SRC +VCC_GFX_CORE
RGB CRT
CHARGER
LVDS
Intel PCIE PCIE x 1 USB 2.0 x 1 New Card BQ24745 45

CardReader (On I/O board)

PCH 100MHz INPUTS OUTPUTS
1394 Connector
1394 HDMI
2.5Gbps
+DC_IN +PWR_SRC
PCIE x 1 USB 2.0 x 1 Mini-Card +PBATT
14 USB 2.0/1.1 ports 802.11a/b/g/n 64

ETHERNET (10/100/1000Mb) SYSTEM DC/DC

(8 in 1)SD/MMC RICOH PCIE High Definition Audio USB 2.0 USB 2.0 x 1 49
Touch Panel TPS51218
MS/MS Pro/xD R5U230
100MHz SATA ports (6) 480Mbps (On LAN board)
INPUTS OUTPUTS
2.5Gbps PCIE ports (8) Free fall sensor
(On I/O board) SM Bus Left Side:
LPC I/F USB 2.0 x 2 +PWR_SRC +1.05V_VTT
USB x 2
400KHz 40 63
ACPI 1.1
B B
PCI/PCI BRIDGE SYSTEM DC/DC
Right Side: 52
Digital Mic Array TPM CONN 76 USB 2.0 x 2
TPS51117
HD AUDIO LPC Bus USB x 2
(Option) HD AUDIO 20,21,22,23,24,25,26,27,28 (On LAN board)
DEBUG BOARD
INPUTS OUTPUTS
33MHz
CODEC GOLDEN FINGER
70
USB 2.0 x 1 CAMERA +PWR_SRC +1.05V_PCH
73
MIC IN (Option)
OP AMP LDO
SATA,USB

KBC 51
Bluetooth APL5930
SPI
SATA

HP OUT SPI SM Bus USB 2.0 x 1

IDT NUVOTON (On Audio board)
37 INPUTS OUTPUTS
NPCE781BA0DX
92HD81-UA
(On Audio board) +3.3V_ALW +1.8V_RUN
USB 2.0 x 1 Biometric 78
LDO
RT9025 87
2CH SPEAKER USB,ESATA ODD Flash ROM Flash ROM Touch Int.
Multi-Port x1 PAD KB
63 HDD59 4MB 256kB 62 68 68 INPUTS OUTPUTS
Thermal +3.3V_ALW +1.8V_RUN_GPU
A & Fan A

EMC2102 39,58 UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Capacity Board
Title

Size Document Number

Block Diagram Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 2 of 90
5 4 3 2 1
 5 4 3 2 1

D D

TPS51116RGER-GP-U
+PWR_SRC 50
Adapter

ISL62883 ADP3211 TPS51218 TPS51218DSCR TPS51117RGYR-GP

AO4407A 47、48 53 86 49 52 +V_DDR_REF +1.5V_SUS
45 Charger
BQ24745 For Clarksfield
+VCC_CORE +CPU_GFXCORE +VCC_GFX_CORE +1.05V_VTT +1.05V_PCH
Battery +PBATT 45 For Intel GPU For NVIDIA GPU Arrandale : 1.05V
Clarksfield:1.1V

FDS8880
TPS51125 87
46

C C
+1.05V_GFX_PCIE
P2703 FDS8880 AO4468
+5V_ALW2 +3.3V_RTC_LDO
42 87 42

+5V_ALW +3.3V_ALW

+1.5V_CPU +1.5V_RUN_GPU +1.5V_RUN

+15V_ALW TPS2062AD AO4468 TPS2062AD TPS2062AD AO3403 TPS2231R FDS8880 APL5930 RT9025 FDS8880 TPS2231R
Daughter BD 42 63 63 Daughter BD Daughter BD 42 51 87 87 Daughter BD

+5V_USB0 +5V_RUN +5V_USB1 +5V_USB2 +3.3V_LAN +3.3V_CARDAUX +3.3V_RUN +1.8V_RUN +1.8V_RUN_GPU +3.3V_RUN_GPU
+1.5V_CARD

B
For USB Port1,4 For USB Port2,3 For ESATA B

RTL8111DL
35
SI3456BDV TPS2231R
54 Daughter BD

DVDD12
+LCDVDD +3.3V_CARD

Power Shape

Regulator LDO Switch

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Power Block Diagram
Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 3 of 90
5 4 3 2 1
 A B C D E

PCH SMBus Block Diagram +3.3V_ALW +3.3V_RUN

KBC SMBus Block Diagram +5V_RUN

‧ ‧ ‧
+3.3V_RUN
SRN2K2J-1-GP SRN2K2J-1-GP SRN10KJ-5-GP
‧
PCH DIMM 1 TouchPad Conn.
1
SMBCLK (H14) PCH_SMB_CLK
‧ ‧PCH_SMBCLK SCL (202) PSDAT1 TPDATA
‧ TPDATA TPDATA
1
SMBDATA (C8) PCH_SMB_DATA
‧ ‧ PCH_SMBDATA SDA (200)
18
PSCLK1 TPCLK
‧ TPCLK TPCLK
68

23 SMBus Address:A0
2N7002SPT KBC_PWR

DIMM 2 ‧
‧PCH_SMBCLK SCL (202)

‧ PCH_SMBDATA SDA (200)

19
SRN4K7J-8-GP
SMBus Address:A2
SRN100J-3-GP Battery Conn. SMBus address:16
Express Clock
SCL1 BAT_SCL
‧ ‧ PBAT_SMBCLK1 CLK_SMB
SDA1 BAT_SDA
‧ ‧ PBAT_SMBDAT1 DAT_SMB 44

SMB_CLK
Card Generator
SMB_CLK
‧PCH_SMBCLK SCL (32)
SMB_DATA
SMB_DATA
76 ‧ PCH_SMBDATA SDA (31) KBC BQ24745
SMBus address:D2 07 NPCE781 BAT_SCL

BAT_SDA
SCL

SDA
SMBus address:12
45

+3.3V_RUN

Minicard
2 ‧ 2

‧PCH_SMBCLK
WLAN
SMB_CLK
KBC_PWR
+3.3V_RUN

‧ PCH_SMBDATA SMB_DATA
SRN4K7J-8-GP
64
‧ ‧
Thermal
SMBus address:7A
SRN4K7J-8-GP ‧ THERM_SCL SMCLK

‧ THERM_SDA SMDATA 39

Free fall
GPIO73/SCL2 KBC_SCL1
‧
PCH_SMBCLK
sensor
SCL/SPC (14)
GPIO74/SDA2 KBC_SDA1
‧
2N7002DW-1-GP

PCH_SMBDATA
SDA/SDI/SDO (13)
40
Capacity
Board SMBus address:0A
(On daughter board)
THERM_SCL SCL
37
THERM_SDA SDA

3 3

VGA SMBus Block Diagram +3.3V_RUN_GPU

‧
SRN2K2J-1-GP

I2CC_SCL LDDC_CLK ‧ NC7SB3157P6X LDDC_CLK_CON

LCD Conn.
I2CC_SDA LDDC_DATA ‧ LDDC_DATA_CON 54

+3.3V_RUN_GPU +5V_CRT_RUN

‧ ‧
+3.3V_RUN

SRN2K2J-1-GP SRN2K2J-1-GP
‧

I2CA_SCL CRT_CLK_DDC DDC_CLK_CON2

‧ DDC_CLK_CON

VGA I2CA_SDA CRT_DAT_DDC

NC7SB3157P6X DDC_DATA_CON2
‧ DDC_DATA_CON CRT CONN
55
N11P-GE1 +3.3V_RUN
2N7002DW-1-GP +5V_RUN

4 ‧ ‧ 4
+3.3V_RUN

SRN2K2J-1-GP SRN2K2J-1-GP
‧ UMA

IFPC_AUX_I2CW_SCL HDMI_SCLK_DDC HDMI_SCLK_CON_L

‧ HDMI_SCLK_CON Wistron Corporation
IFPC_AUX_I2CW_SDA# HDMI_SDATA_DDC
‧
‧ NC7SB3157P6X HDMI_SDATA_CON_L
‧ HDMI_SDATA_CON
HDMI 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
57 Title

81 2N7002DW-1-GP
SMBUS Block Diagram
Size Document Number Rev
A2 SA
Vostro Calpella
Date: Tuesday, September 08, 2009 Sheet 4 of 90
A B C D E
 A B C D E

Thermal Block Diagram Audio Block Diagram

1 1

0R3-0-U-GP
SPKR_PORT_D_L+

SPKR_PORT_D_L-
AUD_SPK_L1

AUD_SPK_L2
AUD_SPK_L1_R

AUD_SPK_L2_R
SPEAKER
SPKR_PORT_D_R- AUD_SPK_R2 AUD_SPK_R2_R

SPKR_PORT_D_R+ AUD_SPK_R1 AUD_SPK_R1_R

DP1 EMC2102_DN1 0R3-0-U-V-GP 44

Q3905
SC470P50V3JN-2GP MMBT3904-3-GP
2 2
DN1 EMC2102_DP1
HP1_PORT_B_L AUD_HP1_JACK_L
HP
System HP1_PORT_B_R AUD_HP1_JACK_R
Thermal OUT
EMC2102 Codec 50

DP2 VGA_THERMDA DPLUS

92HD81-UA
SC470P50V3JN-2GP GPU
DN2 VGA_THERMDC DMINUS
54 DIS HP0_PORT_A_L

HP0_PORT_A_R
AUD_EXT_MIC_L

AUD_EXT_MIC_R
MIC
Q3904
VREFOUT_A_OR_F AUD_VREFOUT_B
IN
MMBT3904-3-GP
50
3 3

UMA

CPU Sockt
DP3 CPU_THERMDA HW T8 sensor
DMIC_CLK/GPIO1 AUD_DMIC_CLK
33R2J-2-GP
AUD_DMIC_CLK_G_R Digital
DN3 CPU_THERMDC
SC470P50V3JN-2GP
Q3901
MMBT3904-3-GP
DMIC0/GPIO2

AUD_DMIC_IN0
MIC
33R2J-2-GP AUD_DMIC_IN0_R
Array 47

28
22

4 4
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 5 of 90
A B C D E
 A B C Processor StrappingD E
PCH Strapping Calpella Schematic Checklist Rev.1_6 Calpella Schematic Checklist Rev.1_6
Pin Name Strap Description Configuration (Default value for each bit is Default
Name Schematics Notes 1 unless specified otherwise) Value
Reboot option at power-up CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
SPKR Default Mode: Internal weak Pull-down. DisplayPort Embedded DisplayPort.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ Presence 0: Enabled - An external Display Port device is
- 10-kΩ weak pull-up resistor. connected to the Embedded Display Port.
INIT3_3V# Internal pull-up. Leave as "No Connect" CFG[3] PCI-Express Static 1: Normal Operation. 1
4 Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 4
Default Mode: Internal pull-up.
GNT3#/ Low (0) = Top Block Swap Mode
GPIO55 Note: Connect to ground with 4.7-kΩ weak pull-down resistor. CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
CRB uses a 1 kΩ; do not stuff resistor. Configuration 0: Bifurcation enabled
Select
INTVRMEN High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
Note: CRB uses a 330-kΩ resistor.

Default (SPI): Leave both GNT0# and GNT1# floating. No pull up

GNT0#, required.
GNT1#
Boot from PCI: Connect GNT1# to ground with 1-kΩ pull-down
resistor. Leave GNT0# Floating.
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kΩ
pull-down resistor.

GNT2#/ Default - Internal pull-up.

GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops).

Enable Intel Anti-Theft Technology:Connect to Vcc3_3

SPI_MOSI with 8.2-kΩ weak pull-up resistor.
3 Disable Intel Anti-Theft Technology:Left floating, no pull-down
3
required.

NV_ALE Enable Intel Anti-Theft Technology:Connect to +NVRAM_Vccq with

8.2-kΩ weak pull-up resistor.[CRB has it pulled up with 1-kΩ
no-stuff resistor]
Disable Intel Anti-Theft Technology:Leave floating.
(internal pull-down)
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0)- Flash Descriptor Security will be overridden. Also, when
HAD_DOCK_EN#
/GPIO[33]
this signals is sampled on the rising edge of PWROK then it will also
disable Intel ME and its features.
PCIE Routing
High (1)-:Security measure defined in the Flash Descriptor
will be enabled. LANE1 Card reader
Platform design should provide appropriate pull-up or pull-down
depending on the desired settings. If a jumper option is used to
LANE2 MiniCard WLAN
tie this signal to GND as required by the functional strap,
the signal should be pulled low through a weak pull-down in order LANE3 LAN
to avoid asserting HDA_DOCK_EN# inadvertently.
CRB recommends 1-kΩ pull-down for FD Override. LANE4 NC
Note: is an internal pull-up of 20 kΩ for HDA_DOCK_EN# which is only
There
2 enabled at boot/reset for strapping functions.
LANE5 New Card 2

HDA_SDO Weak internal pull-down. Do not pull high.

Sampled at rising edge of RSMRST#.
USB Table
USB
HDA_SYNC Weak internal pull-down. Do not pull high. Pair Device
Sampled at rising edge of RSMRST#.
0 USB1 > LAN BOARD
GPIO15 Low (0)-Intel ME Crypto Transport Layer Security (TLS) cipher suite 1 USB4 > LAN BOARD
with no confidentiality
High (1)-:Intel ME Crypto Transport Layer Security (TLS) cipher suite 2 USB2 > M/B
with confidentiality 3 USB3 > M/B
Note:
This is an unmuxed signal. 4 USB for ESATA
This signal has a weak internal pull-down of 20 KΩ which is enabled
when PWROK is low. 5 RESERVED
Sampled at rising edge of RSMRST#. 6 RESERVED
CRB has a 1-kΩ pull-up on this signal to +3.3VA rail. (Not available for HM55)
7 RESERVED
(Not available for HM55)
8 BlUETOOTH
GPIO8 Weak internal pull-up. Do not pull low.
Sampled at rising edge of RSMRST#. 9 Touch Panel
1 GPIO27 Default = Do not connect (floating). Internal pull-up.
10 Biometric UMA 1
High(1) = Enables the internal VccVRM to have a clean supply for 11 CAMERA
analog rails. No need to use on-board filter circuit.
12 New Card Wistron Corporation
Low (0) = Disables the VccVRM. Need to use on-board filter 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
circuits for analog rails. WLAN Taipei Hsien 221, Taiwan, R.O.C.
13
Title

Table of Content
Size Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 6 of 90
 5 4 3 2 1

D D

68.00119.131 0603
+3.3V_RUN +3.3V_RUN_SL585
68.00084.521 0805 +1.05V_PCH
68.00119.131 +1.05V_RUN_SL585_IO
R708 1 2 0R3J-0-U-GP R709 1 2 0R3J-0-U-GP
C701
SC1U10V2KX-1GP

C702
SC10U10V5ZY-1GP

C703
SCD1U10V2KX-4GP

C704
SCD1U10V2KX-4GP

C705
SCD1U10V2KX-4GP

C707
SCD1U10V2KX-4GP

C708
SCD1U10V2KX-4GP

C709
SC1U10V2KX-1GP

C710
SC10U10V5ZY-1GP

C711
SCD1U10V2KX-4GP

C712
SCD1U10V2KX-4GP
1

1
DY DY
DY
2

2
+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO

C C

24

17

29

15

18
1

5
U701 VGA 27M R706 R710

VDD_27

VDD_SRC_IO

VDD_CPU_IO
VDD_CPU

VDD_SRC

VDD_REF

VDD_DOT
SS DY Mount
NON-SS Mount DY +3.3V_RUN_SL585

VR_CLKEN# 47

2
RN701 2 3 CLK_MCH_DREFCLK1# 4 6 CLK_27M R706 2 1 33R2J-2-GP
23 DREFCLK# SRN0J-6-GP 1 4 CLK_MCH_DREFCLK1 3
DOT_96# 27MHZ
7 CLK_27M_SS R710 2 DY 1 33R2J-2-GP
CLK_VGA_27M 81
R705
DY

G
23 DREFCLK DOT_96 27MHZ_SS 10KR2J-3-GP
RN702 2 3 CLK_IN_DMI# 14 +3.3V_RUN
23 CLKIN_DMI# SRC_2#
23 CLKIN_DMI SRN0J-6-GP 1 4 CLK_IN_DMI 13 16 CPU_STOP# R701 2 1 2K2R2J-2-GP

1
SRC_2 CPU_STOP# CK_PW RGD CK_PW RGD
CKPWRGD/PD# 25 D S
23 CLK_PCIE_SATA# RN703 2 3 CLK_PCIE_SATA1# 11 30 FSC R703 2 1 33R2J-2-GP CLK_PCH_14M 23
SRN0J-6-GP 1 CLK_PCIE_SATA1 SRC_1/SATA# REF_0/CPU_SEL
23 CLK_PCIE_SATA 4 10 SRC_1/SATA

1
2N7002A-7-GP
RN704 1 4 CLK_CPU_BCLK1# 22 28 CLK_XTAL_IN EC701 Q701
23 CLK_CPU_BCLK#
23 CLK_CPU_BCLK SRN0J-6-GP 2 3 CLK_CPU_BCLK1 23
CPU_0# XTAL_IN
27 CLK_XTAL_OUT DY SC4D7P50V2CN-1GP

2
CPU_0 XTAL_OUT 2009/07/28
Do Not Stuff TP0701 TP_CPU_1# Change 2N7002 ESD pretect from standard to 1KV type
1 19 CPU_1# SDA 31 PCH_SMBDATA 18,19,23,40,64 P/N:84.2N702.E31
Do Not Stuff TP702 1 TP_CPU_1 20 32
CPU_1 SCL PCH_SMBCLK 18,19,23,40,64

VSS_SATA
VSS_CPU

VSS_SRC

VSS_DOT
VSS_REF

VSS_27
GND

2009/07/15
CLK_XTAL_IN Added R,C For CLK_VGA_27M EMI
B SLG8SP585VTR-GP B
X701
33

26

21

12

1 2 CLK_XTAL_OUT CLK_VGA_27M

2
X-14D31818M-37GP

1
R749
C714 C715 DY 0R2J-2-GP
1st Silego 71.08585.003 SC12P50V2JN-3GP SC12P50V2JN-3GP

1
2nd ICS 71.93197.003

CLK_VGA_27M_RC
+1.05V_PCH
2

R704 FSC 0 1
4K7R2J-2-GP
DY

2
133MHz DY C718
2 1

FSC SPEED 100MHz SC4D7P50V2CN-1GP

1
(Default)
R707
10KR2J-3-GP
1

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock Generator SLG8SP585

Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 7 of 90
5 4 3 2 1
 5 4 3 2 1

D D

CPU1A 1 OF 9
B26 PEG_IRCOMP_R R801 1 2 49D9R2F-GP
PEG_ICOMPI R802 1
PEG_ICOMPO A26 2 750R2F-GP
22 DMI_PTX_CRXN0 A24 DMI_RX#0 PEG_RCOMPO B27
22 DMI_PTX_CRXN1 C23 A25 EXP_RBIAS
DMI_RX#1 PEG_RBIAS PCIE_MRX_GTX_N[0..15]
22 DMI_PTX_CRXN2 B22 DMI_RX#2 PCIE_MRX_GTX_N[0..15] 80
A21 K35 PCIE_MRX_GTX_N15

CLARKSFIELD
22 DMI_PTX_CRXN3 DMI_RX#3 PEG_RX#0
J34 PCIE_MRX_GTX_N14
PEG_RX#1 PCIE_MRX_GTX_N13
22 DMI_PTX_CRXP0 B24 DMI_RX0 PEG_RX#2 J33

DMI
22 DMI_PTX_CRXP1 D23 G35 PCIE_MRX_GTX_N12
DMI_RX1 PEG_RX#3

DMI
22 DMI_PTX_CRXP2 B23 G32 PCIE_MRX_GTX_N11
DMI_RX2 PEG_RX#4 PCIE_MRX_GTX_N10
22 DMI_PTX_CRXP3 A22 DMI_RX3 PEG_RX#5 F34
F31 PCIE_MRX_GTX_N9
PEG_RX#6 PCIE_MRX_GTX_N8
22 DMI_CTX_PRXN0 D24 DMI_TX#0 PEG_RX#7 D35
22 DMI_CTX_PRXN1 G24 E33 PCIE_MRX_GTX_N7
DMI_TX#1 PEG_RX#8 PCIE_MRX_GTX_N6
22 DMI_CTX_PRXN2 F23 DMI_TX#2 PEG_RX#9 C33
22 DMI_CTX_PRXN3 H23 D32 PCIE_MRX_GTX_N5
DMI_TX#3 PEG_RX#10 PCIE_MRX_GTX_N4
PEG_RX#11 B32
22 DMI_CTX_PRXP0 D25 C31 PCIE_MRX_GTX_N3
DMI_TX0 PEG_RX#12 PCIE_MRX_GTX_N2
22 DMI_CTX_PRXP1 F24 DMI_TX1 PEG_RX#13 B28
22 DMI_CTX_PRXP2 E23 B30 PCIE_MRX_GTX_N1
DMI_TX2 PEG_RX#14 PCIE_MRX_GTX_N0
22 DMI_CTX_PRXP3 G23 DMI_TX3 PEG_RX#15 A31
PCIE_MRX_GTX_P[0..15]
PCIE_MRX_GTX_P[0..15] 80
J35 PCIE_MRX_GTX_P15
PEG_RX0 PCIE_MRX_GTX_P14
PEG_RX1 H34
C 22 FDI_TXN0 FDI_TXN0 E22
PEG_RX2 H33
F35
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P12 C
FDI_TXN1 FDI_TX#0 PEG_RX3 PCIE_MRX_GTX_P11
22 FDI_TXN1 D21 FDI_TX#1 PEG_RX4 G33
22 FDI_TXN2 FDI_TXN2 D19 E34 PCIE_MRX_GTX_P10
FDI_TXN3 FDI_TX#2 PEG_RX5 PCIE_MRX_GTX_P9
22 FDI_TXN3 D18 FDI_TX#3 PEG_RX6 F32
22 FDI_TXN4 FDI_TXN4 G21 D34 PCIE_MRX_GTX_P8
FDI_TXN5 FDI_TX#4 PEG_RX7 PCIE_MRX_GTX_P7
22 FDI_TXN5 E19 FDI_TX#5 PEG_RX8 F33
22 FDI_TXN6 FDI_TXN6 F21 B33 PCIE_MRX_GTX_P6
FDI_TX#6 PEG_RX9

Intel(R) FDI
22 FDI_TXN7 FDI_TXN7 G18 D31 PCIE_MRX_GTX_P5
FDI_TX#7 PEG_RX10 PCIE_MRX_GTX_P4
PEG_RX11 A32

PCI EXPRESS -- GRAPHICS

C30 PCIE_MRX_GTX_P3
FDI_TXP0 PEG_RX12 PCIE_MRX_GTX_P2
22 FDI_TXP0 D22 FDI_TX0 PEG_RX13 A28
22 FDI_TXP1 FDI_TXP1 C21 B29 PCIE_MRX_GTX_P1
FDI_TXP2 FDI_TX1 PEG_RX14 PCIE_MRX_GTX_P0 PCIE_MTX_GRX_N[0..15]
22 FDI_TXP2 D20 FDI_TX2 PEG_RX15 A30 PCIE_MTX_GRX_N[0..15] 80
22 FDI_TXP3 FDI_TXP3 C18
FDI_TXP4 FDI_TX3 PCIE_MTX_GRX_C_N15 C829 SCD1U10V2KX-5GP PCIE_MTX_GRX_N15
22 FDI_TXP4 G22 FDI_TX4 PEG_TX#0 L33 1DIS 2
22 FDI_TXP5 FDI_TXP5 E20 M35 PCIE_MTX_GRX_C_N14 C827 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N14
FDI_TXP6 FDI_TX5 PEG_TX#1 PCIE_MTX_GRX_C_N13 C832 SCD1U10V2KX-5GP PCIE_MTX_GRX_N13
22 FDI_TXP6 F20 FDI_TX6 PEG_TX#2 M33 1DIS 2
22 FDI_TXP7 FDI_TXP7 G19 M30 PCIE_MTX_GRX_C_N12 C812 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N12
FDI_TX7 PEG_TX#3 PCIE_MTX_GRX_C_N11 C803 SCD1U10V2KX-5GP PCIE_MTX_GRX_N11
PEG_TX#4 L31 1DIS 2
22 FDI_FSYNC0 F17 K32 PCIE_MTX_GRX_C_N10 C811 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N10
FDI_FSYNC0 PEG_TX#5 PCIE_MTX_GRX_C_N9 C828 SCD1U10V2KX-5GP PCIE_MTX_GRX_N9
22 FDI_FSYNC1 E17 FDI_FSYNC1 PEG_TX#6 M29 1DIS 2
J31 PCIE_MTX_GRX_C_N8 C810 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N8
PEG_TX#7 PCIE_MTX_GRX_C_N7 C823 SCD1U10V2KX-5GP PCIE_MTX_GRX_N7
22 FDI_INT C17 FDI_INT PEG_TX#8 K29 1DIS 2
H30 PCIE_MTX_GRX_C_N6 C804 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N6
PEG_TX#9 PCIE_MTX_GRX_C_N5 C831 SCD1U10V2KX-5GP PCIE_MTX_GRX_N5
22 FDI_LSYNC0 F18 FDI_LSYNC0 PEG_TX#10 H29 1DIS 2
22 FDI_LSYNC1 D17 F29 PCIE_MTX_GRX_C_N4 C825 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N4
FDI_LSYNC1 PEG_TX#11 PCIE_MTX_GRX_C_N3 C821 SCD1U10V2KX-5GP PCIE_MTX_GRX_N3
PEG_TX#12 E28 1DIS 2
D29 PCIE_MTX_GRX_C_N2 C813 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N2
PEG_TX#13 PCIE_MTX_GRX_C_N1 C806 SCD1U10V2KX-5GP PCIE_MTX_GRX_N1
Calpella Platform Design Guide D27 1DIS 2
B PEG_TX#14
PEG_TX#15 C26 PCIE_MTX_GRX_C_N0 C816 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N0 B
Revision 1.6 PCIE_MTX_GRX_P[0..15]
Page 89 PCIE_MTX_GRX_C_P15 C826 SCD1U10V2KX-5GP PCIE_MTX_GRX_P15 PCIE_MTX_GRX_P[0..15] 80
PEG_TX0 L34 1DIS 2
2.4 Arrandale Graphics Disable Guideline M34 PCIE_MTX_GRX_C_P14 C822 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P14
PEG_TX1 PCIE_MTX_GRX_C_P13 C818 SCD1U10V2KX-5GP PCIE_MTX_GRX_P13
PEG_TX2 M32 1DIS 2
It applies to Arrandale and Clarksfield discrete graphic designs. L30 PCIE_MTX_GRX_C_P12 C815 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P12
PEG_TX3 PCIE_MTX_GRX_C_P11 C808 SCD1U10V2KX-5GP PCIE_MTX_GRX_P11
PEG_TX4 M31 1DIS 2
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON, K31 PCIE_MTX_GRX_C_P10 C802 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P10
PEG_TX5 PCIE_MTX_GRX_C_P9 C820 SCD1U10V2KX-5GP PCIE_MTX_GRX_P9
M28 1DIS 2
FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on PEG_TX6
H31 PCIE_MTX_GRX_C_P8 C805 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P8
PEG_TX7 PCIE_MTX_GRX_C_P7 C817 SCD1U10V2KX-5GP PCIE_MTX_GRX_P7
the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors). PEG_TX8 K28 1DIS 2
G30 PCIE_MTX_GRX_C_P6 C801 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P6
PEG_TX9 PCIE_MTX_GRX_C_P5 C814 SCD1U10V2KX-5GP PCIE_MTX_GRX_P5
PEG_TX10 G29 1DIS 2
F28 PCIE_MTX_GRX_C_P4 C824 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P4
PEG_TX11 PCIE_MTX_GRX_C_P3 C830 SCD1U10V2KX-5GP PCIE_MTX_GRX_P3
PEG_TX12 E27 1DIS 2
D28 PCIE_MTX_GRX_C_P2 C809 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P2
PEG_TX13 PCIE_MTX_GRX_C_P1 C807 SCD1U10V2KX-5GP PCIE_MTX_GRX_P1
PEG_TX14 C27 1DIS 2
C25 PCIE_MTX_GRX_C_P0 C819 1DIS 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P0
PEG_TX15

CLARKUNF
for Discrete

CPU SKT:1st:Molex P/N:62.10053.561

2nd:Foxconn P/N:62.10055.321
A UMA
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/DMI/FDI)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 8 of 90
 5 4 3 2 2009/07/28
1
Change 2N7002 ESD pretect from standard to 1KV type
P/N:84.2N702.E31
Processor Compensation Signals 2009/08/06
+1.05V_VTT 2 OF 9 Changed Q901 from 2N7002 to BSS138 MOSFET,For Vgs(th)<=1.5V.
Processor Pullups CPU1B
1 2 H_COMP3 AT23
R901 20R2F-GP COMP3 BCLK_CPU_P_R RN901
A16 1 4 BCLK_CPU_P 25 DDR_RST_GATE 11,25
BCLK

MISC
R902 1 2 49D9R2F-GP H_CATERR# 1 2 H_COMP2 AT24 B16 BCLK_CPU_N_R 2 3 SRN0J-6-GP
COMP2 BCLK# BCLK_CPU_N 25
R903 20R2F-GP

1
C915
SCD1U10V2KX-5GP
+1.5V_SUS

CLOCKS
1 2 H_COMP1 G16 AR30 BCLK_ITP_P
R933 1 2 68R2-GP H_PROCHOT_R# R905 49D9R2F-GP COMP1 BCLK_ITP
AT30 BCLK_ITP_N DY

CLARKSFIELD
H_COMP0 BCLK_ITP#
1 2 AT26

1
R906 49D9R2F-GP COMP0 PEG_CLK_R RN903
E16 1 4 CLK_EXP_P 23
R904 1 H_CPURST# PEG_CLK PEG_CLK#_R
2 68R2-GP SRN0J-6-GP
DY PEG_CLK#
D16 2 3 CLK_EXP_N 23
DYR934

G
Do Not Stuff TP901 1 SKTOCC#_R AH24 1KR2J-1-GP
SKTOCC# DPLL_REF_SSCLK_R RN904
A18 1 4 CLK_DP_P 23

1
DPLL_REF_SSCLK DPLL_REF_SSCLK#_R SRN0J-6-GP
A17 2 UMA 3 CLK_DP_N 23

2
H_CATERR# DPLL_REF_SSCLK#
AK14
CATERR#

THERMAL

D
2 3
DY DDR3_DRAMRST# 18,19
D AT15
SM_DRAMRST#
F6 SM_DRAMRST#
RN905
+1.05V_VTT
Q901
D
25 H_PECI PECI
AL1 SM_RCOMP_0 4 1 BSS138LT1
R936 SM_RCOMP0 SM_RCOMP_1 SM_DRAMRST#
AM1 3 2 1 2
0R2J-2-GP SM_RCOMP1
AN1 SM_RCOMP_2 DY
H_PROCHOT_R# SM_RCOMP2 SRN10KJ-5-GP R988
1 2 AN26 1 2
47 H_PROCHOT# DY PROCHOT#
AN15 PM_EXTTS#0_C 1 4 PM_EXTTS#0 18 R935 100KR2J-1-GP
PM_EXT_TS#0 PM_EXTTS#1_C 0R2J-2-GP
AP15 2 3 PM_EXTTS#1 19
PM_EXT_TS#1
RN906

DDR3
MISC
25,37,42 H_THRMTRIP# AK15
THERMTRIP# SRN0J-6-GP

AT28 XDP_PRDY# DDR3 Compensation Signals

PRDY# XDP_PREQ#
AP27
R931 PREQ# SM_RCOMP_0 R907 1 2 100R2F-L1-GP-U
1KR2J-1-GP AN28 XDP_TCLK
XDP_RST#_R H_CPURST# TCK XDP_TMS SM_RCOMP_1 R910 1
1 2 24D9R2F-L-GP
DY 2 AP26
RESET_OBS# TMS
AP28

PWR MANAGEMENT
AT27 XDP_TRST#
TRST# SM_RCOMP_2

JTAG & BPM

R911 1 2 130R2F-1-GP
AL15 AT29 XDP_TDI_R
22 H_PM_SYNC PM_SYNC TDI
AR27 XDP_TDO_R
TDO XDP_TDI_M
AR29
TDI_M XDP_TDO_M
AN14 AP29
VCCPWRGOOD_1 TDO_M R909
AN25 H_DBR#_R 1 2 XDP_DBRESET# Calpella Platform S3 Power Reduction Platform
VCCPWRGOOD DBR#
25,42 H_PWRGOOD 1 2 AN27
R908 0R2J-2-GP VCCPWRGOOD_0 0R2J-2-GP S3 Power Reduction CRB Implementation
AJ22 XDP_OBS0
PM_DRAM_PWRGD AK13
BPM#0
AK22 XDP_OBS1
Design Details
22 PM_DRAM_PWRGD SM_DRAMPWROK BPM#1
AK24 XDP_OBS2
BPM#2 XDP_OBS3 RN907
AJ24
BPM#3 XDP_OBS4 SRN0J-6-GP
49 H_VTTPWRGD AM15 AJ25
VTTPWRGOOD BPM#4 XDP_OBS5 DPLL_REF_SSCLK_R
AH22 1 4
BPM#5 XDP_OBS6 DPLL_REF_SSCLK#_R
H_PWRGD_XDPAM26 BPM#6
AK23
XDP_OBS7
2 DIS 3
AH23
TAPPWRGOOD BPM#7
R913
21,37,64,70,76,77,80 PLT_RST# 1 2 PLT_RST#_R AL14
RSTIN#

1
1K6R2F-GP
R913:ARD = 1K6R2F-GP P/N:64.16015.6DL R915
C CFD = 1K5R2F-2-GP P/N:64.15015.6DL 750R2F-GP CLARKUNF C

2
425302_425302_Calpella_S3PowerReduction_WhitePape Revision 0.9
Normal
+3.3V_ALW
R937 +1.5V_CPU
R919 R920 R977
10KR2J-3-GP
1 2

1
R919 AUB 1.27k 3k 1.6k(DY)

1
C903 1K27R2F-L-GP
U927 SCD1U10V2KX-4GP
U927_B 1 CFD 1.1k 3k 1.5k(DY)

2
B R977
5

2
VCC 1K6R2F-GP
37,49,50 VTT_PWRGD 2
A VTT_PWRGD_R3 2 PM_DRAM_PWRGD
4 DY 1 S3 Power Reduction circuit

1
Y
3
GND R920
3KR2F-GP R919 R920 R977
74LVC1G08GW-1-GP

2
AUB 1.1k(DY) 0.75k 1.6k

CFD 1.1k(DY) 0.75k 1.5k

+1.05V_VTT

B XDP_TMS 1
DY 2
B
R914 51R2J-2-GP
XDP_TDI_R 1
R916 DY 2 51R2J-2-GP
XDP_PREQ# 1
R917 DY 2 51R2J-2-GP

XDP Connector XDP_TCLK

R918
1
DY 2 51R2J-2-GP

XDP1 +1.05V_VCCP use Decoupling Capacitor close

NP1 XDP_TDI_R 1 2 XDP_TDI XDP_TRST#
61
ITP connector 100 mil ( max ) R921 0R2J-2-GP

1
1 2
62 XDP_TDO_M 1 2 XDP_TDO R923
XDP_PREQ# 3 4
CPU XDP Connector R922 DY 0R2J-2-GP 51R2J-2-GP

1
XDP_PRDY# 5 6
7 8 TCK(PIN 57) R924

2
XDP_OBS0 9 10 TCK(PIN AN28) 0R2J-2-GP
XDP_OBS1 11 12
13 14

2
XDP_OBS2 15 16 XDP_TDI_M 1 2
XDP_OBS3 17 18 R925 DY 0R2J-2-GP
19 20
21 22 XDP_TDO_R 1 2
23 24 +1.05V_VTT R926 0R2J-2-GP
25 26
XDP_OBS4 27 Scan Chain Stuff --> R921, R924, R926 JTAG MAPPING
XDP_OBS5 29
DY 28
30
31 32 (Default) No Stuff --> R922, R925
1

XDP_OBS6 33 34 C901 CPU Only Stuff --> R921, R922

+1.05V_VTT XDP_OBS7 35 36 SCD1U16V2KX-3GP
DY No Stuff --> R924, R926, R925
1

37 38
2

H_PWRGOOD R927 1 2 1KR2J-1-GP H_CPUPWRGD_XDP 39 40 BCLK_ITP_P_R 2 R912 1Do Not Stuff BCLK_ITP_P R928 GMCH Only Stuff --> R926, R925
R929 1 DY 2 0R2J-2-GP PM_PWRBTN#_XDP 41 42 BCLK_ITP_N_R 2 R938 1Do Not Stuff BCLK_ITP_N 51R2J-2-GP
22 PM_PWRBTN#_R DY 43 44 No Stuff --> R921, R922, R924
H_PWRGD_XDP R930 1 2 0R2J-2-GP H_PWRGD_XDP_R 45 46 XDP_RST#_R
DY
2

47 48 XDP_DBRESET# 22
49 50
1

A DY
C902
SCD1U16V2KX-3GP
23 SML0_DATA
23 SML0_CLK
51
53
55
52
54
56
XDP_TRST#
XDP_TDI
XDP_TDO
A
2

XDP_TCLK 57 58 XDP_TMS
59 60
63
64 UMA
NP2 XDP_RST#_R 1 2
R932 DY0R2J-2-GP PLT_RST# 21,37,64,70,76,77,80
Do Not Stuff Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/CLOCK/PM )
Size Document Number Rev

Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 9 of 90

5 4 3 2 1
 5 4 3 2 1

CPU1D 4 OF 9

CPU1C 3 OF 9

SB_CK0 W8 M_CLK_DDR2 19
M_B_DQ[63..0] W9 M_CLK_DDR#2 19

CLARKSFIELD
19 M_B_DQ[63..0] SB_CK#0
AA6 M_CLK_DDR0 18 M_B_DQ0 B5 M3 M_CKE2 19
SA_CK0 M_B_DQ1 SB_DQ0 SB_CKE0
SA_CK#0 AA7 M_CLK_DDR#0 18 A5 SB_DQ1

CLARKSFIELD
M_A_DQ[63..0] P7 M_B_DQ2 C3
18 M_A_DQ[63..0] SA_CKE0 M_CKE0 18 SB_DQ2
M_A_DQ0 A10 M_B_DQ3 B3 V7 M_CLK_DDR3 19
M_A_DQ1 SA_DQ0 M_B_DQ4 SB_DQ3 SB_CK1
D C10 SA_DQ1 E4 SB_DQ4 SB_CK#1 V6 M_CLK_DDR#3 19 D
M_A_DQ2 C7 M_B_DQ5 A6 M2 M_CKE3 19
M_A_DQ3 SA_DQ2 M_B_DQ6 SB_DQ5 SB_CKE1
A7 SA_DQ3 SA_CK1 Y6 M_CLK_DDR1 18 A4 SB_DQ6
M_A_DQ4 B10 Y5 M_CLK_DDR#1 18 M_B_DQ7 C4
M_A_DQ5 SA_DQ4 SA_CK#1 M_B_DQ8 SB_DQ7
D10 SA_DQ5 SA_CKE1 P6 M_CKE1 18 D1 SB_DQ8
M_A_DQ6 E10 M_B_DQ9 D2
M_A_DQ7 SA_DQ6 M_B_DQ10 SB_DQ9
A8 SA_DQ7 F2 SB_DQ10 SB_CS#0 AB8 M_CS2# 19
M_A_DQ8 D8 M_B_DQ11 F1 AD6 M_CS3# 19
M_A_DQ9 SA_DQ8 M_B_DQ12 SB_DQ11 SB_CS#1
F10 SA_DQ9 SA_CS#0 AE2 M_CS0# 18 C2 SB_DQ12
M_A_DQ10 E6 AE8 M_CS1# 18 M_B_DQ13 F5
M_A_DQ11 SA_DQ10 SA_CS#1 M_B_DQ14 SB_DQ13
F7 SA_DQ11 F3 SB_DQ14
M_A_DQ12 E9 M_B_DQ15 G4 AC7 M_ODT2 19
M_A_DQ13 SA_DQ12 M_B_DQ16 SB_DQ15 SB_ODT0
B7 SA_DQ13 H6 SB_DQ16 SB_ODT1 AD1 M_ODT3 19
M_A_DQ14 E7 AD8 M_ODT0 18 M_B_DQ17 G2
M_A_DQ15 SA_DQ14 SA_ODT0 M_B_DQ18 SB_DQ17
C6 SA_DQ15 SA_ODT1 AF9 M_ODT1 18 J6 SB_DQ18
M_A_DQ16 H10 M_B_DQ19 J3
M_A_DQ17 SA_DQ16 M_B_DQ20 SB_DQ19
G8 SA_DQ17 G1 SB_DQ20
M_A_DQ18 K7 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ19 SA_DQ18 M_B_DQ22 SB_DQ21 SB_DM0 M_B_DM1
J8 SA_DQ19 J2 SB_DQ22 SB_DM1 E1
M_A_DQ20 G7 M_B_DQ23 J1 H3 M_B_DM2
M_A_DQ21 SA_DQ20 M_B_DQ24 SB_DQ23 SB_DM2 M_B_DM3
G10 SA_DQ21 J5 SB_DQ24 SB_DM3 K1
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ25 K2 AH1 M_B_DM4
M_A_DQ23 SA_DQ22 SA_DM0 M_A_DM1 M_B_DQ26 SB_DQ25 SB_DM4 M_B_DM5
J10 SA_DQ23 SA_DM1 D7 L3 SB_DQ26 SB_DM5 AL2 M_B_DM[7..0] 19
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ25 SA_DQ24 SA_DM2 M_A_DM3 M_B_DQ28 SB_DQ27 SB_DM6 M_B_DM7
M6 SA_DQ25 SA_DM3 M7 K5 SB_DQ28 SB_DM7 AT8 M_B_DQS#[7..0] 19
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ29 K4
M_A_DQ27 SA_DQ26 SA_DM4 M_A_DM5 M_B_DQ30 SB_DQ29
L9 SA_DQ27 SA_DM5 AM7 M_A_DM[7..0] 18 M4 SB_DQ30
M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ31 N5 M_B_DQS[7..0] 19
M_A_DQ29 SA_DQ28 SA_DM6 M_A_DM7 M_B_DQ32 SB_DQ31
K8 SA_DQ29 SA_DM7 AN13 M_A_DQS#[7..0] 18 AF3 SB_DQ32
C M_A_DQ30 N8 M_B_DQ33 AG1 M_B_A[15..0] 19
C
M_A_DQ31 SA_DQ30 M_B_DQ34 SB_DQ33 M_B_DQS#0
P9 SA_DQ31 AJ3 SB_DQ34 SB_DQS#0 D5
M_A_DQ32 AH5 M_A_DQS[7..0] 18 M_B_DQ35 AK1 F4 M_B_DQS#1
M_A_DQ33 SA_DQ32 M_B_DQ36 SB_DQ35 SB_DQS#1 M_B_DQS#2
AF5 SA_DQ33 AG4 SB_DQ36 SB_DQS#2 J4
M_A_DQ34 AK6 C9 M_A_DQS#0 M_A_A[15..0] 18 M_B_DQ37 AG3 L4 M_B_DQS#3
M_A_DQ35 SA_DQ34 SA_DQS#0 M_A_DQS#1 M_B_DQ38 SB_DQ37 SB_DQS#3 M_B_DQS#4
AK7 SA_DQ35 SA_DQS#1 F8 AJ4 SB_DQ38 SB_DQS#4 AH2
M_A_DQ36 AF6 J9 M_A_DQS#2 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ36 SA_DQS#2 SB_DQ39 SB_DQS#5
DDR SYSTEM MEMORY A

M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6

SA_DQ37 SA_DQS#3 SB_DQ40 SB_DQS#6

DDR SYSTEM MEMORY - B

M_A_DQ38 AJ7 AH7 M_A_DQS#4 M_B_DQ41 AK4 AR8 M_B_DQS#7
M_A_DQ39 SA_DQ38 SA_DQS#4 M_A_DQS#5 M_B_DQ42 SB_DQ41 SB_DQS#7
AJ6 SA_DQ39 SA_DQS#5 AK9 AM6 SB_DQ42
M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ43 AN2
M_A_DQ41 SA_DQ40 SA_DQS#6 M_A_DQS#7 M_B_DQ44 SB_DQ43
AJ9 SA_DQ41 SA_DQS#7 AT13 AK5 SB_DQ44
M_A_DQ42 AL10 M_B_DQ45 AK2
M_A_DQ43 SA_DQ42 M_B_DQ46 SB_DQ45
AK12 SA_DQ43 AM4 SB_DQ46
M_A_DQ44 AK8 M_B_DQ47 AM3
M_A_DQ45 SA_DQ44 M_B_DQ48 SB_DQ47 M_B_DQS0
AL7 SA_DQ45 AP3 SB_DQ48 SB_DQS0 C5
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ49 AN5 E3 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS1 M_B_DQS2
AL8 SA_DQ47 SA_DQS1 F9 AT4 SB_DQ50 SB_DQS2 H4
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ51 AN6 M5 M_B_DQS3
M_A_DQ49 SA_DQ48 SA_DQS2 M_A_DQS3 M_B_DQ52 SB_DQ51 SB_DQS3 M_B_DQS4
AM10 SA_DQ49 SA_DQS3 M9 AN4 SB_DQ52 SB_DQS4 AG2
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ53 AN3 AL5 M_B_DQS5
M_A_DQ51 SA_DQ50 SA_DQS4 M_A_DQS5 M_B_DQ54 SB_DQ53 SB_DQS5 M_B_DQS6
AL11 SA_DQ51 SA_DQS5 AK10 AT5 SB_DQ54 SB_DQS6 AP5
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS7
AN9 SA_DQ53 SA_DQS7 AR13 AN7 SB_DQ56
M_A_DQ54 AT11 M_B_DQ57 AP6
M_A_DQ55 SA_DQ54 M_B_DQ58 SB_DQ57
AP12 SA_DQ55 AP8 SB_DQ58
M_A_DQ56 AM12 M_B_DQ59 AT9
M_A_DQ57 SA_DQ56 M_B_DQ60 SB_DQ59
AN12 SA_DQ57 AT7 SB_DQ60
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ61 AP9
B M_A_DQ59 SA_DQ58 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 B
AT14 SA_DQ59 SA_MA1 W1 AR10 SB_DQ62
M_A_DQ60 AT12 AA8 M_A_A2 M_B_DQ63 AT10 U5 M_B_A0
M_A_DQ61 SA_DQ60 SA_MA2 M_A_A3 SB_DQ63 SB_MA0 M_B_A1
AL13 SA_DQ61 SA_MA3 AA3 SB_MA1 V2
M_A_DQ62 AR14 V1 M_A_A4 T5 M_B_A2
M_A_DQ63 SA_DQ62 SA_MA4 M_A_A5 SB_MA2 M_B_A3
AP14 SA_DQ63 SA_MA5 AA9 SB_MA3 V3
V8 M_A_A6 R1 M_B_A4
SA_MA6 M_A_A7 SB_MA4 M_B_A5
SA_MA7 T1 19 M_B_BS0 AB1 SB_BS0 SB_MA5 T8
Y9 M_A_A8 19 M_B_BS1 W5 R2 M_B_A6
SA_MA8 M_A_A9 SB_BS1 SB_MA6 M_B_A7
18 M_A_BS0 AC3 SA_BS0 SA_MA9 U6 19 M_B_BS2 R7 SB_BS2 SB_MA7 R6
18 M_A_BS1 AB2 AD4 M_A_A10 R4 M_B_A8
SA_BS1 SA_MA10 M_A_A11 SB_MA8 M_B_A9
18 M_A_BS2 U7 SA_BS2 SA_MA11 T2 SB_MA9 R5
U3 M_A_A12 19 M_B_CAS# AC5 AB5 M_B_A10
SA_MA12 M_A_A13 SB_CAS# SB_MA10 M_B_A11
SA_MA13 AG8 19 M_B_RAS# Y7 SB_RAS# SB_MA11 P3
T3 M_A_A14 19 M_B_W E# AC6 R3 M_B_A12
SA_MA14 M_A_A15 SB_WE# SB_MA12 M_B_A13
18 M_A_CAS# AE1 SA_CAS# SA_MA15 V9 SB_MA13 AF7
18 M_A_RAS# AB3 P5 M_B_A14
SA_RAS# SB_MA14 M_B_A15
18 M_A_W E# AE9 SA_WE# SB_MA15 N1

CLARKUNF

A CLARKUNF UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 10 of 90
5 4 3 2 1
 5 4 3 2 1

R1104 1 2 0R2J-2-GP
DY
Q1101
AO3418-GP
CPU1E 5 OF 9
18 M_VREF_DQ_DIMM0 M_VREF_DQ_DIMM0 D CFD S SA_DIMM_VREF#
AJ13

1
RSVD#AJ13
D AJ12 D
R1108 RSVD#AJ12

G
CFD 100KR2J-1-GP AP25

CLARKSFIELD
RSVD#AP25
AL25 AH25
RSVD#AL25 RSVD#AH25
9,25 DDR_RST_GATE AL24 AK26

2
RSVD#AL24 RSVD#AK26
AL22
RSVD#AL22
AJ33 AL26
RSVD#AJ33 RSVD#AL26
AG9 AR2
RSVD#AG9 RSVD_NCTF_37
M27
RSVD#M27
L28 AJ26
SA_DIMM_VREF# RSVD#L28 RSVD#AJ26
J17 AJ27
SB_DIMM_VREF# SA_DIMM_VREF RSVD#AJ27
H17
R1105 1 SB_DIMM_VREF
20R2J-2-GP
DY G25
G17
RSVD#G25
RSVD#G17
Q1102 E31
RSVD#E31
E30
AO3418-GP RSVD#E30

19 M_VREF_DQ_DIMM1 M_VREF_DQ_DIMM1 D CFD S SB_DIMM_VREF#

1
R1110

G
CFD100KR2J-1-GP CFG0 AM30
RSVD#AL28
AL28
AL29
Do Not Stuff TP1101 CFG1 CFG0 RSVD#AL29
9,25 DDR_RST_GATE 1 AM28 AP30

2
Do Not Stuff TP1102 CFG2 CFG1 RSVD#AP30
1 AP31 AP32
CFG3 CFG2 RSVD#AP32
AL32 AL27
CFG4 CFG3 RSVD#AL27
AL30 AT31
Do Not Stuff TP1104 CFG5 CFG4 RSVD#AT31
1 AM31 AT32
Do Not Stuff TP1105 CFG6 CFG5 RSVD#AT32
1 AN29 AP33
CFG7 CFG6 RSVD#AP33
AM32 AR33
Do Not Stuff TP1106 CFG8 CFG7 RSVD#AR33
1 AK32
Do Not Stuff TP1107 CFG9 CFG8
1 AK31

RESERVED
Do Not Stuff TP1108 CFG10 CFG9
C 1 AK28 C
CFG0 Do Not Stuff TP1109 CFG11 CFG10
1 AJ28
Do Not Stuff TP1110 CFG12 CFG11
PCI-Express Configuration Select 1 AN30 AR32
1

Do Not Stuff TP1111 CFG13 CFG12 RSVD#AR32

1 AN32
R1101 Do Not Stuff TP1112 CFG14 CFG13
1 AJ32
3KR2F-GP Do Not Stuff TP1113 CFG15 CFG14
DY 1:Single PEG 1 AJ29
CFG15 RSVD_TP#E15
E15
CFG0 Do Not Stuff TP1114 1 CFG16 AJ30 F15
0:Bifurcation enabled Do Not Stuff TP1115 1 CFG17 AK30
CFG16 RSVD_TP#F15
A2
2

CFG17 KEY
H16 D15
RSVD_TP_86 RSVD#D15
C15
RSVD#C15 RSVD#AJ15 TP1120 Do Not Stuff
AJ15 1
RSVD#AJ15 RSVD#AH15 TP1121 Do Not Stuff
AH15 1
RSVD#AH15
B19
RSVD#B19
A19
RSVD#A19

改5%
DIS改 A20
B20
RSVD#A20
CFG3 RSVD#B20
AA5
SA_CK2
CFG3 - PCI-Express Static Lane Reversal U9 AA4
1

RSVD#U9 SA_CK#2
T9 R8
R1102 RSVD#T9 SA_CKE2
AD3
3KR2F-GP SA_CS#2
1 :Normal Operation AC9
RSVD#AC9 SA_ODT2
AD2
CFG3 0 :Lane Numbers Reversed AB9
RSVD#AB9 SA_CK3
AA2
AA1
2

15 -> 0, 14 -> 1, ... SA_CK#3

R9
SA_CKE3
AG7
SA_CS#3
AE3
SA_ODT3
CFG4 - Display Port Presence
CFG4 V4
SB_CK2
V5
1

SB_CK#2
1:Disabled; No Physical Display Port SB_CKE2
N2
B R1103 CFG4 J29 AD5 VSS (AP34) can be left NC is B
3KR2F-GP attached to Embedded Display Port RSVD#J29 SB_CS#2
DY 0:Enabled; An external Display Port
J28
RSVD#J28 SB_ODT2
AD7
W3 CRB implementation; EDS/DG
SB_CK3
device is connected to the Embedded W2 recommendation to GND.
2

SB_CK#3
N3
Display Port SB_CKE3
AE5
SB_CS#3
AD9
SB_ODT3

Calpella Platform Design Guide VSS

AP34
Revision 1.6
4.8.3.1 LVDS Switching CLARKUNF
Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the
OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap
(CFG[4]) to disabled (not pulled down).
4.8.3.2 eDP Switching
eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for
embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail
through 2.2 kΩ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP
strap CFG[4] as no connect. Page 482,486

CFG7(Reserved) - Temporarily used for early

Clarksfield samples.
A CFG7 A
CFG7 Clarksfield (only for early samples pre-ES1) -
Connect to GND with 3.01K Ohm/5% resistor. UMA
1

R1109
3KR2F-GP
DY Note: Only temporary for early CFD sample
(rPGA/BGA) [For details please refer to the
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

WW33 MoW and sighting report]. Taipei Hsien 221, Taiwan, R.O.C.
For a common M/B design (for AUB and CFD), Title
the pull-down resistor shouble be used. Does
not impact AUB functionality.
Size
CPU (RESERVED)
Document Number Rev

Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 11 of 90
5 4 3 2 1
 5 4 3 2 1

CPU1F 6 OF 9

+VCC_CORE

CLARKSFIELD
+1.05V_VTT
PROCESSOR CORE POWER
AG35 AH14
VCC VTT0
Clarksfield = 52A AG34 AH12

1
VCC VTT0 C1201 C1202 C1217 C1218 C1204 C1205
AG33 AH11
+VCC_CORE VCC VTT0
Arrandale = 48A AG32
VCC VTT0
AH10

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
AG31 J14

2
VCC VTT0
D AG30 J13 D
VCC VTT0
AG29 H14
C1206 C1207 C1208 C1209 C1220 C1210 VCC VTT0
AG28 H12
1

1
VCC VTT0
AG27 G14
VCC VTT0
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AG26 G13
VCC VTT0
AF35 G12
2

2
VCC VTT0
AF34 G11
VCC VTT0
AF33 F14
VCC VTT0
AF32 F13
VCC VTT0
AF31 F12
VCC VTT0
AF30 F11
VCC VTT0
AF29
VCC VTT0
E14 The decoupling capacitors, filter
AF28 E12
AF27
VCC VTT0
D14 recommendations and sense resistors on the
VCC VTT0
AF26
VCC VTT0
D13 CPU/PCH Rails are specific to the CRB

1.1V RAIL POWER

C1212 C1213 C1214 C1215 C1223 C1224 AD35 D12
Implementation. Customers need to follow the
1

1
VCC VTT0
AD34 D11
VCC VTT0
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AD33
VCC VTT0
C14 recommendations in the Calpella Platform
AD32 C13
2

AD31
VCC VTT0
C12 Design Guide.
VCC VTT0
AD30 C11
VCC VTT0
AD29 B14
VCC VTT0
AD28 B12
VCC VTT0
AD27 A14
VCC VTT0
AD26
AC35
VCC VTT0
A13
A12
Please note that the VTT Rail
VCC VTT0
AC34
AC33
VCC VTT0
A11 Values are
VCC +1.05V_VTT
C1225 C1226 C1227 C1228 C1229 C1230 C1231 C1232 AC32 Arrandale VTT=1.05V;
1

VCC
AC31
VCC
Clarksfield VTT=1.1V
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP
AC30 AF10
VCC VTT0
AC29 AE10
2

VCC VTT0 C1234

AC28 AC10

1
VCC VTT0

CPU CORE SUPPLY

C AC27
VCC VTT0
AB10 DIS(Clarksfield +1.05V_VTT) = 14.4A C

SC10U6D3V5MX-3GP
AC26 Y10
VCC VTT0
AA35 W10

2
VCC VTT0
AA34
VCC VTT0
U10 DIS(Arrandale +1.05V_VTT) = 20.95A
AA33 T10
VCC VTT0
AA32 J12
VCC VTT0
AA31
VCC VTT0
J11 UMA(Arrandale +1.05V_VTT) = 19.84A
AA30 J16
C1235 C1236 C1237 C1238 C1239 C1240 C1241 C1242 VCC VTT0
AA29 J15
1

VCC VTT0
AA28
VCC
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

AA27
VCC
AA26
2

VCC
Y35
VCC
Y34
VCC
Y33
VCC
Y32
VCC
Y31
VCC
Y30
VCC
Y29
VCC
Y28
VCC
Y27
C1243 VCC
Y26
1

VCC
V35 AN33 PSI# 47
VCC PSI#
SC10U6D3V5MX-3GP

DY V34
V33
VCC
CPU_VID[6..0] 47
2

VCC CPU_VID0
V32 AK35
VCC VID
V31
V30
V29
VCC
VCC
POWER VID
VID
AK33
AK34
AL35
CPU_VID1
CPU_VID2
CPU_VID3
VCC VID
V28
VCC CPU VIDS VID
AL33 CPU_VID4
V27 AM33 CPU_VID5
VCC VID CPU_VID6
V26 AM35
VCC VID
U35 AM34 PM_DPRSLPVR 47
VCC PROC_DPRSLPVR
B U34 B
VCC
U33
VCC
U32
VCC TP_VTT_SELECT 1
U31 G15
VCC VTT_SELECT TP1203 Do Not Stuff
U30
VCC
U29
VCC
U28
VCC VTT_SELECT = Low, 1.1V
U27
U26
VCC VTT_SELECT = High, 1.05V +VCC_CORE
VCC
R35
VCC
R34

1
VCC
R33
VCC R1201
R32 AN35 IMVP_IMON 47
VCC ISENSE 100R2F-L1-GP-U
R31
VCC
R30
VCC
R29

2
VCC VCC_SENSE
SENSE LINES

R28 AJ34 VCC_SENSE 47

VCC VCC_SENSE VSS_SENSE
R27 AJ35 VSS_SENSE 47
VCC VSS_SENSE
R26

1
VCC
P35
VCC R1204
P34 B15 VTT_SENSE 49
VCC VTT_SENSE TP_VSS_SENSE_VTT 1 100R2F-L1-GP-U
P33 A15
VCC VSS_SENSE_VTT TP1202
P32
VCC Do Not Stuff
P31

2
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC

A A

UMA
CLARKUNF

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

CPU (VCC_CORE) Rev

Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 12 of 90
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU +1.5V_CPU +1.5V_CPU +1.5V_CPU

1
DYC1376 DYC1377 DYC1378 DYC1379
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP

2
+1.5V_SUS +1.5V_SUS +1.5V_SUS +1.5V_SUS

+CPU_GFXCORE CPU1G 7 OF 9 2009/08/12

22A AT21
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.
pdf" document.
VAXG
D AT19 VAXG VAXG_SENSE AR22 VCC_AXG_SENSE 53 D
TC1303 C1324 C1327 C1326 C1328 C1325 C1323

SENSE
LINES
AT18 VAXG VSSAXG_SENSE AT22 VSS_AXG_SENSE 53

1
AT16 VAXG

CLARKSFIELD
SE330U2VDM-L-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AR21
DY
2
DY DY AR19
VAXG

2
VAXG
AR18 VAXG
AR16 VAXG GFX_VID AM22 GFX_VID0 53
AP21 VAXG GFX_VID AP22 GFX_VID1 53

GRAPHICS VIDs
AP19 VAXG GFX_VID AN22 GFX_VID2 53
AP18 VAXG GFX_VID AP23 GFX_VID3 53
AP16 VAXG GFX_VID AM23 GFX_VID4 53
AN21 VAXG GFX_VID AP24 GFX_VID5 53

GRAPHICS
AN19 VAXG GFX_VID AN24 GFX_VID6 53
AN18 VAXG
AN16 VAXG
AM21 VAXG GFX_VR_EN AR25 GFX_VR_EN 53
AM19 AT25 TP_GFX_DPRSLPVR1 TP1303 Do Not Stuff
VAXG GFX_DPRSLPVR
AM18 VAXG GFX_IMON AM24
AM16 GFX_IMON_R 1 UMA R1301
2 GFX_IMON 53
VAXG
AL21 VAXG
AL19 1 DIS 2 0R2J-2-GP ARD=3A
VAXG R1302 +1.5V_CPU
AL18 VAXG
AL16 1KR2J-1-GP CFD=6A
VAXG
AK21 VAXG VDDQ AJ1
AK19 VAXG VDDQ AF1

1
AK18 AE7 C1301 C1302 C1303 C1304 C1305 C1306 C1307

- 1.5V RAILS
VAXG VDDQ

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AK16 AE4 TC1301
VAXG VDDQ SE330U2D5VDM-2GP
AJ21 AC1

2
VAXG VDDQ
AJ19 VAXG VDDQ AB7
C AJ18 AB4 C
VAXG VDDQ
AJ16 VAXG VDDQ Y1
AH21 VAXG VDDQ W7
AH19 VAXG VDDQ W4
AH18 VAXG VDDQ U1
AH16 T7

POWER
VAXG VDDQ
VDDQ T4
VDDQ P1
VDDQ N7
+1.05V_VTT N4
VDDQ

DDR3
Please note that the VTT Rail J24
VDDQ L1
H1
VTT1 VDDQ

FDI
Values are J23
H25
VTT1
VTT1
1

Arrandale VTT=1.05V; C1309

SC10U6D3V5MX-3GP
+1.05V_VTT

Clarksfield VTT=1.1V P10

2

VTT0
VTT0 N10

1
L10 C1310 C1311
VTT0 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
VTT0 K10

2
+1.05V_VTT
+1.05V_VTT
18A

1.1V
VTT1 J22
K26 VTT1 VTT1 J20

1
J27 J18 C1316 C1317
VTT1 VTT1

PEG & DMI

J26 H21 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
VTT1 VTT1
1

C1312 C1313 C1314 C1315 J25 H20

2
B VTT1 VTT1 B
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

H27 VTT1 VTT1 H19

G28
2

VTT1
G27 VTT1 ARD=1.35A +1.8V_RUN
G26 VTT1
F26 CFD=1.1A
VTT1
E26 VTT1 VCCPLL L26

1.8V
E25 VTT1 VCCPLL L27

1
M26 C1318 C1319 C1320 C1321 C1322
VCCPLL

SC1U25V5KX-1GP

SC1U25V5KX-1GP

SC4D7U6D3V5KX-3GP

SC2D2U10V3KX-1GP
SC10U6D3V5MX-3GP

2
CLARKUNF

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

CPU (VCC_GFXCORE) Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 13 of 90
5 4 3 2 1
 5 4 3 2 1

CPU1H 8 OF 9 CPU1I 9 OF 9

AT20 VSS VSS AE34

AT17 VSS VSS AE33
AR31 VSS VSS AE32 K27 VSS
AR28 VSS VSS AE31 K9 VSS

CLARKSFIELD

CLARKSFIELD
AR26 VSS VSS AE30 K6 VSS
AR24 VSS VSS AE29 K3 VSS
D AR23 VSS VSS AE28 J32 VSS D
AR20 VSS VSS AE27 J30 VSS
AR17 VSS VSS AE26 J21 VSS
AR15 VSS VSS AE6 J19 VSS
AR12 VSS VSS AD10 H35 VSS
AR9 VSS VSS AC8 H32 VSS
AR6 VSS VSS AC4 H28 VSS
AR3 VSS VSS AC2 H26 VSS
AP20 VSS VSS AB35 H24 VSS
AP17 VSS VSS AB34 H22 VSS
AP13 VSS VSS AB33 H18 VSS
AP10 VSS VSS AB32 H15 VSS
AP7 VSS VSS AB31 H13 VSS
AP4 VSS VSS AB30 H11 VSS
AP2 VSS VSS AB29 H8 VSS
AN34 VSS VSS AB28 H5 VSS
AN31 VSS VSS AB27 H2 VSS
AN23 VSS VSS AB26 G34 VSS
AN20 VSS VSS AB6 G31 VSS
AN17 VSS VSS AA10 G20 VSS
AM29 VSS VSS Y8 G9 VSS
AM27 VSS VSS Y4 G6 VSS
AM25 VSS VSS Y2 G3 VSS
AM20 VSS VSS W35 F30 VSS
AM17 VSS VSS W34 F27 VSS
AM14 VSS VSS W33 F25 VSS
AM11 VSS VSS W32 F22 VSS
AM8 VSS VSS W31 F19 VSS
AM5 VSS VSS W30 F16 VSS
C AM2 W29 E35 C
VSS VSS VSS
AL34 W28 E32
AL31
AL23
VSS
VSS
VSS
VSS VSS
VSS
VSS
W27
W26
E29
E24
VSS
VSS
VSS
VSS
AL20 VSS VSS W6 E21 VSS
AL17 VSS VSS V10 E18 VSS
AL12 VSS VSS U8 E13 VSS
AL9 VSS VSS U4 E11 VSS
AL6 VSS VSS U2 E8 VSS
AL3 VSS VSS T35 E5 VSS
AK29 VSS VSS T34 E2 VSS
AK27 VSS VSS T33 D33 VSS
AK25 VSS VSS T32 D30 VSS VSS_NCTF AR34
AK20 VSS VSS T31 D26 VSS VSS_NCTF B34
AK17 T30 D9 B2

NCTF
VSS VSS VSS VSS_NCTF
AJ31 VSS VSS T29 D6 VSS
AJ23 VSS VSS T28 D3 VSS

A35,AT1,AT35,B1,A3,A33,A34,
AJ20 T27 C34 A35 TP_MCP_VSS_NCTF1 1 TP1401

AP1,AP35,AR1,AR35,AT2,AT3,
VSS VSS VSS VSS_NCTF#A35 TP_MCP_VSS_NCTF2 TP1402
AJ17 VSS VSS T26 C32 VSS VSS_NCTF#AT1 AT1 1
AJ14 T6 C29 AT35 TP_MCP_VSS_NCTF3 1 TP1406
VSS VSS VSS VSS_NCTF#AT35 TP_MCP_VSS_NCTF4 TP1405
AJ11 VSS VSS R10 C28 VSS VSS_NCTF#B1 B1 1
AJ8 P8 C24 A3

AT33,AT34,C1,C35,B35
VSS VSS VSS RSVD_NCTF#A3
AJ5 VSS VSS P4 C22 VSS RSVD_NCTF#A33 A33
AJ2 VSS VSS P2 C20 VSS RSVD_NCTF#A34 A34
AH35 VSS VSS N35 C19 VSS RSVD_NCTF#AP1 AP1
AH34 VSS VSS N34 C16 VSS RSVD_NCTF#AP35 AP35

NCYF TEST PIN:

AH33 VSS VSS N33 B31 VSS RSVD_NCTF#AR1 AR1
AH32 VSS VSS N32 B25 VSS RSVD_NCTF#AR35 AR35
AH31 VSS VSS N31 B21 VSS RSVD_NCTF#AT2 AT2
B B
AH30 VSS VSS N30 B18 VSS RSVD_NCTF#AT3 AT3
AH29 VSS VSS N29 B17 VSS RSVD_NCTF#AT33 AT33
AH28 VSS VSS N28 B13 VSS RSVD_NCTF#AT34 AT34
AH27 VSS VSS N27 B11 VSS RSVD_NCTF#C1 C1
AH26 VSS VSS N26 B8 VSS RSVD_NCTF#C35 C35
AH20 VSS VSS N6 B6 VSS RSVD_NCTF#B35 B35
AH17 VSS VSS M10 B4 VSS
AH13 VSS VSS L35 A29 VSS
AH9 VSS VSS L32 A27 VSS
AH6 VSS VSS L29 A23 VSS
AH3 VSS VSS L8 A9 VSS
AG10 VSS VSS L5
AF8 VSS VSS L2
AF4 VSS VSS K34
AF2 VSS VSS K33
AE35 VSS VSS K30

CLARKUNF CLARKUNF

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 14 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 15 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 16 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 17 of 90
5 4 3 2 1
 5 4 3 2 1

DM1

SSID = MEMORY M_A_A0

M_A_A1
98
97
A0
A1
NP1
NP2
NP1
NP2
M_A_A2 96
M_A_A3 A2 SA0_DM1
95 A3 RAS# 110 M_A_RAS# 10
M_A_A4 92 113 M_A_W E# 10 SA1_DM1
M_A_A5 A4 WE#
91 A5 CAS# 115 M_A_CAS# 10
M_A_A6 90 A6

1
M_A_A7 86 114 M_CS0# 10
M_A_A8 A7 CS0# R1802 R1801
10 M_A_DQS#[7..0] 89 A8 CS1# 121 M_CS1# 10
M_A_A9 85 10KR2J-3-GP 10KR2J-3-GP
M_A_A10 A9
10 M_A_DQ[63..0] 107 A10/AP CKE0 73 M_CKE0 10
M_A_A11 84 74 M_CKE1 10

2
M_A_A12 A11 CKE1
D 10 M_A_DM[7..0] 83 A12 D
M_A_A13 119 101 M_CLK_DDR0 M_CLK_DDR0 10
M_A_A14 A13 CK0 M_CLK_DDR#0
10 M_A_DQS[7..0] 80 A14 CK0# 103 M_CLK_DDR#0 10
M_A_A15 78
10 M_A_A[15..0] 10 M_A_BS2
M_A_BS2 79
A15
A16/BA2 CK1 102 M_CLK_DDR1 M_CLK_DDR1 10
SMBUS address:A0
104 M_CLK_DDR#1 M_CLK_DDR#1 10
M_A_BS0 CK1#
10 M_A_BS0 109 BA0
M_A_BS1 108 11 M_A_DM0 Note:
10 M_A_BS1 BA1 DM0 M_A_DM1 If SA0_DIM0 = 0, SA1_DIM0 = 0
DM1 28
M_A_DQ0 5 46 M_A_DM2 SO-DIMMA SPD Address is 0xA0
M_A_DQ1 DQ0 DM2 M_A_DM3 If SA0_DIM0 = 1, SA1_DIM0 = 0
7 DQ1 DM3 63
M_A_DQ2 15 136 M_A_DM4 SO-DIMMA SPD Address is 0xA2
M_A_DQ3 DQ2 DM4 M_A_DM5 If SA0_DIM0 = 0, SA1_DIM0 = 1
17 DQ3 DM5 153
Layout Note: M_A_DQ4 4 170 M_A_DM6 SO-DIMMA SPD Address is 0xA4
M_A_DQ5 DQ4 DM6 M_A_DM7
Place near DM1 6 DQ5 DM7 187
+1.5V_SUS M_A_DQ6 16
M_A_DQ7 DQ6 PCH_SMBDATA
18 DQ7 SDA 200 PCH_SMBDATA 7,19,23,40,64
M_A_DQ8 21 202 PCH_SMBCLK
DQ8 SCL PCH_SMBCLK 7,19,23,40,64
C1803
SC10U6D3V5MX-3GP

C1804
SC10U6D3V5MX-3GP

C1812
SC10U6D3V5MX-3GP

C1802
SC10U6D3V5MX-3GP

C1811
SC10U6D3V5MX-3GP

C1816
SC10U6D3V5MX-3GP
TC1803 M_A_DQ9 23 DQ9
1

1
ST330U2D5VBM-1-GP M_A_DQ10 33 198 PM_EXTTS#0 9
M_A_DQ11 DQ10 EVENT# +3.3V_RUN
35 DQ11
M_A_DQ12 22 199
2

2
M_A_DQ13 DQ12 VDDSPD
24 DQ13

C1806
SCD1U16V2KX-3GP

C1807
SC2D2U10V3KX-1GP
M_A_DQ14 34 197 SA0_DM1
DQ14 SA0

1
M_A_DQ15 36 201 SA1_DM1
M_A_DQ16 DQ15 SA1
M_A_DQ17
39
41
DQ16
77
DY

2
M_A_DQ18 DQ17 NC#1
51 DQ18 NC#2 122
M_A_DQ19 53 125 +1.5V_SUS
M_A_DQ20 DQ19 NC#/TEST
40 DQ20
M_A_DQ21 42 75
M_A_DQ22 DQ21 VDD1
C Layout Note: 50 DQ22 VDD2 76 C
M_A_DQ23 52 81
Put close to VTT1,VTT2. M_A_DQ24 DQ23 VDD3
57 DQ24 VDD4 82
+0.75V_DDR_VTT M_A_DQ25 59 87
M_A_DQ26 DQ25 VDD5
67 DQ26 VDD6 88
M_A_DQ27 69 93
DQ27 VDD7
C1814
SC1U10V2KX-1GP

C1813
SC1U10V2KX-1GP

C1815
SC1U10V2KX-1GP

C1801
SC1U10V2KX-1GP

C1823 M_A_DQ28 56 94
DQ28 VDD8
1

SC10U6D3V5MX-3GP M_A_DQ29 58 99
M_A_DQ30 DQ29 VDD9
68 DQ30 VDD10 100
M_A_DQ31 70 105
2

M_A_DQ32 DQ31 VDD11

129 DQ32 VDD12 106
M_A_DQ33 131 111
DQ33 VDD13

Height 5.2mm
M_A_DQ34 141 112
M_A_DQ35 DQ34 VDD14
143 DQ35 VDD15 117
M_A_DQ36 130 118
M_A_DQ37 DQ36 VDD16
132 DQ37 VDD17 123
M_A_DQ38 140 124
M_A_DQ39 DQ38 VDD18
142 DQ39
M_A_DQ40 147 2
M_A_DQ41 DQ40 VSS
149 DQ41 VSS 3
M_A_DQ42 157 8
+1.5V_SUS M_A_DQ43 DQ42 VSS
159 DQ43 VSS 9
M_A_DQ44 146 13
M_A_DQ45 DQ44 VSS
148 DQ45 VSS 14
M_A_DQ46 158 19 put near connector
DQ46 VSS
C1872
SCD1U10V2KX-4GP

C1873
SCD1U10V2KX-4GP

C1874
SCD1U10V2KX-4GP

M_A_DQ47 160 20
C1875 M_A_DQ48 DQ47 VSS M_CLK_DDR0
163 DQ48 VSS 25
1

SCD1U10V2KX-4GP M_A_DQ49 165 26 M_CLK_DDR#0

M_A_DQ50 DQ49 VSS M_CLK_DDR1
175 DQ50 VSS 31
M_A_DQ51 177 32 M_CLK_DDR#1
2

M_A_DQ52 DQ51 VSS

164 DQ52 VSS 37
B M_A_DQ53 166 38 B
M_A_DQ54 DQ53 VSS
174 DQ54 VSS 43
M_A_DQ55 176 44
DQ55 VSS

1
M_A_DQ56 181 48
M_A_DQ57 DQ56 VSS
183 DQ57 VSS 49

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
C1821

C1819

C1820

C1818
2009/08/12 M_A_DQ58 191 54
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. M_A_DQ59 DQ58 VSS
193 DQ59 VSS 55
pdf" document. M_A_DQ60 180 60
M_A_DQ61 DQ60 VSS
182 61

2
M_A_DQ62 DQ61 VSS
192 DQ62 VSS 65
M_A_DQ63 194 66
DQ63 VSS
VSS 71
M_A_DQS#0 10 72
M_A_DQS#1 DQS0# VSS
27 DQS1# VSS 127
M_A_DQS#2 45 128
M_A_DQS#3 DQS2# VSS
62 DQS3# VSS 133
M_A_DQS#4 135 134
M_A_DQS#5 DQS4# VSS
152 DQS5# VSS 138
M_A_DQS#6 169 139
M_A_DQS#7 DQS6# VSS
186 DQS7# VSS 144
VSS 145
M_A_DQS0 12 150
M_A_DQS1 DQS0 VSS
29 DQS1 VSS 151
M_A_DQS2 47 155
+V_DDR_REF M_A_DQS3 DQS2 VSS
64 DQS3 VSS 156
M_A_DQS4 137 161
M_A_DQS5 DQS4 VSS
154 DQS5 VSS 162
+V_DDR_REF M_A_DQS6 171 167
DQS6 VSS
1

M_A_DQS7 188 168

C1810 C1809 DQS7 VSS
VSS 172
1

SCD1U16V2KX-3GP SC2D2U10V3KX-1GP 10 M_ODT0 M_ODT0 116 173

2

R1803 M_ODT1 ODT0 VSS

A 10 M_ODT1 120 ODT1 VSS 178 A
ARD0R2J-2-GP VSS 179 UMA
126 VREF_CA VSS 184
M_VREF_DQ_DIMM0 1 185
2

VREF_DQ VSS

M_VREF_DQ_DIMM0 11 9,19 DDR3_DRAMRST# 30 RESET#

VSS
VSS
189
190 Wistron Corporation
+0.75V_DDR_VTT 195 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS
1

196 Taipei Hsien 221, Taiwan, R.O.C.

C1817 C1805 VSS
203 VTT1 VSS 205
SCD1U16V2KX-3GP SC2D2U10V3KX-1GP 204 206 Title
2

VTT2 VSS 2009/07/30

Change connector to 62.10017.K11
Size Document Number
DDRIII-SODIMM SLOT1 Rev
DDR3-204P-25-GP
Custom
62.10017.K11 Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 18 of 90
5 4 3 2 1
 5 4 3 2 1

DM2

SSID = MEMORY M_B_A0

M_B_A1
98
97
A0
A1
NP1
NP2
NP1
NP2
M_B_A2 96
M_B_A3 A2
95 A3 RAS# 110 M_B_RAS# 10
M_B_A4 92 113 M_B_W E# 10
M_B_A5 A4 WE# +3.3V_RUN
91 A5 CAS# 115 M_B_CAS# 10
M_B_A6 90
M_B_A7 A6
86 A7 CS0# 114 M_CS2# 10
M_B_A8 89 121 M_CS3# 10
A8 CS1#

1
M_B_A9 85
10 M_B_DQS#[7..0] A9
M_B_A10 107 73 M_CKE2 10 R1903 R1904
M_B_A11 A10/AP CKE0 10KR2J-3-GP 10KR2J-3-GP
10 M_B_DQ[63..0]
M_B_A12
84 A11 CKE1 74 M_CKE3 10 DY
D 83 A12 D
M_B_A13 119 101 M_CLK_DDR2 M_CLK_DDR2 10
10 M_B_DM[7..0]

2
M_B_A14 A13 CK0 M_CLK_DDR#2 SA1_DM2
80 A14 CK0# 103 M_CLK_DDR#2 10
M_B_A15 78 SA0_DM2
10 M_B_DQS[7..0] A15
M_B_BS2 79 102 M_CLK_DDR3 M_CLK_DDR3 10
10 M_B_BS2 A16/BA2 CK1 M_CLK_DDR#3
10 M_B_A[15..0] CK1# 104 M_CLK_DDR#3 10

1
M_B_BS0 109
10 M_B_BS0 M_B_BS1 BA0 M_B_DM0 R1901 R1902
10 M_B_BS1 108 BA1 DM0 11
28 M_B_DM1 10KR2J-3-GP DY 10KR2J-3-GP
M_B_DQ0 DM1 M_B_DM2
5 DQ0 DM2 46
M_B_DQ1 7 63 M_B_DM3

2
M_B_DQ2 DQ1 DM3 M_B_DM4
15 DQ2 DM4 136
M_B_DQ3 17 153 M_B_DM5
M_B_DQ4 DQ3 DM5 M_B_DM6
4 DQ4 DM6 170
M_B_DQ5 6 187 M_B_DM7
M_B_DQ6 DQ5 DM7
16 DQ6
M_B_DQ7 18 200 PCH_SMBDATA
M_B_DQ8 21
DQ7
DQ8
SDA
SCL 202 PCH_SMBCLK
PCH_SMBDATA 7,18,23,40,64
PCH_SMBCLK 7,18,23,40,64
SMBUS address:A4
M_B_DQ9 23
M_B_DQ10 DQ9 +3.3V_RUN
33 DQ10 EVENT# 198 PM_EXTTS#1 9
M_B_DQ11 35
M_B_DQ12 DQ11
22 DQ12 VDDSPD 199
Layout Note: M_B_DQ13 24 DQ13

C1906
SCD1U16V2KX-3GP

C1921
SC2D2U10V3KX-1GP
M_B_DQ14 34 197 SA0_DM2
Place near DM2 DQ14 SA0

1
+1.5V_SUS M_B_DQ15 36 201 SA1_DM2
M_B_DQ16 DQ15 SA1
M_B_DQ17
39
41
DQ16
77
DY

2
DQ17 NC#1
C1919
SC10U6D3V5MX-3GP

C1905
SC10U6D3V5MX-3GP

C1911
SC10U6D3V5MX-3GP

C1916
SC10U6D3V5MX-3GP

C1913
SC10U6D3V5MX-3GP

C1920
SC10U6D3V5MX-3GP
TC1903 M_B_DQ18 51 122
ST330U2D5VBM-1-GP M_B_DQ19 DQ18 NC#2 +1.5V_SUS
53 DQ19 NC#/TEST 125
1

1
M_B_DQ20 40
M_B_DQ21 DQ20
42 DQ21 VDD1 75
C M_B_DQ22 50 76 C
2

2
M_B_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
M_B_DQ24 57 82
M_B_DQ25 DQ24 VDD4
59 DQ25 VDD5 87
M_B_DQ26 67 88
M_B_DQ27 DQ26 VDD6
69 DQ27 VDD7 93
M_B_DQ28 56 94
M_B_DQ29 DQ28 VDD8
58 DQ29 VDD9 99
M_B_DQ30 68 100
M_B_DQ31 DQ30 VDD10
70 DQ31 VDD11 105
M_B_DQ32 129 106
M_B_DQ33 DQ32 VDD12
Layout Note: 131 DQ33 VDD13 111
M_B_DQ34 141 112
+0.75V_DDR_VTT Put close to VTT1,VTT2. M_B_DQ35 DQ34 VDD14
143 DQ35 VDD15 117
M_B_DQ36 130 118
M_B_DQ37 DQ36 VDD16
132 DQ37 VDD17 123
C1908
SC1U10V2KX-1GP

C1917
SC1U10V2KX-1GP

C1909
SC1U10V2KX-1GP

C1918
SC1U10V2KX-1GP

M_B_DQ38 140 124

DQ38 VDD18
1

M_B_DQ39 142
M_B_DQ40 DQ39
147 DQ40 VSS 2

Height 9.2mm
M_B_DQ41 149 3
2

M_B_DQ42 DQ41 VSS

157 DQ42 VSS 8 put near connector
M_B_DQ43 159 9
M_B_DQ44 DQ43 VSS M_CLK_DDR2
146 DQ44 VSS 13
M_B_DQ45 148 14 M_CLK_DDR#2
M_B_DQ46 DQ45 VSS M_CLK_DDR3
158 DQ46 VSS 19
M_B_DQ47 160 20 M_CLK_DDR#3
M_B_DQ48 DQ47 VSS
163 DQ48 VSS 25
M_B_DQ49 165 26
M_B_DQ50 DQ49 VSS
175 DQ50 VSS 31
M_B_DQ51 177 32
DQ51 VSS

1
M_B_DQ52 164 37
M_B_DQ53 DQ52 VSS
B 166 DQ53 VSS 38 B

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
C1901

C1904

C1902

C1903
M_B_DQ54 174 43
M_B_DQ55 DQ54 VSS
176 DQ55 VSS 44
+1.5V_SUS M_B_DQ56 181 48
M_B_DQ57 DQ56 VSS
183 49

2
M_B_DQ58 DQ57 VSS
191 DQ58 VSS 54
C1976
SCD1U10V2KX-4GP

C1977
SCD1U10V2KX-4GP

C1978
SCD1U10V2KX-4GP

C1979 M_B_DQ59 193 55

SCD1U10V2KX-4GP M_B_DQ60 DQ59 VSS
180 DQ60 VSS 60
1

M_B_DQ61 182 61
M_B_DQ62 DQ61 VSS
192 DQ62 VSS 65
M_B_DQ63 194 66
2

DQ63 VSS
VSS 71
M_B_DQS#0 10 72
M_B_DQS#1 DQS0# VSS
27 DQS1# VSS 127
M_B_DQS#2 45 128
M_B_DQS#3 DQS2# VSS
62 DQS3# VSS 133
2009/08/12 M_B_DQS#4 135 134
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. M_B_DQS#5 DQS4# VSS
152 DQS5# VSS 138
pdf" document. M_B_DQS#6 169 139
M_B_DQS#7 DQS6# VSS
186 DQS7# VSS 144
VSS 145
M_B_DQS0 12 150
M_B_DQS1 DQS0 VSS
29 DQS1 VSS 151
M_B_DQS2 47 155
+V_DDR_REF M_B_DQS3 DQS2 VSS
64 DQS3 VSS 156
M_B_DQS4 137 161
M_B_DQS5 DQS4 VSS
154 DQS5 VSS 162
+V_DDR_REF M_B_DQS6 171 167
DQS6 VSS
1

M_B_DQS7 188 168

C1907 C1914 DQS7 VSS
VSS 172
1

SCD1U16V2KX-3GP SC2D2U10V3KX-1GP 10 M_ODT2 M_ODT2 116 173

2

R1905 M_ODT3 ODT0 VSS

A 10 M_ODT3 120 ODT1 VSS 178 A
ARD0R2J-2-GP VSS 179 UMA
126 VREF_CA VSS 184
M_VREF_DQ_DIMM1 1 185
2

VREF_DQ VSS
M_VREF_DQ_DIMM1 11
9,18 DDR3_DRAMRST# 30 RESET#
VSS
VSS
189
190 Wistron Corporation
1

195 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

C1910 C1912 +0.75V_DDR_VTT VSS Taipei Hsien 221, Taiwan, R.O.C.
VSS 196
SCD1U16V2KX-3GP SC2D2U10V3KX-1GP 203 205
2

VTT1 VSS 2009/07/30 Title

204 VTT2 VSS 206
Change connector to 62.10017.K01
DDRIII-SODIMM SLOT2
DDR3-204P-24-GP Size Document Number Rev
Custom
62.10017.K01 Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 19 of 90
5 4 3 2 1
 5 4 3 2 1

LCDVDD_EN_PCH 1 2
D
DY D

R2003
100KR2J-1-GP
R2011
0R2J-2-GP
U2001D 4 OF 10
37 PANEL_BKEN_PCH 1 2PANEL_BKEN_PCHR T48 L_BKLTEN SDVO_TVCLKINN BJ46
54 LCDVDD_EN_PCH LCDVDD_EN_PCH T47 BG46
L_VDD_EN SDVO_TVCLKINP
54 LBKLT_CTL_PCH Y48 L_BKLTCTL SDVO_STALLN BJ48
SDVO_STALLP BG48
54 L_DDC_CLK AB48 L_DDC_CLK
54 L_DDC_DATA Y45 L_DDC_DATA SDVO_INTN BF45
RN2001 BH45
LCTLA_CLK SDVO_INTP
+3.3V_RUN 2 3 AB46 L_CTRL_CLK
1 4 LCTLB_DATA V48 L_CTRL_DATA
SRN10KJ-5-GP LIBG AP39 T51
LVD_IBG SDVO_CTRLCLK SDVO_CLK 57,75
1

Do Not Stuff TP2001 1 TP_LVDS_VBG AP41 T53

LVD_VBG SDVO_CTRLDATA SDVO_DAT 57,75
R2002 Place near PCH
2K37R2F-GP AT43 LVD_VREFH
AT42 LVD_VREFL DDPB_AUXN BG44
BJ44
2

DDPB_AUXP
DDPB_HPD AU38 HDMI_HP_DET 21,57,75

LVDS
74 MCH_LVDSA_CLK# AV53 LVDSA_CLK#
74 MCH_LVDSA_CLK AV51 BD42 HDMI_DATA2-_C HDMI_DATA2-_C 75
LVDSA_CLK DDPB_0N HDMI_DATA2+_C
DDPB_0P BC42 HDMI_DATA2+_C 75
74 MCH_LVDSA_DAT0# BB47 BJ42 HDMI_DATA1-_C HDMI_DATA1-_C 75
C LVDSA_DATA#0 DDPB_1N HDMI_DATA1+_C C
74 MCH_LVDSA_DAT1# BA52 BG42 HDMI_DATA1+_C 75

Digital Display Interface

LVDSA_DATA#1 DDPB_1P HDMI_DATA0-_C
74 MCH_LVDSA_DAT2# AY48 LVDSA_DATA#2 DDPB_2N BB40 HDMI_DATA0-_C 75
AV47 BA40 HDMI_DATA0+_C HDMI_DATA0+_C 75
LVDSA_DATA#3 DDPB_2P HDMI_CLK-_C
DDPB_3N AW38 HDMI_CLK-_C 75
74 MCH_LVDSA_DAT0 BB48 BA38 HDMI_CLK+_C HDMI_CLK+_C 75
LVDSA_DATA0 DDPB_3P
74 MCH_LVDSA_DAT1 BA50 LVDSA_DATA1
74 MCH_LVDSA_DAT2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
DDPC_CTRLDATA AB49

74 MCH_LVDSB_CLK# AP48 LVDSB_CLK#

74 MCH_LVDSB_CLK AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
74 MCH_LVDSB_DAT0# AY53 LVDSB_DATA#0 DDPC_HPD AV40
74 MCH_LVDSB_DAT1# AT49 LVDSB_DATA#1
74 MCH_LVDSB_DAT2# AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
74 MCH_LVDSB_DAT0 AY51 LVDSB_DATA0 DDPC_1P BH41
74 MCH_LVDSB_DAT1 AT48 LVDSB_DATA1 DDPC_2N BD38
74 MCH_LVDSB_DAT2 AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36
50 ohm trace to filter
37.5 ohm trace to 150R resistor
74 MCH_BLUE MCH_BLUE AA52 U50
MCH_GREEN CRT_BLUE DDPD_CTRLCLK
74 MCH_GREEN AB53 CRT_GREEN DDPD_CTRLDATA U52
74 MCH_RED MCH_RED AD53 CRT_RED
B B
DDPD_AUXN BC46
2

55 GMCH_DDCCLK V51 CRT_DDC_CLK DDPD_AUXP BD46

R2007
150R2F-1-GP

R2006
150R2F-1-GP

R2005
150R2F-1-GP

55 GMCH_DDCDATA V53 CRT_DDC_DATA DDPD_HPD AT38

DDPD_0N BJ40
74 GMCH_HSYNC Y53 BG40
1

CRT_HSYNC DDPD_0P
74 GMCH_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
Place near PCH 1 2 CRT_IREF AD48 BH37
R2004 DAC_IREF DDPD_2P
AB51 CRT_IRTN DDPD_3N BE36
1KR2D-1-GP BD36
DDPD_3P
IBEXPEAK-M-GP-NF

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (LVDS/CRT/DDI)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 20 of 90
5 4 3 2 1
 5 4 3 2 1

RN2101
PCI_SERR# 1 10 +3.3V_RUN U2001E 5 OF 10
+3.3V_RUN
PCI_REQ1# 2 9 INT_PIRQC# H40 AY9
PCI_FRAME# PCI_STOP# AD0 NV_CE#0
3 8 N34 AD1 NV_CE#1 BD1

1
DGPU_SEL_BUF_# 4 7 PCI_IRDY# C2102 C44 AP15
INT_PIRQD# SCD1U16V2KX-3GP U2101 AD2 NV_CE#2
+3.3V_RUN 5 6 A38 AD3 NV_CE#3 BD8
1 C36

2
SRN8K2J-2-GP-U B AD4
5 VCC J34 AD5 NV_DQS0 AV9
2 PLTRST#_PCH A40 BG8
A AD6 NV_DQS1
9,37,64,70,76,77,80 PLT_RST# 4 Y D45 AD7
GND 3 E36 AD8 NV_DQ0/NV_IO0 AP7
RN2102 H48 AP6
PCI_REQ3# 74LVC1G08GW -1-GP AD9 NV_DQ1/NV_IO1
1 10 +3.3V_RUN E40 AD10 NV_DQ2/NV_IO2 AT6
D INT_PIRQB# 2 9 INT_PIRQA# C40 AT9 D
PCI_REQ0# PCI_PLOCK# AD11 NV_DQ3/NV_IO3
3 8 1 2 M48 BB1
PCI_PERR# 4 7 PCI_TRDY# R2104 DY 0R2J-2-GP M45
AD12 NV_DQ4/NV_IO4
AV6
AD13 NV_DQ5/NV_IO5

1
+3.3V_RUN 5 6 PCI_DEVSEL# F53 BB3
C2101 AD14 NV_DQ6/NV_IO6
M40 AD15 NV_DQ7/NV_IO7 BA4
SRN8K2J-2-GP-U SC220P50V2KX-3GP

NVRAM
M43 BE4
DY

2
AD16 NV_DQ8/NV_IO8
J36 AD17 NV_DQ9/NV_IO9 BB6
K48 AD18 NV_DQ10/NV_IO10 BD6
+3.3V_RUN F40 BB7
AD19 NV_DQ11/NV_IO11
RN2103 C42 BC8
PCH_GPIO3 +3.3V_RUN AD20 NV_DQ12/NV_IO12
1 8 K46 AD21 NV_DQ13/NV_IO13 BJ8
2 7 INT_PIRQE# M51 BJ6
HDMI_HP_DET_R AD22 NV_DQ14/NV_IO14
3 6 J52 AD23 NV_DQ15/NV_IO15 BG6

1
4 5 PCH_GPIO5 C2104 K51
SCD1U16V2KX-3GP U2103 AD24 TP_NV_ALE TP2117Do Not Stuff
SRN10KJ-7GP
DY L34 AD25 NV_ALE BD3
TP_NV_CLE
1
TP2119Do Not Stuff
1 F42 AY6 1

2
B AD26 NV_CLE
5 VCC J40 AD27
2 DGPU_SEL_BUF_# G46
A AD28 TP_NV_RCOMP TP2118Do Not Stuff
54,74 DGPU_SELECT# 4 Y DY F44 AD29 NV_RCOMP AU2 1
GND 3 M47 AD30

PCI
H36 AD31 NV_RB# AV7
74LVC1G08GW -1-GP
J50 C/BE0# NV_WR#0_RE# AY8
+3.3V_RUN +3.3V_RUN 1
R2115
DY 2
0R2J-2-GP
G42 C/BE1# NV_WR#1_RE# AY5
H47 C/BE2# Add USB Port for right side board

1
G34 AV11
C/BE3# NV_WE#_CK0 2009/07/13
1

DY C2113 BF5
R2114 SC220P50V2KX-3GP INT_PIRQA# NV_WE#_CK1
G38

2
R2107 INT_PIRQB# PIRQA#
UMA UMA10KR2J-3-GP H51 PIRQB# USB
C 10KR2J-3-GP INT_PIRQC# B37 H18 C
PIRQC# USBP0N USB_PN0 76
INT_PIRQD# A44 J18 Pair Device
USB_PP0 76
2

DGPU_SELECT# DGPU_PW M_SELECT# PIRQD# USBP0P

USBP1N A18 USB_PN1 76
PCI_REQ0# F51 C18 0 USB1 > LAN BOARD
REQ0# USBP1P USB_PP1 76
1

PCI_REQ1# A46 N20

REQ1#/GPIO50 USBP2N USB_PN2 63
DGPU_SEL_BUF_# B45 P20 1 USB4 > LAN BOARD
REQ2#/GPIO52 USBP2P USB_PP2 63
R2113 DIS R2117 DIS PCI_REQ3# M53 J20
REQ3#/GPIO54 USBP3N USB_PN3 63
10KR2J-3-GP 10KR2J-3-GP TP2116 L20 2 USB2 > M/B
USBP3P USB_PP3 63
Do Not Stuff 1 PCI_GNT0# F48 F20 USB_PN4 63
2

R2116 GNT0# USBP4N

K45 GNT1#/GPIO51 USBP4P G20 USB_PP4 63 3 USB3 > M/B
54 DGPU_PW M_SELECT# DGPU_PW M_SELECT# 0R2J-2-GP 1 DY 2 DGPU_PW M_SELECT#_RF36 A20 TP_USB_PN5
GNT2#/GPIO53 USBP5N TP2129
PCI_GNT3# H53 C20 TP_USB_PP5 4 USB for ESATA
GNT3#/GPIO55 USBP5P TP2130
R2121 M22 TP_USB_PN6
USBP6N TP2128
40 HDD_FALL_INT1 10R2J-2-GP 2 INT_PIRQE# B41 PIRQE#/GPIO2 USBP6P N22 TP_USB_PP6
TP2127 5 RESERVED
R2122 PCH_GPIO3 K53 B21 TP_USB_PN7
PIRQF#/GPIO3 USBP7N TP2126
1 2 HDMI_HP_DET_R A36 D21 TP_USB_PP7 6 RESERVED
20,57,75 HDMI_HP_DET DY PCH_GPIO5 A48
PIRQG#/GPIO4 USBP7P
H22
TP2125
(Not available for HM55)
PIRQH#/GPIO5 USBP8N USB_PN8 77
0R2J-2-GP J22 7 RESERVED
USBP8P USB_PP8 77

USB
Do Not Stuff TP2108 1 PCIRST# K6 E22 TP_USB_PN9
TP2131
(Not available for HM55)
PCIRST# USBP9N TP_USB_PP9
USBP9P F22 TP2132 8 BlUETOOTH
PCI_SERR# E44 A22
SERR# USBP10N USB_PN10 78
PCI_PERR# E50 C22 9 RESERVED
PERR# USBP10P USB_PP10 78
USBP11N G24 USB_PN11 73
USBP11P H24 USB_PP11 73 10 Biometric
BOOT BIOS Strap PCI_IRDY# A42 L24
IRDY# USBP12N USB_PN12 77
H44 PAR USBP12P M24 USB_PP12 77 11 CAMERA
PCI_GNT#0 PCI_GNT#1 BOOT BIOS Location PCI_DEVSEL# F46 A24 USB_PN13 64
PCI_FRAME# DEVSEL# USBP13N
C46 FRAME# USBP13P C24 USB_PP13 64 12 New Card
B
0 0 LPC B
PCI_PLOCK# D49 13 WLAN
PLOCK# USB_RBIAS_PN
0 1 Reserved USBRBIAS# B25 1 2
PCI_STOP# D41
PCI_TRDY# STOP# R2106
1 0 PCI C48 TRDY# USBRBIAS D25
22D6R2F-L1-GP
1 1 SPI(Default) Do Not Stuff TP2115 1 PCH_PME# M7 PME# USB_OC#0_1
OC0#/GPIO59 N16 USB_OC#0_1 76
PLTRST#_PCH D5 J16 USB_OC#2_3 USB_OC#2_3 63
PLTRST# OC1#/GPIO40 USB_OC#4_5
OC2#/GPIO41 F16 USB_OC#4_5 63
R2110 1 2 22R2J-2-GP PCLK_FW H_R N52 L16 USB_OC#6_7
70
23
PCLK_FW H
CLK_PCI_FB R2108 1 DY 2 22R2J-2-GP CLK_PCI_FB_R P53
CLKOUT_PCI0 OC3#/GPIO42
E14 USB_OC#8_9
R2111 1 22R2J-2-GP PCLK_KBC_R CLKOUT_PCI1 OC4#/GPIO43 USB_OC#10_11
37 PCLK_KBC 2 P46 CLKOUT_PCI2 OC5#/GPIO9 G16
76 PCLK_TPM R2112 1 2 22R2J-2-GP PCLK_TPM_R P51 F12 USB_OC#12_13
CLKOUT_PCI3 OC6#/GPIO10 PCH_OC7#
P48 CLKOUT_PCI4 OC7#/GPIO14 T15

IBEXPEAK-M-GP-NF
Calpella Platform Design Guide
Revision 1.6
Table 111. Overcurrent Pin Example Configuration Page 233
These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs.
PLTRST#_PCH
A16 swap override Strap/Top-Block The unused USB ports can be left as no connect.
1

Swap Override jumper C2103

SCD1U16V2KX-3GP
RP2101
A DY UMA A
2

PCI_GNT#3 Low = A16 swap USB_OC#4_5 1 10 +3.3V_ALW

override/Top-Block USB_OC#8_9 2 9 USB_OC#10_11
USB_OC#6_7 USB_OC#2_3
Swap Override enabled
High = Default
USB_OC#12_13
3
4
8
7 USB_OC#0_1 Wistron Corporation
5 6 PCH_OC7# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
+3.3V_ALW Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-L3-GP
R2109 Title
PCI_GNT3# 1
DY 2
PCH (PCI/USB/NVRAM)
4K7R2J-2-GP Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 21 of 90
5 4 3 2 1
 5 4 3 2 1

U2001C 3 OF 10
BA18 FDI_TXN0 FDI_TXN0 8
FDI_RXN0 FDI_TXN1 +3.3V_ALW
8 DMI_CTX_PRXN0 BC24 DMI0RXN FDI_RXN1 BH17 FDI_TXN1 8
8 DMI_CTX_PRXN1 BJ22 BD16 FDI_TXN2 FDI_TXN2 8 RN2201
DMI1RXN FDI_RXN2 FDI_TXN3 SRN10KJ-5-GP
8 DMI_CTX_PRXN2 AW20 DMI2RXN FDI_RXN3 BJ16 FDI_TXN3 8
8 DMI_CTX_PRXN3 BJ20 BA16 FDI_TXN4 FDI_TXN4 8 PM_RI# 4 1
DMI3RXN FDI_RXN4 FDI_TXN5 SUS_PW R_ACK
FDI_RXN5 BE14 FDI_TXN5 8 3 2
8 DMI_CTX_PRXP0 BD24 BA14 FDI_TXN6 FDI_TXN6 8
DMI0RXP FDI_RXN6 FDI_TXN7
8 DMI_CTX_PRXP1 BG22 DMI1RXP FDI_RXN7 BC12 FDI_TXN7 8
D 8 DMI_CTX_PRXP2 BA20 DMI2RXP D
8 DMI_CTX_PRXP3 BG20 BB18 FDI_TXP0 FDI_TXP0 8 PM_BATLOW #_R R2201 1 2 10KR2J-3-GP
DMI3RXP FDI_RXP0 FDI_TXP1
FDI_RXP1 BF17 FDI_TXP1 8
8 DMI_PTX_CRXN0 BE22 BC16 FDI_TXP2 FDI_TXP2 8 PCIE_W AKE# R2202 1 2 1KR2J-1-GP
DMI0TXN FDI_RXP2 FDI_TXP3
8 DMI_PTX_CRXN1 BF21 DMI1TXN FDI_RXP3 BG16 FDI_TXP3 8
8 DMI_PTX_CRXN2 BD20 AW16 FDI_TXP4 FDI_TXP4 8 AC_PRESENT_EC R2217 1 2 10KR2J-3-GP
DMI2TXN FDI_RXP4 FDI_TXP5
8 DMI_PTX_CRXN3 BE18 DMI3TXN FDI_RXP5 BD14 FDI_TXP5 8
BB14 FDI_TXP6 FDI_TXP6 8
FDI_RXP6 FDI_TXP7 PM_RSMRST#_R R2203 1
8 DMI_PTX_CRXP0 BD22 DMI0TXP FDI_RXP7 BD12 FDI_TXP7 8 2 10KR2J-3-GP
8 DMI_PTX_CRXP1 BH21 DMI1TXP
8 DMI_PTX_CRXP2 BC20 DMI2TXP
8 DMI_PTX_CRXP3 BD18 BJ14 FDI_INT FDI_INT 8
DMI3TXP FDI_INT

DMI
FDI
BF13 FDI_FSYNC0 FDI_FSYNC0 8
+1.05V_PCH FDI_FSYNC0
BH25 DMI_ZCOMP
R2204 BH13 FDI_FSYNC1 FDI_FSYNC1 8
DMI_IRCOMP_R FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
BJ12 FDI_LSYNC0 FDI_LSYNC0 8
49D9R2F-GP FDI_LSYNC0
+3.3V_RUN BG14 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 8

1
R2205
10KR2J-3-GP

9 XDP_DBRESET# 2 XDP_DBRESET# T6 SYS_RESET# WAKE# J12 PCIE_W AKE# 76,77

C C
M6 Y1 PM_CLKRUN#
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 37

System Power Management

37 PM_PW ROK R2207 1 2 0R2J-2-GP PM_PW RGD B17 PWROK
R2208 1 2 10KR2J-3-GP
K5 P8 TP_SUS_STAT# 1
MEPWROK SUS_STAT#/GPIO61 TP2205 Do Not Stuff

R2209 1 2 10KR2J-3-GP LAN_RST#1 A10 F3 PCH_SUSCLK 1 2 PCH_SUSCLK_2102 39

LAN_RST# SUSCLK/GPIO62 R2219 0R2J-2-GP

9 PM_DRAM_PW RGD PM_DRAM_PW RGD D9 E4 PCH_SLP_S5# 1 1 2 PCH_SUSCLK_KBC 37

DRAMPWROK SLP_S5#/GPIO63 TP2202Do Not Stuff R2220 0R2J-2-GP

37 RSMRST#_KBC R2210 1 20R2J-2-GP PM_RSMRST#_R C16 H7 PM_SLP_S4#_R 1 2 PM_SLP_S4# 37,50,77

RSMRST# SLP_S4# R2211 0R2J-2-GP

37 SUS_PW R_DN_ACK R2218 1 20R2J-2-GP SUS_PW R_ACK M1 P12 PM_SLP_S3#_R 1 2 PM_SLP_S3# 37,42,50,51,52,77,86
SUS_PWR_DN_ACK/GPIO30 SLP_S3# R2212 0R2J-2-GP
9 PM_PW RBTN#_R

37 PM_PW RBTN# 1 2 PM_PW RBTN#_R P5 K8 SIO_SLP_M#_R 1

R2213 0R2J-2-GP PWRBTN# SLP_M# TP2203Do Not Stuff

37 AC_PRESENT_EC AC_PRESENT_EC 1 2 AC_PRESENT P7 N2 PM_SLP_DSW # 1

R2216 0R2J-2-GP ACPRESENT/GPIO31 TP23 TP2204Do Not Stuff

PM_BATLOW #_R A6 BJ10 H_PM_SYNC

B BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 9 B

PM_RI# F14 F6
RI# SLP_LAN#/GPIO29

IBEXPEAK-M-GP-NF

+3.3V_RUN
R2214
10KR2J-3-GP
PM_CLKRUN# 1 2
1

R2215
Option to " Disable " clkrun. 10KR2J-3-GP
A DY UMA A
Pulling it down will keep the clks running.
Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (DM I/FDI/PM)

Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 22 of 90
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW +3.3V_ALW +3.3V_ALW

U2001B 2 OF 10

1
2

1
2

1
2
R2301
77 PCIE_IRXN1_CTXN1 BG30 B9 SMBALERT# 2 1 10KR2J-3-GP +3.3V_ALW RN2313 RN2302 RN2306
PERN1 SMBALERT#/GPIO11
77 PCIE_IRXP1_CTXP1 BJ30 PERP1 Card SRN2K2J-1-GP SRN2K2J-1-GP SRN2K2J-1-GP
77 PCIE_ITXN1_CRXN1 C2306 2 1 SCD1U16V2KX-3GP PCIE_ITXN1_CRXN1_C BF29 H14 PCH_SMB_CLK
PETN1 SMBCLK PCH_SMB_CLK 77
77 PCIE_ITXP1_CRXP1 C2305 2 1 SCD1U16V2KX-3GP PCIE_ITXP1_CRXP1_C BH29 PETP1 Reader PCH_SMB_DATA
C8 PCH_SMB_DATA 77

4
3

4
3

4
3
SMBDATA
D 64 PCIE_IRXN2_MTXN2 AW30 PERN2 D
BA30 R2302
64 PCIE_IRXP2_MTXP2
C2318 2 1 SCD1U16V2KX-3GP PCIE_ITXN2_MRXN2_C BC30
PERP2 WLAN J14 SML0ALERT# 2 1 10KR2J-3-GP SML0_CLK PCH_SMB_CLK SML1CLK
64 PCIE_ITXN2_MRXN2 PETN2 SML0ALERT#/GPIO60 +3.3V_ALW
64 PCIE_ITXP2_MRXP2 C2310 2 1 SCD1U16V2KX-3GP PCIE_ITXP2_MRXP2_C BD30 SML0_DATA PCH_SMB_DATA SML1DAT
PETP2 SML0_CLK
SML0CLK C6 SML0_CLK 9
76 PCIE_IRXN3_LRTXN3 AU30

SMBus
PERN3 SML0_DATA
76 PCIE_IRXP3_LRTXP3 AT30 PERP3 SML0DATA G8 SML0_DATA 9
C2303 2 1 SCD1U16V2KX-3GP PCIE_ITXN3_LRXN3_C AU32
76 PCIE_ITXN3_LRXN3
C2309 2 1 SCD1U16V2KX-3GP PCIE_ITXP3_LRXP3_C AV32
PETN3 LAN R2303
76 PCIE_ITXP3_LRXP3 PETP3
M14 SML1ALERT# 2 1 10KR2J-3-GP +3.3V_ALW
SML1ALERT#/GPIO74
BA32 PERN4
BB32 E10 SML1CLK
PERP4 SML1CLK/GPIO58 SML1CLK 37 2009/07/28
BD32 PETN4
BE32 G12 SML1DAT +3.3V_RUN Change 2N7002 ESD pretect from standard to 1KV type
PETP4 SML1DATA/GPIO75 SML1DAT 37 P/N:84.2N702.E31

PCI-E*
77 PCIE_IRXN5_NTXN5 BF33 PERN5
BH33 T13 CL_CLK 1 +3.3V_ALW RN2303
77 PCIE_IRXP5_NTXP5 PERP5 New CL_CLK1

Controller
77 PCIE_ITXN5_NRXN5 C2308 2 1 SCD1U16V2KX-3GP PCIE_ITXN5_NRXN5_C BG32 TP2301Do Not Stuff 2 3
PETN5
77 PCIE_ITXP5_NRXP5 C2304 2 1 SCD1U16V2KX-3GP PCIE_ITXP5_NRXP5_C BJ32 PETP5 Card CL_DATA1 T11 CL_DATA 1 1 4

1
TP2302Do Not Stuff

Link
BA34 T9 CL_RST# 1 R2304 SRN2K2J-1-GP
PERN6 CL_RST1# TP2303Do Not Stuff
AW34 PERP6 10KR2J-3-GP
BC34 PETN6
BD34

2
PETP6 PEG_CLKREQ# PCH_SMB_DATA
PEG_A_CLKRQ#/GPIO47 H1 6 1 PCH_SMBDATA 7,18,19,40,64
(Not available for HM55) AT34 PERN7
AU34 RN709 5 2
PERP7 CLK_PCIE_VGA1#
AU36 PETN7 CLKOUT_PEG_A_N AD43 1 4 SRN0J-6-GP CLK_PCIE_VGA# 80
AV36 AD45 CLK_PCIE_VGA1 2 DIS 3 CLK_PCIE_VGA 80 4 3
C PETP7 CLKOUT_PEG_A_P C
(Not available for HM55) BG34 AN4 CLK_EXP_N CLK_EXP_N 9 Q2301
PERN8 CLKOUT_DMI_N

PEG
BJ34 AN2 CLK_EXP_P CLK_EXP_P 9 DMN66D0LDW -7-GP
PERP8 CLKOUT_DMI_P
BG36 PETN8 PCH_SMBCLK 7,18,19,40,64
BJ36 PETP8
AT1 CLK_DP_N CLK_DP_N 9 PCH_SMB_CLK
CLKOUT_DP_N/CLKOUT_BCLK1_N CLK_DP_P 2009/07/28
CLKOUT_DP_P/CLKOUT_BCLK1_P AT3 CLK_DP_P 9 Change 2N7002 ESD pretect from standard to 1KV type
AK48 CLKOUT_PCIE0N P/N:84.2N702.E31
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. AK47 CLKOUT_PCIE0P

From CLK BUFFER

AW24 CLKIN_DMI#
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN CLKIN_DMI_N CLKIN_DMI
CLKIN_DMI# 7
PEG_CLKREQ#
P9 PCIECLKRQ0#/GPIO73 CLKIN_DMI_P BA24 CLKIN_DMI 7

77 CLK_PCIE_NEW # RN2311 1 4 CLK_PCIE_NEW 1# AM43 AP3 CLK_CPU_BCLK# CLK_CPU_BCLK# 7

D
SRN0J-6-GP CLK_PCIE_NEW 1 CLKOUT_PCIE1N CLKIN_BCLK_N CLK_CPU_BCLK
77 CLK_PCIE_NEW 2 3 AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_CPU_BCLK 7

77 NEW CARD_CLKREQ# NEW CARD_CLKREQ# U4 Q2305

PCIECLKRQ1#/GPIO18 DREFCLK#
CLKIN_DOT_96N F18 DREFCLK# 7 25,86,87 DGPU_PW RGD G 2N7002A-7-GP
E18 DREFCLK DREFCLK 7
RN2305 CLK_PCIE_MINI1_1# CLKIN_DOT_96P
64 CLK_PCIE_MINI1# 2 3 AM47 CLKOUT_PCIE2N
64 CLK_PCIE_MINI1 SRN0J-6-GP 1 4 CLK_PCIE_MINI1_1 AM48

S
CLKOUT_PCIE2P CLK_PCIE_SATA# 2009/08/10
CLKIN_SATA_N/CKSSCD_N AH13 CLK_PCIE_SATA# 7
MINI1_CLKREQ# CLK_PCIE_SATA Modify 25MHz crystal schematic
64 MINI1_CLKREQ# N4 PCIECLKRQ2#/GPIO20 CLKIN_SATA_P/CKSSCD_P AH12 CLK_PCIE_SATA 7 for Intel design guideline on PCH.

76 CLK_PCIE_LAN# RN2304 1 4 CLK_PCIE_LAN1# AH42 P41 CLK_PCH_14M CLK_PCH_14M 7

SRN0J-6-GP CLK_PCIE_LAN1 CLKOUT_PCIE3N REFCLK14IN R2308 1 DIS
76 CLK_PCIE_LAN 2 3 AH41 CLKOUT_PCIE3P 2
0R2J-2-GP
76 CLKREQ#_LAN CLKREQ#_LAN A8 J42 CLK_PCI_FB CLK_PCI_FB 21 C2311
B PCIECLKRQ3#/GPIO25 CLKIN_PCILOOPBACK XTAL25_IN B
2 1 SC18P50V2JN-1-GP
UMA

1
AM51 AH51 XTAL25_IN
CLKOUT_PCIE4N XTAL25_IN

1
AM53 AH53 XTAL25_OUT R2305 X2301
CLKOUT_PCIE4P XTAL25_OUT +1.05V_PCH 1MR2J-1-GPUMA
PCIE_CLK_RQ4# XCLK_RCOMP R2306 1
UMA XTAL-25MHZ-67GP
M9 PCIECLKRQ4#/GPIO26 XCLK_RCOMP AF38 2 90D9R2F-1-GP

2
XTAL25_OUT 2 UMA 1
RN2310 1 4 CLK_PCIE_R5U230_1# AJ50 T45 TP_CLK_OUTFLEX0 1 TP2307 C2307
77 CLK_PCIE_R5U230# CLKOUT_PCIE5N CLKOUTFLEX0/GPIO64
77 CLK_PCIE_R5U230 SRN0J-6-GP 2 3 CLK_PCIE_R5U230_1 AJ52 Do Not Stuff SC18P50V2JN-1-GP
CLKOUT_PCIE5P
PCIE_CLK_RQ5# H6 P43 TP_CLK_OUTFLEX1 1 TP2305
Clock Flex

77 PCIE_CLK_RQ5# PCIECLKRQ5#/GPIO44 CLKOUTFLEX1/GPIO65 +3.3V_RUN +3.3V_RUN

Do Not Stuff

AK53 T42 EDID_SELECT_R#

CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66

1
AK51 CLKOUT_PEG_B_P
PEG_B_CLKRQ# P13 N50 TP_CLK_OUTFLEX3 1 TP2306 R2312 DY R2307 UMA
+3.3V_ALW PEG_B_CLKRQ#/GPIO56 CLKOUTFLEX3/GPIO67 Do Not Stuff 10KR2J-3-GP 10KR2J-3-GP

2
RN2307 IBEXPEAK-M-GP-NF EDID_SELECT_R# EDID_SELECT#
8 1 PCIE_CLK_RQ5# +3.3V_RUN

1
7 2 PEG_B_CLKRQ#
6 3 CLKREQ#_LAN
1

5 4 PCIE_CLK_RQ4# C2301 R2309

SCD1U16V2KX-3GP DY U2302 10KR2J-3-GP DIS
SRN10KJ-7GP 1
2

2
B
5 VCC
A 2 EDID_SELECT_R# UMA A
+3.3V_RUN A
54,55,57 EDID_SELECT# 4 Y DY
GND 3
NEW CARD_CLKREQ#
1
2
4
3 MINI1_CLKREQ# 74LVC1G08GW -1-GP Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1 2 Taipei Hsien 221, Taiwan, R.O.C.
RN2308 R2311 DY 0R2J-2-GP
1

SRN10KJ-5-GP Title
C2312
DY SC220P50V2KX-3GP PCH (PCI-E/SMBUS/CLOCK/CL)
2

Size Document Number Rev

Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 23 of 90
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1 +RTC_CELL
R2402
1 2 PCH_RTCX2 20KR2J-L2-GP
R2401 1 2
10MR2J-L-GP INTVRMEN- Integrated SUS

C2401
SC1U6D3V3KX-2GP
1.1V VRM Enable

1
X2401
High - Enable internal VRs
1 4

2
1

1
D C2402 C2403 U2001A 1 OF 10 LPC_LAD[0..3] D
LPC_LAD[0..3] 37,70,76
SC18P50V2JN-1-GP 2 3 SC18P50V2JN-1-GP
PCH_RTCX1 B13 D33 LPC_LAD0
2

2
+RTC_CELL PCH_RTCX2 RTCX1 FWH0/LAD0 LPC_LAD1
D13 RTCX2 FWH1/LAD1 B33
X-32D768KHZ-38GPU R2403 C32 LPC_LAD2
20KR2J-L2-GP FWH2/LAD2 LPC_LAD3
FWH3/LAD3 A32
1 2 PCH_RTCRST# C14 RTCRST#
FWH4/LFRAME# C34 LPC_LFRAME# 37,70,76

2
SRTCRST# D17 SRTCRST#

1
C2404 G2401 A34

RTC

LPC
SC1U6D3V3KX-2GP SM_INTRUDER# LDRQ0#
Do Not Stuff 1 2 A16 INTRUDER# LDRQ1#/GPIO23 F34
R2406 1MR2J-1-GP

2
+RTC_CELL 1 2 PCH_INTVRMEN A14 AB9 INT_SERIRQ 37,76

1
R2404 330KR2F-L-GP INTVRMEN SERIRQ

Flash Descriptor Security 30 PCH_AZ_CODEC_BITCLK

R2405 1 2 33R2J-2-GP ACZ_BIT_CLK A30 HDA_BCLK
HDD
Override/ ME Debug Mode SATA0RXN AK7 SATA_IRXN0_HTXN0_C 59
R2407 1 2 33R2J-2-GP ACZ_SYNC_R D29 AK6 SATA_IRXP0_HTXP0_C 59
30 PCH_AZ_CODEC_SYNC HDA_SYNC SATA0RXP
SATA0TXN AK11 SATA_ITXN0_HRXN0_C 59
30 SB_SPKR P1 SPKR SATA0TXP AK9 SATA_ITXP0_HRXP0_C 59

This strap should only be asserted low via 30 PCH_AZ_CODEC_RST#

R2408 1 2 33R2J-2-GP ACZ_RST#_R C30 HDA_RST#
CAP place near connector ODD
ME_UNLOCK# external pull down in manufacturing/debug SATA1RXN AH6 SATA_IRXN1_OTXN1_C 59
SATA1RXP AH5 SATA_IRXP1_OTXP1_C 59
environments ONLY. G30 AH9
30 PCH_SDIN_CODEC HDA_SDIN0 SATA1TXN SATA_ITXN1_ORXN1_C 59
SATA1TXP AH8 SATA_ITXP1_ORXP1_C 59
F30 HDA_SDIN1
SATA2RXN AF11 CAP place near connector
C E32 AF9 C

IHDA
ME_UNLOCK_R# HDA_SDIN2 SATA2RXP (Not available for HM55)
1 DY 2 SATA2TXN AF7
R2419 1KR2J-1-GP F32 AF6
HDA_SDIN3 SATA2TXP

SATA3RXN AH3
R2409 1 2 33R2J-2-GP ACZ_SDATAOUT_R B29 AH1
30 PCH_SDOUT_CODEC HDA_SDO SATA3RXP (Not available for HM55)
SATA3TXN AF3
AF1
R2417 1 2 0R2J-2-GP ME_UNLOCK_R# H32
SATA3TXP ESATA

SATA
37 ME_UNLOCK# HDA_DOCK_EN#/GPIO33
SATA4RXN AD9 ESATA_IRX_DTX_N4_C 63
J30 HDA_DOCK_RST#/GPIO13 SATA4RXP AD8 ESATA_IRX_DTX_P4_C 63
SATA4TXN AD6 ESATA_ITX_DRX_N4_C 63
+3.3V_RUN NO REBOOT STRAP SATA4TXP AD5 ESATA_ITX_DRX_P4_C 63

No Reboot Strap R23 Do Not Stuff TP2404 1 PCH_JTAG_TCK M3 JTAG_TCK SATA5RXN AD3 CAP place near connector
SATA5RXP AD1
1 DY 2 SB_SPKR Low = Default Do Not Stuff TP2405 1 PCH_JTAG_TMS K3 JTAG_TMS SATA5TXN AB3
R2410 1KR2J-1-GP HDA_SPKR High = No Reboot AB1
Do Not Stuff TP2406 PCH_JTAG_TDI SATA5TXP
1 K1 JTAG_TDI

JTAG
1 2 INT_SERIRQ Do Not Stuff TP2407 1 PCH_JTAG_TDO J2 AF16
R2411 10KR2J-3-GP JTAG_TDO SATAICOMPO +1.05V_PCH
Do Not Stuff TP2408 1 PCH_JTAG_RST# J4 AF15 SATAICOMP R2412 1 2 37D4R2F-GP
TRST# SATAICOMPI

62 PCH_SPI_CLK R2413 1 2 15R2J-GP SPI_CLK_R BA2 SPI_CLK

62 PCH_SPI_CS0# R2414 1 2 15R2J-GP SPI_CS#0_R AV3
B SPI_CS0# B

AY3 SPI_CS1# SATALED# T3 SATA_LED# 66

62 PCH_SPI_DO R2415 1 2 15R2J-GP SPI_MOSI_R AY1 Y9 GPIO_DSM GPIO_DSM 76

SPI_MOSI SATA0GP/GPIO21

SPI
62 PCH_SPI_DI AV1 V1 PCH_GPIO19
SPI_MISO SATA1GP/GPIO19

IBEXPEAK-M-GP-NF

+3.3V_RUN

R2418
10KR2J-3-GP
PCH_GPIO19 1 2

R2416
10KR2J-3-GP
GPIO_DSM 1 2

2009/08/06
R2416 made STUFF ,For Lan chip connecter senser Pin.

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (SPI/RTC/LPC/SATA/IHDA)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 24 of 90
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN_GPU

1
+3.3V_RUN_GPU +3.3V_RUN
R2555

1
2K2R2J-2-GP
R2552 R2508
10KR2J-3-GP Q2515_1 10KR2J-3-GP U2001F 6 OF 10

1 2
Q2515 DEEPIDLE_W AKE_INT# Y3 AH45

2
MMBT3904-7-F-GP BMBUSY#/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
2 3 37 ECSCI# ECSCI# C38
81 DEEPIDLE_W AKE_INT_R# TACH1/GPIO1
78 BIO_DET# BIO_DET# D37 TACH2/GPIO6
D
CLKOUT_PCIE7N AF48 D

MISC
ECSW I# J32 AF47
37 ECSW I# TACH3/GPIO7 CLKOUT_PCIE7P
C2501 37 ECSMI# ECSMI# F10 GPIO8

1
SC47P50V2JN-3GP
K9 U2
DY LAN_PHY_PWR_CTRL/GPIO12 A20GATE KA20GATE 37

2
PCH_GPIO15 T7 GPIO15
80 DGPU_HOLD_RST# DGPU_HOLD_RST# AA2 AM3 BCLK_CPU_N 9 +1.05V_VTT
SATA4GP/GPIO16 CLKOUT_BCLK0_N/CLKOUT_PCIE8N

23,86,87 DGPU_PW RGD R2506 1 2 0R2J-2-GP DGPU_PW RGD_R F38 AM1 BCLK_CPU_P 9
TACH0/GPIO17 CLKOUT_BCLK0_P/CLKOUT_PCIE8P

2
54 LCD_CBL_DET# R3749 1 2 100R2J-2-GP LCD_CBL_DET_R# Y7 BG10 R2509
SCLOCK/GPIO22 PECI H_PECI 9

GPIO
56R2J-4-GP
H10 GPIO24 RCIN# T1 KBRCIN# 37

1
PCH_GPIO27 AB12 BE10 H_PW RGOOD 9,42
GPIO27 PROCPWRGD

CPU
PCH_GPIO28 V13 BD10 PCH_THERMTRIP_R 1 2 H_THRMTRIP# 9,37,42
GPIO28 THRMTRIP# R2511
STP_PCI# M11 56R2J-4-GP
STP_PCI#/GPIO34
Placed Within 2" from PCH
PCH_GPIO35 V6 SATACLKREQ#/GPIO35
2

37 DGPU_PW R_EN# DGPU_PW R_EN# AB7 BA22

SATA2GP/GPIO36 TP1
R2525 DGPU_PRSNT# AB13 AW22
10KR2J-3-GP SATA3GP/GPIO37 TP2
C PCH_GPIO38 V3 BB22 C
1

SLOAD/GPIO38 TP3

68 KB_DET# R2548 1 2 KB_DET_R# P3 AY45

100R2J-2-GP SDATAOUT0/GPIO39 TP4
PCIECLKRQ6# H3 AY46
+3.3V_ALW PCIECLKRQ6#/GPIO45 TP5

9,11 DDR_RST_GATE DDR_RST_GATE F1 AV43

10KR2J-3-GP PCIECLKRQ7#/GPIO46 TP6
2 1 R2530 PCH_GPIO28
40 FFS_INT2_R FFS_INT2_R AB6 AV45
10KR2J-3-GP SDATAOUT1/GPIO48 TP7
2 1 R2523 PCH_GPIO57
37 TURBO_BOOST_ALERT# TURBO_BOOST_ALERT#
AA4 AF13
1KR2J-1-GP SATA5GP/GPIO49 TP8
2 1 R2532 PCH_GPIO15
PCH_GPIO57 F8 M18
10KR2J-3-GP GPIO57 TP9
2 1 R2521 PCIECLKRQ6#
TP10 N18
10KR2J-3-GP 2 1 R2522 DDR_RST_GATE
A4 VSS_NCTF_1 TP11 AJ24
10KR2J-3-GP 2 1 R2531 ECSMI# A49

NCTF
VSS_NCTF_2

RSVD
Do Not Stuff TP2510 1 PCH_NCTF_1 A5 AK41
VSS_NCTF_3 TP12
A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
+3.3V_RUN B2 M32
VSS_NCTF_7 TP14
B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
10KR2J-3-GP 2 1 R2524 ECSW I# B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
10KR2J-3-GP 2 1 R2515 KB_DET_R# BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
B 10KR2J-3-GP B
2 1 R2517 STP_PCI# BF53 VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
10KR2J-3-GP 2 1 R2518 BIO_DET# BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
10KR2J-3-GP 2 1 R2519 PCH_GPIO38 BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
10KR2J-3-GP 2 1 R2529 DGPU_PW R_EN# BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
10KR2J-3-GP 2 1R2507 DGPU_PW RGD_R BJ49
Do Not Stuff TP2511 PCH_NCTF_2 VSS_NCTF_22
1 BJ5 VSS_NCTF_23 NC_3 AB42
10KR2J-3-GP 2 1 R2510 LCD_CBL_DET_R# BJ50
Do Not Stuff TP2512 PCH_NCTF_3 VSS_NCTF_24
1 BJ52 VSS_NCTF_25 NC_4 AB41
10KR2J-3-GP 2 1 R2512 ECSCI# BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
10KR2J-3-GP 2 1 R2526 PCH_GPIO27 D2
DY D53
VSS_NCTF_28
10KR2J-3-GP VSS_NCTF_29
2 1R2520 FFS_INT2_R E1 P6 INIT3_3V# 1 TP2506Do Not Stuff
DY Do Not Stuff TP2509 1 PCH_NCTF_4 E53
VSS_NCTF_30 INIT3_3V#
VSS_NCTF_31
TP24 C10

IBEXPEAK-M-GP-NF
+3.3V_RUN +3.3V_RUN
1

R2527 R2516
DIS10KR2J-3-GP DY 10KR2J-3-GP

A UMA A
2

DGPU_PRSNT# DGPU_HOLD_RST#
1

R2528 R2533 Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY 10KR2J-3-GP 10KR2J-3-GP
Taipei Hsien 221, Taiwan, R.O.C.
2

Title

PCH (GPIO/CPU)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 25 of 90
5 4 3 2 1
 5 4 3 2 1

+1.05V_PCH +3.3V_CRT_LDO
69mA
U2001G POWER 7 OF 10 L2603 R2602
1.432A AB24 VCCCORE VCCADAC AE50 +VCCA_DAC_1_2 1 2 1 2 +3.3V_RUN

C2601
SC10U10V5ZY-1GP

C2602
SC1U10V2KX-1GP

C2604
SCD01U16V2KX-3GP

C2605
SCD1U10V2KX-5GP

C2603
SC10U6D3V5MX-3GP
AB26 BLM18PG181SN1D-GP
VCCCORE

1
AB28 AE52 0R2J-2-GP
VCCCORE VCCADAC
AD26 VCCCORE

CRT
D AD28 1.432A AF53 D

2
VCCCORE VSSA_DAC
AF26 VCCCORE

VCC CORE
AF28 VCCCORE VSSA_DAC AF51
AF30 VCCCORE
AF31 VCCCORE
AH26 VCCCORE
AH28 +3VS_VCCA_LVD +3.3V_RUN
VCCCORE
AH30
AH31
AJ30
VCCCORE
VCCCORE <1mA VCCALVDS AH38 2
R2609
1 <1mA
0R3J-0-U-GP
VCCCORE
AJ31 AH39 1 2C2623
VCCCORE VSSA_LVDS DY SCD1U10V2KX-5GP +1.8V_RUN

+1.05V_PCH
VCCTX_LVDS AP43 +1.8VS_VCCTX_LVDS 1 2 59mA

C2625
SCD01U16V2KX-3GP

C2624
SCD01U16V2KX-3GP

C2626
SC10U6D3V5MX-3GP
AP45 L2604 IND-D1UH-17-GP
VCCTX_LVDS

1
59mA VCCTX_LVDS AT46

LVDS
AK24 AT45
+1.05V_PCH VCCIO VCCTX_LVDS DY

2
40mA 1
DY 2 L2601 +1.05VS_VCCAPLL_EXP BJ24 VCCAPLLEXP
+3.3V_CRT_LDO +5V_RUN

C2606
SC10U6D3V5MX-3GP
IND-1UH-2-GP AB34
VCC3_3

1
U2601
+3.3V_RUN
DY AN20 VCCIO 357mA VCC3_3 AB35
AN22 5 1
357mA

HVCMOS
2
VCCIO OUT IN
AN23 VCCIO VCC3_3 AD35
AN24 2 C2629
VCCIO DY GND

1
AN26 C2607 C2628
VCCIO

SC1U10V3KX-3GP
+1.05V_PCH AN28 3.062A SCD1U10V2KX-5GP SC10U6D3V5MX-3GP 4 3
BJ26
VCCIO DY NC#4 SHDN# DY
3.062A

2
C VCCIO C
BJ28 VCCIO
C2608
SC10U6D3V5MX-3GP

C2609
SC1U10V3KX-3GP

C2610
SC1U10V3KX-3GP

C2611
SC1U10V3KX-3GP

C2612
SC1U10V3KX-3GP
AT26 MAX8511EXK33-T-GP
VCCIO
1

1
AT28 +VCC_VRM
VCCIO
AU26 VCCIO
AU28 2009/07/29
2

2
VCCIO Change power rail to +1.05V_VTT for CFD.
AV26
AV28
AW26
VCCIO
VCCIO VCCVRM AT24 35mA +1.05VS_VCC_DMI R2601 +1.05V_VTT
VCCIO 0R2J-2-GP
AW28 VCCIO
58mA

DMI
BA26 VCCIO VCCDMI AT16 1 2
BA28 VCCIO

1
BB26 AU16 C2613
VCCIO VCCDMI SC1U10V3KX-3GP
BB28 VCCIO
BC26

2
VCCIO

PCI E*
BC28 VCCIO
BD26 VCCIO
+3.3V_RUN BD28 VCCIO +3.3V_RUN 2009/07/31
BE26 AM16
BE28
VCCIO
VCCIO
VCCPNAND
VCCPNAND AK16 156mA Changed +V_NVRAM_VCCQ_PCH power rail from 1.8V to 3.3V,
Removed Braidwood Changed power rail.
C2614
SCD1U10V2KX-4GP

BG26 VCCIO VCCPNAND AK20

1

BG28 VCCIO 156mA VCCPNAND AK19

1
BH27 AK15 C2615
VCCIO VCCPNAND SCD1U10V2KX-5GP
AK13
2

VCCPNAND
AN30 AM12

2
VCCIO VCCPNAND

NAND / SPI
AN31 VCCIO VCCPNAND AM13
VCCPNAND AM15
+1.8V_RUN

R2606
357mA AN35 VCC3_3 +3.3V_RUN
B 0R2J-2-GP +VCC_VRM B

1
+1.05V_PCH L2602 +1.05VS_VCCAPLL_FDI 2 1 +VCC_VRM AT22
IND-1UH-2-GP VCCVRM[1] R2605
1 2 BJ18 AM8
DY VCCFDIPLL VCCME3_3
AM9 85mA 0R2J-2-GP
VCCME3_3
1

FDI

C2616 +1.05V_PCH AM23 85mA AP11

2
SC10U6D3V5MX-3GP VCCIO VCCME3_3 PCH_VCCME3_3
AP9
DY VCCME3_3
2

1
C2622
SCD1U10V2KX-5GP
IBEXPEAK-M-GP-NF

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (POWER1)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 26 of 90
5 4 3 2 1
 5 4 3 2 1

+1.05V_PCH +1.05VS_VCCA_CLK
L2701
52mA 1
DY 2
POWER

C2701
SC10U6D3V5MX-3GP

C2702
SC1U10V2KX-1GP
U2001J 10 OF 10 +1.05V_PCH

1
IND-10UH-30-GP
AP51 V24
DY DY VCCACLK
52mA
VCCIO
V26

2
VCCIO

1
AP53 Y24 C2706
VCCACLK VCCIO SC1U10V2KX-1GP
VCCIO Y26

2
AF23 VCCLAN VCCSUS3_3 V28
R2708 +3.3V_ALW
320mA VCCSUS3_3 U28
1 2 PCH_VCC_LAN AF24 VCCLAN VCCSUS3_3 U26
D 0R2J-2-GP U24 D
VCCSUS3_3
VCCSUS3_3 P28

1
DCPSUSBYP Y20 P26
DCPSUSBYP VCCSUS3_3 C2703
VCCSUS3_3 N28

1
C2707 N26 SCD1U10V2KX-4GP

2
SCD1U10V2KX-4GP VCCSUS3_3
AD38 VCCME VCCSUS3_3 M28
+1.05V_PCH M26

2
VCCSUS3_3
AD39 L28

USB
VCCME VCCSUS3_3
L26
1.849A AD41 VCCME
VCCSUS3_3
VCCSUS3_3 J28

C2705
SC10U6D3V5MX-3GP

C2708
SC1U10V2KX-1GP
VCCSUS3_3 J26

1
AF43 VCCME VCCSUS3_3 H28
163mA VCCSUS3_3 H26
AF41 1.849A G28

2
VCCME VCCSUS3_3
VCCSUS3_3 G26
AF42 F28 +3.3V_ALW
VCCME VCCSUS3_3
VCCSUS3_3 F26
V39 E28 +3.3V_ALW
VCCME VCCSUS3_3
E26

Clock and Miscellaneous

VCCSUS3_3

2
V41 VCCME VCCSUS3_3 C28

C2704
SC10U6D3V5MX-3GP

C2710
SC1U10V2KX-1GP
C26 D2701
VCCSUS3_3

1
V42 B27 CH751H-40PT +5V_ALW
VCCME VCCSUS3_3 C2709
VCCSUS3_3 A28
Y39 A26 SCD1U10V2KX-4GP
DY

1
VCCME VCCSUS3_3 +3.3V_RUN
+1.05V_PCH Y41 U23 +1.05V_PCH 1 2
VCCME VCCSUS3_3
1 2 +1.05VS_VCCA_A_DPL Y42 VCCME VCCIO V23 R2701

2
C2734
SC10U6D3V5MX-3GP

C2711
SC1U10V2KX-1GP

L2702 100R2J-2-GP
1

1
C IND-10UH-81-GP +5VALW _PCH_VCC5REFSUS C2712 D2702 +5V_RUN C
<1mA V5REF_SUS F24
SC1U10V2KX-1GP
DY +VCCRTCEXT V9
CH751H-40PT
2

2
DCPRTC

1
1
C2713 +VCC_VRM
SCD1U10V2KX-4GP <1mA K49 +5VS_PCH_VCC5REF 1 2
V5REF
AU24
2

VCCVRM

PCI/GPIO/LPC
1 2 +1.05VS_VCCA_B_DPL R2702

1
+3.3V_RUN
C2735

C2714
SC1U10V2KX-1GP

L2703 J38 100R2J-2-GP

VCC3_3
1

1
SC10U6D3V5MX-3GP

IND-10UH-81-GP BB51 C2715

68mA +1.05VS_VCCA_A_DPL BB53
VCCADPLLA
68mA L38 SC1U10V2KX-1GP

2
VCCADPLLA VCC3_3
DY
2

1
M36
69mA +1.05VS_VCCA_B_DPL BD51 VCCADPLLB
VCC3_3 C2716
SCD1U10V2KX-4GP
+3.3V_RUN
BD53 69mA N36

2
VCCADPLLB VCC3_3
+1.05V_PCH AH23 P36
VCCIO VCC3_3

1
AJ35 VCCIO
AH35 U35 C2717
VCCIO VCC3_3
SCD1U10V2KX-4GP

2
1

C2718 C2719 C2720 AF34

SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP VCCIO
VCC3_3 AD13
AH34
2

VCCIO +1.05VS_VCCAPLL +1.05V_PCH

L2704
AF32

+VCCSST V12
VCCIO
VCCSATAPLL AK3
AK1
1
DY 2 32mA
DCPSST VCCSATAPLL

1
C2721 C2722 IND-10UH-30-GP
SC1U10V2KX-1GP
DY DYSC1U10V2KX-1GP
1

B +1.05V_PCH B

2
C2723 +1.05VALW _INT_VCCSUS Y22
SCD1U10V2KX-4GP DCPSUS
AH22
2

VCCIO
1

C2724

1
SCD1U10V2KX-4GP +VCC_VRM C2725
P18 196mA AT20 SC1U10V2KX-1GP
2

VCCSUS3_3 VCCVRM

2
+3.3V_ALW U19
SATA

VCCSUS3_3
PCI/GPIO/LPC

AH19
163mA U20 VCCSUS3_3
VCCIO
AD20
VCCIO
1

U22 VCCSUS3_3
C2726 AF22
SCD1U10V2KX-4GP +3.3V_RUN VCCIO
2

VCCIO AD19
V15 VCC3_3 VCCIO AF20
VCCIO AF19
1

V16 VCC3_3 VCCIO AH20

C2727
SCD1U10V2KX-4GP Y16 AB19
2

VCC3_3 VCCIO
VCCIO AB20
+1.05V_VTT AB22
VCCIO +1.05V_PCH
AD22
<1mA AT18 V_CPU_IO
VCCIO
C2728
SC4D7U6D3V5KX-3GP

C2729
SCD1U10V2KX-4GP

C2730
SCD1U10V2KX-4GP

AA34
CPU

VCCME
1

<1mA VCCME Y34

AU18 V_CPU_IO VCCME Y35
AA35
2

VCCME +3VS_+1.5VS_HDA_IO
A UMA A

+RTC_CELL 6mA
RTC

A12 VCCRTC 2mA 6mA VCCSUSHDA L30 1 2 +3.3V_ALW

HDA

R2707 0R2J-2-GP
2mA Wistron Corporation
1
C2732
SCD1U10V2KX-4GP

C2733

SCD1U10V2KX-4GP

IBEXPEAK-M-GP-NF C2731 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1

SC1U10V2KX-1GP Taipei Hsien 221, Taiwan, R.O.C.

2

Title
2

PCH (POWER2)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 27 of 90
5 4 3 2 1
 5 4 3 2 1

U2001I 9 OF 10
AY7 VSS VSS H49
B11 VSS VSS H5
B15 VSS VSS J24
B19 VSS VSS K11
B23 VSS VSS K43
B31 VSS VSS K47
B35 VSS VSS K7
B39 VSS VSS L14
B43 VSS VSS L18
B47 VSS VSS L2
D B7 VSS VSS L22 D
U2001H 8 OF 10 BG12 L32
VSS VSS
AB16 VSS BB12 VSS VSS L36
BB16 VSS VSS L40
AA19 VSS VSS AK30 BB20 VSS VSS L52
AA20 VSS VSS AK31 BB24 VSS VSS M12
AA22 VSS VSS AK32 BB30 VSS VSS M16
AM19 VSS VSS AK34 BB34 VSS VSS M20
AA24 VSS VSS AK35 BB38 VSS VSS N38
AA26 VSS VSS AK38 BB42 VSS VSS M34
AA28 VSS VSS AK43 BB49 VSS VSS M38
AA30 VSS VSS AK46 BB5 VSS VSS M42
AA31 VSS VSS AK49 BC10 VSS VSS M46
AA32 VSS VSS AK5 BC14 VSS VSS M49
AB11 VSS VSS AK8 BC18 VSS VSS M5
AB15 VSS VSS AL2 BC2 VSS VSS M8
AB23 VSS VSS AL52 BC22 VSS VSS N24
AB30 VSS VSS AM11 BC32 VSS VSS P11
AB31 VSS VSS BB44 BC36 VSS VSS AD15
AB32 VSS VSS AD24 BC40 VSS VSS P22
AB39 VSS VSS AM20 BC44 VSS VSS P30
AB43 VSS VSS AM22 BC52 VSS VSS P32
AB47 VSS VSS AM24 BH9 VSS VSS P34
AB5 VSS VSS AM26 BD48 VSS VSS P42
AB8 VSS VSS AM28 BD49 VSS VSS P45
AC2 VSS VSS BA42 BD5 VSS VSS P47
AC52 VSS VSS AM30 BE12 VSS VSS R2
AD11 VSS VSS AM31 BE16 VSS VSS R52
AD12 VSS VSS AM32 BE20 VSS VSS T12
C AD16 AM34 BE24 T41 C
VSS VSS VSS VSS
AD23 VSS VSS AM35 BE30 VSS VSS T46
AD30 VSS VSS AM38 BE34 VSS VSS T49
AD31 VSS VSS AM39 BE38 VSS VSS T5
AD32 VSS VSS AM42 BE42 VSS VSS T8
AD34 VSS VSS AU20 BE46 VSS VSS U30
AU22 VSS VSS AM46 BE48 VSS VSS U31
AD42 VSS VSS AV22 BE50 VSS VSS U32
AD46 VSS VSS AM49 BE6 VSS VSS U34
AD49 VSS VSS AM7 BE8 VSS VSS P38
AD7 VSS VSS AA50 BF3 VSS VSS V11
AE2 VSS VSS BB10 BF49 VSS VSS P16
AE4 VSS VSS AN32 BF51 VSS VSS V19
AF12 VSS VSS AN50 BG18 VSS VSS V20
Y13 VSS VSS AN52 BG24 VSS VSS V22
AH49 VSS VSS AP12 BG4 VSS VSS V30
AU4 VSS VSS AP42 BG50 VSS VSS V31
AF35 VSS VSS AP46 BH11 VSS VSS V32
AP13 VSS VSS AP49 BH15 VSS VSS V34
AN34 VSS VSS AP5 BH19 VSS VSS V35
AF45 VSS VSS AP8 BH23 VSS VSS V38
AF46 VSS VSS AR2 BH31 VSS VSS V43
AF49 VSS VSS AR52 BH35 VSS VSS V45
AF5 VSS VSS AT11 BH39 VSS VSS V46
AF8 VSS VSS BA12 BH43 VSS VSS V47
AG2 VSS VSS AH48 BH47 VSS VSS V49
AG52 VSS VSS AT32 BH7 VSS VSS V5
AH11 VSS VSS AT36 C12 VSS VSS V7
AH15 VSS VSS AT41 C50 VSS VSS V8
B B
AH16 VSS VSS AT47 D51 VSS VSS W2
AH24 VSS VSS AT7 E12 VSS VSS W52
AH32 VSS VSS AV12 E16 VSS VSS Y11
AV18 VSS VSS AV16 E20 VSS VSS Y12
AH43 VSS VSS AV20 E24 VSS VSS Y15
AH47 VSS VSS AV24 E30 VSS VSS Y19
AH7 VSS VSS AV30 E34 VSS VSS Y23
AJ19 VSS VSS AV34 E38 VSS VSS Y28
AJ2 VSS VSS AV38 E42 VSS VSS Y30
AJ20 VSS VSS AV42 E46 VSS VSS Y31
AJ22 VSS VSS AV46 E48 VSS VSS Y32
AJ23 VSS VSS AV49 E6 VSS VSS Y38
AJ26 VSS VSS AV5 E8 VSS VSS Y43
AJ28 VSS VSS AV8 F49 VSS VSS Y46
AJ32 VSS VSS AW14 F5 VSS VSS P49
AJ34 VSS VSS AW18 G10 VSS VSS Y5
AT5 VSS VSS AW2 G14 VSS VSS Y6
AJ4 VSS VSS BF9 G18 VSS VSS Y8
AK12 VSS VSS AW32 G2 VSS VSS P24
AM41 VSS VSS AW36 G22 VSS VSS T43
AN19 VSS VSS AW40 G32 VSS VSS AD51
AK26 VSS VSS AW52 G36 VSS VSS AT8
AK22 VSS VSS AY11 G40 VSS VSS AD47
AK23 VSS VSS AY43 G44 VSS VSS Y47
AK28 VSS VSS AY47 G52 VSS VSS AT12
AF39 VSS VSS AM6
IBEXPEAK-M-GP-NF H16 AT13
VSS VSS
H20 VSS VSS AM5
A H30 VSS VSS AK45 UMA A
H34 VSS VSS AK39
H38 VSS VSS AV14
H42 VSS Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

IBEXPEAK-M-GP-NF Title

PCH (VSS)
Size Document Number Rev
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 28 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 29 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO
+3.3V_RUN
+AVDD
+5V_RUN

2
+3.3V_RUN

0R2J-2-GP
R3002
L3002
Close to codec 1 2
Close to codec

SC1U10V3KX-3GP
SCD1U10V2KX-4GP
AUD_DVDDCORE 0R5J-5-GP +5V_RUN

1
+PVDD

SCD1U10V2KX-4GP

1
C3015

C3016
C3003 L3001

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP
2

1
C3005

C3004
SC10U6D3V5MX-3GP 1 2

C3017

2
U3001 0R5J-5-GP

SC1U10V3KX-3GP

SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
1

1
C3014

C3001

C3011
1 27 L3003
DVDD_CORE AVDD
D 38 1 2 D
AVDD
9

2
PCH_AZ_CODEC_BITCLK DVDD 0R5J-5-GP
39
PVDD
3 45
DVDD_IO PVDD
13 AUD_SENSE_A
1

PCH_AZ_CODEC_BITCLK SENSE_A AUD_SENSE_B

6 14
C3009 24 PCH_AZ_CODEC_BITCLK HDA_BITCLK SENSE_B C3008
DY SC4D7P50V2CN-1GP R3003 1 2 33R2J-2-GP PCH_SDIN_CODEC_C0 8 AUD_EXT_MIC_L_C 1 2SC1U10V3KX-3GP AUD_EXT_MIC_L
2

24 PCH_SDIN_CODEC HDA_SDI AUD_EXT_MIC_L 77

28 C3019
PCH_SDOUT_CODEC HP0_PORT_A_L AUD_EXT_MIC_R_C 1
5 29 2SC1U10V3KX-3GP AUD_EXT_MIC_R AUD_EXT_MIC_R 77
24 PCH_SDOUT_CODEC HDA_SDO HP0_PORT_A_R AUD_VREFOUT_B
23 AUD_VREFOUT_B 77
PCH_AZ_CODEC_SYNC VREFOUT_A_OR_F
10
24 PCH_AZ_CODEC_SYNC HDA_SYNC AUD_HP1_JACK_L_C R3017 AUD_HP1_JACK_L
31 1 2 60D4R2F-GP
PCH_AZ_CODEC_RST# HP1_PORT_B_L AUD_HP1_JACK_R_C R3019 AUD_HP1_JACK_R AUD_HP1_JACK_L 77
11 32 1 2 60D4R2F-GP
+3.3V_RUN 24 PCH_AZ_CODEC_RST# HDA_RST# HP1_PORT_B_R AUD_HP1_JACK_R 77

PORT_C_L
19
20
check~
PORT_C_R
24 with vwndor, PC BEEP circuit
1

AUD_DMIC_CLK VREFOUT_C
2
R3004 AUD_DMIC_IN0 DMIC_CLK/GPIO1 AUD_SPK_L+
73 AUD_DMIC_IN0
4
DMIC0/GPIO2 SPKR_PORT_D_L+
40
AUD_SPK_L+ 60 From SB
10KR2J-3-GP 41 AUD_SPK_L- C3006 R3010
SPKR_PORT_D_L- AUD_SPK_L- 60 SB_SPKR_R
46 2 1 SCD1U10V2KX-4GP 1 2 SB_SPKR 24
DMIC1/GPIO0/SPDIF_OUT_1 AUD_SPK_R- 499KR2F-1-GP
43
2

SPKR_PORT_D_R- AUD_SPK_R+ AUD_SPK_R- 60 KBC_BEEP_R

48 44 2 1 SCD1U10V2KX-4GP 1 2 KBC_BEEP 37
AMP_MUTE# SPDIF_OUT_0 SPKR_PORT_D_R+ AUD_SPK_R+ 60 R3015
AMP_MUTE# 47 15 C3007 499KR2F-1-GP From EC
37 AMP_MUTE# EAPD PORT_E_L
16
PORT_E_R
PUMP_CAPN 17
PORT_F_L AUD_PC_BEEP
35 18

1
CAP- PORT_F_R
C3002 12
SC2D2U25V5KX-1GP 2 36
PC_BEEP AUD_PC_BEEP
CAP+
PUMP_CAPP
MONO_OUT
25 Trace width>15 mils
7
DVSS
+3.3V_RUN 33 22 AUD_CAP2
U3002 AVSS CAP2
30
AVSS AUD_VREFFLT
5 1 26 21
VCC OE# AVSS VREFFILT
C
AUD_DMIC_CLK_Y 4
DY A
2
3 42 34 AUD_V_B
C

Y GND PVSS V-
74LVC1G125DC-GP 49 37 AUD_VREG
1

GND VREG

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP
0R2J-2-GP

C3010

C3013
92HD81B1A5NLGXUAX8-GP
DY R3007

1
C3018

C3012
2

R3014

2
1 2 33R2J-2-GP AUD_DMIC_CLK
73 AUD_DMIC_CLK_G
1

EC3001
SC22P50V2JN-4GP DY
2

Close to codec

+AVDD
Azalia I/F EMI
Place this block
1

PCH_SDOUT_CODEC
R3018 close to Audio Codec Pin13
2K49R2F-GP
1

R3006
2

47R2J-2-GP AUD_SENSE_A
DY +AVDD
1
2

C3026

1
PCH_AZ_CODEC_SDOUT1

SC1KP50V2KX-1GP
2

R3008
2K49R2F-GP
1

2
R3022 R3021 AUD_SENSE_B
20KR2F-L-GP 39K2R2F-L-GP

B
Close to Pin14 B
2

EXT_MIC_JD# 77
1

C3020
DY SCD1U10V2KX-4GP
2

AUD_HP1_JD# 77

A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
AUDIO CODEC 92HD81
Document Number Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 30 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 31 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserve
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 32 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 33 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 34 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
(Reserve)
Document Number Rev
A3 SA
Vostro Calpella
Date: Tuesday, September 08, 2009 Sheet 35 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
TPM
Size Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 36 of 90
5 4 3 2 1
 5 +3.3V_RUN_GPU 4 3 2 1
+3.3V_RTC_LDO +3.3V_RTC_LDO Added 10mW circuit SSID = KBC

1
+3.3V_RUN_GPU KBC_PWR
R3748 Check~ +3.3V_RTC_LDO
2009/06/04

1
2K2R2J-2-GP

2
R3745 R3733 +3.3V_RTC_LDO +3.3V_RUN
DY DY

1
R3723 R3753 100KR2J-1-GP 100KR2J-1-GP

1 2
10KR2J-3-GP Q3714_1 10KR2J-3-GP R3744
+3.3V_RTC_LDO D3704
DY 100KR2J-1-GP U3703

2
EC_PWR_SHDN 1

S
1

1
2 3 THERMTRIP_VGA_R# 4 3 KBC_SDA1
23 SML1DAT

2
81 THERMTRIP_VGA# Q3714 KBC_ON#
78 KBC_PWRBTN# D3705 DY 3 G
2

MMBT3904-7-F-GP Q3704 5 2
R3747 K A KBC_PWRBTN_EC# 2 SI2301BDS-T1-GP DY
0R5J-5-GP 2009/07/28
Change 2N7002 ESD pretect from standard to 1KV type
DY KBC_SCL1 6 1 SML1CLK 23
BAT54ALT1G-GP

D
D P/N:84.2N702.E31 BAS16XV2T1G-GP-U KBC_PWR DMN66D0LDW-7-GP
D
1

2009/0806
2009/07/28
Changed Q3714 from N-MOS to BJT Gate,For cost down.
KBC_PWR Change 2N7002 ESD pretect from standard to 1KV type
1 2
KBC_PWR

+3.3V_RUN R3746 0R2J-2-GP P/N:84.2N702.E31

KBC_PWR Put 0.1uf close to VCC-GND pin pair.
+3.3V_RUN
L3701 1 2 BLM18AG601SN-3GP VBAT

1
C3714
C3703 SC4D7U6D3V3KX-GP
DY D3712 U3702
C3702
SC2D2U10V3KX-1GP

C3712
SCD1U10V2KX-4GP

C3711
SCD1U10V2KX-4GP

C3713
SCD1U10V2KX-4GP

C3708
SCD1U10V2KX-4GP

C3701
SCD1U10V2KX-4GP

C3706
SC2D2U10V3KX-1GP

C3715
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

2
1

1
2 PANEL_BKEN_GPU 81 4 3 KBC_SDA1
39,78 THERM_SDA
DY PANEL_BKEN 3 5 2
2

115

102
KBC_SCL1

88
76
46
19

80
1 PANEL_BKEN_PCH 20 6 1 THERM_SCL 39,78

4
U3701A 1 OF 2
BAT_IN# 44
DMN66D0LDW-7-GP

VCC
VCC
VCC
VCC
VCC

AVCC

VDD

GPIO41
BAT54C-7-F-GP
AGND
KBC_PWR
104 124 CAP_LOCK_LED# CAP_LOCK_LED# 66 RN3702
VREF GPIO10/LPCPD# PLT_RST1#_1 KBC_SCL1
LRESET# 7 4 1
AD_IA_KBC +1.05V_VTT KBC_SDA1
45 AD_IA_KBC
1.8_GFX_ON
97
98
GPI90/AD0 A/D LCLK 2
3
PCLK_KBC 21 3 2
51,87 1.8_GFX_ON GPI91/AD1 LFRAME# LPC_LFRAME# 24,70,76
THERMTRIP_VGA_R# 99 126 LPC_LAD0 SRN4K7J-8-GP EC3701
GPI92/AD2 LAD0

1
PS_ID_EC 100 127 LPC_LAD1 LPC_LAD[0..3] 24,70,76 RN3701 SCD1U16V2KX-3GP
43 PS_ID_EC GPI93/AD3 LAD1
TURBO_BOOST_ALERT# 108 128 LPC_LAD2 R3737 BAT_SDA 4 1
25 TURBO_BOOST_ALERT#
KBC_THERMTRIP# GPIO05 LAD2 LPC_LAD3 2K2R2J-2-GP BAT_SCL DY
96 LPC 1 3 2

2
GPIO04 LAD3
SERIRQ 125 INT_SERIRQ 24,76
8 PM_CLKRUN# 22 C3716 SRN4K7J-8-GP

2
GPIO11/CLKRUN# THERMTRIP_GATE 2
KBRST# 122 KBRCIN# 25 1
22 SUS_PWR_DN_ACK SUS_PWR_DN_ACK 101 121 KA20GATE 25 KBC_PWRBTN# R3734 1 2 100KR2J-1-GP

B
R3712 1 GPI94 GA20 SCD1U16V2KX-3GP R3709
68 KB_BL_DET# 2KB_BL_DET_R# 105 GPI95 ECSCI#/GPIO54 29 ECSCI#_KBC
100R2J-2-GP DGPU_PWR_EN# PANEL_BKEN KBC_THERMTRIP# 2 100KR2J-1-GP
C KBC_PWR 25 DGPU_PWR_EN#
CAPA2_INT_R#
106
107
GPI96 D/A GPIO65/SMI# 9
123 ECSWI#_KBC E C KBC_THERMTRIP#
1
C
GPI97 GPIO67/PWUREQ# 9,25,42 H_THRMTRIP# CAPA_RST#_R R3739 1
Pull High : Discrete 2 100KR2J-1-GP
internal Pull Low for UMA Q3701
1

CH3904PT-GP
R3716 64 68 KBC_SDA1
DIS 2K2R2J-2-GP 22,42,50,51,52,77,86 PM_SLP_S3#
KBC_PWRBTN_EC# GPIO01/TB2 GPIO74/SDA2 KBC_SCL1 D3702
R3751 1 2AC_IN_R#
95
93
GPIO03 SMB GPIO73/SCL2 67
69 BAS16XV2T1G-GP-U +3.3V_RUN
45 AC_IN# GPIO06 GPIO22/SDA1 BAT_SDA 44,45
69 LID_CLOSE# 100R2J-2-GP LID_CLOSE# 94 70 25 ECSWI# A K ECSWI#_KBC
BAT_SCL 44,45
2

PCB_VER0 GPIO07 GPIO17/SCL1 R3754

119
SW_UMA_ID GPIO23 D3703 TURBO_BOOST_ALERT#
6 1 2 10KR2J-3-GP
1D5V_VGA_ON GPIO24 BAS16XV2T1G-GP-U
87 1D5V_VGA_ON 109
GPIO30 R3725 1
PCB_VER1 120 SP 81 BATT_WHITE_LED A K ECSCI#_KBC E51_RxD 2 10KR2J-3-GP
GPIO31 GPIO66/G_PWM BATT_WHITE_LED 66 25 ECSCI# DY
1

R3729 PWRLED# 65
66 PWRLED# GPIO32/D_PWM
2K2R2J-2-GP PWR_BTN_LED# D3701 ECSCI#_KBC R3752 1 2 10KR2J-3-GP
66 PWR_BTN_LED#
KB_BL_CTRL
66
16
GPIO33/H_PWM BAS16XV2T1G-GP-U DY
DY 68 KB_BL_CTRL
43 AD_OFF AD_OFF 17
GPIO40/F_PWM
84 ECSMI#_KBC 25 ECSMI# A K ECSMI#_KBC KB_BL_DET# R3750 1 2 10KR2J-3-GP
RSMRST#_KBC GPIO42/TCK GPIO77
22 RSMRST#_KBC 20 SPI 83 BLUETOOTH_EN 77
2

PM_SLP_S4# GPIO43/TMS GPIO76/SHBM D3706 KA20GATE R3743 1

22,50,77 PM_SLP_S4# 21 GPIO 82 WIFI_RF_EN 64 2 10KR2J-3-GP
NUM_LOCK_LED# GPIO44/TDI GPIO75 BAS16XV2T1G-GP-U
66 NUM_LOCK_LED# 22 91 WIRELESS_ON#/OFF 77
3V_5V_POK GPIO45/E_PWM GPIO81
46 3V_5V_POK 23 78 CAPA_RST# A K CAPA_RST#_R KBRCIN# R3742 1 2 10KR2J-3-GP
R3706 1 GPIO46/TRST# R3740
22 PM_PWROK 2PM_PWROK_R 24
0R2J-2-GP EC_SPI_WP#_R GPIO47 WIRELESS_ON#/OFF 1
Remove 62 EC_SPI_WP#_R 25 2 100KR2J-1-GP
EC_PWR_SHDN GPIO50/TDO E51_TxD
HDD_FALL_INT1 26 111 E51_TxD 64
GPIO51 GPO83/SOUT_CR/BADDR1 R3728 1
54 BLON_OUT BLON_OUT 27 113 E51_RxD E51_RxD 64 S5_ENABLE 2 10KR2J-3-GP
R3719 1 GPIO52/RDY# GPIO87/SIN_CR
47 IMVP_VR_ON 2IMVP_VR_ON_R 28 112 AC_PRESENT_EC 22
0R2J-2-GP GPIO53 GPO84/BADDR0 R3714 1
PSID_DISABLE# KCOL0 2 10KR2J-3-GP
43
86
PSID_DISABLE#
GFX_CORE_EN GFX_CORE_EN
73
74
GPIO70
114 PM_LAN_ENABLE 76 R3717 DY
ME_UNLOCK# GPIO71 GPIO16 VTT_PWRGD_G34
75 14 1 2 R3731 SHBM_LCDTST_EN 1 2 10KR2J-3-GP
24
63,76
ME_UNLOCK#
USB_PWR_EN# USB_PWR_EN# 110
GPIO72 GPIO34
15 S5_ENABLE 42 0R2J-2-GP
VTT_PWRGD 9,49,50 DY
GPO82/TRIS# GPIO36 BLUETOOTH_EN R3721
SER/IR 1 2 10KR2J-3-GP
R3741
10R2J-2-GP PANEL_BKEN R3722 1 2 10KR2J-3-GP
44 KBC_VCORF
VCORF U3701B 2 OF 2
22 PCH_SUSCLK_KBC 1 2

B KCOL[0..16] 68
B

1
AGND

+3.3V_RUN
GND
GND
GND
GND
GND
GND

C3710 KBC_XI 77 53 KCOL0

SC1U10V3KX-3GP 32KX1/32KCLKIN KBSOUT0/JENK# KCOL1
52

2
NPCE781BA0DX-GP R3710 KBSOUT1/TCK KCOL2
51
116
89
78
45
18
5

2AGND103

PLACE NEAR PIN 0R2J-2-GP KBSOUT2/TMS KCOL3

50
KBSOUT3/TDI
1

10KR2J-3-GP

CAPA_RST#_R 2 1 KBC_XO 79 49 KCOL4

32KX2 KBSOUT4/JEN0#
R3732

30 AMP_MUTE# AMP_MUTE# 30 48 KCOL5

R3701 GPIO55/CLKOUT KBSOUT5/TDO KCOL6
47
10KR2J-3-GP DY DY MB VERSION 47 IMVP_VR_PWRGD 63
KBSOUT6/RDY#
43 KCOL7
R3730 GPIO14/TB1 KBSOUT7 KCOL8
22 PM_PWRBTN# 117 KBC 42
2

GPIO20/TA2 KBSOUT8
ID VER1 VER0 0R2J-2-GP 54 SHBM_LCDTST_EN SHBM_LCDTST_EN 31
GPIO56/TA1 KBSOUT9
41 KCOL9
PCB_VER0 30 KBC_BEEP 32 40 KCOL10
PCB_VER1 GPIO15/A_PWM KBSOUT10 KCOL11
66 BATT_ORANGE_LED 118 39
SA 0 0
1

GPIO21/B_PWM KBSOUT11 KCOL12

54 LBKLT_CTL_EC 62 38
GPIO13/C_PWM KBSOUT12/GPIO64 KCOL13
37
SB 0 1 KBSOUT13/GPIO63
1

36 KCOL14
KBSOUT14/GPIO62
10KR2J-3-GP

35 KCOL15
SC 1 0 KBSOUT15/GPIO61/XOR_OUT
R3711

R3708 87 3.3V_RUN_GPU_EN 3.3V_RUN_GPU_EN 13 34 KCOL16

10KR2J-3-GP 1.05V_GFX_ON GPIO12/PSDAT3 GPIO60/KBSOUT16 TP_KCOL17 TP3701
87 1.05V_GFX_ON 12 33 1
-1 1 1 66 SCR_LOCK_LED# SCR_LOCK_LED# 11
GPIO25/PSCLK3 GPIO57/KBSOUT17
KROW[0..7] 68
2

R3707 2 GPIO27/PSDAT2
54 LCD_TST 10R2J-2-GP LCD_TST_R 10
R3720 TPDATA GPIO26/PSCLK2 KROW0
68 TPDATA 71 54
PLT_RST1#_1 TPCLK GPIO35/PSDAT1 KBSIN0 KROW1
2 1
0R2J-2-GP PLT_RST# 9,21,64,70,76,77,80 68 TPCLK 72
GPIO37/PSCLK1 PS/2 KBSIN1
55
56 KROW2
KBSIN2 KROW3
57
KBSIN3
1

58 KROW4
C3717 EC_SPI_DI KBSIN4 KROW5
86 59
DY SC470P50V2KX-3GP
62 EC_SPI_DI
SPI_DIO R3755 1 2 0R2J-2-GP EC_SPI_DO 87
F_SDI KBSIN5
60 KROW6
KBC CLK 62 SPI_DIO
2

EC_SPI_CS# F_SDO KBSIN6 KROW7

62 EC_SPI_CS#
EC_SPI_CLK R3735 1 2 0R2J-2-GP EC_SPI_CLK_C
90
92
F_CS0# FIU KBSIN7
61
62 EC_SPI_CLK F_SCK
EMI PCLK_KBC
2

85 ECRST#
VCC_POR#
R3726
DY 0R2J-2-GP +3.3V_RUN KBC_PWR
A NPCE781BA0DX-GP A
1

ECRST#
PCLK_KBC_RC

E51_TxD UMA
2

R3738
2

2K2R2J-2-GP R3727 KBC_PWR R3724

4K7R2J-2-GP 10KR2J-3-GP Wistron Corporation

1
DYR3736 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

E
1 2

4K7R2J-2-GP Q3709 Q3709_1 1 2 C3707 Taipei Hsien 221, Taiwan, R.O.C.

1

MMBT3904-7-F-GP 39,42 PURE_HW_SHUTDOWN# 1 2 ECRST#_C B SC1U10V3KX-3GP

1

2
2

Title
C3704 2 3 CAPA2_INT_R# R3702 Q3702
78 CAPA_INT#
KBC Nuvoton NPCE781BA0DX

C
0R2J-2-GP CH3906PT-GP
DY SC4D7P50V2CN-1GP
1

2009/08/05
Added BJT Gate Q3709
Size Document Number Rev
Custom
For prevent electric leakage issue
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 37 of 90
 5 4 3 2 1

D D

C C

(Blank)

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 38 of 90
5 4 3 2 1
 5 4 3 2 1

+5V_RUN +3.3V_RUN +5V_RUN

SSID = Thermal 25mil R3912
0R2J-2-GP

1
1

1
R3907 1 2
C3910 C3909 10KR2J-3-GP DY R3901
SC4D7U6D3V5KX-3GP SCD1U16V2KX-3GP DY 10KR2J-3-GP

2
D3901

2
B0530WS-7-F-GP

EMC2102_FAN_TACH A K EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 58

D D
EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 58
25mil
RN3901
3 2 +3.3V_RUN
4 1
SRN4K7J-8-GP
THERM_SCL 37,78
THERM_SDA 37,78

1. CPU System Sensor

1 EMC2102_VDD_3D3

29

28

27

26

25

24

23

22
+3.3V_RUN 2
Q3905 must be near CPU R3908 U3901
49D9R2F-GP

GND

TACH

VDD_5Va

FANa

FANb

VDD_5Vb

SMCLK

SMDATA
2
C3912 must be near Q3905
C3905
C3914 SCD1U16V2KX-3GP

1
2

2
SC470P50V3JN-2GP
Q3905 1 C3912
PMBS3904-1-GP DY SC470P50V3JN-2GP C3914 must be 1 21
2

VDD_3V NC#21
near EMC2102
3

EMC2102_DN1 2 20
DN1 GND
EMC2102_DP1 3 19 TP_ALERT# 1 TP3903 Do Not Stuff
DP1 ALERT#
Layout notice: EMC2102 +3.3V_RUN
CH2_THERMDC 4 18 CLK_32K
H_THERMDA, H_THERMDC routing together, DN2 CLK_IN R3906 GND = Internal Oscillator Selected
C C
Trace width / Spacing = 10 / 10 mil CH2_THERMDA 5 DP2 CLK_SEL 17 EMC2102_CLK_SEL 1 2 10KR2J-3-GP
+3.3V = External 32.768kHz Clock Selected
T8_THERMDC 6 16 TP_EM2102_RESET# 1
DN3 RESET# TP3904 Do Not Stuff
2. GPU Sensor (DIS)
T8_THERMDA 7 15
DP3 NC#15

THERMTRIP#

POWER_OK#
R3918 DIS 0R2J-2-GP

SYS_SHDN#
1 2

FAN_MODE
81 VGA_THERMDC

SHDN_SEL

TRIP_SET
1

C3906
C3906 must be SC470P50V3JN-2GP

NC#8
near EMC2102
2

GND = Channel 1
R3919 1 DIS 2 0R2J-2-GP EMC2102-DZK-GP

10

11

12

13

14
81 VGA_THERMDA OPEN = Channel 3
+3.3V = Disabled RN3902
CH2_TDC R3920 1 UMA 2 0R2J-2-GP EMC2102_PWROK 3 2 +3.3V_RUN
R3903 EMC2102_THERMTRIP# 4 1
2 EMC2102_SHDN
DY 1
E

+3.3V_RUN SRN10KJ-5-GP
Q3904 UMA B UMA C3913 C3913 must be near Q3904 10KR2J-3-GP
MMBT3904-3-GP SC470P50V3JN-2GP

1
+3.3V_RUN
C

R3921 R3916 R3910

CH2_TDA 1 UMA 2 0R2J-2-GP 2 1 EMC2102_FAN_mode 10KR2J-3-GP +3.3V_RUN
DY
0R2J-2-GP

SYS_SHDN#

SHDN#_G
Layout notice :

2
KBC_PWR
Both VGA_THERMDA and THERMDC routing
10 mil trace width and 10 mil spacing.

1
B 1 R3914 2 B

1
C3901 must be near Q3901 10KR2J-3-GP R3917 C3902 R3902

G
Q3903 10KR2J-3-GP SCD1U16V2KX-3GP 10KR2F-2-GP
2N7002A-7-GP

2
E

2
2

S D PURE_HW_SHUTDOWN# 37,42 TRIP_SET Pin Voltage

Q3901
MMBT3904-3-GP
B
DY C3901
SC470P50V3JN-2GP
C3903
SC470P50V3JN-2GP
GND = Fan is OFF
V_DEGREE V_DEGREE=(((Degree-75)/21)
1

C3903 must be OPEN = Fan is at 60% full-scale T8 shutdown is set 88 deg-C.

C

near EMC2102 +3.3V = Fan is at 75% full-scale

1
1
3.HW T8 sensor C3904 R3904
SCD1U16V2KX-3GP 2K37R2F-GP

2
Layout notice :

2
Both DN3 and DP3 routing 10 mil
trace width and 10 mil spacing.

32K suspend clock output

Q3902
2N7002A-7-GP
R3913
22 PCH_SUSCLK_2102 D S CLK_32K_R 1 2 CLK_32K
A A
UMA
10R2J-2-GP
1

C3911
DY Wistron Corporation
G

SC4D7P50V2CN-1GP
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
RUN_POWER_ON 42 Title

Size
Thermal/Fan Controllor EMC2102
Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 39 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

D D

Free Fall Sensor

Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
+3.3V_RUN - design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can

1
C4001 C4002
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP

2
+3.3V_RUN
C C

1
+3.3V_RUN U4001

1
R4004
7,18,19,23,64 PCH_SMBCLK
DY 100KR2J-1-GP

VDD

VDD_IO
7,18,19,23,64 PCH_SMBDATA
1

2
R4001
0R2J-2-GP PCH_SMBCLK 14 8 HDD_FALL_INT1
SCL/SPC INT1 HDD_FALL_INT1 21
DY PCH_SMBDATA 13 9 FFS_INT2_R
2

HDD_FALL_SDO SDA/SDI/SDO INT2 +3.3V_RUN

+3.3V_RUN HDD_FALL_SDO 12 SDO
1

1
R4002 7 CS R4005
0R2J-2-GP GND 2
4 100KR2J-1-GP
DY 3
GND
5
2

RESERVED#3 GND
11 10

2
RESERVED#11 GND
FALL_INT2

DE351DLTR8-GP

1
09/0422 +3.3V_RUN +5V_RUN
Q4002
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild DMN66D0LDW-7-GP

1
(#2) FAE/ DY is ok, chip internal pull-up resistors

6
B R4006 R4008 B
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
100KR2J-1-GP DY 10KR2J-3-GP

Pull GND SAD is 0011100b

2
FFS_INT2_R
FFS_INT2 59
1
R4007
DY 0R2J-2-GP
2

FFS_INT2_R
FFS_INT2_R 25

A A
UMA

Note
(1) Keep all signals are the same trace width. (included VDD, GND). Wistron Corporation
(2) No VIA under IC bottom. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Free Fall Sensor Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 40 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 41 of 90
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU: Calpella Platform S3 Power Reduction Platform +0.75V_DDR_VTT

S3 Power Reduction CRB Implementation
SSID = Reset.Suspend Design Details 1 2
DY R4212
22R2J-2-GP

Q4204_D
+1.5V_SUS +1.5V_CPU

D
D D
Q4204
R4215 1 2 0R3J-0-U-GP 2N7002A-7-GP
H_THRMTRIP# 9,25,37 PS_S3CNTRL G
R4222 1 2 0R3J-0-U-GP

S
R4214 R4223 1 2 0R3J-0-U-GP
H_PWRGD_R
9,25 H_PWRGOOD
1
DY 2 B
DY Q4201

1
1KR2J-1-GP CHT2222APT-GP

C
C4208
SCD1U10V2KX-4GP DY Rds(on) = 4.7 mOhm (Max)

2
+1.5V_CPU
R4226
Q4205
D4201 8 D S 1 1 2
BAS16XV2T1G-GP-U
PURE_HW_SHUTDOWN# 37,39
7 D S 2
DY
A K 6 D S 3
46 3V_5V_EN 221R2F-2-GP
5 D G 4

Q4203_D
R4221
1

1 2 S5_ENABLE 37 10KR2J-3-GP SIR460DP-T1-GE3-GP

1
R4209
200KR2J-L1-GP

R4203 1KR2J-1-GP RUN_POWER_ON 1 2 1.5V_CPU_ENABLE

DY
DY DY C4210
SC10U6D3V5KX-1GP

2
1
2

C4209

D
SCD01U50V2KX-1GP

2
Q4203
C 2N7002A-7-GP C
PS_S3CNTRL G

S
+3.3V_RTC_LDO
1

R4201
100KR2J-1-GP
Design current: 4246.6mA
+5V_RUN +5V_ALW
2

2009/08/10 U4201
Changed R8708,R8710,R8711 current-limiting resistor S D
value from 10k to 100k ohm.
1 8
2 S D 7
50 PS_S3CNTRL PS_S3CNTRL R4205 3 S D 6
RUN_POWER_ON 1 2 10KR2J-3-GP RUN_ON_5V 4 G D 5
B +15V_ALW B
AO4468-GP

1
11.6A
C4204
SC6800P25V2KX-1GP Rds=14m ohm

2
3

Q4202
DMN66D0LDW-7-GP
R4206
100KR2J-1-GP
4

Design current: 6480.6mA

1

+3.3V_RUN +3.3V_ALW
U4202
1 S D 8
2 S D 7
22,37,50,51,52,77,86 PM_SLP_S3# RUN_POWER_ON 39
R4211 3 S D 6
2009/07/28 1 2 10KR2J-3-GP RUN_ON_3D3V 4 G D 5
Change 2N7002 ESD pretect from standard to 1KV type
P/N:84.2N702.E31 FDS8880-NL-GP
1

10.7A
C4203
SCD01U50V2KX-1GP Rds=12m ohm
2

Design current: 2783.6mA

A UMA A

+1.5V_RUN +1.5V_SUS
U4204
1 S D 8 Wistron Corporation
2 S D 7 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R4213 3 S D 6 Taipei Hsien 221, Taiwan, R.O.C.
1 214K7R2F-L-GP RUN_ON_1D5VR 4 G D 5
Title
1

AO4468-GP
C4206
SCD01U50V2KX-1GP
11.6A
Size
Power Plane Enable
Document Number Rev
2

Rds=14m ohm Custom

Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 42 of 90
5 4 3 2 1
 5 4 3 2 1

D D

SSID = PWR.Support +5V_ALW

1
PR4306

1
15KR2J-1-GP
PR4303 DY

E
10KR2J-3-GP PD4302

1
PSID_PRO B CH3904PT-GP Do Not Stuff +3.3V_ALW +3.3V_ALW

3
PQ4304

2
2
PR4301

1
PR4309 PSID_DISABLE#_R 1 2
100KR2J-1-GP DY PSID_DISABLE# 37
PR4304
Do Not Stuff 2K2R2J-2-GP

G
1
PQ4303 PD4301

2
FDV301N-NL-GP BAV99-4-GP

3
PR4302
D S PS_ID 1 2

D
PS_ID_EC 37
C C
33R2J-2-GP

DCin CONN PR4310

1
DY 2 This cap should be used
only as last resort for
Do Not Stuff
EMI suppression.
+DC_IN +DC_IN_SS
PU4301
+DC_IN 1 S D 8

SC1U25V5KX-1GP

SC10U25V6KX-1GP
S D

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP
2 7

240KR3-GP
PS_ID_R PR4305 1 2 0R3J-0-U-GP PS_ID_R2 3 S D 6

1
PC4302

PC4304

PC4306

PC4305

PC4301
PC4303 G D

PR4308
4 5
DY Do Not Stuff

2
AO4407A-GP
K

2
2
1

CON8 PD4304
1A 1B 1SMB22AT3G-GP-U PD4303 Id=-12A
PQ4302
2A 2B
DY Do Not Stuff PQ4301
R2
E Qg=-25nC
A

3A 3B 3 OUT AD_OFF_L B Rdson=10~38mohm

DY
2

R1
4A 4B 1 R1 C AD_OFF_R
5A 5B
37 AD_OFF DY 2 GND
IN 2009/06/01

2
6A 6B R2 Do Not Stuff
7A 7B PR4307
Do Not Stuff 47KR3J-L-GP

B FOX-CONN14G-GP B

1
20.D0276.107

AFTP4304 1 +DC_IN
AFTP4305 1 PS_ID_R
AFTP4306 1 GND

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

DC IN Rev
Custom
Vostro Montevina Discrete SA
Date: Tuesday, September 08, 2009 Sheet 43 of 90
5 4 3 2 1
 5 4 3 2 1

Batt Connecter
BAT1
11
9 1 PR4401
AFTP4406
D 8 2 1 KBC_PW R D
7 PBAT_ALARM# 1 AFTP4403
6 470KR2J-2-GP
5 PBAT_PRES1# PR4402 1 2 100R2J-2-GP BAT_IN# 37
4 PBAT_SMBDAT1 3 2
PRN4401 BAT_SDA 37,45
3 PBAT_SMBCLK1 4 1 SRN100J-3-GP BAT_SCL 37,45
2

1 +PBATT
10 PG4401 BATT_SENSE 45

1
2 1
SYN-CON9-13-GP PC4402 PC4401
20.81180.009 SCD1U50V3KX-GP SC2200P50V2KX-2GP Do Not Stuff

2
AFTP4401 PBAT_PRES1#

BAT_IN#

BAT_SDA

BAT_SCL
1
AFTP4402 1 PBAT_SMBDAT1
AFTP4404 1 PBAT_SMBCLK1
AFTP4405 1 +PBATT

C C

3
PD4401 PD4403 PD4402
BAV99-4-GP BAV99-4-GP BAV99-4-GP

2
KBC_PW R

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

BATT CONN Rev
A3
Vostro Montevina Discrete SA
Date: Tuesday, September 08, 2009 Sheet 44 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = Charger +SDC_IN +PWR_SRC

PU4501 PU4502 +PBATT
+DC_IN_SS 8 D S 1 AO4407A-GP
7 D S 2 1 2 1 S D 8

1
6 D S 3 PR4508 2 S D 7

PR4512
D G D01R2512F-4-GP S D

100KR2J-1-GP
5 4 3 6

1
+DC_IN_SS 4 G D 5
AO4407A-GP PG4509 PG4501

2
Do Not Stuff Do Not Stuff

2
Id=-12A PR4513_03

10KR2J-3-GP
PR4527

1
Qg=-25nC

2
D PR4514 D
Id=-12A

2
Rdson=10~38mohm

10KR2F-2-GP
+DC_IN_SS

PG4503

PG4510

PG4506

PG4512

PG4511

PG4513
PR4533_02
470KR2J-2-GP

PR4513

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
Qg=-25nC

1
2
DY 1 Rdson=10~38mohm

2
PQ4502_03
2009/08/03 PR4538

1
PQ4502 2009/08/03

PQ4502_05
Do Not Stuff PR4524_03
2009/08/03

1
0R2J-2-GP
3 4

0R2J-2-GP
316KR3F-2-GP
1

PR4533

PR4524
BQ24745_ACOK 2 5
PR4520

1 6

2
CHAGER_SRC

Do Not Stuff
1 2
2

PC4519

Do Not Stuff
2N7002DW-1-GP

PC4545
SCD1U50V3KX-GP

Do Not Stuff
2
2 PR4522 1 CHAGER_SRC

Do Not Stuff
1

EC4502

EC4501
PC4521 CHG_AGND

1
SC10U25V6KX-1GP

SC10U25V6KX-1GP
0R2J-2-GP PC4520

SCD1U50V3KX-GP
DY

ICREF

1
PR4503

PC4528

PC4532

PC4512

PC4546
SCD1U50V3KX-GP BQ24745_DCIN 22 28 BQ24745_CSSP1 2
DY DY

Do Not Stuff
2
DCIN CSSP

5
6
7
8

2
BQ24745_ACIN SCD1U50V3KX-GP

SI4800BDY-T1
D
D
D
D
2
BQ24745_REF ACIN BQ24745_CSSN CHG_AGND DY DY
SCD1U10V2KX-4GP

+3.3V_RTC_LDO 27

2
BQ24745_LDO CSSN BQ24745_ICOUT
2 10KR2F-2-GP

11 26

2
VDDSMB ICOUT PR4534
PD4501
Do Not Stuff
1

1
PR4511

PC4513

PU4503
0R3J-0-U-GP CHG_AGND
48K7R3F-1-GP

SCD01U50V2KX-1GP
1

PR4515 25 BQ24745_BOOT_1
1 2BQ24745_BST1 K A 1 2
Charger Current=1.4~3.6A

G
S
S
S
BOOT
1

PC4548

PR4528

0R2J-2-GP 21 BQ24745_LDO PC4531

DY
2

4
3
2
1
VDDP
PR4502

C 2 1 BQ24745_ACOK 13 SD103AWS-1-GP SCD1U50V3KX-GP C

ACOK
2

ACAV_IN CHG_AGND 24 BQ24745_CHARGER_UGATE

2

UGATE

1
2 1 BAT_SCL_1 10 1 2 PC4517 +VCHGR1 +PBATT
37,44 BAT_SCL SCL PL4501
PG4505 Do Not Stuff PC4522 Do Not Stuff PR4519
DY
1

23 1 2 SCD1U50V3KX-GP BQ24745_LX1 1 2 1 2
Do Not Stuff

2
PHASE 0R3J-0-U-GP PR4536 IND-5D6UH-43-GP D01R2512F-3-GP

Do Not Stuff

Do Not Stuff

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
2 1 BAT_SDA_1 9 BQ24745_PHASE_GND 1 2
DY 37,44 BAT_SDA DY

Do Not Stuff
SDA
PR4504

CHG_AGND PG4508 Do Not Stuff BQ24745_LGATE_1 PC4536

SCD1U50V3KX-GP
20

Do Not Stuff
LGATE

5
6
7
8

PC4511

PC4524

PC4530

PC4533

PC4523
Do Not Stuff
2

1
PG4502

PG4507

PD4502
SI4800BDY-T1
D
D
D
D
2 1 14 19
DY
NC#14 PGND DY

SCD1U50V3KX-GP

2
37 AD_IA_KBC PR4530 18 BQ24745_CSOP_1

A
CSOP

PC4514

PU4505
0R2J-2-GP CHG_AGND

2
17

G
S
S
S
BQ24745_VICM CSON
4K7R2J-2-GP

4
3
2
1
BQ24745_FBO VICM BQ24745_PR4505
SC220P50V2JN-3GP

1
1

PR4537
PR4539

200KR2F-L-GP

0R2J-2-GP
SCD1U50V3KX-GP
Do Not Stuff

PR4505
1 2

2
PR4506

6 CHG_AGND 1 PR4532 2 BQ24745_CSOP

FBO
PC4516

BQ24745_EAI 0R2J-2-GP
1BQ24745_FBO1

5 16
2

EAI NC#16

2
PC4540 BQ24745_EAO 4
PR4526 EAO
1

PC4541
1 2SC2200P50V2KX-2GP BQ24745_REF 3 VREF
1

2 1PR4526_01
2 7K5R2F-1-GP
1 1 2 BQ24745_CE 7

1
PC4518 PR4510 CE PR4531 BQ24745_CSON
12 15
DY
GND

SC150P50V2JN-3GP 0R2J-2-GP GND VFB 0R2J-2-GP

1 2
Do Not Stuff

Do Not Stuff
2

PC4543
BAT_SENSE 2 1
DY DY BATT_SENSE 44
2

PC4525 PU4504
DY
29

1
PC4526

SC56P50V2JN-2GP BQ24745RHDR-GP
B
DY B
2

1
PR4509
DY

Do Not Stuff

Do Not Stuff
2

PC4544

PR4521
2 1
PC4515 PC4537 PC4529 PC4534 DY DY
Do Not Stuff Do Not Stuff Do Not Stuff SC1U6D3V2KX-GP 0R2J-2-GP

2
CHG_AGND
CHG_AGND
CHG_AGND CHG_AGND

This Resistor
must be 1%
tolerance.

+3.3V_RTC_LDO
1

PR4523
100KR2J-1-GP
2

2009/07/28
37 AC_IN# Change 2N7002 ESD pretect from standard to 1KV type
SCD1U25V3KX-GP

P/N:84.2N702.E31
PC4527
1

A A
UMA
D

PQ4504
2N7002A-7-GP
2

G ACAV_IN Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
S

Title

Size Document Number

CHARGER BQ24745 Rev
Custom
DW Calpella SA
Date: Tuesday, September 08, 2009 Sheet 45 of 90
5 4 3 2 1
 A B C D E

+3.3V_ALW_2
51125_VCLK

1
PC4602 PC4604

SC1KP50V2KX-1GP
PC4603
PR4601 SCD1U25V3KX-GP SCD1U25V3KX-GP
2009/07/28 100KR2J-1-GP

2
Change 2N7002 ESD pretect from standard to 1KV type
P/N:84.2N702.E31

PD3903_1

PD3904_1
2
51125_ENTRIP

PQ4601

D
+PWR_SRC +PWR_SRC_3D3V 2N7002A-7-GP 51125_ENTIP1

3
1

1
4 PG4603 4
1 2 42 3V_5V_EN G PC4605 DY PR4602 PD4603 PD4604

Do Not Stuff
160KR2F-GP BAT54S-5-GP BAT54S-5-GP

4
Do Not Stuff
PG4605 PQ4602

1
1 2 DMN66D0LDW-7-GP +15V_ALW +5V_PWR
PG4610

PD3903_04
Do Not Stuff Do Not Stuff

3
+3.3V_ALW +3D3V_PWR PG4607
PG4602 1 2 1 2 PD3903_2
2 1
Do Not Stuff 51125_ENTIP2

1
Do Not Stuff PG4609 PC4609

1
PG4604 DIS(Clarksfied) 1 2 SC1U25V3KX-1-GP PC4607

Do Not Stuff

1
2 1 PR4603 SCD1U25V3KX-GP

2
1
Design Current =6.58A

PC4608
Do Not Stuff DY 160KR2F-GP
Do Not Stuff 10.34A<OCP<12.23A PC4606

2
PG4606 SCD1U25V3KX-GP

2
2 1

Do Not Stuff
PG4608 DIS(Auburndale)
2 1
Design Current =6.76A +PWR_SRC_3D3V +PWR_SRC
Do Not Stuff 10.61A<OCP<12.54A +PWR_SRC_5V
PG4611 DIS(Clarksfied)
2 1 PC4612 PC4613
Design Current =8.53A

Do Not Stuff

SCD01U50V2KX-1GP
1

1
Do Not Stuff PC4610 PC4627 PC4611 DY 13.41A<OCP< 15.84A
1

1
Do Not Stuff

+5V_PWR +5V_ALW
PG4613 UMA(Auburndale)
SC10U25V6KX-1GP

SC10U25V6KX-1GP

2 1 DY PG4614

2
Design Current =5.58A D D PC4614 PC4615 PC4616 DIS(Auburndale) 1 2
2

8
7
6
5

5
6
7
8

1
Do Not Stuff +PWR_SRC +PWR_SRC_5V
8.77A<OCP<10.36A

D
D
D
D
Design Current =8.53A
D
D
D
D

SC10U25V6KX-1GP

SC10U25V6KX-1GP

Do Not Stuff
PG4627 PU4601 PU4602 DY Do Not Stuff

16
2 1 SIS412DN-T1-GE3-GP SIS412DN-T1-GE3-GP 13.41A<OCP< 15.84A PG4615

2
PU4603 PG4612 1 2
Do Not Stuff PC4617 PR4605 1 2

VIN
SCD1U25V3KX-GP PR4604 0R3J-0-U-GP Do Not Stuff

G
S
S
S
0R3J-0-U-GP SCD1U25V3KX-GP Do Not Stuff
S
S
S
G

UMA(Auburndale) PG4616
3 PC4618 G S PG4624 1 2 3
1
2
3
4

4
3
2
1
S G 2 1 51125_VBST2_1 1 251125_VBST2 9 22 51125_VBST1 1 2 51125_VBST1_1 1 2 Design Current =8.53A 1 2
VBST2 VBST1 Do Not Stuff
+3D3V_PWR 51125_DRVH2 51125_DRVH1 +5V_PWR
13.41A<OCP< 15.84A
PL4601 10 21 Do Not Stuff PG4617
DRVH2 DRVH1 PL4602
PG4625 1 2
1 2 51125_LL2 11 20 51125_LL1 1 2 1 2
IND-3D3UH-115-GP LL2 LL1 COIL-2D2UH-11-GP Do Not Stuff
1

PTC4603 PTC4601 D 51125_DRVL2 12 19 51125_DRVL1 Do Not Stuff PG4619

DRVL2 DRVL1
1

1
PC4619 D PG4628 1 2
DY
8
7
6
5

5
6
7
8
ST100U6D3VBM-5GP

ST220U6D3VDM-15GP

PG4618 PR4606
DY DY DYPR4607 1 2

D
D
D
D
Do Not Stuff

D
D
D
D
151125_LL2_R

Do Not Stuff PU4604 51125_VO2 7 24 51125_VO1 PU4605 PG4620 PC4601 PTC4602 PTC4604 Do Not Stuff
2

VO2 VO1
1

1
Do Not Stuff

Do Not Stuff
151125_LL1_R
Do Not Stuff Do Not Stuff PG4601
2

SI7716ADN-T1-GE3-GP

SI7716ADN-T1-GE3-GP

Do Not Stuff

ST220U6D3VDM-15GP

ST100U6D3VBM-5GP
51125_FB2 5 2 51125_FB1 PG4629 1 2
DY

2
VFB2 VFB1
1 2

2
Do Not Stuff
2

2
G
S
S
S
DYDo2 Not51125_EN 3V_5V_POK Do Not Stuff
S
S
S
G

1 13 23 PG4621
PR4608 Stuff EN0 PGOOD
G S PG4631 1 2
1
2
3
4

4
3
2
1
PC4620 S G 51125_ENTIP2 6 1 51125_ENTIP1 1 2
Do Not Stuff 51125_VREF ENTRIP2 ENTRIP1 PC4621 Do Not Stuff
DY
2

3 15 Do Not Stuff Do Not Stuff PG4622

DY

2
VREF GND
PG4633 1 2
1
SCD22U10V2KX-1GP

PC4622

51125_TONSEL 4 25 1 2
TONSEL GND Do Not Stuff

1
PR4611 Do Not Stuff PG4632
2
1

14 18 51125_VCLK Do Not Stuff 1 2

SKIPSEL VCLK

1
PR4610 51125_SKIPSEL DY
PR4609 DY Do Not Stuff PR4612 Do Not Stuff

VREG3

VREG5
6K65R2F-GP 33KR2F-GP PG4626

1 2
TPS51125RGER-GP 51125_FB1_R 1 2
2

1 2

51125_FB2_R 74.51125.073

2
PC4624 PC4623 DY Do Not Stuff
3D3V_AUX_S5_5_51125 8

DYDo Not Stuff 17 +5V_ALW2 +3.3V_RTC_LDO Do Not Stuff PG4630

2
+3.3V_ALW_2 1 2
2

PG4623

1
1 2 Do Not Stuff
1

PR4616 PR4614 PR4615 PG4635

PR4613 2 Do Not Stuff 21K5R2F-GP
10KR2F-2-GP
51125_VREF DYDo1 Not Stuff 100KR2J-1-GP 1 2

PR4617 Close to VFB Pin (pin2) Do Not Stuff

2
2 2 1 PG4634 2
+3.3V_ALW_2 3V_5V_POK 37
2

SC22U6D3V5MX-2GP
0R2J-2-GP 1 2
PC4625

PC4628

51125_VREF 2 PR4618
1 Do Not Stuff
1

0R2J-2-GP PC4626
SC4D7U10V5KX-4GP

Close to VFB Pin (pin5) 2009/08/26

SC10U10V5KX-2GP

2 PR4619
1 +3.3V_ALW_2 +3.3V_RTC_LDO
+3.3V_ALW_2 DY
2

Do Not Stuff
PR4620
2 PR4621
1 1 2
DY Do Not Stuff I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
0R2J-2-GP
Inductor: PCMC104T-2R2MN Cyntec 7 mohm Isat =27Arms 68.2R210.20C
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
Inductor: 3.3UH PCMB104T-3R3MS Cyntec 11.8mohm Isat =16Arms 68.3R310.20C O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L H/S: SIS412DN/ 24mohm/[email protected]/ 84.00412.037
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 L/S: SI7716ADN/ 13.5mOhm/[email protected]/ 84.07716.037
H/S: SIS412DN/ 24mohm/[email protected]/ 84.00412.037
L/S: SI7716ADN/ 13.5mOhm/[email protected]/ 84.07716.037

TONSEL CH1 CH2 SKIPSEL VREG3 or VREG5 VREF(2V) GND

GND 200kHz 265kHz Operating OOA Auto Skip Auto Skip
Mode PWM only
VREF 245kHz 305kHz
VREG3 300kHz 375kHz
VREG5 365kHz 460kHz EN0 Open 820kΩ to GND GND
Operating
Mode enable both enable both LDOs, disable all
LDOs, VCLK on VCLK off and circuit
and ready to ready to turn on
1 turn on switcher channels 1
switcher
channels

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
TPS51125_5V/3D3V
Document Number Rev
Custom DW Calpella X00
Date: Tuesday, September 08, 2009 Sheet 46 of 90
A B C D E
 5 4 3 2 1

PM_DPRSLPVR 12
7 VR_CLKEN#
IMVP_VR_ON 37
+5V_ALW +PWR_SRC_CPU1
CPU_VID[6..0] 12 PR4736
0R2J-2-GP PC4735 2009/08/20

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
+3.3V_RUN 2 1 1 2

SC1U10V2KX-1GP PR4735 PC4737 PC4738 PC4733 PC4734

1
BOOT3 1 2 6208_PHASE3

6208_FCCM

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
2D2R3J-2-GP

2
5
6
7
8
0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP
D PC4736 PU4702 D

D
D
D
D
5

SI7686DP-T1-GP
PU4705 SCD22U16V3KX-1-GP

1
BOOT
VCC
2

2
2 7 PHASE3
PW M PHASE

G
S
S
S
6208_PWM
8 UGATE3
PR4747 UGATE LGATE3
4

4
3
2
1
1K91R2F-1-GP LGATE
6 FCCM

GND
GND
1

62883_DPRSLPVR 1

1
PR4744

PR4745

PR4737

PR4738

PR4746

PR4739

PR4740

PR4741

PR4742

PR4743
UGATE3

2
+VCC_CORE
PL4701

62883_CLK_EN#
ISL6208CRZ-TGP-U

9
3
62883_VR_ON
PHASE3 1 2

62883_VID6

62883_VID5

62883_VID4

62883_VID3

62883_VID2

62883_VID1

62883_VID0
L-D36UH-1-GP

1
PTC4701 PTC4702
DYPR4701

5
6
7
8

SE330U2VDM-6-GP

SE330U2VDM-6-GP
+3.3V_RUN PU4703 Do Not Stuff

Do Not Stuff

Do Not Stuff

2
D
D
D
D
SIR460DP-T1-GE3-GP
NTC 470K close to H/S MOSFET of Phase1

1 SNUBBER3 2
2
40

39

38

37

36

35

34

33

32

31
1

1
PU4701 PR4750

PG4713

PG4714
PR4749 0R2J-2-GP LGATE3

CLK_EN#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
DPRSLPVR

VR_ON
+1.05V_VTT 1K91R2F-1-GP

S
S
S
G
+5V_ALW

2
PR4753
2

4
3
2
1
1

1 2 62883_PGOOD 1 30 BOOT2 BOOT2 48 Do Not Stuff

PR4751 37 IMVP_VR_PWRGD PR4748 0R2J-2-GP PGOOD BOOT2 PC4701

+VCC_CORE_PHASE3
PHASE3_R
2 DY 1
68R2-GP 1 2 62883_PSI# 2 29 UGATE2 Do Not Stuff
12 PSI# UGATE2 48
DY

2
PSI# UGATE2

2
PR4752 0R2J-2-GP
62883_AGND 1 2 62883_RBIAS 3 28 PHASE2
PHASE2 48 PR4755
2

PR4754 147KR2F-GP RBIAS PHASE2

C 0R3J-0-U-GP C
4 27 ISEN3 1 2
9 H_PROCHOT# VR_TT# VSSP2 PR4756 51KR2F-L-GP

1
1 DY 26266A_NTC_R 1 2 PR4758 62883_NTC 5 26 LGATE2 VSUM+ 1 2
62883_AGND
PR4757 DY NTC-470K-8-GP NTC ISL62883HRTZ-T-GP LGATE2 LGATE2 48
PR4759 3K65R3F-GP
Do Not Stuff1 62883_VW 62883_VCCP VSUM-
62883_AGND DY 2
Do Not Stuff
6 VW VCCP 25 1
PR4760
2
1R2F-GP
PC4739 1 2 62883_COMP 7 24 62883_PWM3 PC4741 PC4742 ISEN1 1 2
COMP PW M3/LGATE1#

1
PR4761 PR4762 51KR2F-L-GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
8K06R2F-GP 62883_FB 8 23 LGATE1 ISEN2 1 2
FB LGATE1 LGATE1 48
PR4763 51KR2F-L-GP

2
1 2 ISEN3 9 22
PC4740 ISEN3/FB2 VSSP1
SC1000P50V3JN-GP ISEN2 10 21 PHASE1
ISEN2 PHASE1 PHASE1 48
1

UGATE1
PC4745

BOOT1
ISUM+
ISEN1

ISUM-
PC4743
SCD22U25V3KX-GP

SCD22U25V3KX-GP

VSEN

IMON
41
Intel support POC (power on current).
VDD
RTN

GND

VIN
62883_AGND 1 DY 2 1 2
VSUM-2

VSUM-2

PR4764 PC4744

2
Do Not Stuff SC33P50V2JN-3GP
11

12

13
62883_ISUM- 14

15

16

17

18

19

20
62883_AGND PC4746 +1.05V_VTT
SCD22U16V3KX-1-GP

1
62883_VDD

ISEN3 2 62883_COMP_R1 ISEN1 UGATE1

1 DY 2 1 2
62883_VIN

UGATE1 48
PC4747 PC4748 PR4766 BOOT1 1 2 BOOT1_PHASE1
1

SCD22U25V3KX-GP
PC4749

Do Not Stuff SC150P50V2JN-3GP 324KR2F-GP IMVP_IMON PR4767 2D2R3J-2-GP IMVP_IMON 12

+PWR_SRC_CPU1 PR4770 PR4771 PR4772 PR4773 PR4774 PR4775 PR4776 PR4777 PR4778

1
1 2 PR4799
VSUM-2

1KR2J-1-GP

1KR2J-1-GP

1KR2J-1-GP

Do Not Stuff

Do Not Stuff

1KR2J-1-GP

Do Not Stuff

1KR2J-1-GP

Do Not Stuff
PR4768 0R2J-2-GP 2009/08/20
PC4751 +5V_ALW
1 2 +1.05V_VTT DY
DY DY DY DY

1
SC390P50V2KX-GP 1 2 PC4750 100KR2F-L1-GP

8K25R2F-1-GP
PR4781
1R2F-GP SCD22U10V2KX-1GP

2
1

B 1 2 62883_FB_VSEN
1 2 PC4752 PC4753 PR4769 B

2
48 ISEN1 ISEN1 PR4779
SC1U10V2KX-1GP

SCD22U25V3KX-GP

562R2F-GP PR4794 CPU_VID0

2

2
ISEN2 1 2 2 1 CPU_VID1
48 ISEN2
CPU_VID2
VSS_SENSE 12
ISEN3 PR4780 0R2J-2-GP CPU_VID3
48 ISEN3
2K37R2F-GP CPU_VID4
62883_AGND
62883_AGND ARD:8.25Kohm/64.82515.6DL CPU_VID5
ARD:2.37Kohm/64.23715.6DL CPU_VID6
CFD:5.62Kohm/64.56215.6DL PM_DPRSLPVR
CFD:2.21Kohm/64.22115.6DL
1

PSI#
PC4754 2009/08/26
2009/08/26 SC330P50V2KX-3GP PR4785 PR4786 PR4787 PR4788 PR4789 PR4790 PR4791 PR4792 PR4793
2

1
VSUM+ VSUM+ 48

Do Not Stuff

Do Not Stuff

Do Not Stuff

1KR2J-1-GP

1KR2J-1-GP

Do Not Stuff

1KR2J-1-GP

Do Not Stuff

1KR2J-1-GP
1

1
DY DY DY DY DY
62883_AGND PR4782 PR4783
12 VCC_SENSE 82D5R2F-1-GP PC4756 2K61R2F-1-GP

2
SCD33U16V3KX-1GP
1

PC4759 PC4757 PR4784

1 VSUM_RR
VSUM_RC 2

2
SCD01U16V2KX-3GP

SC330P50V2KX-3GP
11KR2F-L-GP
2

12 VSS_SENSE
62883_AGND
2
1

PC4760 PR4795
2

SC1000P50V3JN-GP PC4758 NTC-10K-26-GP

SCD01U25V2KX-3GP
2

1 2 VSUM- VSUM- 48
PR4796 NTC 10K close to Choke of Phase1
A 768R2F-1-GP Do Not Stuff A
1

1 2 UMA
62883_AGND PC4762
ARD:768ohm/64.76805.6DL SCD1U25V3KX-GP
2

PR4798
CFD:698ohm/64.69805.6DL 62883_AGND Wistron Corporation
62883_AGND 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2009/08/26 Taipei Hsien 221, Taiwan, R.O.C.

Title
ISL62883_CPU_CORE_1/2
Size Document Number Rev
Custom
DW Calpella X00
Date: Tuesday, September 08, 2009 Sheet 47 of 90
5 4 3 2 1
 5 4 3 2 1

+PW R_SRC_CPU2
+PW R_SRC +PW R_SRC_CPU1 +PW R_SRC +PW R_SRC_CPU2

PG4807
PG4813 2009/08/20
1 2
1 2 PC4863 PC4864 PC4865 PC4866

1
Do Not Stuff

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
Do Not Stuff PG4814 DIS(Clarksfield)
PG4808 1 2
Design Current = 34A

2
1 2

5
6
7
8
Do Not Stuff PU4801 Peak Current=52A

D
D
D
D
SI7686DP-T1-GP
Do Not Stuff PG4815
PG4809 1 2
62.4A<OCP<72.8A
1 2
D Do Not Stuff D
Do Not Stuff PG4816

G
S
S
S
PG4810 1 2 DIS(Auburndale)
1 2
Design Current = 34A

4
3
2
1
Do Not Stuff
Do Not Stuff Peak Current=48A
PG4811 UGATE2 +VCC_CORE
1 2
47 UGATE2 PL4801 57.6A<OCP< 67.2A
PHASE2 1 2
Do Not Stuff 47 PHASE2 L-D36UH-1-GP

1
PG4812

1
1 2 PR4812 PTC4801 PTC4802 UMA(Auburndale)
DYPR4815

Do Not Stuff

Do Not Stuff
BOOT2 1 2B00T2_R 1 2
47 BOOT2 Design Current = 34A

5
6
7
8

SE330U2VDM-6-GP

SE220U2VDM-12GP
Do Not Stuff 2D2R3J-2-GP PC4867 PU4803 Do Not Stuff

2
1

1
D
D
D
D
SIR460DP-T1-GE3-GP
PG4805 SCD22U16V3KX-1-GP Peak Current=48A

1SNUBBER2 2

PG4801

PG4802
1 2 57.6A<OCP< 67.2A
Do Not Stuff

2
PG4806

S
S
S
G
1 2

4
3
2
1
Do Not Stuff
PC4802

PHASE2_R

+VCC_CORE_PHASE2
Do Not Stuff
DY

2
LGATE2
47 LGATE2

ISEN2 1 2
47 ISEN2 PR4801 51KR2F-L-GP
VSUM+ 1 2
47 VSUM+ PR4802 3K65R3F-GP
C VSUM- 1 2 C
47 VSUM- PR4803 1R2F-GP
+PW R_SRC ISEN1 1 2
47 ISEN1 PR4804 51KR2F-L-GP
ISEN3 1 2
47 ISEN3 PR4805 51KR2F-L-GP
1

TC4801
DY
SE100U25VM-10GP
2

+PW R_SRC_CPU1

2009/08/20

1
PC4868 PC4869 PC4870 PC4871

SCD1U50V3KX-GP
SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
2009/08/20

2
PU4802

5
6
7
8
SI7686DP-T1-GP

D
D
D
D
G
S
S
S
4
3
2
1
UGATE1 +VCC_CORE
47 UGATE1 PL4802
B B
PHASE1 1 2
47 PHASE1 L-D36UH-1-GP

1
PTC4803 PTC4804

DYPR4816
5
6
7
8

SE330U2VDM-6-GP

SE220U2VDM-12GP
PU4804

2
D
D
D
D
SIR460DP-T1-GE3-GP

Do Not Stuff

Do Not Stuff

Do Not Stuff
SNUBBER1 2

1
PG4803

PG4804
S
S
S

LGATE1
G

47 LGATE1
4
3
2
1

2
1

PC4803

+VCC_CORE_PHASE1
Do Not Stuff
DY
2

PHASE1_R

ISEN1 1 2
47 ISEN1 PR4807 51KR2F-L-GP
VSUM+ 1 2
47 VSUM+ PR4808 3K65R3F-GP
VSUM- 1 2
47 VSUM- PR4809 1R2F-GP
ISEN2 1 2
47 ISEN2 PR4810 51KR2F-L-GP
A ISEN3 1 2 A
47 ISEN3 PR4811 51KR2F-L-GP UMA
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.36UH ETQP4LR36WFC PANASONIC 1.1mohm/ 68.R3610.20A Wistron Corporation
O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L Taipei Hsien 221, Taiwan, R.O.C.
H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037 Title
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037 ISL62883_CPU_CORE_2/2
Freq=300KHz@PER PHASE Size Document Number Rev
Custom
DW Calpella X00
Date: Tuesday, September 08, 2009 Sheet 48 of 90
5 4 3 2 1
 5 4 3 2 1

+PWR_SRC +PWR_SRC_VTT TPS51218 for +1.05V/+1.1V_VTT

PG4902
1 2

Do Not Stuff
PG4903
1 2
+PWR_SRC_VTT
DIS(Clarksfield 1.1V_RUN)
Do Not Stuff Design Current = 14.4A
PG4904 19.8A<OCP<23.4A
1 2
D D
Do Not Stuff DIS(Arrandale 1.05V_VCCP) +1.05V_VTT_P +1.05V_VTT +1.05V_VTT_P +1.05V_VTT

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP

SC4D7U25V5KX-GP
PG4905
1 2 Design Current = 20.95A PG4908 PG4909

2
28.8A<OCP<34.04A 1 2 1 2

PC4924

PC4909

PC4903

PC4904

PC4902

PC4905
Do Not Stuff
PG4906 PU4902 PU4905
ARD Do Not Stuff Do Not Stuff

1
5
6
7
8

5
6
7
8
SI7686DP-T1-GP

SI7686DP-T1-GP
1 2 PG4910 PG4901

D
D
D
D

D
D
D
D
DIS Clarksfield:80.6K/64.80625.6DL UMA(Arrandale 1.05V_VCCP) 1 2 1 2
Do Not Stuff DIS Arrandale:56K/64.56025.6DL Design Current = 19.84A Do Not Stuff Do Not Stuff
UMA Arrandale:53.6K/64.53625.6DL ARD 27.28A<OCP<32.24A PG4911 PG4912
1 2 1 2

G
S
S
S

G
S
S
S
2009/08/16 9,37,50 VTT_PWRGD
PU4901 PR4901 PC4906 Do Not Stuff Do Not Stuff
DIS:1.5uH/68.1R510.10J

4
3
2
1

4
3
2
1
SCD1U25V3KX-GP UMA:0.56uH/68.R5610.10D PG4913 PG4914
PR4902 1 11 2D2R3J-2-GP 1 2 1 2
51218_VTT_TRIP PGOOD GND 51218_VBST_VTT 1 51218_VBST_VTT1
1 2 2
TRIP VBST
10 2 2 1 PL4901
80K6R2F-GP 51218_VTT_EN 3 9 51218_DRVH_VTT +1.05V_VTT_P Do Not Stuff Do Not Stuff
51218_VTT_VFB EN DRVH 51218_SW_VTT PG4915 PG4916
4 8 1 2
PR4921 1 51218_VTT_CCM VFB SW IND-D56UH-12-GP
50,51,52 RUNPWROK 2 5
RF V5IN
7 +5V_ALW 1 2 1 2

Do Not Stuff

SC4D7U6D3V5KX-3GP

SCD1U10V2KX-4GP
1KR2F-3-GP 6 51218_DRVL_VTT PC4901 PC4910 PTC4902 PTC4901
DRVL
1

1
Do Not Stuff Do Not Stuff

PG4921

SE330U2VDM-L-GP

SE330U2VDM-L-GP
PC4908 PR4904
DY Do Not Stuff ARD PG4917 PG4918
1

5
6
7
8

5
6
7
8

1
PC4907

PR4903 TPS51218DSCR-GP-U SC1U10V2KX-1GP PU4903 PU4904

SC1KP50V2KX-1GP

1 2 1 2

2
D
D
D
D

D
D
D
D
SIR460DP-T1-GE3-GP

SIR460DP-T1-GE3-GP
470KR2F-GP
Do Not Stuff Do Not Stuff
2

1 51218_SW_GND_VTT 2
PG4919 PG4920

2
ARD 1 2 1 2

S
S
S

S
S
S
Do Not Stuff Do Not Stuff

G
1 PG4925 PG4927
C DY 2 C

4
3
2
1

4
3
2
1
VTT_SENSE 12
1 2 1 2

PR4905
PR4912

5K1R2F-2-GP
Do Not Stuff
Do Not Stuff Do Not Stuff Do Not Stuff
R1 PG4926 PG4928
+3.3V_RUN 1 2 1 2
PC4911

2
Do Not Stuff Do Not Stuff
2009/08/05 DY PG4933 PG4934

2
+3.3V_ALW 1 2 1 2
Vout=0.704V*(R1+R2)/R2
51218_VTT_VFB Do Not Stuff Do Not Stuff
1

PG4935 PG4936
1

PR4908 1 2 1 2
PR4907 100KR2J-1-GP
10KR2J-3-GP Do Not Stuff Do Not Stuff

75KR2F-GP

10K2R2F-GP
1

1
PR4910

PR4906
2

CFD 2009/08/26
2

1 6 R2
VTT_PWRGD 2 5 H_VTTPWRGD_R

2
+1.05V_VTT +1.05V_PCH +1.05V_VTT
2009/08/16
3 4
1

PC4912 PR4910 Vout=0.704V*(R1+R2)/R2

1

SCD1U25V3KX-GP R4901
PQ4901 PR4909 1 ARD 2 0R6J-L-GP
2

DMN66D0LDW-7-GP 1KR2J-1-GP AUB DY Vout=1.05V

R4903
2

CFD ASM Vout=1.1V 1 ARD 2 0R6J-L-GP

H_VTTPWRGD
H_VTTPWRGD 9
B B
2009/07/28
Change 2N7002 ESD pretect from standard to 1KV type 2009/07/27
P/N:84.2N702.E31
Co-lay AUB and CFD VTT.

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
Frequency setting Inductor: 1.5uH PCMC104T-1R5MN Cyntec DCR:4.2mohm Isat=33Arms 68.1R510.10J
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
470K -->290KHz H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037
200K -->340KHz L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
A 100K -->380KHz A
UMA
39K -->430KHz
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51218_+1.05V_VTT
Size Document Number Rev
Custom
DJ1 Discrete X00
Date: Tuesday, September 08, 2009 Sheet 49 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p5v0p75v
+5V_ALW PR5012 1 2 0R2J-2-GP 0D75V_EN
22,37,42,51,52,77,86 PM_SLP_S3#
DIS Clarksfield:11.5K/64.11525.6DL
PR5006 PR5014 1 2 Do Not Stuff
DIS Arrandale:9.76K/64.97615.6DL 22,37,77 PM_SLP_S4# DY

1
5D1R3J-GP PR5015 1 2 0R2J-2-GP 1D5V_EN
+5V_ALW 22,37,77 PM_SLP_S4#
UMA Arrandale:6.65K/64.66515.6DL

1
PR5007
2009/07/09 PC5022
2009/08/16 DY

2
1 2 TPS51116_VDD follow vostro 15 inch schematic SCD1U10V2KX-4GP

2
1
+5V_ALW

SC1U10V3KX-3GP
D 11K5R2F-GP D
PC5001
DY

PC5019
1 2 Do Not Stuff

2
1
SC1U10V3KX-3GP

1
PC5003 PC5018 2009/07/29

2
+3.3V_ALW SC1KP50V2KX-1GP PD5001 Reserved R,C By PM_SLP_S4# ,for time delay
DY
+PWR_SRC_1D5V Do Not Stuff

2
TPS51116_ILIM
2

16

14

15
PR5004 PU5002 +PWR_SRC +PWR_SRC_1D5V
PG5002
DY Do Not Stuff

VDDP

VDDP
ILIM
2 1
22 TPS51116_VBST 1 2 TPS51116_VBST1
PR5003 R5034
1

BST 0R3J-0-U-GP Do Not Stuff 100KR2J-1-GP

49,51,52 RUNPWROK 13 PGD PG5004 1 2 0D75V_EN
PR50111 2 Do Not Stuff TPS51116_NC#12 12 21 TPS51116_UGT 2 1
9,37,49 VTT_PWRGD DY
DY NC#12 DH
1D5V_EN 11 Do Not Stuff
EN/PSV PG5006

D
0D75V_EN 10 20 TPS51116_PHS 2 1 +1.5V_SUS_P +1.5V_SUS
RT: Non_ASM VTTEN LX Q5003 PG5001
TI: ASM
+1.5V_SUS_P 23
VTTIN
Do Not Stuff DY 2N7002A-7-GP 1 2
PG5008 PS_S3CNTRL G
1 42 PS_S3CNTRL
19 TPS51116_LGT 2 1 Do Not Stuff
PC5002 7 DL PG5003
+5V_ALW NC#7
SC1U10V3KX-3GP Do Not Stuff 1 2
2

S
PR50011 2 Do Not Stuff TPS51116RGER-GP-U
DY 1 18 Do Not Stuff
C +1.5V_SUS_P PGND2 PGND1 PG5005 C
17
PR50021 TPS51116_TON PGND1
2 0R2J-2-GP 4 1 2
TON TPS51116_VDDQSNS
8
VDDQS
2

Do Not Stuff
PC5017 24 9 TPS51116_VDDQSET DIS(Clarksfied) PG5007
Do Not Stuff DY VTT FB
1 2
1

+0D75V_DDR_P 2 +5V_ALW PR5005 Design Current = 14.52A

VTTS +PWR_SRC_1D5V Do Not Stuff
VCCA
6 1
DY 2 22.82A<OCP<26.97A
VSSA

PG5009
GND

REF
Do Not Stuff 1 2

1
DIS(Auburndale)
DY PC5020 Do Not Stuff
25

+V_DDR_REF Do Not Stuff Design Current = 12.42A PG5011

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

PC5007
SCD1U50V3KX-GP

SC4D7U25V5KX-GP
19.52A<OCP<23.07A 1 2
1TPS51116_REF

PC5035

PC5004

PC5005

PC5006
1 PR5013 2

1
Do Not Stuff Do Not Stuff
PU5003 UMA(Auburndale) PG5012
DIS

5
6
7
8
SI7686DP-T1-GP
1 2

2
Design Current = 8.51A

D
D
D
D
Design Current = 0.7A 2009/08/05 Do Not Stuff
13.37A<OCP<15.8A
PG5013
PC5021 1 2
+0D75V_DDR_P SCD033U16V3KX-GP
2

G
S
S
S
Do Not Stuff
DIS:1.0uH/68.1R01A.20A PG5019

4
3
2
1
1 2
+0D75V_DDR_P +0.75V_DDR_VTT UMA:1.5uH/68.1R510.10J +1.5V_SUS_P
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
PC5008

PC5009

PC5010

PC5011
SCD1U10V2KX-4GP

PG5014 TPS51116_UGT Do Not Stuff

PL5001
1

1 2 PG5020
B TPS51116_VBST1 1 TPS51116_PHS B
2 1 2 1 2
Do Not Stuff COIL-1UH-33-GP
2

PG5015 PC5012 Do Not Stuff

SC4D7U6D3V5KX-3GP
1

SCD1U10V2KX-4GP
1 2 SCD1U25V3KX-GP PG5018

PC5013

PC5014
PTC5001 PTC5002 1 2

5
6
7
8

5
6
7
8

1
Do Not Stuff PU5001 PU5008 PR5008
DY

D
D
D
D

D
D
D
D
SIR460DP-T1-GE3-GP

SIR460DP-T1-GE3-GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
PG5016
Do Not Stuff Do Not Stuff
DY PG5017

2
Do Not Stuff
1 2

1
TPS51116_LGT TPS51116_PHS_SET
DY Do Not Stuff

1
S
S
S

S
S
S
PG5021

G
State S3 S5 VDDR VTTREF VTT DY PC5015 1 2

4
3
2
1

4
3
2
1
S0 Hi Hi On On On Do Not Stuff DIS:EEFSX0D331ER/79.33719.L01

2
Do Not Stuff
UMA:EEFCX0D221R/79.22719.20L PG5022
S3 Lo Hi On On Off(Hi-Z)
TPS51116_VDDQSNS 1 2

1
S4/S5 Lo Lo Off Off Off

1
Do Not Stuff
PR5009 DY PC5016 PG5058
30KR2F-GP Do Not Stuff 1 2

2
2
TPS51116_VDDQSET Do Not Stuff

1
VDDQSET VDDQ (V) VTTREF and VTT NOTE I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 1.0uH PCMC104T-1R0MN Cyntec DCR:3.5mohm Isat=40Arms 68.1R01A.20A PR5010
GND 2.5 VVDDQSNS/2 DDR O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01 30KR2F-GP
A O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms PANASONIC/ 79.22719.20L UMA A

2
H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037 Close to VFB Pin (pin5)
V5IN 1.8 VVDDQSNS/2 DDR2
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
Switching freq-->400KHz Wistron Corporation
FB Resistors Adjustable VVDDQSNS/2 1.5 V < VVDDQ < 3 V 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51116_+1.5V_SUS
Size Document Number Rev
Custom
DW Calpella X00
Date: Tuesday, September 08, 2009 Sheet 50 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p8v
APL5930 for +1.8V_RUN +3.3V_ALW

PG5102
D 2 1 D

+5V_ALW Do Not Stuff

PG5103
2 1

SC1U10V3KX-3GP

Do Not Stuff

SC10U6D3V5MX-3GP
1

1
PC5102

PC5104

PC5103
Do Not Stuff
DY DIS(Clarksfield) +1.8V_RUN_P +1.8V_RUN
Design Current =0.9A

2
UMA(Arrandale)
PG5104
Design Current =11.24A 1 2

6
PU5102
Do Not Stuff

VCNTL
49,50,52 RUNPW ROK 7 5 1D8V_VIN PG5105
POK VIN#5 +1.8V_RUN_P
VIN#9 9 1 2
PR5102
22,37,42,50,52,77,86 PM_SLP_S3# 1 21D8V_RUN_EN 8 EN VOUT#3 3 Do Not Stuff

SC22U6D3V5MX-2GP
VOUT#4 4

SC68P50V2JN-1GP

PC5106

PC5107

Do Not Stuff
2K2R2J-2-GP

1
PC5108
PR5104
1 2 2
DY
DY

GND
37,87 1.8_GFX_ON FB

15KR2F-GP

2
PR5103

5912_1.8V_RUN_FB
APL5930KAI-TRG-GP

2
Do Not Stuff SO-8-P
C C

1
Do Not Stuff

PC5105
DY

2
Vout=0.8V*(R1+R2)/R2

1
PR5105
12KR2F-L-GP

2009/07/30

2
B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

APL5930_+1.8V_RUN
Size Document Number Rev
A3
DW Calpella X00
Date: Tuesday, September 08, 2009 Sheet 51 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p05v

+PW R_SRC +PW R_SRC_1D05V

D PG5214 D
2 1

Do Not Stuff
PG5215
2 1

Do Not Stuff
PG5216
2 1

Do Not Stuff
PG5217
2 1

Do Not Stuff

+PW R_SRC_1D05V
+5V_ALW

PC5220
SC10U25V6KX-1GP

PC5217
SC10U25V6KX-1GP

PC5213
SCD1U50V3KX-GP
C C

Do Not Stuff
PC5215
1

1
1

CFD CFD CFD DY

1

PR5220

2
PC5216 CFD CFD 300R3-GP

5
6
7
8
SC1U10V3KX-3GP
2

D
D
D
D
PU5202
2

SIS412DN-T1-GE3-GP
CFD
1

DIS(Clarksfield)
+5V_ALW CFD PC5222 PR5215
SC1U10V3KX-3GP Design Current = 8.84A

G
S
S
S
0R3J-0-U-GP
2

2 CFD 1 +1.05V_LL1 2 PC5221

1 CFD 12.16A<OCP<14.36A

4
3
2
1
A

SCD1U25V3KX-GP
PD5201 PU5201
CFD B0530W S-7-F-GP +1.05V_V5FILT 4 13 +1.05V_DRVH
V5FILT DRVH +1.05V_DRVL +1.05V_PCH
10 V5DRV DRVL 9
PL5201
K

+1.05V_VFB 5 12 +1.05V_LL 1 CFD 2

VFB LL

PC5219
SCD1U10V2KX-4GP
K CFD A +1.05V_VBST 14 CFD IND-2D2UH-46-GP-U
VBST

1
PD5202 SDMK0340L-7-F-GP 3 +1.05V_VOUT PTC5201
VOUT

5
6
7
8

1
Do Not Stuff
6 2009/07/30 SE220U2VDM-8GP
PGOOD RUNPW ROK 49,50,51

D
D
D
D
PR5213 1 CFD 2 100KR2J-1-GP +1.05V_EN 1 7 PU5203 PR5222 PG5229 CFD CFD
22,37,42,50,51,77,86 PM_SLP_S3# EN_PSV GND DY

1
2009/08/26 +1.05V_TON 2 8 SI7716ADN-T1-GE3-GP Do Not Stuff

2
PR5218 TON PGND
1 CFD 2 255KR2F-GP +1.05V_TRIP 11 15 PR5219 1 2 +3.3V_RUN CFD

2
TRIP GND 100KR2J-1-GP
PC5223

2009/08/16
SCD01U50V2KX-1GP

1
+PWR_SRC_1D05V

PR5217 TPS51117RGYR-GP
PR5211

+1.05V_LL_R

2
1

G
S
S
S
1 2 PR5216
DY
17K4R2F-GP

B RT: Non_ASM Do Not Stuff B

CFD CFD DY

4
3
2
1
TI: ASM Do Not Stuff
2

2 +5V_RUN
2

+1.05V_LL 3

1
+1.05V_VOUT
1 PM_SLP_S3# PC5214 Vout=0.75V*(R1+R2)/R2

1
2009/08/26 PD5203 Do Not Stuff PR5221
DY

1
BAW 56-2-GP 12KR2F-L-GP
CFD PC5218
DY Do Not Stuff

2
RT: Non_ASM TI: Non_ASM

2
TI: ASM RT :ASM +1.05V_VFB
TI: Non_ASM

1
RT :ASM PR5214
30KR2F-GP
CFD

2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
ASM Non_ASM Inductor:2.2UH PCMC063T-2R2MN Cyntec DCR:20mohm Isat =14Arms 68.2R210.20B
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
TI PR5218, PR5211 PR5217, PR5216 H/S: SIS412DN/ 24mohm/[email protected]/ 84.00412.037
L/S: SI7716ADN/ 13.5mOhm/[email protected]/ 84.07716.037
A RT PR5217, PR5216 PR5218, PR5211 Switching freq-->320KHz UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DC to DC 1.05V
Size Document Number Rev
A3
DW Calpella (Clarksfield) SA
Date: Tuesday, September 08, 2009 Sheet 52 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.GFX.Regulator

+PWR_SRC +PWR_SRC_CPU_GFXCORE +5V_ALW

PG5302 PR5302 1 2 0R2J-2-GP 3211_VID6

13 GFX_VID6
1 2
D PR5303 1 3211_VID5 D
13 GFX_VID5 2 0R2J-2-GP
Do Not Stuff +CPU_GFXCORE_P +CPU_GFXCORE
PG5303 PR5304 1 2 0R2J-2-GP 3211_VID4
13 GFX_VID4
1 2 PG5304

1
PR5305 1 2 0R2J-2-GP 3211_VID3 1 2
13 GFX_VID3
Do Not Stuff
PG5305 PR5307 1 2 0R2J-2-GP 3211_VID2 PR5306 Do Not Stuff
13 GFX_VID2 10R3J-3-GP
1 2 PG5306
PR5308 1 2 0R2J-2-GP 3211_VID1 1 2
13 GFX_VID1

2
Do Not Stuff
PG5307 PR5309 1 2 0R2J-2-GP 3211_VID0 Do Not Stuff
13 GFX_VID0 +PWR_SRC_CPU_GFXCORE
1 2 PG5301
PR5301 1 2 Do Not Stuff
Do Not Stuff
+1.05V_VTT DY 1 2

PG5309 1 2 3211_GFX_VR_EN Do Not Stuff

13 GFX_VR_EN
PR5310 0R2J-2-GP

SC1U10V2KX-1GP
1 2 PG5308

1
1 2
Do Not Stuff +1.05V_VTT PR5311

1
4K7R2J-2-GP PU5302 PC5305 PC5303 PC5304 PC5306 Do Not Stuff

5
6
7
8

1
SI7686DP-T1-GP
PC5301 PG5310

D
D
D
D

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD01U25V2KX-3GP
1 2

2
PR5312

2
+3.3V_ALW UMA Do Not Stuff
DY Do Not Stuff
GND_3211_I PG5311
GND_3211_I Thermal Design Current = 12A 1 2

G
S
S
S
Max. Current = 22A

32
31
30
29
28
27
26
25
13 GFX_IMON PR5313 PU5301 Do Not Stuff
24.2A<OCP<28.6A

4
3
2
1
1

10KR2J-3-GP PG5312

VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
PR5314 1 2
5K9R2F-GP PC5307 PC5308

1
SC68P50V2JN-1GP SCD22U16V3KX-2-GP Do Not Stuff
3211_PWRGD 1 24 3211_VCC +CPU_GFXCORE_P PG5313
2

PWRGD VCC 3211_BST PR5315

2009/08/05 1 2 2 23 1 2 1R3J-L1-GP 3211_BST_1 1 2 PL5301 1 2
IMON BST 3211_DRVH 3211_DRVH
3 22
3211_FBRTN CLKEN# DRVH 3211_SW Do Not Stuff
4 21 1 2
3211_FB FBRTN SW IND-D56UH-12-GP
5 20 +5V_ALW PG5314
C 3211_COMP FB PVCC 3211_DRVL C
6 19 1 2
COMP DRVL

SC3D3U10V5KX-2GP
7 18
SC47P50V2JN-3GP

+5V_ALW GPU PGND

1
1 23211_ILIM 8 17 PR5317 Do Not Stuff
SC220P50V2JN-3GP

ILIM GND

Do Not Stuff
1

5
6
7
8
33 PU5303 PG5315

CSCOMP
GND
1

1
Do Not Stuff

Do Not Stuff
D
D
D
D
SIR460DP-T1-GE3-GP
PR5316 9K09R2F-GP PC5310 PTC5302 PTC5301 PC5312 PC5313 1 2
DY

CSREF
RAMP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
LLINE

CSFB
PC5309 PC5311 PG5323 PG5324

IREF
RPM

1
2009/08/05 Do Not Stuff

SCD01U25V2KX-3GP
RT
2

13211_SW_GND 2

SC1U10V2KX-1GP
PG5316
PR5318 PC5314 20KR2F-L-GP 3211_CSCOMP GND_3211_I 1 2

9
10
11
12
13
14
15
16

S
S
S
23211_PC53141 ADP3211MNR2G-GP

G
1 2 1 2

2
Do Not Stuff

4
3
2
1
1KR2F-3-GP PR5319 1 2 3211_IREF PG5317

Do Not Stuff
SC470P50V2KX-3GP PR5320 80K6R2F-GP 1 2

3211_CSCOMP
1 2 3211_RPM

3211_CSREF
3211_RAMP
3211_LLINE

3211_CSFB
PR5322 237KR2F-GP PC5315 Do Not Stuff
1 2 3211_RT PG5318
PR5323 340KR2F-1-GP 3211_DRVL
DY 1 2

2
2009/08/05 Do Not Stuff
SC1KP50V2KX-1GP

GND_3211_I PG5321
1

PC5316 1 2

Do Not Stuff
2

+PWR_SRC_CPU_GFXCORE 2 13211_RAMP_1 1 2
PR5325 422KR2F-1-GP
PR5326 PR5327 PR5328
PR5324
1KR2F-3-GP 1 2 3211_CSCOMP_1 1 2 1 2 3211_SW_L
1

GND_3211_I PC5317 110KR2F-GP

SC1000P100V3KX-GP PC5318 PC5319 178KR3F-GP 64K9R2F-1-GP
2

SC270P50V2KX-1GP

SC1KP50V2KX-1GP
PR5330
2009/08/05
3211_FB_1

1
NTC-220K-2-GP
Do Not Stuff
1

GND_3211_I 1 2
DY
2

B B
PR5329
2

PR5335
2009/08/05
1

1 2 +CPU_GFXCORE
0R2J-2-GP

100R2F-L1-GP-U
2009/08/20 PR5333
2

PR5331 1 2 0R2J-2-GP
3211_CSCOMP

VCC_AXG_SENSE 13
1

PC5320
SC1KP50V2KX-1GP
PR5332 1 2 0R2J-2-GP VSS_AXG_SENSE 13
2

GND_3211_I

PR5336
1 2

100R2F-L1-GP-U
2009/08/20

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

PG5325 Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
1 2 O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
A H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037 A
Do Not Stuff L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
GND_3211_I
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ADP3211 CPU_GFXCORE
Size Document Number Rev
Custom DW Calpella UMA X00
Date: Tuesday, September 08, 2009 Sheet 53 of 90
5 4 3 2 1
 +3.3V_RUN +3.3V_RUN_GPU
SSID = VIDEO Close PCH Close GPU

2
1

2
1
RN5404
SRN2K2J-1-GP
RN5409
SRN2K2J-1-GP
DIS SSID = Inverter

3
4

3
4
20 L_DDC_DATA 81 LDDC_DATA
20 L_DDC_CLK 81 LDDC_CLK

UMA/DIS LVDS DDC CLK/DAT select circuit INVERTER POWER

R5409 1 UMA 2 0R2J-2-GP
+3.3V_RUN
U5444 +PWR_SRC_GFX +PWR_SRC

3 4 LDDC_DATA_CON
81 LDDC_DATA B0 A
2 5 2 1 F5401
GND VCC EDID_SELECT# POLYSW-1D1A24V-1-GP
20 L_DDC_DATA 1 6
B1 S

2
DIS C5407
DISSCD1U10V2KX-4GP C5401 C5405
NC7SB3157P6X-1GP SC1KP50V2KX-1GP SCD1U50V3KX-GP

1
73.03157.C0H
23,55,57 EDID_SELECT# EDID_SELECT# LDDC_DATA_CON
LDDC_CLK_CON
H=>B1 -iGPU PCH (UMA) R5411 1 UMA 2 0R2J-2-GP

1
+3.3V_RUN
L=>B0 -dGPU GPU (DIS) U5445
DY DY EV @ LVDS side

2
3 4 LDDC_CLK_CON
81 LDDC_CLK B0 A
2 GND VCC 5
1 6 EDID_SELECT#
20 L_DDC_CLK B1 S

1
DIS C5414 C5415

NC7SB3157P6X-1GP
DIS
C5408
SC22P50V2JN-4GP SC22P50V2JN-4GP SSID = VIDEO

2
73.03157.C0H SCD1U10V2KX-4GP

LVDS CONNECTOR +LCDVDD

LCD1 +PWR_SRC_GFX +LCDVDD

SCD1U10V2KX-4GP

48

1
41 50 C5403 C5406
1

C5402

1 SC10U6D3V5KX-1GP SCD1U10V2KX-4GP
+3.3V_RUN
LCD POWER

2
2
2

3
1

42
5
6
DYR5410
10KR2J-3-GP
7 R5404 33R2J-2-GP
8 +3.3V_EEPROM 1 2 +3.3V_RUN
2

9 LCD_BRIGHTNESS LCD_BRIGHTNESS +3.3V_RUN

10
11 BLON_OUT_R R5406
1 2100R2J-2-GP BLON_OUT 37
12 LCD_TST Q5401
43 13 LDDC_CLK_CON
LCD_TST 37
UMA/DIS LVDS PWM select circuit 1 D D 6 +LCDVDD
14 LDDC_DATA_CON 2 D D 5
15 LCD_DET_G 1 2 2009/07/27 3 G S 4
16 Added LCD brightness control by EC.

1
17 VGA_TXBOUT0- R5408 2 1 SI3456BDV-T1-GP
VGA_TXBOUT0- 74 2009/07/29 +15V_ALW
18 VGA_TXBOUT0+ VGA_TXBOUT0+ 74 100R2J-2-GP R5402 330KR2J-L1-GP R5401
19 Removed LCD brightness control,Combine EC and GPU 1 2 FPVCC_CTL1 120R3J-2-GP
44 20 VGA_TXBOUT1- VGA_TXBOUT1- 74 +3.3V_RUN C5404 SCD1U50V3KX-GP
21 VGA_TXBOUT1+
VGA_TXBOUT1+ 74

2
22 R5438 1 2 LCD_BRESS 1 2
23 VGA_TXBOUT2-
VGA_TXBOUT2- 74
37 LBKLT_CTL_EC
0R2J-2-GP DY R5403 DY Do Not Stuff
Q5402

1
24 VGA_TXBOUT2+ U5448 C5409
VGA_TXBOUT2+ 74
25 DISSCD1U10V2KX-4GP 4 3 LCDVDD_1
26 VGA_TXBCLK- R5439 1 DIS 2 0R2J-2-GP 3 4 LCD_BRIGHTNESS
VGA_TXBCLK- 74 81 LBKLT_CTL_GPU

2
VGA_TXBCLK+ B0 A
45 27 VGA_TXBCLK+ 74 2
GND VCC
5 5 2
28 20 LBKLT_CTL_PCH 1
B1 S
6
29 VGA_TXAOUT0- DIS 6 1
VGA_TXAOUT0- 74 DGPU_PWM_SELECT# 21
30 VGA_TXAOUT0+
VGA_TXAOUT0+ 74 2009/07/28
31 NC7SB3157P6X-1GP H=>B1 -iGPU PCH (UMA)
VGA_TXAOUT1- Change 2N7002 ESD pretect from standard to 1KV type DMN66D0LDW-7-GP
32
VGA_TXAOUT1+
VGA_TXAOUT1- 74 73.03157.C0H L=>B0 -dGPU GPU (DIS) P/N:84.2N702.E31
33 VGA_TXAOUT1+ 74
46 34
35 VGA_TXAOUT2- 1 2
VGA_TXAOUT2- 74 +3.3V_ALW
36 VGA_TXAOUT2+ LBKLT_CTL_EC R5412 1 UMA 2 0R2J-2-GP R5405 47KR2J-2-GP
VGA_TXAOUT2+ 74
37 LBKLT_CTL_PCH R5413 1 UMA 2 0R2J-2-GP LCD_BRIGHTNESS 1
37 SHBM_LCDTST_EN
38 VGA_TXACLK-
VGA_TXACLK- 74 3 OUT FPVCC_CTL3
39 VGA_TXACLK+ 3 ENVDD_D 2 R1
VGA_TXACLK+ 74
40 LCD_CBL_DET# IN 1 GND
LCD_CBL_DET# 25 LVDVDD_EN 2 R2
47 51
Q5403
49 D5402 DDTC144EUA-7F-GP
BAT54C-7-F-GP
IPEX-CONN40-2R-GP
20.F1093.040
+3.3V_RUN
R5414 1 UMA 2 0R2J-2-GP
LCD_BRIGHTNESS BLON_OUT_R
U5446

1
LCD_TST C5410
1
SC33P50V2JN-3GP

SC33P50V2JN-3GP

3 4 LVDVDD_EN DISSCD1U10V2KX-4GP
81 LCDVDD_EN_GPU B0 A
EC5402

EC5401

R5407 2 5

2
GND VCC
1

10KR2J-3-GP 20 LCDVDD_EN_PCH 1 6
B1 S
DIS DGPU_SELECT#
DY DY DGPU_SELECT# 21,74
2

NC7SB3157P6X-1GP
73.03157.C0H

H=>B1 -iGPU PCH (UMA) UMA

For EMI request L=>B0 -dGPU GPU (DIS)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

LCD/Inverter Connector Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 54 of 90
 5 4 3 2 1

SSID = VIDEO +5V_CRT_RUN

D5504
+5V_RUN

B0530W S-7-F-GP
K A

1
C5510
SCD01U16V2KX-3GP

2
CRT1
L5502 16
74 M_RED 1 2 CRT_R
D BLM18BA220SN1D-GP 6 D
CRT_R 1 11
L5501
74 M_GREEN 1 2 CRT_G 7
BLM18BA220SN1D-GP CRT_G 2 12 DDC_DATA_CON
8
L5503 +5V_CRT_RUN CRT_B 3 13 JVGA_HS JVGA_HS 74
74 M_BLUE 1 2 CRT_B 9
BLM18BA220SN1D-GP 4 14 JVGA_VS JVGA_VS 74
1

C5509
SC8P250V2CC-GP

C5507
SC8P250V2CC-GP

C5512
SC8P250V2CC-GP

C5508
SC8P250V2CC-GP

C5501
SC8P250V2CC-GP

C5506
SC8P250V2CC-GP
10

1
R5502
150R2F-1-GP

R5501
150R2F-1-GP

R5503
150R2F-1-GP
5 15 DDC_CLK_CON
DY DY DY

1
AFTP5502 1 17

2
2

2
VIDEO-15-127-GP-U
DYDY

2
20.20401.015
C5502 C5504
Layout Note: SC33P50V2JN-3GP SC33P50V2JN-3GP

CRT_R CRT_G CRT_B *Pi-filter & 150 Ohm pull-down AFTP5503 1 +5V_CRT_RUN
3

3
AFTP5501 1 DDC_DATA_CON
D5501 D5502 D5503
resistors should be as close AFTP5509 DDC_CLK_CON
1
as to CRT CONN. AFTP5507 1 CRT_R
DY BAV99-4-GP
DY BAV99-4-GP
DY BAV99-4-GP
* RGB signal will hit 75 Ohm AFTP5506 1 CRT_G
AFTP5508 1 CRT_B
C +3.3V_RUN +3.3V_RUN +3.3V_RUN first, then pi-filter, finally AFTP5504 1 JVGA_HS C
1

2
CRT CONN. AFTP5505 1 JVGA_VS

+3.3V_RUN +3.3V_RUN_GPU +5V_CRT_RUN

Close PCH Close GPU
2
1

2
1

2
1
RN5510 RN5511 DIS RN5513
SRN2K2J-1-GP SRN2K2J-1-GP SRN2K2J-1-GP
3
4

3
4

3
4
B B

20 GMCH_DDCDATA 81 CRT_DAT_DDC
DDC_DATA_CON
20 GMCH_DDCCLK 81 CRT_CLK_DDC
DDC_CLK_CON
UMA/DIS CRT DDC CLK/DAT select circuit

1
DY DY
R5504 1 UMA 2 0R2J-2-GP

2
+3.3V_RUN
U5542

3 4 DDC_DATA_CON2 C5519 C5520

SCD1U10V2KX-4GP

81 CRT_DAT_DDC B0 A
2 5 SC22P50V2JN-4GP SC22P50V2JN-4GP
GND VCC EDID_SELECT#
20 GMCH_DDCDATA 1 B1 S 6 5V @ CRT side
1

C5503

DIS +3.3V_RUN

NC7SB3157P6X-1GP
DIS
2

73.03157.C0H
23,54,57 EDID_SELECT# EDID_SELECT#
Q5517
H=>B1 -iGPU PCH (UMA) R5505 1 UMA 2 0R2J-2-GP DDC_DATA_CON2 4 3 DDC_DATA_CON
+3.3V_RUN
L=>B0 -dGPU GPU (DIS) U5543
5 2

3 4 DDC_CLK_CON2 6 1
SCD1U10V2KX-4GP

81 CRT_CLK_DDC B0 A 2009/07/28
2 GND VCC 5
EDID_SELECT# Change 2N7002 ESD pretect from standard to 1KV type
A 20 GMCH_DDCCLK 1 B1 S 6 DMN66D0LDW -7-GP P/N:84.2N702.E31 UMA A
1

C5505

DIS
NC7SB3157P6X-1GP
DIS DDC_CLK_CON2
Wistron Corporation
2

73.03157.C0H DDC_CLK_CON
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

CRT Connector Rev
A3 SA
Vostro Calpella
Date: Tuesday, September 08, 2009 Sheet 55 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 56 of 90
5 4 3 2 1
 5 4 3 2 1

HDMI1
HDMI_HP_DET_CON

3
R5708 R5702
0R3J-0-U-GP 0R3J-0-U-GP D5705 23
1 2 1 2 +5V_RUN
DY BAV99-4-GP
21
HDMI_TXD#1_C HDMI_TXD#0_C Close HDMI Connect
75 HDMI_TXD#1 75 HDMI_TXD#0
+5V_RUN HDMI_HP_DET_CON 19

2
18

4
17
HDMI_SDATA_CON 16
HDMI_SCLK_CON 15
L5702 L5706 14
D
DY Do Not Stuff
DY Do Not Stuff 13 D
HDMI_TX#C_C 12
11
HDMI_TXC_C 10
HDMI_TXD#0_C 9

3
8
HDMI_TXD1_C HDMI_TXD0_C HDMI_TXD0_C 7
75 HDMI_TXD1 75 HDMI_TXD0
HDMI_TXD#1_C 6
1 2 1 2 5
HDMI_TXD1_C 4
R5703 R5705 HDMI_TXD#2_C 3
0R3J-0-U-GP 0R3J-0-U-GP 2

R5707 R5711 HDMI_TXD2_C 1

0R3J-0-U-GP 0R3J-0-U-GP
1 2 1 2 20

HDMI_TXD#2_C HDMI_TX#C_C 22
75 HDMI_TXD#2 75 HDMI_TX#C
1

4
SKT-HDMI19P-25-GP

L5704 L5703
DY Do Not Stuff
DY Do Not Stuff +3.3V_RUN_GPU 22.10296.061

2
HDMI level shift circuit
2

3
C R5718 C

75 HDMI_TXD2
HDMI_TXD2_C
75 HDMI_TXC
HDMI_TXC_C DY10KR2J-3-GP +5V_RUN
1 2 1 2

1
R5706 R5712 R5716
0R3J-0-U-GP 0R3J-0-U-GP +5V_RUN
Q5702
DIS20KR2J-L2-GP

D
2N7002A-7-GP

2
1
1
D5704 D5703
RB751V-40-1-GP RB751V-40-1-GP DY G HDMI_HP_DET_R#

2+5V_HDMI_C
2
1+5V_HDMI 2
+3.3V_RUN

S
+3.3V_RUN +3.3V_RUN_GPU
Close PCH Close GPU
2
1

1
2

2
3

1
R5717
RN5714 RN5715 DIS 10KR2J-3-GP
SRN2K2J-1-GP SRN2K2J-1-GP DIS RN5711 Q5703 DIS
SRN2K2J-1-GP DMN66D0LDW -7-GP

1
3
4

4
3

6
3
4
20,75 SDVO_DAT 81 HDMI_SDATA_DDC
75 HDMI_HP_DET_CON HDMI_HP_DET_CON HDMI_HPD_3D3_CON
20,75 SDVO_CLK 81 HDMI_SCLK_DDC
HDMI_SDATA_CON
B HDMI_SCLK_CON B

UMA/DIS HDMI DDC CLK/DAT select circuit

1

+3.3V_RUN DY DY UMA/DIS HDMI Detection select circuit

U5746
2

U5749 +5V_RUN
3 4 HDMI_SDATA_CON_L
81 HDMI_SDATA_DDC B0 A
2 5 C5721 C5722 81 HDMI_HP_DET_VGA 3 4 HDMI_HPD_3D3_CON
GND VCC EDID_SELECT# SC22P50V2JN-4GP SC22P50V2JN-4GP B0 A
20,75 SDVO_DAT 1 B1 DIS S 6 2 GND VCC 5
1

C5701 20,21,75 HDMI_HP_DET 1 6 EDID_SELECT# 23,54,55

B1 S
DISSCD1U10V2KX-4GP 5V @ HDMI side DIS

1
NC7SB3157P6X-1GP C5703
2

2
73.03157.C0H NC7SB3157P6X-1GP DISSCD1U10V2KX-4GP
+3.3V_RUN R5745 R5746 73.03157.C0H

2
100KR2J-1-GPDIS100KR2J-1-GPUMA
23,54,55 EDID_SELECT# EDID_SELECT# R5722 H=>B1 -iGPU PCH (UMA)
0R2J-2-GP
Close GPU Close PCH L=>B0 -dGPU GPU (DIS)

1
+3.3V_RUN 1 2
U5747 Q5720 DY
HDMI_SDATA_CON_L 4 3 HDMI_SDATA_CON
HDMI_SDATA_CON 75
3 4 HDMI_SCLK_CON_L
81 HDMI_SCLK_DDC B0 A
2 GND VCC 5
EDID_SELECT#
5 DIS 2
20,75 SDVO_CLK 1 B1 DIS S 6
1

C5702 6 1
2009/07/28
NC7SB3157P6X-1GP
DISSCD1U10V2KX-4GP Change 2N7002 ESD pretect from standard to 1KV type
2

DMN66D0LDW -7-GP P/N:84.2N702.E31

73.03157.C0H
A UMA A
HDMI_SCLK_CON_L
H=>B1 -iGPU PCH (UMA) HDMI_SCLK_CON
HDMI_SCLK_CON 75
L=>B0 -dGPU GPU (DIS) Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

HDMI Connector Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 57 of 90
5 4 3 2 1
 5 4 3 2 1

D D

SSID = Thermal

C AFTP5803 1 EMC2102_FAN_TACH_1
Fan Connector C

AFTP5802 1 EMC2102_FAN_DRIVE

FAN1
5
39 EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 3
2

39 EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 1
AFTP5801 1 4
*Layout* 15 mil

K
FOX-CON3-6-GP-U

1
D5801 20.D0210.103
C5801 SDMK0340L-7-F-GP
SC22U6D3V5MX-2GP

A
B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

58_FAN Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 58 of 90
5 4 3 2 1
SSID = SATA SSID = SATA

ODD Connector SATA HDD Connector

HDD1
SATA HDD Interface comment
23
******************************
NP1 --- GND
ODD1 S1
C5906 1
RX+
8 24 SATA_ITXP0_HRXP0_C 2SCD01U50V2KX-1GP
NP1 SATA_ITXP0_HRXP0 S2 RX-
24 SATA_ITXN0_HRXN0_C C5908 1 2 SATA_ITXN0_HRXN0 S3 --- GND
S1 SCD01U50V2KX-1GP S4
C5913 1 2SCD01U50V2KX-1GP SATA_IRXN0_HTXN0 S5 TX-
24 SATA_IRXN0_HTXN0_C
24 SATA_ITXP1_ORXP1_C C5905 1 2 SCD01U50V2KX-1GP SATA_ITXP1_ORXP1 S2 SATA_IRXP0_HTXP0 S6 TX+
C5904 1 2 SCD01U50V2KX-1GP SATA_ITXN1_ORXN1 S3 1 2 S7
24 SATA_ITXN1_ORXN1_C 24 SATA_IRXP0_HTXP0_C
C5914 SCD01U50V2KX-1GP
--- GND
S4
24 SATA_IRXN1_OTXN1_C C5911 2 1 SCD01U50V2KX-1GP SATA_IRXN1_OTXN1 S5 +3.3V_RUN 1 ******************************
24 SATA_IRXP1_OTXP1_C C5912 2 1 SCD01U50V2KX-1GP SATA_IRXP1_OTXP1 S6 2 ------------ 3.3V
S7 3
4
------------ 3.3V
SATA_RX- and SATA_RX+ Trace +5V_RUN 5 ------------ 3.3V
P1 6 --- GND
Length match within 20 mil P2 7
+5V_RUN
P3 8 --- GND / Dell Detected Pin
1

P4 9 --- GND
P5 10
P6 FFS_INT2 11
------------ 5V
40 FFS_INT2
2

NP2 12 ------------ 5V
9 13 ------------ 5V
C5915 C5909 14
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP SKT-SATA7P+6P-51-GP 15 --- GND
NP2
62.10065.671 24
(Dell: FFS_INT for supported HDD)
--- GND
SKT-SATA22P-65-GP
------------ 12V
------------ 12V
62.10065.B81 ------------ 12V
******************************
Close to CONN Close to CONN
5V power pin 3.3V power pin

+5V_RUN +3.3V_RUN

C5903

C5907

C5902

C5901
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
DY DY
2

2
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDD/ODD Connector
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 59 of 90
 5 4 3 2 1

SSID = AUDIO

D D

AFTP6004 1 AUD_SPK_L-_C
AFTP6002 1 AUD_SPK_L+_C
AFTP6001 1 AUD_SPK_R-_C

C
Speaker Connector AFTP6003 1 AUD_SPK_R+_C

SPK1
5
AUD_SPK_L- R6006 1 2 0R3J-0-U-GP AUD_SPK_L-_C 1
30 AUD_SPK_L-
AUD_SPK_L+ R6007 1 2 0R3J-0-U-GP AUD_SPK_L+_C 2
30 AUD_SPK_L+ AUD_SPK_R- R6001 1
30 AUD_SPK_R- 2 0R3J-0-U-GP AUD_SPK_R-_C 3
AUD_SPK_R+ R6002 1 2 0R3J-0-U-GP AUD_SPK_R+_C 4
30 AUD_SPK_R+
6

ACES-CON4-7-GP-U
MLVG0402220NV05-GP

MLVG0402220NV05-GP

MLVG0402220NV05-GP

MLVG0402220NV05-GP
1

1
20.F0772.004
EC6003

EC6008

EC6006

EC6007
DY
2
DY DY DY AFTP6005 1

2
B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Speaker/HP/MIC Jack
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 60 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 61 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM SSID = RBATT

D D

SPI FLASH ROM (256K Bytes) for KBC

RN6201
SRN100KJ-6-GP
KBC_PW R 4 1 EC_SPI_CS#
3 2 EC_SPI_HOLD# KBC_PW R

RTC Connector

1
DY

2
+3.3V_RTC_LDO
KBC_PW R C6201 C6203 C6204
C SC10U6D3V5MX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP C
1

+RTC_CELL D6201
R6201 1
100KR2J-1-GP +RTC_VCC
3 RTC1
R6202 3
2

U6203 KBC_PW R 2 RTC_PW R 1 2 1

1
37 EC_SPI_CS# EC_SPI_CS# 1 8 C6202 BAT54CW -1-GP 1KR2J-1-GP 2
R6205 1 CS# VCC
37 EC_SPI_DI 2 0R2J-2-GP SPI_DO 2 7 EC_SPI_HOLD# SC1U10V3KX-3GP 4

2
R6204 1 SO HOLD#
37 EC_SPI_W P#_R 2 0R2J-2-GP EC_SPI_W P# 3 WP# SCK 6 EC_SPI_CLK 37 AFTP6202 1
4 5 SPI_DIO 37 FOX-CON2-17-GP
GND SI
Width=20mils 20.D0210.102
1

1
EC6202
DY SC4D7P50V2CN-1GP AT25DF021-SSH-T-GP DY DY
2

EC6201 EC6203
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
AFTP6201 1 +RTC_VCC

B B

SPI FLASH ROM (4M Bytes) for PCH

RN6202 +3.3V_RUN
SRN4K7J-8-GP
+3.3V_RUN 1 4 PCH_SPI_W P#
2 3 PCH_SPI_HOLD_0#
1

C6205 DY C6206
SC10U6D3V5MX-3GP SCD1U16V2KX-3GP
2

+3.3V_RUN
1

R6207
4K7R2J-2-GP U6202 +3.3V_RUN
2

24 PCH_SPI_CS0# 1 CS# VCC 8

24 PCH_SPI_DI 1 2 PCH_SPI_DI_R 2 7 PCH_SPI_HOLD_0#
PCH_SPI_W P# SO HOLD#
3 WP# SCK 6 PCH_SPI_CLK 24
R6206 4 5 PCH_SPI_DO 24
15R2J-GP GND SI
A UMA A
1

EC6205
1

SC4D7P50V2CN-1GP AT25DF321-SU-GP
DY DY DY
Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

EC6204 EC6206 Title

SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
EEPROM/RTC Connector
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 62 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = USB
+5V_USB1

USB Power +5V_USB1 USB2

D6305 1
+5V_ALW U6303 +5V_USB1 USB_P2- USB_PWR
1 4 2
USB_P2+ USB-
3
USB+
at least 80 mil 1
GND OC1#
8 at least 80 mil DY 4
GND
2 7 5
IN OUT1 GND
3 6 6

1
EN1# OUT2 GND
C6302
SCD1U10V2KX-4GP

R6307
100KR2J-1-GP

C6306
SCD1U10V2KX-4GP

C6305
SC1U10V3KX-3GP

TC6303
ST100U6D3VBML1GP
4 5 7

1
37,76 USB_PWR_EN# EN2# OC2# NC#7
8
1

USB_P2- USB_P2+ NC#8

TPS2062AD-GP DY 2 3

2
PRTR5V0U2X-GP AFTP6317 1 USB_P2- SKT-USB-115-GP-U1
D
DY D
2

2
AFTP6316 1 USB_P2+ 22.10218.K01
USB_OC#2_3 21 AFTP6321 +5V_USB1
1
AFTP6320 1 GND

+5V_USB1

USB3

1
USB_P3- USB_PWR
2
R6302 R6303 USB_P3+ USB-
3
USB+
1 2 1 2 4
+5V_USB1 GND
5
USB_PP2 0R3J-0-U-GP USB_P2+ USB_PP3 0R3J-0-U-GP USB_P3+ GND
21 USB_PP2 21 USB_PP3 6
D6304 GND
7
NC#7
1 4 8
1

2
NC#8
AFTP6315 USB_P3-
TR6304 TR6305 DY AFTP6314
1
1 USB_P3+ SKT-USB-115-GP-U1
DY L-63UH-GP L-63UH-GP AFTP6318 1 +5V_USB1 22.10218.K01
DY AFTP6319 1 GND

USB_P3- 2 3 USB_P3+
4

3
21 USB_PN2 USB_PN2 USB_P2- 21 USB_PN3 USB_PN3 USB_P3- PRTR5V0U2X-GP
R6308 R6309
1 2 1 2

0R3J-0-U-GP 0R3J-0-U-GP

C
ESATA Power C

+5V_ALW U6302 +5V_USB2 R6301 +5V_USB2

1 2
at least 80 mil 1 8 at least 80 mil USBESATA1
GND OC1# USB_PN4 0R3J-0-U-GP USB_P4-
2 7 21 USB_PN4 1
IN OUT1 VBUS
3 6
1

EN1# OUT2
C6301
SCD1U10V2KX-4GP

R6305
100KR2J-1-GP

C6303
SCD1U10V2KX-4GP

C6304
SC1U10V3KX-3GP

TC6302
ST100U6D3VBML1GP
4 5 4
1

3
37,76 USB_PWR_EN# EN2# OC2# SATA_ITX_DRX_P4 GND
6 5
1

SATA_ITX_DRX_N4 A+ GND
7 8
TPS2062AD-GP DY TR6301 A- GND
DY DY 11
2

2 L-63UH-GP SATA_IRX_DTX_P4 GND

10 12
2

SATA_IRX_DTX_N4 B+ GND
9 13
USB_OC#4_5 21 B- GND
14
USB_P4+ GND
3 15

2
USB_P4- D+ GND
2
USB_PP4 USB_P4+ D-
21 USB_PP4 AFTP6306
R6306 SKT-USB+SATA-GP-U

RN6301
1 2 22.10254.161 1

SRN0J-6-GP 0R3J-0-U-GP
+5V_USB2
ESATA_ITX_DRX_P4_C 2 3 ESATA_ITX_DRX_P4_C_R
ESATA_ITX_DRX_N4_C 1 4 ESATA_ITX_DRX_N4_C_R D6306
+3.3V_RUN +3.3V_RUN 1 4
+3.3V_RUN R6313
10R2J-2-GP
2 1 P412_EN
DY
DY
1

R6314 R6315 U6301

R6318
DY 4K7R2F-GP
DY 4K7R2F-GP
6 7 0R2J-2-GP USB_P4- 2 3 USB_P4+
VCC EN ESATA_ITX_DRX_P4_R
10 1
DY 2 1 2
2

VCC ESATA_ITX_DRX_P4_U C6311 SCD01U50V2KX-1GP PRTR5V0U2X-GP AFTP6308 +5V_USB2

20 15 1
D0 C6309 VCC TX_0P ESATA_ITX_DRX_N4_U 1 ESATA_ITX_DRX_N4_R AFTP6309 USB_P4-
16 14 2 1 2 1
D1 SCD01U50V2KX-1GP VCC TX_0N DYR6319 C6312 SCD01U50V2KX-1GP AFTP6302 1 USB_P4+
1 2 5 ESATA_IRX_DTX_P4 0R2J-2-GP 2 1
24 ESATA_ITX_DRX_P4_C DY DY ESATA_IRX_DTX_P4_C 24
1

ESATA_ITX_DRX_P4 1 TX_1P C6313 SCD01U16V2KX-3GP

4
R6316 R6317 SCD01U50V2KX-1GP ESATA_ITX_DRX_N4 2 RX_0P TX_1N ESATA_IRX_DTX_N4
1
24 ESATA_ITX_DRX_N4_C DY2 C6310 RX_0N C6314
2 1
DYSCD01U16V2KX-3GP
ESATA_IRX_DTX_N4_C 24
DY 0R2J-2-GPDY 0R2J-2-GP ESATA_IRX_DTX_P4_R C6315 2 1 R6320 2 1ESATA_IRX_DTX_P4_U R6304
B SCD01U50V2KX-1GP 0R2J-2-GP DY 11
12
RX_1P GND
3
13 ESATA_ITX_DRX_P4_R 1 2 SATA_ITX_DRX_P4 B
2

ESATA_IRX_DTX_N4_R C6316 RX_1N GND

2 1 2 1ESATA_IRX_DTX_N4_U
SCD01U50V2KX-1GP R6321 DY GND
17
18 0R3J-0-U-GP
0R2J-2-GP D0 GND
9 19
D1 D0 GND
8 21

2
+3.3V_RUN D1 GND

SN75LVCP412RTJR-GP
L-63UH-GP
DY TR6302
C6307

C6308

C6317
SC1U10V3KX-3GP
SCD1U10V2KX-4GP

SCD01U50V2KX-1GP
1

RN6302
DY DY DY

3
ESATA_IRX_DTX_N4_C_R 1 4 ESATA_IRX_DTX_N4_C
2

ESATA_IRX_DTX_P4_C_R 2 3 ESATA_IRX_DTX_P4_C
R6310
ESATA_ITX_DRX_N4_R 1 2 SATA_ITX_DRX_N4
SRN0J-6-GP
0R3J-0-U-GP

R6311
ESATA_IRX_DTX_N4_R 1 2 SATA_IRX_DTX_N4

0R3J-0-U-GP
If you added U6301(SN75LVCP412RTJR-GP).

2
You need to BOM change
TR6303
L-63UH-GP
R6313, R6314, R6315, R6318, R6319, R6320, R6321 DY
ASM C6309, C6310, C6313, C6314, C6307, C6308, C6317

3
R6312
ESATA_IRX_DTX_P4_R 1 2 SATA_IRX_DTX_P4
DY RN6301, RN6302 0R3J-0-U-GP

A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

USB /ESATA Port Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 63 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = Wireless

D D

Mini Card Connector(802.11a/b/g/n)

+1.5V_RUN +3.3V_RUN

W LAN1
53
NP1
1 2
+5V_ALW +3.3V_RUN 3 4
77 W LAN_ACT
77 BT_ACT 5 6
23 MINI1_CLKREQ# 7 8
1

9 10
C C6401 C6403 11 12 C
SCD1U16V2KX-3GP DY SCD1U16V2KX-3GP
23 CLK_PCIE_MINI1#
23 CLK_PCIE_MINI1 13 14
2

15 16

R6404 1 2 0R2J-2-GP E51_RXD_R 17 18

+3.3V_RUN +1.5V_RUN
37 E51_RXD
R6403 1 DY 2 0R2J-2-GP E51_TXD_R 19 20
37 E51_TXD DY 21 22 PLT_RST#
W IFI_RF_EN 37
PLT_RST# 9,21,37,70,76,77,80
23 24
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

23 PCIE_IRXN2_MTXN2 +3.3V_RUN
23 PCIE_IRXP2_MTXP2 25 26
1

1
C6405

C6402

C6404

C6406

27 28
29 30 PCH_SMBCLK
DY DY DY 23 PCIE_ITXN2_MRXN2 31 32 PCH_SMBDATA
PCH_SMBCLK 7,18,19,23,40
PCH_SMBDATA 7,18,19,23,40
2

23 PCIE_ITXP2_MRXP2 33 34
35 36 USB_P13-
37 38 USB_P13+
+3.3V_RUN 39 40
41 42
43 44 LED_W LAN_W IMAX_OUT# 66
W LAN_ACT 45 46
47 48
1

R6402 49 50
EC6401 1 2 +5V_MINI_DEBUG 51 52
SC220P50V2KX-3GP
+5V_ALW DY NP2
2

0R3J-0-U-GP 54

PTW O-CONN52A-4-GP-U
20.F1286.052
B R6406 B
0R3J-0-U-GP
USB_P13- 1 2 USB_PN13
2009/07/28 USB_PN13 21
Change connector to 20.F1286.052

3
DY
DLW 21SN900SQ2LUGP
L6401

2
USB_P13+ 1 2 USB_PP13
USB_PP13 21
R6405
0R3J-0-U-GP

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MINICARD(WLAN)/ITP CONN
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 64 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

WWAN Connector
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 65 of 90
5 4 3 2 1
 5 4 3 2 1

PWR BTN LED For LED & Capacity board

PW R_BTN_LED# 2 1PW R_BTN_LED_R# PW R_BTN_LED_R# 78
37 PW R_BTN_LED#
R6628 20KR2J-L2-GP
For LED & Capacity board:
LED Type Color Power rail SCRLK LED
D D
SCRL LED White ALW
SCR_LOCK_LED# 2 1 SCRL_LED_R# SCRL_LED_R# 78
37 SCR_LOCK_LED#
R6620 20KR2J-L2-GP
CAP LED White ALW

NUM LED White ALW CAPS LED

PWR BTN LED White ALW CAP_LOCK_LED# 2 1 CAP_LED_R# CAP_LED_R# 78
37 CAP_LOCK_LED#
R6621 20KR2J-L2-GP

SATA ACT LED1 White RUN

NUM LED
BT ACT LED White RUN
NUM_LOCK_LED# 2 1 NUM_LED_R# NUM_LED_R# 78
37 NUM_LOCK_LED#
WLAN WIMAX LED White RUN R6622 20KR2J-L2-GP

Bluetooth LED
77 BT_ACTIVE_K# 2 1 LED_BT_ACT_K_R# 78
R6623 20KR2J-L2-GP
C C

WLAN LED
For IO board: 64 LED_W LAN_W IMAX_OUT# 2 1 W LAN_W IMAX_LED_R# 78
R6624 20KR2J-L2-GP

LED Type Color Power rail

PWR LED2 White(Multi-color) ALW 2009/07/29

HD LED Update R6625 from 10k to 20k ohm +5V_RUN
For LED&Capacity board:
Amber(Multi-color) ALW Q6606
R2
BATTERY LED2 E R6626
2 1 SATA_ACT_C# B
24 SATA_LED# R1
White(Multi-color) ALW R6625 20KR2J-L2-GP C HDD_LED 1 2 SATA1_ACT_LED SATA1_ACT_LED 78
DDTA143ECA-7-F-GP
0R2J-2-GP

B B

2009/08/12
Power & Battery LED Changed battery LED be one LED with bi-color
(white and amber). For I/O board. Update Spec.

R6630
Orange For IO board
R6617
0R2J-2-GP Q6607
C BAT_O_LED 1 2 BATT_LED_ORANGE
BAT_O_LED_R R1 BATT_LED_ORANGE 77
37 BATT_ORANGE_LED 1 2 B
E 0R2J-2-GP
R2

PDTC124EU-1-GP

R6632
White
R6629
0R2J-2-GP Q6609
C BAT_W _LED 1 2 BATT_LED_W HITE
BAT_W _LED_R R1 BATT_LED_W HITE 77
37 BATT_W HITE_LED 1 2 B
E 0R2J-2-GP
R2

PDTC124EU-1-GP

A UMA A
White +5V_ALW
R6631 Q6608
20KR2J-L2-GP
R2
E R6619
Wistron Corporation
1 2 POW ER_LED_R# B 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
37 PW RLED# R1
Taipei Hsien 221, Taiwan, R.O.C.
C POW ER_LED_L 1 2 PW R2_LED
PW R2_LED 77
DDTA143ECA-7-F-GP Title
0R2J-2-GP
LED
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 66 of 90
5 4 3 2 1
 5 4 3 2 1

D D

(Blank)
C C

B B

A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 67 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = KBC SSID = Touch.Pad

Internal KeyBoard Connector

D D
KB1
31
1 KB_DET# KB_DET# 25

2 KROW7 1 AFTP6837
3 KROW6 1 AFTP6836
4 KROW4 1 AFTP6839
5 KROW2 1 AFTP6838
6 KROW5 1 AFTP6841 KROW[0..7] 37
7 KROW1 1 AFTP6840
8 KROW3 1 AFTP6842
9 KROW0 1 AFTP6843 KCOL[0..16] 37
10 KCOL5 1 AFTP6844
11 KCOL4 1 AFTP6845
12 KCOL7 1 AFTP6847 +5V_RUN +5V_RUN
13 KCOL6 1 AFTP6846
14 KCOL8 1 AFTP6849 EC6801 EC6802
15 KCOL3 1 AFTP6848 KROW7 1 8 KROW5 1 8
KCOL1 AFTP6851 KROW6 KROW1

SCD1U16V2KX-3GP
16 1 2 7 2 7

C6805
17 KCOL2 1 AFTP6850 KROW4 3 6 KROW3 3 6
DY DY

2
1

1
18 KCOL0 1 AFTP6853 KROW2 4 5 KROW0 4 5
19 KCOL12
KCOL16
1 AFTP6852
AFTP6855 SRC100P50V-2-GP SRC100P50V-2-GP RN6802
TouchPad Connector
20 1

2
21 KCOL15 1 AFTP6854 SRN10KJ-5-GP
22 KCOL13 1 AFTP6857 TPAD1
23 KCOL14 1 AFTP6856 5

3
4
24 KCOL9 1 AFTP6859 1
25 KCOL11 1 AFTP6858 EC6803 EC6804
C 26 KCOL10 1 AFTP6860 KCOL5 1 8 KCOL8 1 8 37 TPCLK 2 C
27 KCOL4 2 7 KCOL3 2 7 37 TPDATA 3 AFTP6835
28 KCOL7 3 6 KCOL1 3 6 4
DY DY

1
1
29 KCOL6 4 5 KCOL2 4 5 6 1
30 C6804 C6806
32 SRC100P50V-2-GP SRC100P50V-2-GP SC33P50V2JN-3GP SC33P50V2JN-3GP

2
2
PTWO-CON4-1-GP-U1
ACES-CON30-3-GP 20.K0265.004
20.K0421.030 EC6805 EC6806
KCOL0 1 8 KCOL13 1 8
KCOL12 2 7 KCOL14 2 7 AFTP6815 1 +5V_RUN
Change TouchPad Connector
KCOL16 3 6 KCOL9 3 6 AFTP6816 1 TPCLK 2009/07/17
KCOL15 4
DY 5 KCOL11 4
DY 5 AFTP6817 1 TPDATA

SRC100P50V-2-GP SRC100P50V-2-GP

SC100P50V2JN-3GP
EC6807
KCOL10 1 2
DY

Added KB1 EMI Cap

B
KB Backlight CONN 2009/06/17 B

Place near CON5

+5V_RUN +5V_RUN

CON5
C6802
SCD1U16V2KX-3GP

C6801
SC4D7U10V3KX-1-GP

5
1

R6815 1
1KR2J-1-GP DY
2

1 2CN7_P2 2
37 KB_BL_DET# KB_BL_DET# 3
KB_BL_CTRL# 4

6
D

ACES-CON4-10-GP-U
Q6808
37 KB_BL_CTRL G AO3418-GP
20.K0320.004
S
2

R6803
100KR2J-1-GP
A A
UMA
1

+5V_RUN
AFTP6833
AFTP6832
1
1 CN7_P2 Wistron Corporation
AFTP6834 1 KB_BL_DET# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AFTP6861 1 KB_BL_CTRL# Taipei Hsien 221, Taiwan, R.O.C.
Modified CON5 pin define & added N-MOS Title
2009/07/17 Keyboard/Touch Pad
Size Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 68 of 90
5 4 3 2 1
 5 4 3 2 1

D D

Hall Sensor Connector

+3.3V_ALW

C C

1
+3.3V_ALW C6902
SCD1U16V2KX-3GP

2
1
HALL1
R6903
1
DY 100KR2J-1-GP VDD
2

2
VSS

37 LID_CLOSE# LID_CLOSE# 1 2 LID_CLOSE#_1 3 OUTPUT

1
R6901 10R2J-2-GP
C6901
SCD047U10V2KX-2GP EM-6781-T30-GP

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Hall sensor Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 69 of 90
5 4 3 2 1
 5 4 3 2 1

D D

GOLDEN FINGER FOR DEBUG BOARD

+3.3V_RUN DBT1
C 1 C

24,37,76 LPC_LAD0 2
24,37,76 LPC_LAD1 3
24,37,76 LPC_LAD2 4
24,37,76 LPC_LAD3 5
24,37,76 LPC_LFRAME# 6
9,21,37,64,76,77,80 PLT_RST# 7
8
21 PCLK_FW H 9
10
11
12

MLX-CON10-7-GP
20.D0183.110

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Debug port Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 70 of 88
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blank)

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PX Swith-2
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 71 of 90
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Braidwood Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 72 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface
For EMI

2009/07/31
Change CAMERA1 connector pin define.
Camera Connector 1
R7302
2
For cable is already to be finished
0R3J-0-U-GP
D USB_PP11 21 D
CAMERA1
9

2
1
Camera Power 2 CAMERA_USB1+ L7301
+3.3V_RUN +3.3V_CAMERA 3 CAMERA_USB1- DY DLW 21SN900SQ2LUGP
R7301 4 +3.3V_CAMERA R7304
1 2 5 AUD_DMIC_IN0_R 2 1 33R2J-2-GP AUD_DMIC_IN0 30
6

3
0R3J-0-U-GP 7 AUD_DMIC_CLK_G AUD_DMIC_CLK_G 30
1

8
EC7304 C7305 10 1
SCD1U16V2KX-3GP DY SC4D7U6D3V3KX-GP
R7303
AFTP6010
2

ACES-CON8-3-GP-U 1 2 USB_PN11 21
20.F0779.008 0R3J-0-U-GP

1
MLVG0402220NV05-GP
EC7302 EC7303

MLVG0402220NV05-GP
DY DY

2
AFTP7302 1 AUD_DMIC_CLK_G
AFTP7303 1 AUD_DMIC_IN0_R
AFTP7304 1 +3.3V_CAMERA
AFTP7305 1 CAMERA_USB1-
AFTP7306 1 CAMERA_USB1+ For EMI
C C

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Camera Connector
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 73 of 90
5 4 3 2 1
 5 4 3 2 1

UMA/DIS LVDS signal select circuit

+1.8V_RUN +1.8V_RUN
U7411 U7412

38 2 38 2

1
81 VGA_LVDSA_DAT2 ATMDS2+ VDD 81 VGA_LVDSB_DAT2 ATMDS2+ VDD
37 8 37 8
81 VGA_LVDSA_DAT2# ATMDS2- VDD C7404 81 VGA_LVDSB_DAT2# ATMDS2- VDD C7406
36 16 36 16
81 VGA_LVDSA_DAT1 ATMDS1+ VDD SCD1U10V2KX-4GP 81 VGA_LVDSB_DAT1 ATMDS1+ VDD SCD1U10V2KX-4GP
35 18 35 18

2
81 VGA_LVDSA_DAT1# ATMDS1- VDD 81 VGA_LVDSB_DAT1# ATMDS1- VDD
34 20 34 20
81 VGA_LVDSA_DAT0 ATMDS0+ VDD 81 VGA_LVDSB_DAT0 ATMDS0+ VDD
33 30 33 30
81 VGA_LVDSA_DAT0# ATMDS0- VDD C7401 C7403 81 VGA_LVDSB_DAT0# ATMDS0- VDD C7402 C7405
32 40 32 40
81 VGA_LVDSA_CLK ATMDSCLK+ VDD SCD1U10V2KX-4GP SCD1U10V2KX-4GP 81 VGA_LVDSB_CLK ATMDSCLK+ VDD SCD1U10V2KX-4GP SCD1U10V2KX-4GP
31 42 31 42
81 VGA_LVDSA_CLK# ATMDSCLK- VDD 81 VGA_LVDSB_CLK# ATMDSCLK- VDD
D 29 29 D
20 MCH_LVDSA_DAT2 BTMDS2+ 20 MCH_LVDSB_DAT2 BTMDS2+
28 3 VGA_TXAOUT2+ 54 28 3 VGA_TXBOUT2+ 54
20 MCH_LVDSA_DAT2# BTMDS2- TMDS2+ 20 MCH_LVDSB_DAT2# BTMDS2- TMDS2+
27 4 VGA_TXAOUT2- 54 27 4 VGA_TXBOUT2- 54
20 MCH_LVDSA_DAT1 BTMDS1+ TMDS2- 20 MCH_LVDSB_DAT1 BTMDS1+ TMDS2-
26 6 VGA_TXAOUT1+ 54 26 6 VGA_TXBOUT1+ 54
20 MCH_LVDSA_DAT1# BTMDS1- TMDS1+ 20 MCH_LVDSB_DAT1# BTMDS1- TMDS1+
25 7 VGA_TXAOUT1- 54 25 7 VGA_TXBOUT1- 54
20 MCH_LVDSA_DAT0 BTMDS0+ TMDS1- 20 MCH_LVDSB_DAT0 BTMDS0+ TMDS1-
24 11 VGA_TXAOUT0+ 54 24 11 VGA_TXBOUT0+ 54
20 MCH_LVDSA_DAT0# BTMDS0- TMDS0+ 20 MCH_LVDSB_DAT0# BTMDS0- TMDS0+
23 12 VGA_TXAOUT0- 54 23 12 VGA_TXBOUT0- 54
20 MCH_LVDSA_CLK BTMDSCLK+ TMDS0- 20 MCH_LVDSB_CLK BTMDSCLK+ TMDS0-
22 14 VGA_TXACLK+ 54 22 14 VGA_TXBCLK+ 54
20 MCH_LVDSA_CLK# BTMDSCLK- TMDSCLK+ 20 MCH_LVDSB_CLK# BTMDSCLK- TMDSCLK+
15 VGA_TXACLK- 54 15 VGA_TXBCLK- 54
TMDSCLK- TMDSCLK-
9 +1.8V_RUN 9
SEL SEL
1 1

1
VSS VSS
5 5
VSS R7486 VSS
10 10
VSS 20KR2F-L-GP VSS
13 13
VSS VSS
17 17
VSS VSS
19 19

2
DGPU_1D8_SEL# VSS DGPU_1D8_SEL# VSS
21 21
VSS VSS
39 39
VSS VSS
41 41

GND

GND
D
VSS VSS
Q7411
H=>ATMDS -dGPU GPU (DIS) TS3DV421RUAR-GP 2N7002A-7-GP TS3DV421RUAR-GP
43

43
DGPU_SELECT
L=>BTMDS -iGPU PCH (UMA) 71.03421.003
71.03412.B0G
G 71.03421.003
71.03412.B0G

S
H=>ATMDS -dGPU GPU (DIS)
L=>BTMDS -iGPU PCH (UMA)

C C

+5V_CRT_RUN
1

C7407
SCD1U10V2KX-4GP
2

UMA/DIS CRT Hsync/Vsync select circuit

DGPU_SELECT Hsync & Vsync level shift
DGPU_SELECT# R7577 1 DY 2 0R2J-2-GP
+5V_CRT_RUN UMA/DIS CRT signal select circuit
14

U7408A C7408 +5V_CRT_RUN

SSAHCT125PWR-GP SCD1U10V2KX-4GP
2 3 VSYNC_5 U7435
20 GMCH_VSYNC
2 1 16
+5V_CRT_RUN DGPU_SELECT# 1 VCC
4 M_BLUE 55
S YA
14

2
7
4

B 81 VGA_BLUE IA0 B
3 7 M_GREEN 55
20 MCH_BLUE IA1 YB
5
VSYNC_5 81 VGA_GREEN IB0
5 6 6 9 M_RED 55
81 VGA_VSYNC 20 MCH_GREEN IB1 YC
11
81 VGA_RED IC0
10 12
U7408B 20 MCH_RED IC1 YD
14
7

SSAHCT125PWR-GP ID0
DGPU_SELECT# H=> -iGPU PCH (UMA) 13
ID1 OE#
15
RN7445 8
L=> -dGPU GPU (DIS) HSYNC_5 2 3
GND
VSYNC_5 1 JVGA_HS 55
4 JVGA_VS 55 PI5C3257QE-GP
+3.3V_RUN DGPU_SELECT 73.53257.B0C
SRN33J-5-GP-U 2ND = 73.03257.C0B
1

H=>IA1 -iGPU PCH (UMA)

R7485 DGPU_SELECT# +5V_CRT_RUN
20KR2F-L-GP U7408C L=>IA0 -dGPU GPU (DIS)
14

10

SSAHCT125PWR-GP
2

DGPU_SELECT 9 8 HSYNC_5
20 GMCH_HSYNC
+5V_CRT_RUN
D

14

13

Q7410
DGPU_SELECT# G 2N7002A-7-GP 12 11 HSYNC_5
21,54 DGPU_SELECT# 81 VGA_HSYNC
S

U7408D
SSAHCT125PWR-GP
2009/07/28
Change 2N7002 ESD pretect from standard to 1KV type
P/N:84.2N702.E31

A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

PX Swith-1 Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 74 of 90
5 4 3 2 1
 5 4 3 2 1

D Close to connector D

C7569 2 DIS1 SCD1U10V2KX-4GP IFPC_C_D2+

81 IFPC_D2+ C7564 SCD1U10V2KX-4GP IFPC_C_D2-
81 IFPC_D2-
2 DIS1
C7570 2 DIS1 SCD1U10V2KX-4GP IFPC_C_D1+
81 IFPC_D1+ C7565 SCD1U10V2KX-4GP IFPC_C_D1-
2 DIS1
81
81
IFPC_D1-
IFPC_D0+
C7568 2 DIS1 SCD1U10V2KX-4GP IFPC_C_D0+ UMA/DIS HDMI signal select circuit
C7567 2 DIS1 SCD1U10V2KX-4GP IFPC_C_D0-
81 IFPC_D0- C7571 SCD1U10V2KX-4GP IFPC_C_TXC+
81 IFPC_TXC+
2 DIS1
C7566 2 DIS1 SCD1U10V2KX-4GP IFPC_C_TXC-
81 IFPC_TXC-

IFPC_C_D2+ R7529 1 DIS 2 499R2F-2-GP

IFPC_C_D2- R7532 1 DIS 2 499R2F-2-GP
IFPC_C_D1+ R7533 1 DIS 2 499R2F-2-GP
IFPC_C_D1- R7534 1 DIS 2 499R2F-2-GP HDMI_L_DATA2+ R7561 1 UMA 2 0R2J-2-GP
IFPC_C_D0+ R7535 1 DIS 2 499R2F-2-GP HDMI_L_DATA2- R7562 1 UMA 2 0R2J-2-GP
IFPC_C_D0- R7536 1 DIS 2 499R2F-2-GP HDMI_L_DATA1+ R7563 1 UMA 2 0R2J-2-GP
IFPC_C_TXC+ R7537 1 DIS 2 499R2F-2-GP HDMI_L_DATA1- R7564 1 UMA 2 0R2J-2-GP
IFPC_C_TXC- R7530 1 DIS 2 499R2F-2-GP HDMI_L_DATA0+ R7565 1 UMA 2 0R2J-2-GP
HDMI_L_DATA0- R7566 1 UMA 2 0R2J-2-GP

IFPC_Lo
HDMI_L_CLK+ R7567 1 UMA 2 0R2J-2-GP
HDMI_L_CLK- R7568 1 UMA 2 0R2J-2-GP

IFPC_C_D2+ R7569 1 DIS 2 0R2J-2-GP HDMI_TXD2 57

IFPC_C_D2- R7570 1 DIS 2 0R2J-2-GP HDMI_TXD#2 57

D
IFPC_C_D1+ R7571 1 DIS 2 0R2J-2-GP HDMI_TXD1 57
IFPC_C_D1- R7572 1 DIS 2 0R2J-2-GP HDMI_TXD#1 57
+3.3V_RUN_GPU IFPC_C_D0+ R7573 1 DIS 2 0R2J-2-GP HDMI_TXD0 57
G DIS IFPC_C_D0- R7574 1 DIS 2 0R2J-2-GP HDMI_TXD#0 57
2N7002A-7-GP IFPC_C_TXC+ R7575 0R2J-2-GP
1 DIS 2 HDMI_TXC 57
Q7501 IFPC_C_TXC- R7576 1 DIS 2 0R2J-2-GP HDMI_TX#C 57

S
2009/07/28
Change 2N7002 ESD pretect from standard to 1KV type
P/N:84.2N702.E31
C C

UMA HDMI level shift circuit

C7561 2 UMA
1 SCD1U10V2KX-4GP HDMI_C_DATA2+
20 HDMI_DATA2+_C C7557 SCD1U10V2KX-4GP HDMI_C_DATA2-
20 HDMI_DATA2-_C
2 UMA
1
C7562 2 UMA
1 SCD1U10V2KX-4GP HDMI_C_DATA1+ C7508 C7505 +3.3V_RUN +3.3V_RUN
B 20 HDMI_DATA1+_C C7556 SCD1U10V2KX-4GP HDMI_C_DATA1- SCD1U10V2KX-4GP SCD1U10V2KX-4GP B
20 HDMI_DATA1-_C
2 UMA
1
C7560 2 UMA
1 SCD1U10V2KX-4GP HDMI_C_DATA0+ R7520 1 2 4K7R2J-2-GP
20 HDMI_DATA0+_C C7559 2 UMA
1 SCD1U10V2KX-4GP HDMI_C_DATA0- R7521 1 DY 2 4K7R2J-2-GP
20 HDMI_DATA0-_C C7563 UMA SCD1U10V2KX-4GP HDMI_C_CLK+ DY

8101_NC35
8101_NC34
2 1
20 HDMI_CLK+_C C7558 SCD1U10V2KX-4GP HDMI_C_CLK-
2 UMA
1
1

20 HDMI_CLK-_C
UMA UMA UMA UMA
Close to PCH
2

11
15
21
26
33
40
46

35
34
2

U7502
C7507 C7506

NC#35
NC#34
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SCD1U10V2KX-4GP SCD1U10V2KX-4GP

HDMI_C_CLK- 38 23 HDMI_L_CLK- +3.3V_RUN

HDMI_C_CLK+ IN_D1- OUT_D1- HDMI_L_CLK+
39 22
IN_D1+ OUT_D1+

1
HDMI_C_DATA0- 41 20 HDMI_L_DATA0-
HDMI_C_DATA0+ IN_D2- OUT_D2- HDMI_L_DATA0+ R7515
42 19
IN_D2+ OUT_D2+
UMA20KR2J-L2-GP
HDMI_C_DATA1- 44 17 HDMI_L_DATA1-
HDMI_C_DATA1+ IN_D3- OUT_D3- HDMI_L_DATA1+
45 16

2
IN_D3+ OUT_D3+ 8101_OE#
HDMI_C_DATA2- 47 UMA 14 HDMI_L_DATA2-
HDMI_C_DATA2+ IN_D4- OUT_D4- HDMI_L_DATA2+
48 13

D
+3.3V_RUN IN_D4+ OUT_D4+

R7522 2 UMA 1 4K7R2J-2-GP PC0 3 8 UMA Q7503

PC0 SDA SDVO_DAT 20,57
R7525 2 1 4K7R2J-2-GP PC1 4 9 HDMI_HP_DET_CON G
DY SDVO_CLK 20,57 2N7002A-7-GP
1

PC1 SCL HDMI_HP_DET

7 HDMI_HP_DET 20,21,57
R7523 HPD
UMA5K1R2F-2-GP REXT_HDMI 6 2009/07/28

S
+3.3V_RUN REXT HDMI_HP_DET_CON Change 2N7002 ESD pretect from standard to 1KV type
10 30 HDMI_HP_DET_CON 57
R7524 8101_OE# RT_EN# HPD_SINK HDMI_SDATA_CON P/N:84.2N702.E31
25 29
2

OE# SDA_SINK HDMI_SDATA_CON 57

2 4K7R2J-2-GP
1 DDC_EN_PS8101 32 28 HDMI_SCLK_CON
DDC_EN SCL_SINK HDMI_SCLK_CON 57
UMA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2

R7526
UMA499R2F-2-GP
1
5
12
18
24
27
31
36
37
43
49

PS8101-GP
A A
1

71.P8101.003
2ND = 71.03411.B03

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

(Reserve) Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 75 of 90
5 4 3 2 1
 5 4 3 2 1

LAN baord CON

CON1

43 41
Place near CON1
42 NP1
2 1 +5V_ALW

D 4 3 PCIE_IRXP3_LRTXP3 +3.3V_ALW +3.3V_RUN D

PCIE_IRXP3_LRTXP3 23
+5V_ALW 6 5 PCIE_IRXN3_LRTXN3 PCIE_IRXN3_LRTXN3 23
8 7

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C7690
SC4D7U10V3KX-GP

C7602

C7606

C7604
10 9 PCIE_ITXP3_LRXP3 PCIE_ITXP3_LRXP3 23

1
12 11 PCIE_ITXN3_LRXN3 PCIE_ITXN3_LRXN3 23
14 13
USB_OC#0_1 16 15 CLK_PCIE_LAN DY

2
21 USB_OC#0_1 CLK_PCIE_LAN# CLK_PCIE_LAN 23
18 17 CLK_PCIE_LAN# 23
USB_PN1 20 19
21 USB_PN1
USB_PP1 22 21 GPIO_DSM GPIO_DSM 24
21 USB_PP1
24 23 PCIE_W AKE# PCIE_W AKE# 22,77
USB_PN0 26 25 PLT_RST#
21 USB_PN0 PLT_RST# 9,21,37,64,70,77,80
USB_PP0 28 27 CLKREQ#_LAN CLKREQ#_LAN 23
21 USB_PP0
30 29 PM_LAN_ENABLE
PM_LAN_ENABLE 37
USB_PW R_EN# 32 31
37,63 USB_PW R_EN#
34 33 +3.3V_ALW
+3.3V_RUN 36 35
38 37
40 39

46 44
45 NP2

ACES-CONN40D-2-GP

AFTP7664 1 +5V_ALW
20.F1009.040 AFTP7665 1 +3.3V_ALW
2009/07/28 AFTP7666 1 +3.3V_RUN
C Change connector to 20.F0692.060 AFTP7636 USB_PW R_EN# C
2009/08/17
1
AFTP7672 1 USB_OC#0_1
Change connector to 20.F1044.040
and chenge pin define AFTP7637 1 USB_PN0
2009/08/25 AFTP7638 1 USB_PP0
Change connector to 20.F1009.040 AFTP7648 1 USB_PN1
2009/07/27 AFTP7649 1 USB_PP1
Change TPM to connector AFTP7659 GPIO_DSM
2009/07/30
1
AFTP7639 1 PCIE_IRXP3_LRTXP3
Change TPM1 connector to 20.K0238.010
AFTP7640 1 PCIE_IRXN3_LRTXN3
AFTP7641 1 PCIE_ITXP3_LRXP3
AFTP7642 1 PCIE_ITXN3_LRXN3
AFTP7643 1 CLK_PCIE_LAN
AFTP7644 CLK_PCIE_LAN#
Place near TPM1 AFTP7645
1
1 CLKREQ#_LAN
AFTP7646 1 PLT_RST#
+3.3V_RUN AFTP7647 1 PM_LAN_ENABLE
AFTP7658 1 PCIE_W AKE#

SCD1U16V2KX-3GP
C7611
TPM board CON 1
2

TPM1
+3.3V_RUN 11
1

LPC_LAD0 2
24,37,70 LPC_LAD0
LPC_LAD1 3
B 24,37,70 LPC_LAD1 B
LPC_LAD2 4
24,37,70 LPC_LAD2
LPC_LAD3 5
24,37,70 LPC_LAD3
24,37,70 LPC_LFRAME# LPC_LFRAME# 6
PLT_RST# 7
9,21,37,64,70,77,80 PLT_RST# INT_SERIRQ
24,37 INT_SERIRQ 8
PCLK_TPM 9
21 PCLK_TPM
1 10 +3.3V_RUN : 30mA
AFTP7681 12

ACES-CON10-4-GP

20.K0238.010

AFTP7673 1 LPC_LAD0
AFTP7671 1 LPC_LAD1
AFTP7674 1 LPC_LAD2
AFTP7675 1 LPC_LAD3
AFTP7676 1 LPC_LFRAME#
AFTP7677 1 PLT_RST#
AFTP7678 1 INT_SERIRQ
AFTP7679 1 PCLK_TPM
AFTP7680 1 +3.3V_RUN

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LAN Board Connector
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 76 of 88
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

Audio board CON IO baord CON

CON6
41
D +3.3V_ALW 1 D
CON4
21
Place near CON4 Place near CON6 2
+3.3V_RUN
+3.3V_RUN 1 3
+3.3V_RUN +3.3V_ALW +1.5V_RUN 4
W IRELESS_ON#/OFF 2 5
37 W IRELESS_ON#/OFF
BT_ACT 3 23 PCIE_CLK_RQ5# PCIE_CLK_RQ5# 6
64 BT_ACT

C7705
SCD1U16V2KX-3GP

C7704
SCD1U16V2KX-3GP
BLUETOOTH_EN 4 C7703 +1.5V_RUN 7
37 BLUETOOTH_EN

1
W LAN_ACT 5 SCD1U16V2KX-3GP 8
64 W LAN_ACT
BT_LED 6 23 NEW CARD_CLKREQ# NEW CARD_CLKREQ# 9
7 10

2
USB_PP8 8 23 PCIE_IRXN5_NTXN5 PCIE_IRXN5_NTXN5 11
21 USB_PP8
USB_PN8 9 23 PCIE_IRXP5_NTXP5 PCIE_IRXP5_NTXP5 12
21 USB_PN8
10 23 PCIE_ITXN5_NRXN5 PCIE_ITXN5_NRXN5 13
11 23 PCIE_ITXP5_NRXP5 PCIE_ITXP5_NRXP5 14
12 +5V_RUN +5V_RUN +5V_RUN 15
EXT_MIC_JD# 13 23 CLK_PCIE_NEW # CLK_PCIE_NEW # 16
30 EXT_MIC_JD# AUD_EXT_MIC_L CLK_PCIE_NEW
30 AUD_EXT_MIC_L 14 23 CLK_PCIE_NEW 17

C7701
SCD1U16V2KX-3GP

C7708
SCD1U16V2KX-3GP

C7709
SCD1U16V2KX-3GP
AUD_EXT_MIC_R 15 +3.3V_RUN +3.3V_RUN +3.3V_RUN 18
30 AUD_EXT_MIC_R

1
AUD_HP1_JD# 16 21 USB_PN12 USB_PN12 19
30 AUD_HP1_JD# AUD_HP1_JACK_L USB_PP12
30 AUD_HP1_JACK_L 17 21 USB_PP12 20

C7707
SCD1U16V2KX-3GP

C7706
SCD1U16V2KX-3GP

C7710
SCD1U16V2KX-3GP
AUD_HP1_JACK_R 18 21
30 AUD_HP1_JACK_R

1
19 22,37,42,50,51,52,86 PM_SLP_S3# PM_SLP_S3# 22
20 22,37,50 PM_SLP_S4# PM_SLP_S4# 23
AFTP7723 1 22 66 BATT_LED_ORANGE BATT_LED_ORANGE 24

2
66 PW R2_LED PW R2_LED 25
ACES-CON20-8-GP +5V_RUN +5V_RUN +5V_RUN 66 BATT_LED_W HITE BATT_LED_W HITE 26
20.K0315.020 27

C7791
SC4D7U10V3KX-1-GP

C7794
SC4D7U10V3KX-1-GP

C7795
SC4D7U10V3KX-1-GP
9,21,37,64,70,76,80 PLT_RST# PLT_RST# 28

1
C +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN 29 C
30 AUD_VREFOUT_B
C7702
SC1U10V3KX-3GP

CLK_PCIE_R5U230 30
DY DY DY 23 CLK_PCIE_R5U230
1
R7702
4K7R2J-2-GP

R7703
4K7R2J-2-GP

C7792
SC4D7U10V3KX-1-GP

C7793
SC4D7U10V3KX-1-GP

C7797
SC4D7U10V3KX-1-GP

C7796
SC4D7U10V3KX-1-GP
23 CLK_PCIE_R5U230# CLK_PCIE_R5U230# 31

2
1

1
32
PCIE_ITXP1_CRXP1 33
DY DY DY DY 23 PCIE_ITXP1_CRXP1
2

23 PCIE_ITXN1_CRXN1 PCIE_ITXN1_CRXN1 34

2
23 PCIE_IRXP1_CTXP1 PCIE_IRXP1_CTXP1 35
23 PCIE_IRXN1_CTXN1 PCIE_IRXN1_CTXN1 36
2

22,76 PCIE_W AKE# PCIE_W AKE# 37

23 PCH_SMB_DATA PCH_SMB_DATA 38
AUD_EXT_MIC_L 23 PCH_SMB_CLK PCH_SMB_CLK 39
AUD_EXT_MIC_R +5V_ALW 40
42

2009/07/27 AFTP7706 1 +3.3V_RUN

Change CON4 PIN define AFTP7709 1 W IRELESS_ON#/OFF PTW O-CON40-1-GP
Remove +15V_ALW AFTP7702 W LAN_ACT
20.K0359.040
1
2009/07/29 AFTP7703 1 BLUETOOTH_EN
Change CON4 connector to 20.K0275.028 AFTP7704 1 BT_LED
And change CON4 pin define AFTP7705 1 BT_ACT 2009/07/28
AFTP7707 1 USB_PP8 Change CON6 connector to 20.K0286.040
2009/08/03 AFTP7708 USB_PN8 AFTP7786 PCIE_CLK_RQ5#
1 1 2009/08/05
Change CON4 pin define. AFTP7758 1 +3.3V_ALW
2009/08/18 AFTP7713 1 EXT_MIC_JD# AFTP7757 1 +3.3V_RUN Change CON6 pin define
Change CON4 connector P/N:20.K0315.020 AFTP7714 1 AUD_EXT_MIC_L AFTP7760 1 +1.5V_RUN 2009/08/12
AFTP7715 1 AUD_EXT_MIC_R AFTP7762 1 USB_PN12 Change CON6 pin define
2009/08/19 AFTP7716 AUD_HP1_JD# AFTP7759 USB_PP12
1 1
Remove AUD_VREFOUT_B from Audio board to main board. AFTP7717 1 AUD_VREFOUT_B AFTP7761 1 PCIE_IRXN5_NTXN5
B AFTP7718 AUD_HP1_JACK_L AFTP7765 PCIE_IRXP5_NTXP5 B
1 1
AFTP7719 1 AUD_HP1_JACK_R AFTP7764 1 PCIE_ITXN5_NRXN5
AFTP7763 1 PCIE_ITXP5_NRXP5
AFTP7771 1 CLK_PCIE_NEW #
AFTP7770 1 CLK_PCIE_NEW
AFTP7766 1 PCIE_W AKE#
AFTP7769 1 NEW CARD_CLKREQ#
AFTP7768 1 PCH_SMB_CLK
AFTP7767 1 PCH_SMB_DATA
AFTP7777 1 PM_SLP_S3#
AFTP7776 1 PM_SLP_S4#
AFTP7774 1 BATT_LED_W HITE
AFTP7773 1 BATT_LED_ORANGE
AFTP7772 1 PW R2_LED
AFTP7775 1 CLK_PCIE_R5U230
AFTP7780 1 CLK_PCIE_R5U230#
AFTP7779 1 PCIE_ITXP1_CRXP1
+5V_RUN AFTP7778 1 PCIE_ITXN1_CRXN1
AFTP7783 1 PCIE_IRXP1_CTXP1
AFTP7782 1 PCIE_IRXN1_CTXN1
1

AFTP7781 1 PLT_RST#
R7701
100KR2J-1-GP
2

BT_ACTIVE_K#
66 BT_ACTIVE_K#
3

A UMA A
Q7701 1 BT_LED
MMBT3904-7-F-GP

Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
IO Board/Audio Board ConnectorRev
Document Number
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 77 of 90
5 4 3 2 1
 5 4 3 2 1

D D

Finger Printer Connector

LED&Capacity board CONN
+3.3V_RUN

Close to CON2

1
C7801 CON3 CON2 +5V_RUN +5V_ALW +3.3V_RUN
SCD1U10V2KX-4GP 8 21

C7803

C7804

C7805
R7802

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
6 +5V_RUN 1

1
0R3J-0-U-GP 5
21 USB_PN10 1 2 Biometric_USBPN 4 +5V_ALW 2
21 USB_PP10 1 2 Biometric_USBPP 3 3

2
2 4
R7801 KBC_PWRBTN# 5
0R3J-0-U-GP BIO_DET# 37 KBC_PWRBTN# WLAN_WIMAX_LED_R#
25 BIO_DET# 1 66 WLAN_WIMAX_LED_R# 6
7 66 SCRL_LED_R# SCRL_LED_R# 7
AFTP7801 1 66 CAP_LED_R# CAP_LED_R# 8
PTWO-CON6-2-GP 66 NUM_LED_R# NUM_LED_R# 9
4

20.K0293.006 66 SATA1_ACT_LED SATA1_ACT_LED 10

66 LED_BT_ACT_K_R# LED_BT_ACT_K_R# 11
EL7801 12
DLW21SN900SQ2LUGP PWR_BTN_LED_R# 13
DY 66 PWR_BTN_LED_R#
CAPA_INT# 14
37 CAPA_INT# CAPA_RST# AFTP7808 SCRL_LED_R#
37 CAPA_RST# 15 1
16 AFTP7809 1 CAP_LED_R#
1

THERM_SDA 17 AFTP7810 1 NUM_LED_R#

37,39 THERM_SDA
C
THERM_SCL 18 AFTP7811 1 SATA1_ACT_LED C
37,39 THERM_SCL
AFTP7805 1 BIO_DET# 19 AFTP7812 1 LED_BT_ACT_K_R#
AFTP7802 1 +3.3V_RUN +3.3V_RUN 20 AFTP7813 1 WLAN_WIMAX_LED_R#
AFTP7803 1 Biometric_USBPN 22 AFTP7814 1 CAPA_INT#
AFTP7804 1 Biometric_USBPP AFTP7815 1 CAPA_RST#
PTWO-CON20-2-GP AFTP7816 1 THERM_SDA
AFTP7817 1 THERM_SCL
AFTP7818 1 +3.3V_RUN
20.K0392.020 AFTP7819 1 +5V_RUN
AFTP7820 1 +5V_ALW
AFTP7821 1 PWR_BTN_LED_R#
AFTP7822 1 KBC_PWRBTN#

B B

A A
UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Finger Printer
Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 78 of 90
5 4 3 2 1
 5 4 3 2 1

EMI Request
+PWR_SRC +1.8V_RUN +3.3V_RUN +1.05V_PCH
SSID = Mechanical

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP
1

1
EC7901

EC7902

EC7903

EC7904
2

2
D BOSS: D

HOLE:
WLAN Thermal
BOSS2 BOSS3 H1 H2 H3 +3.3V_RUN_GPU
STF256R89H178-GP STF237R117H83-1-GP

34.4B417.001 34.4CK01.001

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP
1

1
EC7905

EC7906

EC7907

EC7908
2

2
Do Not Stuff Do Not Stuff Do Not Stuff
Do Not Stuff Do Not Stuff Do Not Stuff

H4
2009/07/30
Change connector

1
C C
For CPU HOLE:
H13 H14 H15
Do Not Stuff Do Not Stuff Do Not Stuff
Do Not Stuff
Do Not Stuff
1

H5 H6

Do Not Stuff Do Not Stuff Do Not Stuff

1
H16
Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff Do Not Stuff
1

B H8 B

Do Not Stuff

1
Do Not Stuff
Do Not Stuff

H10 H11 H12

1

1
A A
UMA

Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Miscellaneous Components Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 79 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
U8001C 3 OF 10
PCIE_MTX_GRX_P[0..15]
PCIE_MTX_GRX_P[0..15] 8
PCIE_MTX_GRX_P0 AP17 AL17 PCIE_MRX_GTX_C_P0 C8015 1 2 SCD1U16V2KX-3GP PCIE_MRX_GTX_P0
PCIE_MTX_GRX_N0 PEX_RX0 PEX_TX0 PCIE_MRX_GTX_C_N0 SCD1U16V2KX-3GP 1 C8010PCIE_MRX_GTX_N0
AN17 AM17 2C8010
PCIE_MTX_GRX_P1 PEX_RX0# PEX_TX0# PCIE_MRX_GTX_C_P1 C8031 1 PCIE_MRX_GTX_P1 PCIE_MTX_GRX_N[0..15]
AN19 AM18 2 SCD1U16V2KX-3GP PCIE_MTX_GRX_N[0..15] 8
PCIE_MTX_GRX_N1 PEX_RX1 PEX_TX1 PCIE_MRX_GTX_C_N1 SCD1U16V2KX-3GP 1 C8028PCIE_MRX_GTX_N1
AP19 AM19 2C8028
PCIE_MTX_GRX_P2 PEX_RX1# PEX_TX1# PCIE_MRX_GTX_C_P2 C8032 1 PCIE_MRX_GTX_P2
AR19 AL19 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N2 PEX_RX2 PEX_TX2 PCIE_MRX_GTX_C_N2 SCD1U16V2KX-3GP 1 C8007PCIE_MRX_GTX_N2
AR20 AK19 2C8007
PCIE_MTX_GRX_P3 PEX_RX2# PEX_TX2# PCIE_MRX_GTX_C_P3 C8003 1 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P[0..15]
AP20 AL20 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N3 PEX_RX3 PEX_TX3 PCIE_MRX_GTX_C_N3 SCD1U16V2KX-3GP 1 C8018PCIE_MRX_GTX_N3 PCIE_MRX_GTX_P[0..15] 8
AN20 AM20 2C8018
PCIE_MTX_GRX_P4 PEX_RX3# PEX_TX3# PCIE_MRX_GTX_C_P4 C8019 1 PCIE_MRX_GTX_P4
AN22 AM21 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N4 PEX_RX4 PEX_TX4 PCIE_MRX_GTX_C_N4 SCD1U16V2KX-3GP 1 C8011PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N[0..15]
AP22 AM22 2C8011
PCIE_MTX_GRX_P5 PEX_RX4# PEX_TX4# PCIE_MRX_GTX_C_P5 C8026 1 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_N[0..15] 8
D AR22 AL22 2 SCD1U16V2KX-3GP D
PCIE_MTX_GRX_N5 PEX_RX5 PEX_TX5 PCIE_MRX_GTX_C_N5 SCD1U16V2KX-3GP 1 C8004PCIE_MRX_GTX_N5
AR23 AK22 2C8004
PCIE_MTX_GRX_P6 PEX_RX5# PEX_TX5# PCIE_MRX_GTX_C_P6 C8022 1 PCIE_MRX_GTX_P6
AP23 AL23 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N6 PEX_RX6 PEX_TX6 PCIE_MRX_GTX_C_N6 SCD1U16V2KX-3GP 1 C8002 PCIE_MRX_GTX_N6
AN23 AM23 2C8002
PCIE_MTX_GRX_P7 PEX_RX6# PEX_TX6# PCIE_MRX_GTX_C_P7 C8014 1 PCIE_MRX_GTX_P7
AN25 AM24 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N7 PEX_RX7 PEX_TX7 PCIE_MRX_GTX_C_N7 SCD1U16V2KX-3GP 1 C8024 PCIE_MRX_GTX_N7
AP25 AM25 2C8024
PCIE_MTX_GRX_P8 PEX_RX7# PEX_TX7# PCIE_MRX_GTX_C_P8 C8012 1 PCIE_MRX_GTX_P8
AR25 AL25 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N8 PEX_RX8 PEX_TX8 PCIE_MRX_GTX_C_N8 SCD1U16V2KX-3GP 1 C8030 PCIE_MRX_GTX_N8
AR26 AK25 2C8030
PCIE_MTX_GRX_P9 PEX_RX8# PEX_TX8# PCIE_MRX_GTX_C_P9 C8013 1 PCIE_MRX_GTX_P9
AP26 AL26 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N9 PEX_RX9 PEX_TX9 PCIE_MRX_GTX_C_N9 SCD1U16V2KX-3GP 1 C8016 PCIE_MRX_GTX_N9
AN26 AM26 2C8016
PCIE_MTX_GRX_P10 PEX_RX9# PEX_TX9# PCIE_MRX_GTX_C_P10 C8029 1 PCIE_MRX_GTX_P10
AN28 AM27 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N10 PEX_RX10 PEX_TX10 PCIE_MRX_GTX_C_N10 SCD1U16V2KX-3GP 1 C8008 PCIE_MRX_GTX_N10
AP28 AM28 2C8008
PCIE_MTX_GRX_P11 PEX_RX10# PEX_TX10# PCIE_MRX_GTX_C_P11 C8006 1 PCIE_MRX_GTX_P11
AR28 AL28 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N11 PEX_RX11 PEX_TX11 PCIE_MRX_GTX_C_N11 SCD1U16V2KX-3GP 1 C8025 PCIE_MRX_GTX_N11
AR29 AK28 2C8025
PCIE_MTX_GRX_P12 PEX_RX11# PEX_TX11# PCIE_MRX_GTX_C_P12 C8023 1 PCIE_MRX_GTX_P12
AP29 AK29 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N12 PEX_RX12 PEX_TX12 PCIE_MRX_GTX_C_N12 SCD1U16V2KX-3GP 1 C8020 PCIE_MRX_GTX_N12
AN29 AL29 2C8020
PCIE_MTX_GRX_P13 PEX_RX12# PEX_TX12# PCIE_MRX_GTX_C_P13 C8027 1 PCIE_MRX_GTX_P13
AN31 AM29 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N13 PEX_RX13 PEX_TX13 PCIE_MRX_GTX_C_N13 SCD1U16V2KX-3GP 1 C8009 PCIE_MRX_GTX_N13
AP31 AM30 2C8009
PCIE_MTX_GRX_P14 PEX_RX13# PEX_TX13# PCIE_MRX_GTX_C_P14 C8021 1 PCIE_MRX_GTX_P14
AR31 AM31 2 SCD1U16V2KX-3GP Revised decoupling C 2009/05/28
PCIE_MTX_GRX_N14 PEX_RX14 PEX_TX14 PCIE_MRX_GTX_C_N14 SCD1U16V2KX-3GP 1 C8005 PCIE_MRX_GTX_N14
AR32 AM32 2C8005
PCIE_MTX_GRX_P15 PEX_RX14# PEX_TX14# PCIE_MRX_GTX_C_P15 C8017 1 PCIE_MRX_GTX_P15
AR34 AN32 2 SCD1U16V2KX-3GP
PCIE_MTX_GRX_N15 PEX_RX15 PEX_TX15 PCIE_MRX_GTX_C_N15 SCD1U16V2KX-3GP 1 C8001 PCIE_MRX_GTX_N15
+1.05V_GFX_PCIE
AP34
PEX_RX15# PEX_TX15#
AP32 2C8001 Place under GPU Place near GPU +1.05V_GFX_PCIE

AG11 AK16
PEX_IOVDDQ PEX_IOVDD
AG12 AK17
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SC22U6D3V5MX-2GP

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
1

1
PEX_IOVDDQ PEX_IOVDD
C8069

C8074

C8064

C8067

C8068

C8066

C8065

C8059

C8060

C8063

C8062

C8061

C8073

C8041
AG13 AK21
PEX_IOVDDQ PEX_IOVDD
AG15 AK24
PEX_IOVDDQ PEX_IOVDD
AG16 AK27
2

2
PEX_IOVDDQ PEX_IOVDD
AG17
PEX_IOVDDQ
AG18
PEX_IOVDDQ CLK_PCIE_VGA
AG22 AR16 CLK_PCIE_VGA 23
PEX_IOVDDQ PEX_REFCLK CLK_PCIE_VGA#
AG23 AR17 CLK_PCIE_VGA# 23
PEX_IOVDDQ PEX_REFCLK#
AG24
PEX_IOVDDQ
AG25
PEX_IOVDDQ PEX_TEST_PLL_CLK_OUT
Place near GPU Place under GPU AG26
PEX_IOVDDQ PEX_TSTCLK_OUT
AJ17 2
DY 1
AJ14 AJ18 PEX_TEST_PLL_CLK_OUT# 200R2F-L-GP R8002 2009/07/28
PEX_IOVDDQ PEX_TSTCLK_OUT# DUMMY R8002 WITH NV FAE recommend
AJ15
PEX_IOVDDQ
Revised decoupling C 2009/05/28 AJ19
AJ21
PEX_IOVDDQ
AR13 PEX_CLKREQ# R8004 1 2
PEX_IOVDDQ PEX_CLKREQ# +3.3V_RUN_GPU
AJ22 AM16 PEX_RST# 10KR2J-3-GP
PEX_IOVDDQ PEX_RST#
C AJ24 C
PEX_IOVDDQ
AJ25 AG19 +3.3V_RUN_GPU
PEX_IOVDDQ PEX_SVDD_3V3
AJ27
PEX_IOVDDQ PEX_TERMP
AK18 AG21 1 2 R8001 2K49R2F-GP
PEX_IOVDDQ PEX_TERMP

C8049
AK20

SCD1U10V2KX-4GP
1
PEX_IOVDDQ
AK23 AG14 +PEX_PLLVDD
PEX_IOVDDQ PEX_PLLVDD
AK26
PEX_IOVDDQ
AL16 AE9 +GPU_PLLVDD

2
PEX_IOVDDQ PLLVDD

N10P-GB1-128-GP
Place under GPU

+3.3V_RUN
2009/07/28
Added 8033 CAP.
1

C8033
SCD1U10V2KX-4GP
U8028 PEX_PLLVDD = 120mA Place under GPU Place near GPU
2

1 +PEX_PLLVDD +1.05V_GFX_PCIE +1.05V_GFX_PCIE

25 DGPU_HOLD_RST# B L8011 (Per pin)
+GPU_PLLVDD
5 L8005
PLT_RST#_RC 2 VCC
9,21,37,64,70,76,77 PLT_RST# 1 R8039 2 1 2
A PEX_RST#
C8070

4 IND-D1UH-20-GP 1 2
SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP
1

Y
C8086

C8046

0R2J-2-GP 3
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP
1

1
GND
100NH 0603

C8071

C8072
IND-100NH-7-GP
2

C8076

C8075
DY DCR= 0.13 ohm
2

74LVC1G08GW-1-GP I SP_PLLVDD=45mA
2

2
R8016
100KR2J-1-GP
1

R8040 Place near GPU

1 DY 2

0R2J-2-GP
Revised decoupling C 2009/05/28 Revised decoupling C 2009/05/28

B B

A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-PCIE/LVDS(1/4)
Size Document Number Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 80 of 90
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN_GPU

SSID = VIDEO

1
2
RN8112
U8001F 6 OF 10 SRN2K2J-1-GP

K1 G1 CRT_CLK_DDC
GPIO0 I2CA_SCL CRT_CLK_DDC 55
K2 G4 CRT_DAT_DDC

4
3
57 HDMI_HP_DET_VGA GPIO1 I2CA_SDA CRT_DAT_DDC 55
LBKLT_CTL_GPU K3
54 LBKLT_CTL_GPU GPIO2
R8135 1 2 0R2J-2-GP LCDVDD_EN_GPU_C H3 G3 I2CB_SCL I2CB_SCL
54 LCDVDD_EN_GPU GPIO3 I2CB_SCL I2CB_SDA I2CB_SDA
37 PANEL_BKEN_GPU H2 G2
PWRCNTL_0 GPIO4 I2CB_SDA
86 PWRCNTL_0 H1
PWRCNTL_1 GPIO5 LDDC_CLK
86 PWRCNTL_1 H4 E3 LDDC_CLK 54
GPIO6 I2CC_SCL LDDC_DATA
H5 E4 LDDC_DATA 54
GPIO7 I2CC_SDA
37 THERMTRIP_VGA#
R8136 1 2 0R2J-2-GP THERMTRIP_VGA# H6 CLK GEN 27M select: X8101
GPIO8
J7 F6
GPIO9 I2CH_SCL
D K4 G6 Main 82.30034.651 D
GPIO10 I2CH_SDA XTAL_IN R8123 1
K5 DY 2 0R2J-2-GP CLK_VGA_27M 7 2 3
GPIO11
H7 E2
GPIO12 I2CS_SCL XTAL_SSIN R8131 1
J4 E1 DY 2 0R2J-2-GP
GPIO13 I2CS_SDA
J6

1
GPIO14 GPU_XTAL_IN
L1 1 4
GPIO15 TP_JTAG_TDI_GPU TP8102 R8132 DY R8125
L2 AN14 1

1
GPIO16 JTAG_TDI TP_JTAG_TDO_GPU TP8104 10KR2J-3-GP 10KR2J-3-GP
L4 AN16 1
DEEPIDLE_WAKE_INT_R# GPIO17 JTAG_TDO R8115 XTAL-27MHZ-84-GP
25 DEEPIDLE_WAKE_INT_R# M4
GPIO18 TP_JTAG_TMS_GPU TP8101
L7 AR14 1 1MR2J-1-GP

2
GPIO19 JTAG_TMS JTAG_RST#_GPU
L5 AP16 2 1
GPIO20 JTAG_TRST# TP_JTAG_TCK_GPU 1KR2J-1-GP TP8103 R8120
K6 AP14 1

2
GPIO21 JTAG_TCK GPU_XTALOUT
L6
GPIO22
M6 VGA 27M R8123 R8131 R8125 R8132

1
GPIO23 ROM_SO_GPU C8135 C8138
C4 ROM_SO_GPU 83
ROM_SO ROM_SI_GPU SC10P50V2JN-4GP SC10P50V2JN-4GP
ROM_SI
D3 ROM_SI_GPU 83 SS DY POP DY POP
74 VGA_BLUE AL14

2
DACA_BLUE ROM_SCLK_GPU
74 VGA_GREEN AM14
DACA_GREEN ROM_SCLK
D4 ROM_SCLK_GPU 83 NON-SS POP DY POP DY
74 VGA_RED AM15 C3
DACA_RED ROM_CS#

1
AL13 Added CLK GEN 27M select circuit 2009/06/15

150R2F-1-GP

150R2F-1-GP

150R2F-1-GP
74 VGA_VSYNC DACA_VSYNC XTAL_IN GPU_XTAL_IN

R8116

R8118

R8119
+DACA_VDD = 120mA 74 VGA_HSYNC AM13 B1 R8114 2 0R2J-2-GP
1
DACA_HSYNC XTAL_IN
DACA_RSET XTAL_OUT
B2 GPU_XTALOUT_1 R8113 2 0R2J-2-GP
1 GPU_XTALOUT Added R8132 (DY) 2009/06/17
AK13
+DACA_VDD DACA_RSET XTALBUFF R8124 2
Place near GPU Place under GPU AJ12 D1 1 10KR2J-3-GP

2
DACA_VREF DACA_VDD XTAL_OUTBUFF XTAL_SSIN
AK12 D2
+DACA_VDD DACA_VREF XTAL_SSIN

R8106
124R2F-U-GP
+3.3V_RUN_GPU AJ4 R8133

SCD1U10V2KX-5GP
L8106 DACB_BLUE STRAP_CAL_PU_GND0

C8103
16mil AL4 N9 1 2

1
+DACA_VDD DACB_GREEN MULTI_STRAP_REF0_GND STRAP_CAL_PU_GND1
1 2 AK4 M9 1 2 40K2R2F-GP

1
BLM18SG331TN1D-GP DACB_RED MULTI_STRAP_REF1_GND R8126 40K2R2F-GP
C8153

C8154

C8144

C8143

C8118

C8108

C8107
AM2

SC470P50V2KX-3GP
SC4700P50V2KX-1GP
SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP

2
VGA_THERMDC 39
1

1
DACB_VSYNC
AM1
DACB_HSYNC THERMDN
B4 Place near GPU +1.05V_GFX_PCIE
C8102
Spec 300 ohm, AH7
THERMDP
B5
DY SC2200P50V2KX-2GP +SP_PLLVDD
VGA_THERMDA 39 L8110
2

2
DACB_RSET
ESR<0.25 ohm DACB_VDD AG7
DACB_VDD HDCP_TESTMODE R8107 2
AK6 AP35 1 10KR2J-3-GP 1 2
DACB_VREF TESTMODE CEC R8127 2 10KR2J-3-GP
AB5 1

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP
+3.3V_RUN_GPU

1
CEC IND-100NH-7-GP
AF9 +SP_PLLVDD
STRAP0 SP_PLLVDD

C8127

C8120
R8111 W5 A5
83 STRAP0 STRAP1 STRAP0 SPDIF
10KR2F-2-GP W7 I SP_PLLVDD=45mA

2
83 STRAP1 STRAP2 STRAP1
C
83 STRAP2 V7 A4 C
STRAP2 BUFRST#
Revised decoupling C 2009/05/28

2
N10P-GB1-128-GP

Revised decoupling C 2009/05/28

+IFPAB_IOVDD
+IFPC_IOVDD

U8001E 5 OF 10 +1.8V_RUN_GPU +1.05V_GFX_PCIE

IFPAB_IOVDD = 285mA
L8107 IFPAB_IOVDD = 220mA L8105
74 VGA_LVDSA_CLK AM11 AR8
IFPA_TXC IFPD_L0 +IFPAB_IOVDD +IFPC_IOVDD
74 VGA_LVDSA_CLK# AM12 AR7 1 2 1 2
IFPA_TXC# IFPD_L0#
AP7
IFPD_L1

C8126

C8149

C8150

C8129

C8119

C8111

C8122
AM8 AN7 BLM18PG181SN1D-GP BLM18BB221SN1D-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
74 VGA_LVDSA_DAT0

1
IFPA_TXD0 IFPD_L1#
74 VGA_LVDSA_DAT0# AL8 AN5
IFPA_TXD0# IFPD_L2
74 VGA_LVDSA_DAT1 AM10 AP5
IFPA_TXD1 IFPD_L2#
AM9 AR5

2
74 VGA_LVDSA_DAT1# IFPA_TXD1# IFPD_L3
AK10 AR4 R8129
74 VGA_LVDSA_DAT2 IFPA_TXD2 IFPD_L3#
AL10 10KR2J-3-GP Place under GPU
74 VGA_LVDSA_DAT2# IFPA_TXD2#
AK11 AK8 IFPD_IOVDD 2 1 Place near GPU
AL11
IFPA_TXD3 IFPD_IOVDD
AC6 IFPD_PLLVDD near IFPA_IOVDD
IFPA_TXD3# IFPD_PLLVDD
2 1 Place near GPU Place under GPU
+IFPAB_IOVDD AG9 AB6 R8128
IFPA_IOVDD IFPD_RSET 10KR2J-3-GP +IFPAB_IOVDD
Revised decoupling C 2009/05/28
+IFPAB_PLLVDD AK9 IFPD_AUX_I2CX_SCL
AP4 Revised decoupling C 2009/05/28

C8151
AN4

SCD1U10V2KX-4GP
1
IFPAB_PLLVDD IFPD_AUX_I2CX_SDA#
1 IFPAB_RSET AJ11
R8121 DY 2
IFPAB_RSET
AH6

2
1KR2F-3-GP IFPE_L0
IFPE_L0#
AH5 Place under GPU
74 VGA_LVDSB_CLK AP13 AH4
AN13
IFPB_TXC IFPE_L1
AG4 near IFPB_IOVDD
74 VGA_LVDSB_CLK# IFPB_TXC# IFPE_L1#
AF4
B IFPE_L2 B
74 VGA_LVDSB_DAT0 AN8 AF5
IFPB_TXD4 IFPE_L2#
74 VGA_LVDSB_DAT0# AP8 AE6
IFPB_TXD4# IFPE_L3 R8137
74 VGA_LVDSB_DAT1 AP10 AE5
IFPB_TXD5 IFPE_L3# 10KR2J-3-GP
74 VGA_LVDSB_DAT1# AN10
IFPB_TXD5# IFPE_IOVDD
74 VGA_LVDSB_DAT2 AR11 AE7 2 1
IFPB_TXD6 IFPE_IOVDD
74 VGA_LVDSB_DAT2# AR10
IFPB_TXD6#
AN11 AE4
IFPB_TXD7 IFPE_AUX_I2CY_SCL
AP11 AD4
IFPB_TXD7# IFPE_AUX_I2CY_SDA#
+IFPAB_IOVDD AG10
IFPB_IOVDD
AL2
IFPF_L0
AM7
IFPF_L0#
AL3
AJ3
+IFPC_PLLVDD
75 IFPC_D2+
AM6
IFPC_L0 IFPF_L1
AJ2
+IFPAB_PLLVDD
75 IFPC_D2- IFPC_L0# IFPF_L1# +3.3V_RUN_GPU
75 IFPC_D1+
AL5
IFPC_L1 IFPF_L2
AJ1 Revised decoupling C 2009/05/28 IFPAB_PLLVDD = 220mA
AM5 AH1 L8109
75 IFPC_D1- IFPC_L1# IFPF_L2#
AM3 AH2
75 IFPC_D0+ IFPC_L2 IFPF_L3 R8138 +1.05V_GFX_PCIE +IFPC_PLLVDD
AM4 AH3 1 2
75 IFPC_D0- IFPC_L2# IFPF_L3# 10KR2J-3-GP BLM18SG331TN1D-GP
75 IFPC_TXC+
AP1
IFPC_L3 L8108 IFPAB_PLLVDD = 220mA
IFPF_IOVDD

C8112

C8115

C8116

C8117

C8123
AR2 AD7 2 1

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
1

1
75 IFPC_TXC- IFPC_L3# IFPF_IOVDD +IFPAB_PLLVDD
AJ6 1 2
+IFPC_IOVDD IFPF_PLLVDD IFPF_PLLVDD
+IFPC_PLLVDD
AJ8
IFPC_IOVDD
2 1 Spec 300 ohm, DY DY

C8128

C8152
AJ9 AL1 R8130 BLM18PG181SN1D-GP

SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP

2
1

1
IFPC_PLLVDD IFPF_RSET
IFPAC_RSET
10KR2J-3-GP ESR<0.25 ohm
1 2 AK7 AF3
R8122 IFPC_RSET IFPF_AUX_I2CZ_SCL
AF2

2
1KR2F-3-GP IFPF_AUX_I2CZ_SDA#
57 HDMI_SCLK_DDC AP2
AN3
IFPC_AUX_I2CW_SCL Unused IFP Place near GPU Place under GPU
57 HDMI_SDATA_DDC IFPC_AUX_I2CW_SDA#
Interfaces setting Place near GPU 2009/07/28
N10P-GB1-128-GP 2009/06/03 Revised decoupling C 2009/05/28 DUMMY C8117, C8123

A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-LVDS/CRT/DP PORT
Size Document Number Rev
A2 SA
Vostro Calpella
Date: Tuesday, September 08, 2009 Sheet 81 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

2009/08/05
Added +VCC_GFX_CORE and +1.5V_RUN_GPU
FBVDD/Q = 2.24A
+VCC_GFX_CORE = 31.66A U8001J 10 OF 10
power decoupling capacitors.
Place under GPU +1.5V_RUN_GPU B3 AP33
+VCC_GFX_CORE GND GND
B6 AP30
U8001I 9 OF 10 GND GND
Place under GPU B9
GND GND
AP27

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

SCD047U10V2KX-2GP
+VCC_GFX_CORE

C8222

C8235

C8209

C8210

C8251

C8252

C8253
B12 AP24

1
GND GND
L11 AD24 B15 AP21
VDD VDD GND GND
L12 AD22 B21 AP18
VDD VDD +1.5V_RUN_GPU GND GND
D L13 AD18 B24 AP15 D

2
VDD VDD GND GND

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
L14 AD16 U8001G 7 OF 10 B27 AP12
VDD VDD GND GND
L15 AD14 B30 AP9
VDD VDD GND GND

C8245

C8260

C8259

C8255

C8254

C8261
L16 AD12 B18 AJ28 B33 AP6

1
VDD VDD FBVDDQ FBVDDQ +1.5V_RUN_GPU GND GND
L17 AC25 E21 AE27 C2 AP3
VDD VDD FBVDDQ FBVDDQ GND GND
L18 AC24 G17 AD27 C34 AN34
VDD VDD FBVDDQ FBVDDQ GND GND
L19 AC23 G18 AC27 E6 AN2

2
VDD VDD FBVDDQ FBVDDQ GND GND

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP
L20 AC22 G22 AB29 E9 AL30
VDD VDD FBVDDQ FBVDDQ GND GND
L21 AC21 G8 AB27 E12 AL27
VDD VDD FBVDDQ FBVDDQ GND GND

C8241

C8242

C8243

C8220
L22 AC20 G9 AA31 E15 AL24

1
VDD VDD FBVDDQ FBVDDQ GND GND
L23 AC19 H29 AA29 E18 AL21
VDD VDD FBVDDQ FBVDDQ GND GND
L24 AC18 J14 AA27 E24 AL18
VDD VDD FBVDDQ FBVDDQ GND GND

SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

SC4700P50V2KX-1GP

SC4700P50V2KX-1GP
L25 AC17 J15 Y27 E27 AL15

2
VDD VDD FBVDDQ FBVDDQ GND GND
M12 AC16 J16 W27 E30 AL12
VDD VDD FBVDDQ FBVDDQ GND GND

C8256

C8258

C8257

C8262

C8263
M14 AC15 J17 V34 F2 AL9

1
VDD VDD FBVDDQ FBVDDQ GND GND
M16 AC14 J20 V29 F31 AL6
VDD VDD FBVDDQ FBVDDQ GND GND
M18 AC13 J21 V27 F34 AK34
VDD VDD FBVDDQ FBVDDQ GND GND
M20 AC12 J22 U29 F5 AK31

2
VDD VDD FBVDDQ FBVDDQ +1.5V_RUN_GPU GND GND
M22
VDD VDD
AC11 J23
FBVDDQ FBVDDQ
U27 Place near GPU J2
GND GND
AK14
M24 AB25 J24 T27 J5 AK5
VDD VDD FBVDDQ FBVDDQ GND GND
P11 AB23 J29 R27 J31 AK2
VDD VDD FBVDDQ FBVDDQ GND GND

SC4D7U6D3V3KX-GP
C8219
P13 AB21 N27 P27 J34 AG34

1
VDD VDD FBVDDQ FBVDDQ GND GND
P15 AB19 K9 AG31
VDD VDD GND GND

SCD022U25V2KX-GP

SCD022U25V2KX-GP

SCD022U25V2KX-GP

SCD022U25V2KX-GP
P17 AB17 L9 AG5
VDD VDD N10P-GB1-128-GP GND GND
P19 AB15 M2 AG2

2
VDD VDD GND GND

C8264

C8265

C8266

C8267
P21 AB13 M5 AE25

1
VDD VDD GND GND
P23 AB11 M11 AE24
VDD VDD GND GND
Place near GPU P25
VDD VDD
Y24 M13
GND GND
AE23
R11 Y22 M15 AE22

2
VDD VDD GND GND
R12 Y20 M17 AE21
SC4D7U6D3V3KX-GP

VDD VDD GND GND

C8240

R13 Y18 M19 AE20

VDD VDD GND GND
R14 Y16 M21 AE19
1

VDD VDD GND GND

R15 Y14 Revised decoupling C 2009/05/28 M23 AE18
VDD VDD GND GND
R16 Y12 M25 AE17
VDD VDD GND GND

C8233

C8212

C8214

C8215
R17 W25 M31 AE16

SC1U6D3V2KX-GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP
SC4D7U6D3V3KX-GP
2

1
VDD VDD GND GND
R18 W24 M34 AE15
VDD VDD GND GND
R19 W23 N11 AE14
VDD VDD GND GND
R20 W22 N12 AE13

2
VDD VDD GND GND
R21 W21 N13 AE12
VDD VDD GND GND
R22 W20 N14 AE11
VDD VDD GND GND
R23 W19 N15 AD34
VDD VDD GND GND
C R24 W18 N16 AD31 C
VDD VDD GND GND
R25 W17 N17 AD25
VDD VDD GND GND
T12 W16 N18 AD23
VDD VDD GND GND
T14 W15 N19 AD21
VDD VDD GND GND
T16 W14 N20 AD17
VDD VDD GND GND
T18
T20
VDD VDD
W13
W12
Revised decoupling C 2009/05/28 N21
N22
GND GND
AD15
AD13
VDD VDD GND GND
T22 W11 N23 AD11
VDD VDD +3.3V_RUN_GPU GND GND
T24
VDD VDD
V25 Place under GPU Place near GPU N24
GND GND
AD5
V11 N25 AD2
VDD GND GND
V13 J13 P12 AC9
VDD VDD33 GND GND
C8229

C8230

C8232

C8211

C8231
V15 J12 P14 AB24

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP
1

1
VDD VDD33 GND GND
V17 J11 P16 AB22
VDD VDD33 GND GND
V19 J10 P18 AB20
VDD VDD33 GND GND
V21 J9 P20 AB18
2

2
VDD VDD33 GND GND
+VCC_GFX_CORE V23
VDD
P22
GND GND
AB16
P24 AB14
R8201 2 VDD_SENSE GND GND
0R2J-2-GP DY 1 AD20
VDD_SENSE VID_PLLVDD
AD9 R2
R5
GND GND
AB12
AA34
GND GND
R31 AA25
N10P-GB1-128-GP GND GND
+GPU_PLLVDD R34 AA24
GND GND
Layout notice: T11
GND GND
AA23
VDD_SENSE need check layout SPEC. T13 AA22
GND GND
T15 AA21
GND GND
T17 AA20
GND GND
T19 AA19
GND GND
T21 AA18
GND GND
T23 AA17
GND GND
T25 AA16
GND GND
U11 AA15
GND GND
U12 AA14
GND GND
U13 AA13
GND GND
U14 AA12
GND GND
U15 AA11
GND GND
U16 AA5
GND GND
U17 AA2
GND GND
U18 Y25
GND GND
U19 Y23
GND GND
U20 Y21
GND GND
U21 Y19
GND GND
U22 Y17
B GND GND B
U23 Y15
U8001D 4 OF 10 U8001H 8 OF 10 GND GND
U24 Y13
GND GND
U25 Y11
GND GND
N1 Y1 A2 L29 V2 V31
MIOA_D0 MIOB_D0 NC#A2 NC#L29 GND GND
P4 Y2 A7 AL7 V5 V24
MIOA_D1 MIOB_D1 NC#A7 NC#AL7 GND GND
P1 Y3 B7 AK15 V9 V22
MIOA_D2 MIOB_D2 NC#B7 NC#AK15 GND GND
P2 AB3 C5 AJ5 V12 V20
MIOA_D3 MIOB_D3 NC#C5 NC#AJ5 GND GND
P3 AB2 C7 AH29 V14 V18
MIOA_D4 MIOB_D4 NC#C7 NC#AH29 GND GND
T3 AB1 D5 AG29 V16
MIOA_D5 MIOB_D5 NC#D5 NC#AG29 GND
T2 AC4 D6 AG20 AD19
MIOA_D6 MIOB_D6 NC#D6 NC#AG20 GND_SENSE
T1 AC1 D7 AG6
MIOA_D7 MIOB_D7 Do Not Stuff TP8201 TP_VDD_SENSE NC#D7 NC#AG6
U4 AC2 1 D35 AF6
MIOA_D8 MIOB_D8 NC#D35 NC#AF6 N10P-GB1-128-GP
U1 AC3 E5 AE29
MIOA_D9 MIOB_D9 NC#E5 NC#AE29
U2 AE3 E7 AD29
MIOA_D10 MIOB_D10 NC#E7 NC#AD29
U3 AE2 E35 AD6
MIOA_D11 MIOB_D11 NC#E35 NC#AD6
R6 U6 F4 AC5
MIOA_D12 MIOB_D12 NC#F4 NC#AC5
T6 W6 F7 AB7
MIOA_D13 MIOB_D13 NC#F7 NC#AB7
N6 Y6 +3.3V_RUN_GPU G5 AB4
R8240 MIOA_D14 MIOB_D14 R8239 NC#G5 NC#AB4
G11 AA4
10KR2J-3-GP 10KR2J-3-GP NC#G11 NC#AA4
G12 Y4

1
NC#G12 NC#Y4

C8246
SCD01U16V2KX-3GP
2 1 MIOA_CLKIN N4 AE1 MIOB_CLKIN 2 1 G14 V6
MIOA_CLKIN MIOB_CLKIN NC#G14 NC#V6
G15 U7
NC#G15 NC#U7
R4 V4 G27 R29

2
MIOA_CLKOUT MIOB_CLKOUT NC#G27 NC#R29
T4 W4 G28 R7
MIOA_CLKOUT# MIOB_CLKOUT# NC#G28 NC#R7
G24 P29
NC#G24 NC#P29
G25 P7
NC#G25 NC#P7 TP_VDD_SENSE TP8202 Do Not Stuff
U5 AA7 H32 P6 1
MIOA_CAL_PD_VDDQMIOB_CAL_PD_VDDQ NC#H32 NC#P6
T5 AA6 J18 M29
MIOA_CAL_PU_GND MIOB_CAL_PU_GND NC#J18 NC#M29
J19 M7
NC#J19 NC#M7
J25 J26
NC#J25 NC#J26
L3 W2
MIOA_VSYNC MIOB_VSYNC 2009/07/28
N3 W1
+3.3V_RUN_GPU MIOA_HSYNC MIOB_HSYNC +3.3V_RUN_GPU Added 8246 CAP. N10P-GB1-128-GP

P9 AA9
SCD1U10V2KX-4GP

MIOA_VDDQ MIOB_VDDQ
R9 AB9
SCD1U10V2KX-4GP

MIOA_VDDQ MIOB_VDDQ
C8237

T9 W9
1

MIOA_VDDQ MIOB_VDDQ
C8238

U9 Y9
1

MIOA_VDDQ MIOB_VDDQ
2

P5 W3
2

A MIOA_CTL3 MIOB_CTL3 A
N2 Y5
MIOA_DE MIOB_DE
N5 AF1
MIOA_VREF MIOB_VREF

N10P-GB1-128-GP

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-POWER/GND(3/4)
Size Document Number Rev
A2 Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 82 of 90
5 4 3 2 1
 5 4 3 2 1

Strap pin resistor need use 1% resistor (NV Design Guide) +3.3V_RUN_GPU

SSID = VIDEO Strap pin define

45K3R2F-L-GP

34K8R2F-1-GP

4K99R2F-L-GP

4K99R2F-L-GP

4K99R2F-L-GP
1

1
U8001A 1 OF 10 U8001B 2 OF 10

10KR2F-2-GP
84,85 MDA[0..63] 89,90 MDC[0..63]

R8306

R8302

R8305

R8309

R8311

R8312
MDA0 L32 V32 FBA_CMD_0 MDC0 B13 C17 FBC_CMD_0
MDA1 N33
FBA_D0 FBA_CMD0
W31 FBA_CMD_1 FBA_CMD_0 84 MDC1 D13
FBC_D0 FBC_CMD0
B19 FBC_CMD_1 FBC_CMD_0 89 DY DY DY
FBA_D1 FBA_CMD1 FBA_CMD_1 84,85 FBC_D1 FBC_CMD1 FBC_CMD_1 89,90
MDA2 L33 U31 FBA_CMD_2 MDC2 A13 D18 FBC_CMD_2

2
FBA_D2 FBA_CMD2 FBA_CMD_2 84 FBC_D2 FBC_CMD2 FBC_CMD_2 89
MDA3 N34 Y32 FBA_CMD_3 MDC3 A14 F21 FBC_CMD_3
FBA_D3 FBA_CMD3 FBA_CMD_3 84,85 FBC_D3 FBC_CMD3 FBC_CMD_3 89,90
MDA4 N35 AB35 FBA_CMD_4 MDC4 C16 A23 FBC_CMD_4 STRAP0
FBA_D4 FBA_CMD4 FBA_CMD_4 84,85 FBC_D4 FBC_CMD4 FBC_CMD_4 89,90 81 STRAP0
MDA5 P35 AB34 FBA_CMD_5 MDC5 B16 D21 FBC_CMD_5
MDA6 FBA_D5 FBA_CMD5 FBA_CMD_6 FBA_CMD_5 84,85 MDC6 FBC_D5 FBC_CMD5 FBC_CMD_6 FBC_CMD_5 89,90 STRAP1
P33 W35 FBA_CMD_6 84,85 A17 B23 FBC_CMD_6 89,90 81 STRAP1
MDA7 FBA_D6 FBA_CMD6 FBA_CMD_7 MDC7 FBC_D6 FBC_CMD6 FBC_CMD_7
D P34 W33 FBA_CMD_7 84,85 D16 E20 FBC_CMD_7 89,90 D
MDA8 FBA_D7 FBA_CMD7 FBA_CMD_8 MDC8 FBC_D7 FBC_CMD7 FBC_CMD_8 STRAP2
K35 W30 FBA_CMD_8 84,85 C13 G21 FBC_CMD_8 89,90 81 STRAP2
MDA9 FBA_D8 FBA_CMD8 FBA_CMD_9 MDC9 FBC_D8 FBC_CMD8 FBC_CMD_9
K33 T34 FBA_CMD_9 84,85 B11 F20 FBC_CMD_9 89,90
MDA10 FBA_D9 FBA_CMD9 FBA_CMD_10 MDC10 FBC_D9 FBC_CMD9 FBC_CMD_10 ROM_SCLK_GPU
K34 T35 FBA_CMD_10 84,85 C11 F19 FBC_CMD_10 89,90 81 ROM_SCLK_GPU
MDA11 FBA_D10 FBA_CMD10 FBA_CMD_11 MDC11 FBC_D10 FBC_CMD10 FBC_CMD_11
H33 AB31 FBA_CMD_11 85 A11 F23 FBC_CMD_11 90
MDA12 FBA_D11 FBA_CMD11 FBA_CMD_12 MDC12 FBC_D11 FBC_CMD11 FBC_CMD_12 ROM_SI_GPU
G34 Y30 FBA_CMD_12 84,85 C10 A22 FBC_CMD_12 89,90 81 ROM_SI_GPU
MDA13 FBA_D12 FBA_CMD12 FBA_CMD_13 MDC13 FBC_D12 FBC_CMD12 FBC_CMD_13
G33 Y34 FBA_CMD_13 84,85 C8 C22 FBC_CMD_13 89,90
MDA14 FBA_D13 FBA_CMD13 FBA_CMD_14 MDC14 FBC_D13 FBC_CMD13 FBC_CMD_14 ROM_SO_GPU
E34 W32 FBA_CMD_14 84,85 B8 B17 FBC_CMD_14 89,90 81 ROM_SO_GPU
MDA15 FBA_D14 FBA_CMD14 FBA_CMD_15 TP8301 Do Not Stuff MDC15 FBC_D14 FBC_CMD14 FBC_CMD_15 TP8303
E33 AA30 1 A8 F24 1
MDA16 FBA_D15 FBA_CMD15 FBA_CMD_16 MDC16 FBC_D15 FBC_CMD15 FBC_CMD_16 Do Not Stuff
G31 AA32 FBA_CMD_16 85 E8 C25 FBC_CMD_16 90
MDA17 FBA_D16 FBA_CMD16 FBA_CMD_17 MDC17 FBC_D16 FBC_CMD16 FBC_CMD_17
F30 Y33 FBA_CMD_17 84,85 F8 E22 FBC_CMD_17 89,90
MDA18 FBA_D17 FBA_CMD17 FBA_CMD_18 MDC18 FBC_D17 FBC_CMD17 FBC_CMD_18
G30 U32 F10 C20

10KR2F-2-GP
4K99R2F-L-GP

4K99R2F-L-GP
FBA_CMD_18 84,85 FBC_CMD_18 89,90

1
MDA19 FBA_D18 FBA_CMD18 FBA_CMD_19 MDC19 FBC_D18 FBC_CMD18 FBC_CMD_19
G32 Y31 F9 B22

15KR2F-GP

20KR2F-L-GP

10KR2F-2-GP
FBA_D19 FBA_CMD19 FBA_CMD_19 84,85 FBC_D19 FBC_CMD19 FBC_CMD_19 89,90
MDA20 FBA_CMD_20 MDC20 FBC_CMD_20

R8307

R8301

R8316

R8304

R8308

R8313
K30 U34 FBA_CMD_20 84,85 F12 A19 FBC_CMD_20 89,90
MDA21 FBA_D20 FBA_CMD20 FBA_CMD_21 MDC21 FBC_D20 FBC_CMD20 FBC_CMD_21
K32 Y35 D8 D22
MDA22 H30
FBA_D21 FBA_CMD21
W34 FBA_CMD_22 FBA_CMD_21 84,85 MDC22 D11
FBC_D21 FBC_CMD21
D20 FBC_CMD_22 FBC_CMD_21 89,90 DY DY DY
FBA_D22 FBA_CMD22 FBA_CMD_22 84,85 FBC_D22 FBC_CMD22 FBC_CMD_22 89,90
MDA23 K31 V30 FBA_CMD_23 1 TP8302 Do Not Stuff MDC23 E11 E19 FBC_CMD_23 1 TP8304

2
MDA24 FBA_D23 FBA_CMD23 FBA_CMD_24 MDC24 FBC_D23 FBC_CMD23 FBC_CMD_24 Do Not Stuff
L31 U35 FBA_CMD_24 84,85 D12 D19 FBC_CMD_24 89,90
MDA25 FBA_D24 FBA_CMD24 FBA_CMD_25 MDC25 FBC_D24 FBC_CMD24 FBC_CMD_25
L30 U30 FBA_CMD_25 84 E13 F18 FBC_CMD_25 89
MDA26 FBA_D25 FBA_CMD25 FBA_CMD_26 MDC26 FBC_D25 FBC_CMD25 FBC_CMD_26
M32 U33 FBA_CMD_26 84,85 F13 C19 FBC_CMD_26 89,90
MDA27 FBA_D26 FBA_CMD26 FBA_CMD_27 MDC27 FBC_D26 FBC_CMD26 FBC_CMD_27
N30 AB30 FBA_CMD_27 85 F14 F22 FBC_CMD_27 90
MDA28 FBA_D27 FBA_CMD27 FBA_CMD_28 MDC28 FBC_D27 FBC_CMD27 FBC_CMD_28
M30 AB33 FBA_CMD_28 84,85 F15 C23 FBC_CMD_28 89,90
MDA29 FBA_D28 FBA_CMD28 FBA_CMD_29 MDC29 FBC_D28 FBC_CMD28 FBC_CMD_29
P31 T33 FBA_CMD_29 84,85 E16 B20 FBC_CMD_29 89,90
MDA30 FBA_D29 FBA_CMD29 FBA_CMD_30 MDC30 FBC_D29 FBC_CMD29 FBC_CMD_30
R32 W29 FBA_CMD_30 84,85 F16 A20 FBC_CMD_30 89,90
MDA31 FBA_D30 FBA_CMD30 MDC31 FBC_D30 FBC_CMD30
R30 F17
MDA32 FBA_D31 MDC32 FBC_D31
AG30 D29
MDA33 FBA_D32 DQMA#0 MDC33 FBC_D32 DQMC#0
AG32 P32 DQMA#0 84 F27 A16 DQMC#0 89
MDA34 FBA_D33 FBA_DQM0 DQMA#1 MDC34 FBC_D33 FBC_DQM0 DQMC#1
AH31
FBA_D34 FBA_DQM1
H34 DQMA#1 84 F28
FBC_D34 FBC_DQM1
D10 DQMC#1 89 Resistor Value
MDA35 AF31 J30 DQMA#2 MDC35 E28 F11 DQMC#2 Strap pin Strap pin define Default Setting
FBA_D35 FBA_DQM2 DQMA#2 84 FBC_D35 FBC_DQM2 DQMC#2 89
MDA36 AF30 P30 DQMA#3 MDC36 D26 D15 DQMC#3
FBA_D36 FBA_DQM3 DQMA#3 84 FBC_D36 FBC_DQM3 DQMC#3 89
MDA37 AE30 AF32 DQMA#4 MDC37 F25 D27 DQMC#4 Pull-up Pull-low
FBA_D37 FBA_DQM4 DQMA#4 85 FBC_D37 FBC_DQM4 DQMC#4 90
MDA38 AC32 AL32 DQMA#5 MDC38 D24 D34 DQMC#5
MDA39 FBA_D38 FBA_DQM5 DQMA#6 DQMA#5 85 MDC39 FBC_D38 FBC_DQM5 DQMC#6 DQMC#5 90
AD30
FBA_D39 FBA_DQM6
AL34 DQMA#6 85 E25
FBC_D39 FBC_DQM6
A34 DQMC#6 90
R8305
MDA40 AN33 AF35 DQMA#7 MDC40 E32 D28 DQMC#7 N11P-GE1
FBA_D40 FBA_DQM7 DQMA#7 85 FBC_D40 FBC_DQM7 DQMC#7 90
MDA41 AL31 MDC41 F32 N11P-GE1 R8316
MDA42 FBA_D41 MDC42 FBC_D41 10K ohm
AM33
FBA_D42
D33
FBC_D42 STRAP2 PCI_DEVID[3:0] 1 0 0 1 DY
MDA43 AL33 L35 QSA#0 MDC43 E31 B14 QSC#0 N10P-GE
MDA44 FBA_D43 FBA_DQS_RN0 QSA#1
QSA#0 84
MDC44 FBC_D43 FBC_DQS_RN0 QSC#1
QSC#0 89 N10P-GE 5K ohm
AK30 G35 QSA#1 84 C33 B10 QSC#1 89
MDA45 FBA_D44 FBA_DQS_RN1 QSA#2 MDC45 FBC_D44 FBC_DQS_RN1 QSC#2 1 0 0 0
AK32 H31 QSA#2 84 F29 D9 QSC#2 89
MDA46 FBA_D45 FBA_DQS_RN2 QSA#3 MDC46 FBC_D45 FBC_DQS_RN2 QSC#3
AJ30 N32 QSA#3 84 D30 E14 QSC#3 89
MDA47 FBA_D46 FBA_DQS_RN3 QSA#4 MDC47 FBC_D46 FBC_DQS_RN3 QSC#4
AH30
FBA_D47 FBA_DQS_RN4
AD32 QSA#4 85 E29
FBC_D47 FBC_DQS_RN4
F26 QSC#4 90
R8308
C MDA48 AH33 AJ31 QSA#5 MDC48 B29 D31 QSC#5 SAMSUNG SAMSUNG C
FBA_D48 FBA_DQS_RN5 QSA#5 85 FBC_D48 FBC_DQS_RN5 QSC#5 90
MDA49 AH35 AJ35 QSA#6 MDC49 C31 A31 QSC#6 ROM_SI_GPU RAM_CFG[3:0] 0 0 1 1 R8311
MDA50 FBA_D49 FBA_DQS_RN6 QSA#7
QSA#6 85
MDC50 FBC_D49 FBC_DQS_RN6 QSC#7
QSC#6 90 20K ohm
AH34 AC34 QSA#7 85 C29 A26 QSC#7 90 HYNIX DY
MDA51 FBA_D50 FBA_DQS_RN7 MDC51 FBC_D50 FBC_DQS_RN7 HYNIX
AH32 B31
MDA52 FBA_D51 MDC52 FBC_D51 QSC0 0 0 1 0 15k OHM
AJ33 C32 C14 QSC0 89
MDA53 FBA_D52 QSA0 MDC53 FBC_D52 FBC_DQS_WP0 QSC1
AL35 L34 QSA0 84 B32 A10 QSC1 89
MDA54 FBA_D53 FBA_DQS_WP0 QSA1 MDC54 FBC_D53 FBC_DQS_WP1 QSC2
AM34 H35 QSA1 84 B35 E10 QSC2 89
MDA55 FBA_D54 FBA_DQS_WP1 QSA2 MDC55 FBC_D54 FBC_DQS_WP2 QSC3
AM35 J32 QSA2 84 B34 D14 QSC3 89
MDA56 FBA_D55 FBA_DQS_WP2 QSA3 MDC56 FBC_D55 FBC_DQS_WP3 QSC4
AF33 N31 QSA3 84 A29 E26 QSC4 90
MDA57 FBA_D56 FBA_DQS_WP3 QSA4 MDC57 FBC_D56 FBC_DQS_WP4 QSC5
AE32 AE31 QSA4 85 B28 D32 QSC5 90
MDA58 FBA_D57 FBA_DQS_WP4 QSA5 MDC58 FBC_D57 FBC_DQS_WP5 QSC6
AF34 AJ32 QSA5 85 A28 A32 QSC6 90
MDA59 FBA_D58 FBA_DQS_WP5 QSA6 MDC59 FBC_D58 FBC_DQS_WP6 QSC7
AE35 AJ34 QSA6 85 C28 B26 QSC7 90
MDA60 FBA_D59 FBA_DQS_WP6 QSA7 MDC60 FBC_D59 FBC_DQS_WP7
AE34 AC33 QSA7 85 C26
MDA61 FBA_D60 FBA_DQS_WP7 MDC61 FBC_D60
AE33 D25
MDA62 FBA_D61 MDC62 FBC_D61 CLKC0
AB32 B25 E17
2009/07/28 MDA63 FBA_D62 CLKA0 MDC63 FBC_D62 FBC_CLK0 CLKC0# CLKC0 89
AC35 T32 A25 D17
Change power rail to +1.5V_RUN_GPU FBA_D63 FBA_CLK0 CLKA0# CLKA0 84 FBC_D63 FBC_CLK0# CLKC0# 89
T31
FBA_CLK0# CLKA0# 84 CLKC1
D23
40D2R2F-GP FB_CAL_PU_GND CLKA1 FBC_CLK1 CLKC1# CLKC1 90
2 1R8303 L27 AC31 G19 E23
40D2R2F-GP FB_CAL_PD_VDDQ FB_CAL_PU_GND FBA_CLK1 CLKA1# CLKA1 85 FBC_DEBUG FBC_CLK1# CLKC1# 90
+1.5V_RUN_GPU 2 1R8314 K27 AC30
40D2R2F-GP FB_CAL_TERM_GND M27 FB_CAL_PD_VDDQ FBA_CLK1# CLKA1# 85
2 1R8315
FB_CAL_TERM_GND N10P-GB1-128-GP
T30
FBA_DEBUG
L8301 AF27
FB_PLLAVDD0
16mil AG27 J27
+FB_PLLVDD FB_DLLAVDD0 FB_REF
+1.05V_GFX_PCIE 1 2 nVIDIA recommend
BLM18SG331TN1D-GP
N10P-GB1-128-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1

1
C8302

C8301

Place near GPU

2

FB_PLLAVDD+FB_DLLAVDD=100mA

B B

A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-MEMORY(5/5)
Size Document Number Rev
A2 Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 83 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
+1.5V_RUN_GPU +1.5V_RUN_GPU
MDA[0..63] 83,85 MDA[0..63] 83,85
U8401 U8402

K8 E3 MDA11 K8 E3 MDA0
VDD DQL0 MDA13 VDD DQL0 MDA5
K2 F7 K2 F7
VDD DQL1 MDA9 VDD DQL1 MDA2
N1 F2 N1 F2
VDD DQL2 MDA12 VDD DQL2 MDA4
R9 F8 R9 F8
VDD DQL3 MDA8 VDD DQL3 MDA3
B2 H3 B2 H3
VDD DQL4 MDA14 VDD DQL4 MDA7
D9 H8 D9 H8
VDD DQL5 MDA10 VDD DQL5 MDA1
G7 G2 G7 G2
VDD DQL6 MDA15 VDD DQL6 MDA6
R1 H7 MDA[0..63] 83,85 R1 H7 MDA[0..63] 83,85
VDD DQL7 VDD DQL7
D N9 N9 D
VDD MDA26 VDD MDA22
D7 D7
DQU0 MDA29 DQU0 MDA18
A8 C3 A8 C3
+1.5V_RUN_GPU VDDQ DQU1 MDA24 +1.5V_RUN_GPU VDDQ DQU1 MDA23
A1 C8 A1 C8
VDDQ DQU2 MDA31 VDDQ DQU2 MDA16
C1 C2 C1 C2
VDDQ DQU3 MDA28 VDDQ DQU3 MDA20
C9 A7 C9 A7
1

1
VDDQ DQU4 MDA30 VDDQ DQU4 MDA19
D2 A2 D2 A2
VDDQ DQU5 MDA25 VDDQ DQU5 MDA21
E9 B8 E9 B8
R8404 VDDQ DQU6 MDA27 R8403 VDDQ DQU6 MDA17
F1 A3 F1 A3
1KR2F-3-GP VDDQ DQU7 1KR2F-3-GP VDDQ DQU7
H9 H9
VDDQ QSA3 VDDQ QSA2
H2 C7 H2 C7
2

2
VDDQ DQSU QSA3 83 VDDQ DQSU QSA2 83
B7 QSA#3 B7 QSA#2
DQSU# QSA#3 83 DQSU# QSA#2 83
VREFA1 H1 VREFA2 H1
VREFDQ QSA1 VREFDQ QSA0
M8 F3 QSA1 83 M8 F3 QSA0 83
VREFCA DQSL VREFCA DQSL
1 2 ZQ_VRAMA11 L8 G3 QSA#1 1 2 ZQ_VRAMA12 L8 G3 QSA#0
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
QSA#1 83 QSA#0 83
1

1
ZQ DQSL# ZQ DQSL#
C8420

C8421
R8406 243R2F-2-GP R8407 243R2F-2-GP
1

1
K1 FBA_CMD_25 K1 FBA_CMD_25
ODT FBA_CMD_25 83 ODT FBA_CMD_25 83
R8401 FBA_CMD_7 N3 R8402 FBA_CMD_7 N3
83,85 FBA_CMD_7 83,85 FBA_CMD_7

1
1KR2F-3-GP FBA_CMD_20 A0 1KR2F-3-GP FBA_CMD_20 A0
P7 P7
2

2
83,85 FBA_CMD_20 A1 83,85 FBA_CMD_20 A1
FBA_CMD_4 P3 L2 FBA_CMD_2 R8409 FBA_CMD_4 P3 L2 FBA_CMD_2
83,85 FBA_CMD_4 FBA_CMD_2 83 83,85 FBA_CMD_4 FBA_CMD_2 83
2

2
FBA_CMD_14 A2 CS# FBA_CMD_28 FBA_CMD_14 A2 CS# FBA_CMD_28
83,85 FBA_CMD_14 N2 T2 FBA_CMD_28 83,85 10KR2J-3-GP 83,85 FBA_CMD_14 N2 T2 FBA_CMD_28 83,85
FBA_CMD_17 A3 RESET# FBA_CMD_17 A3 RESET#
83,85 FBA_CMD_17 P8 83,85 FBA_CMD_17 P8
FBA_CMD_6 A4 R8410 1 FBA_CMD_6 A4
P2 210KR2J-3-GP P2

2
83,85 FBA_CMD_6 A5 83,85 FBA_CMD_6 A5
FBA_CMD_26 R8 T7 FBA_CMD_26 R8 T7 FBA_CMD_29
83,85 FBA_CMD_26 FBA_CMD_3 A6 NC#T7 83,85 FBA_CMD_26 FBA_CMD_3 A6 NC#T7 FBA_CMD_29 83,85
83,85 FBA_CMD_3 R2 L9 83,85 FBA_CMD_3 R2 L9
FBA_CMD_1 A7 NC#L9 FBA_CMD_29 FBA_CMD_1 A7 NC#L9
83,85 FBA_CMD_1 T8 L1 FBA_CMD_29 83,85 83,85 FBA_CMD_1 T8 L1
FBA_CMD_10 A8 NC#L1 FBA_CMD_10 A8 NC#L1
83,85 FBA_CMD_10 R3 J9 83,85 FBA_CMD_10 R3 J9
FBA_CMD_21 A9 NC#J9 FBA_CMD_21 A9 NC#J9
83,85 FBA_CMD_21 L7 J1 83,85 FBA_CMD_21 L7 J1
FBA_CMD_5 A10/AP NC#J1 FBA_CMD_5 A10/AP NC#J1
83,85 FBA_CMD_5 R7 83,85 FBA_CMD_5 R7
FBA_CMD_22 A11 FBA_CMD_22 A11
83,85 FBA_CMD_22 N7 83,85 FBA_CMD_22 N7
FBA_CMD_18 A12/BC# FBA_CMD_18 A12/BC#
83,85 FBA_CMD_18 T3 J8 83,85 FBA_CMD_18 T3 J8
FBA_CMD_30 A13 VSS FBA_CMD_30 A13 VSS
83,85 FBA_CMD_30 M7 M1 83,85 FBA_CMD_30 M7 M1
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
FBA_CMD_12 VSS CLKA0 FBA_CMD_12 VSS
83,85 FBA_CMD_12 M2 P9 83,85 FBA_CMD_12 M2 P9
FBA_CMD_9 BA0 VSS FBA_CMD_9 BA0 VSS
83,85 FBA_CMD_9 N8 G8 83,85 FBA_CMD_9 N8 G8
FBA_CMD_13 BA1 VSS FBA_CMD_13 BA1 VSS
83,85 FBA_CMD_13 M3 B3 83,85 FBA_CMD_13 M3 B3

1
BA2 VSS BA2 VSS
T1 T1
VSS R8418 VSS
A9 A9
CLKA0 VSS 243R2F-2-GP CLKA0 VSS
83 CLKA0 J7 T9 83 CLKA0 J7 T9
CLKA0# CK VSS CLKA0# CK VSS
83 CLKA0# K7 E1 83 CLKA0# K7 E1
CK# VSS CK# VSS
C P1 P1 C

2
FBA_CMD_0 VSS FBA_CMD_0 VSS
83 FBA_CMD_0 K9 83 FBA_CMD_0 K9
1

CKE CLKA0# CKE

G1 G1
VSSQ VSSQ
R8411

F9 F9
10KR2J-3-GP

DQMA#3 VSSQ DQMA#2 VSSQ

83 DQMA#3 D3 E8 83 DQMA#2 D3 E8
DQMA#1 DMU VSSQ DQMA#0 DMU VSSQ
83 DQMA#1 E7 E2 83 DQMA#0 E7 E2
DML VSSQ DML VSSQ
D8 D8
2

VSSQ VSSQ
D1 D1
FBA_CMD_19 VSSQ FBA_CMD_19 VSSQ
83,85 FBA_CMD_19 L3 B9 83,85 FBA_CMD_19 L3 B9
FBA_CMD_8 WE# VSSQ FBA_CMD_8 WE# VSSQ
83,85 FBA_CMD_8 K3 B1 83,85 FBA_CMD_8 K3 B1
FBA_CMD_24 CAS# VSSQ FBA_CMD_24 CAS# VSSQ
83,85 FBA_CMD_24 J3 G9 83,85 FBA_CMD_24 J3 G9
RAS# VSSQ RAS# VSSQ

K4W1G1646E-HC12-GP
Close to VRAM side K4W1G1646E-HC12-GP

64X16 SAMSUNG K4W1G1646E-HC12 P/N:72.41164.H0U

64X16 HYNIX H5TQ1G63BFR-12C P/N:72.51G63.C0U

+1.5V_RUN_GPU +1.5V_RUN_GPU
Place under / near VRAM Place under / near VRAM
SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP
C8422

C8423

C8424

C8425

C8427

C8426

C8428

C8429
1

1
2

2
B B

+1.5V_RUN_GPU +1.5V_RUN_GPU
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
C8404

C8408

C8410

C8411

C8412

C8405

C8409

C8414

C8415

C8413
2

2
A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VRAM(1/2)
Size Document Number Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 84 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

+1.5V_RUN_GPU
+1.5V_RUN_GPU
U8501
MDA[0..63] 83,84
U8502
MDA[0..63] 83,84
K8 E3 MDA53
VDD DQL0 MDA49 MDA38
K2 F7 K8 E3
VDD DQL1 MDA52 VDD DQL0 MDA35
N1 F2 K2 F7
VDD DQL2 MDA48 VDD DQL1 MDA39
R9 F8 N1 F2
VDD DQL3 MDA54 VDD DQL2 MDA33
B2 H3 R9 F8
VDD DQL4 MDA50 VDD DQL3 MDA36
D9 H8 B2 H3
VDD DQL5 MDA55 VDD DQL4 MDA32
G7 G2 MDA[0..63] 83,84 D9 H8
VDD DQL6 MDA51 VDD DQL5 MDA37
D R1 H7 G7 G2 MDA[0..63] 83,84 D
VDD DQL7 VDD DQL6 MDA34
N9 R1 H7
VDD MDA57 VDD DQL7
D7 N9
DQU0 MDA63 VDD MDA41
A8 C3 D7
+1.5V_RUN_GPU VDDQ DQU1 MDA59 DQU0 MDA44
A1 C8 A8 C3
VDDQ DQU2 MDA62 +1.5V_RUN_GPU VDDQ DQU1 MDA42
C1 C2 A1 C8
VDDQ DQU3 MDA61 VDDQ DQU2 MDA47
C9 A7 C1 C2
1

VDDQ DQU4 MDA58 VDDQ DQU3 MDA43

D2 A2 C9 A7

1
VDDQ DQU5 MDA60 VDDQ DQU4 MDA45
E9 B8 D2 A2
R8510 VDDQ DQU6 MDA56 VDDQ DQU5 MDA40
F1 A3 E9 B8
1KR2F-3-GP VDDQ DQU7 R8501 VDDQ DQU6 MDA46
H9 F1 A3
VDDQ QSA7 1KR2F-3-GP VDDQ DQU7
H2 C7 H9
2

VDDQ DQSU QSA7 83 VDDQ

B7 QSA#7 H2 C7 QSA5

2
DQSU# QSA#7 83 VDDQ DQSU QSA5 83
VREFA3 H1 B7 QSA#5
VREFDQ QSA6 VREFA4 DQSU# QSA#5 83
M8 F3 QSA6 83 H1
VREFCA DQSL VREFDQ
1 2 ZQ_VRAMA21 L8 G3 QSA#6 M8 F3 QSA4
SCD01U16V2KX-3GP

QSA#6 83 QSA4 83
1

ZQ DQSL# VREFCA DQSL

2 ZQ_VRAMA22 QSA#4
C8503

R8509 243R2F-2-GP 1 L8 G3

SCD01U16V2KX-3GP
QSA#4 83
1

1
FBA_CMD_16 ZQ DQSL#

C8506
K1 R8503 243R2F-2-GP
FBA_CMD_16 83

1
R8507 FBA_CMD_22 ODT FBA_CMD_16
83,84 FBA_CMD_22 N3 K1 FBA_CMD_16 83
1KR2F-3-GP FBA_CMD_4 A0 R8504 FBA_CMD_22 ODT
83,84 FBA_CMD_4 P7 83,84 FBA_CMD_22 N3
2

1
FBA_CMD_20 A1 FBA_CMD_11 1KR2F-3-GP FBA_CMD_4 A0
P3 L2 P7
2

2
83,84 FBA_CMD_20 A2 CS# FBA_CMD_11 83 83,84 FBA_CMD_4 A1
FBA_CMD_9 N2 T2 FBA_CMD_28 R8506 FBA_CMD_20 P3 L2 FBA_CMD_11

2
83,84 FBA_CMD_9 A3 RESET# FBA_CMD_28 83,84 83,84 FBA_CMD_20 A2 CS# FBA_CMD_11 83
FBA_CMD_6 P8 10KR2J-3-GP FBA_CMD_9 N2 T2 FBA_CMD_28
83,84 FBA_CMD_6 A4 83,84 FBA_CMD_9 A3 RESET# FBA_CMD_28 83,84
FBA_CMD_17 P2 FBA_CMD_6 P8
83,84 FBA_CMD_17 FBA_CMD_3 A5 FBA_CMD_18 83,84 FBA_CMD_6 FBA_CMD_17 A4
83,84 FBA_CMD_3 R8 T7 FBA_CMD_18 83,84 83,84 FBA_CMD_17 P2

2
FBA_CMD_26 A6 NC#T7 FBA_CMD_3 A5 FBA_CMD_18
83,84 FBA_CMD_26 R2 L9 83,84 FBA_CMD_3 R8 T7 FBA_CMD_18 83,84
FBA_CMD_1 A7 NC#L9 FBA_CMD_26 A6 NC#T7
83,84 FBA_CMD_1 T8 L1 83,84 FBA_CMD_26 R2 L9
FBA_CMD_5 A8 NC#L1 FBA_CMD_1 A7 NC#L9
83,84 FBA_CMD_5 R3 J9 83,84 FBA_CMD_1 T8 L1
FBA_CMD_19 A9 NC#J9 FBA_CMD_5 A8 NC#L1
83,84 FBA_CMD_19 L7 J1 83,84 FBA_CMD_5 R3 J9
FBA_CMD_10 A10/AP NC#J1 FBA_CMD_19 A9 NC#J9
83,84 FBA_CMD_10 R7 83,84 FBA_CMD_19 L7 J1
FBA_CMD_7 A11 FBA_CMD_10 A10/AP NC#J1
83,84 FBA_CMD_7 N7 83,84 FBA_CMD_10 R7
FBA_CMD_29 A12/BC# FBA_CMD_7 A11
83,84 FBA_CMD_29 T3 J8 83,84 FBA_CMD_7 N7
FBA_CMD_13 A13 VSS FBA_CMD_29 A12/BC#
83,84 FBA_CMD_13 M7 M1 83,84 FBA_CMD_29 T3 J8
NC#M7 VSS FBA_CMD_13 A13 VSS
M9 83,84 FBA_CMD_13 M7 M1
VSS NC#M7 VSS
J2 M9
FBA_CMD_12 VSS CLKA1 VSS
83,84 FBA_CMD_12 M2 P9 J2
FBA_CMD_14 BA0 VSS FBA_CMD_12 VSS
83,84 FBA_CMD_14 N8 G8 83,84 FBA_CMD_12 M2 P9
FBA_CMD_30 BA1 VSS FBA_CMD_14 BA0 VSS
83,84 FBA_CMD_30 M3 B3 83,84 FBA_CMD_14 N8 G8

1
BA2 VSS FBA_CMD_30 BA1 VSS
T1 83,84 FBA_CMD_30 M3 B3
VSS R8517 BA2 VSS
A9 T1
CLKA1 VSS 243R2F-2-GP VSS
83 CLKA1 J7 T9 A9
CLKA1# CK VSS CLKA1 VSS
C
83 CLKA1# K7 E1 83 CLKA1 J7 T9 C
CK# VSS CLKA1# CK VSS
P1 K7 E1

2
VSS 83 CLKA1# CK# VSS
FBA_CMD_27 K9 CLKA1# P1
83 FBA_CMD_27 CKE VSS
G1 FBA_CMD_27 K9
83 FBA_CMD_27
1

VSSQ CKE
F9 G1
R8508 DQMA#7 VSSQ VSSQ
83 DQMA#7 D3 E8 F9
DQMA#6 DMU VSSQ DQMA#5 VSSQ
10KR2J-3-GP 83 DQMA#6 E7 E2 83 DQMA#5 D3 E8
DML VSSQ DQMA#4 DMU VSSQ
D8 83 DQMA#4 E7 E2
VSSQ DML VSSQ
D1 D8
2

FBA_CMD_21 VSSQ VSSQ

83,84 FBA_CMD_21 L3 B9 D1
FBA_CMD_8 WE# VSSQ FBA_CMD_21 VSSQ
83,84 FBA_CMD_8 K3 B1 83,84 FBA_CMD_21 L3 B9
FBA_CMD_24 CAS# VSSQ FBA_CMD_8 WE# VSSQ
83,84 FBA_CMD_24 J3 G9 83,84 FBA_CMD_8 K3 B1
RAS# VSSQ FBA_CMD_24 CAS# VSSQ
83,84 FBA_CMD_24 J3 G9
RAS# VSSQ
K4W1G1646E-HC12-GP
Close to VRAM side
K4W1G1646E-HC12-GP

+1.5V_RUN_GPU
Place under / near VRAM +1.5V_RUN_GPU
Place under / near VRAM
SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP
C8534

C8533

C8531

C8532

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP
1

C8538

C8537

C8536

C8535
1

1
2

2
B B

+1.5V_RUN_GPU
+1.5V_RUN_GPU
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C8520

C8519

C8518

C8517

C8516

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

C8525

C8524

C8523

C8522

C8521
1

1
2

2
A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VRAM
Size Document Number Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 85 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_GFX
+PWR_SRC +PWR_SRC_GFX_CORE
Vout=0.704V*(R1+R2)/R2
PG8617
1 2

Do Not Stuff
D PG8613 +PWR_SRC_GFX_CORE D
1 2

Do Not Stuff
PG8620

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP

Do Not Stuff
PC8603
1 2

1
PC8612

PC8611

PC8606

PC8609

PC8604
Do Not Stuff +3.3V_RUN_GPU
PG8605 PU8601 PU8605
DY DIS

2
Thermal Design Current = 21.5A

5
6
7
8

5
6
7
8
SI7686DP-T1-GP

SI7686DP-T1-GP
1 2

D
D
D
D

D
D
D
D
PR8634 Max Current = 31.66A
Do Not Stuff DY 100KR2J-1-GP
PG8611 34.83A<OCP<41.16A
1 2

G
S
S
S

G
S
S
S
Do Not Stuff
23,25,87 DGPU_PWRGD

4
3
2
1

4
3
2
1
+VCC_GFX_CORE +VCC_GFX_CORE
PU8603 PR8633 PC8616
2009/08/16 2D2R3J-2-GP SCD1U25V3KX-GP +VCC_GFX_COREP +VCC_GFX_COREP +VCC_GFX_COREP
PR8632 1 11
+GFX_CORE_TRIP PGOOD GND +GFX_CORE_VBST 1
1 2 2 TRIP VBST 10 2+GFX_CORE_VBST12 1 PL8601
+GFX_CORE_EN 3 9 +GFX_CORE_DRVH PG8601 PG8603
71K5R2F-1-GP +GFX_CORE_FB EN DRVH +GFX_CORE_SW
4 VFB SW 8 1 2 2 1 1 2
PR8631 1 2 +GFX_CORE_CCM 5 7 +5V_ALW L-D36UH-1-GP
37 GFX_CORE_EN CCM V5IN

1
1KR2F-3-GP 6 +GFX_CORE_DRVL Do Not Stuff Do Not Stuff

SCD1U10V2KX-4GP
DRVL
1

1
Do Not Stuff
PTC8601 PTC8602 PTC8603 PG8619 PG8616

SE330U2VDM-L-GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
PR8638 1 2 PR8604 PC8617 PR8606 2 1 1 2
22,37,42,50,51,52,77 PM_SLP_S3# DY DY

5
6
7
8

5
6
7
8

1
1+GFX_CORE_LL_R
470KR2F-GP

PG8604
TPS51218DSCR-GP-U SC1U10V2KX-1GP PU8602 PU8604 Do Not Stuff

2
1

D
D
D
D

D
D
D
D
SIR460DP-T1-GE3-GP

SIR460DP-T1-GE3-GP
C Do Not Stuff Do Not Stuff Do Not Stuff C

PC8602
2
PG8618 PG8625
SC1KP50V2KX-1GP

2 1 2 1
2

2
PC5034

Do Not Stuff Do Not Stuff

S
S
S

S
S
S
G

G
PG8622 PG8627
1 2 1 2

4
3
2
1

4
3
2
1
PC8614 Do Not Stuff Do Not Stuff
Do Not Stuff PG8612 PG8631
DY

2
1 2 1 2

Do Not Stuff Do Not Stuff

PG8621 PG8624
2009/08/05 1 2 1 2

1
PR8603 Do Not Stuff Do Not Stuff
Frequency setting 5K1R2F-2-GP PG8614 PG8633
1 2 1 2
470K -->290KHz

2
Do Not Stuff Do Not Stuff
200K -->340KHz PG8607 PG8628
+GFX_CORE_FB 1 2 1 2
100K -->380KHz Do Not Stuff Do Not Stuff

1
39K -->430KHz PR8613 PR8611 PR8607 1
PG8606
2 1
PG8632
2
45K3R2F-L-GP 34KR2F-GP 45K3R2F-L-GP
+3.3V_RUN_GPU Do Not Stuff Do Not Stuff
B B
PD8601 PG8608 PG8630

2
A PD8601_A 1

PWRCNTL_0#
K 2 1 2 1 2
2009/08/26

1
B0530WS-7-F-GP PR8614 Do Not Stuff Do Not Stuff
PR8619 5K1R2F-2-GP PG8602 PG8634
10KR2F-2-GP 1 2 1 2

PWRCNTL_1#
PQ8602 Do Not Stuff Do Not Stuff

2
PR8618 2N7002A-7-GP PG8615 PG8626
81 PWRCNTL_0 2 1 PWRCNTL_0_R G 1 2 1 2
10KR2F-2-GP

2
+3.3V_RUN_GPU Do Not Stuff Do Not Stuff

Do Not Stuff
PC8610 PG8610 PG8629

PR8602

S
SCD1U16V2KX-3GP 1 2 1 2
DY

2
PWRCNTL_0 PWRCNTL_1 +VCC_GFX_CORE 1 2009/08/05
PR8620 Do Not Stuff Do Not Stuff

D
1
H H 0.96V 10KR2F-2-GP PG8609 PG8623
2009/08/05 PQ8601 1 2 1 2
H L 0.88V PR8617 2N7002A-7-GP
2

2 1 PWRCNTL_1_R G Do Not Stuff Do Not Stuff

SCD1U16V2KX-3GP
PC8608
L L 0.8V 81 PWRCNTL_1

2
10KR2F-2-GP

Do Not Stuff
PR8616
DY

S
2
PG8638 PG8635
2009/07/28 1 2 1 2

1
PD8615 Change 2N7002 ESD pretect from standard to 1KV type
P/N:84.2N702.E31
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L K A PD8615_A 1 2 Do Not Stuff Do Not Stuff
A nductor: 0.36UH ETQP4LR36WFC PANASONIC 1.1mohm/ 68.R3610.20A B0530WS-7-F-GP PR8615
UMA 2009/08/26 A

O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01 5K1R2F-2-GP

H/S: SI7686DP/ POWERPAK-8/11mOhm/[email protected]/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/[email protected]/ 84.00460.037
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Switching freq-->350KHz Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51218 +VCC_GFX_CORE
Size Document Number Rev
Custom
DW Calpella (Discrete) X00
Date: Tuesday, September 08, 2009 Sheet 86 of 90
5 4 3 2 1
 5 4 3 2 1

2009/08/10
Changed R8708,R8710,R8711 current-limiting resistor
value from 10k to 100k ohm.
Added R8713,R8716,R8717 current-limiting resistor
+3.3V_RTC_LDO between the N-FET gate and turn on 12-V logic .
+3.3V_RUN_GPU +15V_ALW

2
R8714

2
100KR2J-1-GP +3.3V_RUN_GPU

1
3D3V_VGA_ON# R8711
100KR2J-1-GP
Design current:2485mA

1
1
D C8704 D
SC10U6D3V5KX-1GP +3.3V_ALW

2
6

4
D8706 U8707
1 Q8707 1 S D 8
DMN66D0LDW-7-GP 2 S D 7
3 3 S D 6
BAS16-1-GP RUN_ON_3D3GFX_R 1 2 RUN_ON_3D3GFX 4 G D 5

3
2 R8713
R8778 2009/07/28 10KR2J-3-GP FDS8880-NL-GP

1
2KR2F-3-GP Change 2N7002 ESD pretect from standard to 1KV type
P/N:84.2N702.E31
10.7A
2 1 C8708
37 3.3V_RUN_GPU_EN SCD01U50V2KX-1GP Rds=12m ohm

2
1
C8786 3.3V_GPU_EN_R
SC1U6D3V2KX-GP
2

Added +1.05V_GFX_PCIE, +1.5V_RUN_GPU power switch 2009/05/25

+3.3V_RTC_LDO
+1.05V_GFX_PCIE: +15V_ALW
2

R8712
2

C 100KR2J-1-GP +1.05V_GFX_PCIE C
1

1D05V_VGA_ON# R8708
100KR2J-1-GP
Design current:2485mA

1
1

C8701
SC10U6D3V5KX-1GP +1.05V_PCH

2
6

U8703
Q8704 1 S D 8
DMN66D0LDW-7-GP 2 S D 7
3 S D 6
2009/07/28 RUN_ON_1D05V_R 1 2 RUN_ON_1D05V 4 G D 5
1

Change 2N7002 ESD pretect from standard to 1KV type R8716

P/N:84.2N702.E31 10KR2J-3-GP FDS8880-NL-GP

1
10.7A
C8705
SCD01U50V2KX-1GP Rds=12m ohm

2
1.05V_GFX_ON
Added discharge circuit
37 1.05V_GFX_ON
2009/06/17
+3.3V_RTC_LDO +1.5V_RUN_GPU
Place near device side(VGA chip),
+1.5V_RUN_GPU: +15V_ALW
use 10 mil trace between power
rail and Q8701 Drain
2

R8715 Q8701
2

100KR2J-1-GP +1.5V_RUN_GPU
1D5V_VGA_ON# G DY 2N7002A-7-GP
1

1D5V_VGA_ON# R8710
100KR2J-1-GP
Design current:2961mA
1
1

C8702
SC10U6D3V5KX-1GP +1.5V_SUS
2
6

U8705
Q8705 1 S D 8
DMN66D0LDW-7-GP 2 S D 7
2009/07/28 3 S D 6
Change 2N7002 ESD pretect from standard to 1KV type RUN_ON_1D5V_R 1 2 RUN_ON_1D5V 4 G D 5
1

B P/N:84.2N702.E31 R8717 B
10KR2J-3-GP FDS8880-NL-GP
1

10.7A
C8707
SCD01U50V2KX-1GP Rds=12m ohm
2

1D5V_VGA_ON
37 1D5V_VGA_ON

+1.8V_RUN_GPU RT9025 for +1.8V_RUN_GPU PG8706

+3.3V_ALW

1 2

Do Not Stuff
PG8707
+3D3V_1D8_LDO 1 2 DIS:
1

PC8716
DY PC8715
Do Not Stuff Design current = 0.21A
SC10U10V5KX-2GP SC10U10V5KX-2GP
2

+1.8V_PWR +1.8V_RUN_GPU
PG8708
PU8701 1 2

DGPU_PWRGD 1 8 Do Not Stuff

23,25,86 DGPU_PWRGD PGOOD GND
1 2 RT9025_EN 2 7 PG8709
37,51 1.8_GFX_ON EN ADJ
3 6 1 2
VIN VOUT
4 5
GND

A PR8711 VDD NC#5 PC8718 PC8719 PC8720 A

Do Not Stuff
0R2J-2-GP PR8712
SC100P50V2JN-3GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

RT9025-25PSP-GP 15KR2F-GP
9

2
2

RT9025_FB UMA
1

+5V_ALW
PR8713
12KR2F-L-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

Taipei Hsien 221, Taiwan, R.O.C.

PC8717
Vo=0.8*(1+(R1/R2))
2

SC1U16V3KX-2GP Title
2

LDO 1.8V
Added+1.8V_RUN_GPU 2009/07/17 Size Document Number Rev
Custom
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 87 of 90
5 4 3 2 1
 5 4 3 2 1

Item Page# Date Request By Issue description Solution Description Rev.

1 12 2009/07/13 DW70 need support Clarksfield(Qual core) Add VTT_SELECT pin to control VTT_CORE voltage level SA
2 21 2009/07/13 Add USB port for right side board SA
D
3 23 2009/07/13 Follow 15 inch PCI-E port SA D

4 65 2009/07/13 Add SIM card schematic SA

5 76 2009/07/13 Add LAN board connector schematic SA
6 77 2009/07/13 Change IO board connector and add Audio board connector SA
7 78 2009/07/13 Add Finger Printer Connector schematic SA
8 30,60 2009/07/14 Remove AUDIO Schematic and speaker connector SA
9 35 2009/07/14 Remove LAN Schematic SA
C 10 54 2009/07/14 LCD_BRIGHTNESS follow 15 inch schematic SA C

B B

A UMA A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change List(1/3)
Size Document Number Rev
A3
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 88 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
+1.5V_RUN_GPU +1.5V_RUN_GPU
MDC[0..63] 83,90
U8901 U8902
MDC[0..63] 83,90
K8 E3 MDC7 K8 E3 MDC21
VDD DQL0 MDC0 VDD DQL0 MDC18
K2 F7 K2 F7
VDD DQL1 MDC4 VDD DQL1 MDC17
N1 F2 N1 F2
VDD DQL2 MDC3 VDD DQL2 MDC22
R9 F8 R9 F8
VDD DQL3 MDC6 VDD DQL3 MDC16
B2 H3 B2 H3
VDD DQL4 MDC2 VDD DQL4 MDC20
D9 H8 D9 H8
VDD DQL5 MDC5 VDD DQL5 MDC19
G7 G2 MDC[0..63] 83,90 G7 G2
VDD DQL6 MDC1 VDD DQL6 MDC23
R1 H7 R1 H7 MDC[0..63] 83,90
VDD DQL7 VDD DQL7
D N9 N9 D
VDD MDC12 VDD MDC25
D7 D7
DQU0 MDC11 DQU0 MDC27
A8 C3 A8 C3
+1.5V_RUN_GPU VDDQ DQU1 MDC14 +1.5V_RUN_GPU VDDQ DQU1 MDC30
A1 C8 A1 C8
VDDQ DQU2 MDC10 VDDQ DQU2 MDC28
C1 C2 C1 C2
VDDQ DQU3 MDC13 VDDQ DQU3 MDC31
C9 A7 C9 A7
1

1
VDDQ DQU4 MDC8 VDDQ DQU4 MDC26
D2 A2 D2 A2
VDDQ DQU5 MDC15 VDDQ DQU5 MDC29
E9 B8 E9 B8
R8904 VDDQ DQU6 MDC9 R8903 VDDQ DQU6 MDC24
F1 A3 F1 A3
1KR2F-3-GP VDDQ DQU7 1KR2F-3-GP VDDQ DQU7
H9 H9
VDDQ QSC1 VDDQ QSC3
H2 C7 H2 C7
2

2
VDDQ DQSU QSC1 83 VDDQ DQSU QSC3 83
B7 QSC#1 B7 QSC#3
DQSU# QSC#1 83 DQSU# QSC#3 83
VREFC1 H1 VREFC2 H1
VREFDQ QSC0 VREFDQ QSC2
M8 F3 QSC0 83 M8 F3 QSC2 83
VREFCA DQSL VREFCA DQSL
1 2 ZQ_VRAMC11 L8 G3 QSC#0 1 2 ZQ_VRAMC12 L8 G3 QSC#2
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
QSC#0 83 QSC#2 83
1

1
ZQ DQSL# ZQ DQSL#
C8920

C8721
R8906 243R2F-2-GP R8907 243R2F-2-GP
1

1
K1 FBC_CMD_25 K1 FBC_CMD_25
ODT FBC_CMD_25 83 ODT FBC_CMD_25 83
R8901 FBC_CMD_7 N3 R8902 FBC_CMD_7 N3
83,90 FBC_CMD_7 A0 83,90 FBC_CMD_7 A0
1KR2F-3-GP FBC_CMD_20 P7 1KR2F-3-GP FBC_CMD_20 P7
2

2
83,90 FBC_CMD_20 A1 83,90 FBC_CMD_20 A1
FBC_CMD_4 P3 L2 FBC_CMD_2 FBC_CMD_4 P3 L2 FBC_CMD_2
83,90 FBC_CMD_4 FBC_CMD_2 83 83,90 FBC_CMD_4 FBC_CMD_2 83
2

2
1
FBC_CMD_14 A2 CS# FBC_CMD_28 FBC_CMD_14 A2 CS# FBC_CMD_28
83,90 FBC_CMD_14 N2 T2 FBC_CMD_28 83,90 83,90 FBC_CMD_14 N2 T2 FBC_CMD_28 83,90
FBC_CMD_17 A3 RESET# R8909 FBC_CMD_17 A3 RESET#
83,90 FBC_CMD_17 P8 83,90 FBC_CMD_17 P8
FBC_CMD_6 A4 R8910 1 FBC_CMD_6 A4
83,90 FBC_CMD_6 P2 210KR2J-3-GP 10KR2J-3-GP 83,90 FBC_CMD_6 P2
FBC_CMD_26 A5 FBC_CMD_26 A5 FBC_CMD_29
83,90 FBC_CMD_26 R8 T7 83,90 FBC_CMD_26 R8 T7 FBC_CMD_29 83,90
FBC_CMD_3 A6 NC#T7 FBC_CMD_3 A6 NC#T7
83,90 FBC_CMD_3 R2 L9 83,90 FBC_CMD_3 R2 L9

2
FBC_CMD_1 A7 NC#L9 FBC_CMD_29 FBC_CMD_1 A7 NC#L9
83,90 FBC_CMD_1 T8 L1 FBC_CMD_29 83,90 83,90 FBC_CMD_1 T8 L1
FBC_CMD_10 A8 NC#L1 FBC_CMD_10 A8 NC#L1
83,90 FBC_CMD_10 R3 J9 83,90 FBC_CMD_10 R3 J9
FBC_CMD_21 A9 NC#J9 FBC_CMD_21 A9 NC#J9
83,90 FBC_CMD_21 L7 J1 83,90 FBC_CMD_21 L7 J1
FBC_CMD_5 A10/AP NC#J1 FBC_CMD_5 A10/AP NC#J1
83,90 FBC_CMD_5 R7 83,90 FBC_CMD_5 R7
FBC_CMD_22 A11 FBC_CMD_22 A11
83,90 FBC_CMD_22 N7 83,90 FBC_CMD_22 N7
FBC_CMD_18 A12/BC# FBC_CMD_18 A12/BC#
83,90 FBC_CMD_18 T3 J8 83,90 FBC_CMD_18 T3 J8
FBC_CMD_30 A13 VSS FBC_CMD_30 A13 VSS
83,90 FBC_CMD_30 M7 M1 83,90 FBC_CMD_30 M7 M1
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
FBC_CMD_12 VSS CLKC0 FBC_CMD_12 VSS
83,90 FBC_CMD_12 M2 P9 83,90 FBC_CMD_12 M2 P9
FBC_CMD_9 BA0 VSS FBC_CMD_9 BA0 VSS
83,90 FBC_CMD_9 N8 G8 83,90 FBC_CMD_9 N8 G8
FBC_CMD_13 BA1 VSS FBC_CMD_13 BA1 VSS
83,90 FBC_CMD_13 M3 B3 83,90 FBC_CMD_13 M3 B3

1
BA2 VSS BA2 VSS
T1 T1
VSS R8918 VSS
A9 A9
CLKC0 VSS 243R2F-2-GP CLKC0 VSS
83 CLKC0 J7 T9 83 CLKC0 J7 T9
CLKC0# CK VSS CLKC0# CK VSS
83 CLKC0# K7 E1 83 CLKC0# K7 E1
CK# VSS CK# VSS
C P1 P1 C

2
FBC_CMD_0 VSS FBC_CMD_0 VSS
83 FBC_CMD_0 K9 83 FBC_CMD_0 K9
1

CKE CLKC0# CKE

G1 G1
VSSQ VSSQ
R8911

F9 F9
10KR2J-3-GP

DQMC#1 VSSQ DQMC#3 VSSQ

83 DQMC#1 D3 E8 83 DQMC#3 D3 E8
DQMC#0 DMU VSSQ DQMC#2 DMU VSSQ
83 DQMC#0 E7 E2 83 DQMC#2 E7 E2
DML VSSQ DML VSSQ
D8 D8
2

VSSQ VSSQ
D1 D1
FBC_CMD_19 VSSQ FBC_CMD_19 VSSQ
83,90 FBC_CMD_19 L3 B9 83,90 FBC_CMD_19 L3 B9
FBC_CMD_8 WE# VSSQ FBC_CMD_8 WE# VSSQ
83,90 FBC_CMD_8 K3 B1 83,90 FBC_CMD_8 K3 B1
FBC_CMD_24 CAS# VSSQ FBC_CMD_24 CAS# VSSQ
83,90 FBC_CMD_24 J3 G9 83,90 FBC_CMD_24 J3 G9
RAS# VSSQ RAS# VSSQ

K4W1G1646E-HC12-GP
Close to VRAM side K4W1G1646E-HC12-GP

64X16 SAMSUNG K4W1G1646E-HC12 P/N:72.41164.H0U

64X16 HYNIX H5TQ1G63BFR-12C P/N:72.51G63.C0U

+1.5V_RUN_GPU +1.5V_RUN_GPU
Place under / near VRAM Place under / near VRAM
SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP
C8922

C8923

C8924

C8925

C8927

C8926

C8928

C8929
1

1
2

2
B B

+1.5V_RUN_GPU +1.5V_RUN_GPU
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
C8904

C8908

C8910

C8911

C8912

C8905

C8909

C8914

C8915

C8913
2

2
A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VRAM(1/2)
Size Document Number Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 89 of 90
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

+1.5V_RUN_GPU
+1.5V_RUN_GPU
MDC[0..63] 83,89
U9001
U9002
MDC[0..63] 83,89
K8 E3 MDC59
VDD DQL0 MDC60 MDC36
K2 F7 K8 E3
VDD DQL1 MDC57 VDD DQL0 MDC33
N1 F2 K2 F7
VDD DQL2 MDC62 VDD DQL1 MDC37
R9 F8 N1 F2
VDD DQL3 MDC58 VDD DQL2 MDC34
B2 H3 R9 F8
VDD DQL4 MDC61 VDD DQL3 MDC38
D9 H8 B2 H3
VDD DQL5 MDC56 VDD DQL4 MDC32
G7 G2 D9 H8
VDD DQL6 MDC63 VDD DQL5 MDC39
D R1 H7 MDC[0..63] 83,89 G7 G2 MDC[0..63] 83,89 D
VDD DQL7 VDD DQL6 MDC35
N9 R1 H7
VDD MDC51 VDD DQL7
D7 N9
DQU0 MDC53 VDD MDC41
A8 C3 D7
+1.5V_RUN_GPU VDDQ DQU1 MDC48 DQU0 MDC43
A1 C8 A8 C3
VDDQ DQU2 MDC54 +1.5V_RUN_GPU VDDQ DQU1 MDC42
C1 C2 A1 C8
VDDQ DQU3 MDC49 VDDQ DQU2 MDC46
C9 A7 C1 C2
1

VDDQ DQU4 MDC55 VDDQ DQU3 MDC40

D2 A2 C9 A7

1
VDDQ DQU5 MDC50 VDDQ DQU4 MDC45
E9 B8 D2 A2
R9010 VDDQ DQU6 MDC52 VDDQ DQU5 MDC44
F1 A3 E9 B8
1KR2F-3-GP VDDQ DQU7 R9001 VDDQ DQU6 MDC47
H9 F1 A3
VDDQ QSC6 1KR2F-3-GP VDDQ DQU7
H2 C7 H9
2

VDDQ DQSU QSC6 83 VDDQ

B7 QSC#6 H2 C7 QSC5

2
DQSU# QSC#6 83 VDDQ DQSU QSC5 83
VREFC3 H1 B7 QSC#5
VREFDQ QSC7 VREFC4 DQSU# QSC#5 83
M8 F3 QSC7 83 H1
VREFCA DQSL VREFDQ
1 2 ZQ_VRAMC21 L8 G3 QSC#7 M8 F3 QSC4
SCD01U16V2KX-3GP

QSC#7 83 QSC4 83
1

ZQ DQSL# VREFCA DQSL

2 ZQ_VRAMC22 QSC#4
C8803

R9009 243R2F-2-GP 1 L8 G3

SCD01U16V2KX-3GP
QSC#4 83
1

1
FBC_CMD_16 ZQ DQSL#

C8806
K1 R9003 243R2F-2-GP
FBC_CMD_16 83

1
R9007 FBC_CMD_22 ODT FBC_CMD_16
83,89 FBC_CMD_22 N3 K1 FBC_CMD_16 83
1KR2F-3-GP FBC_CMD_4 A0 R9004 FBC_CMD_22 ODT
83,89 FBC_CMD_4 P7 83,89 FBC_CMD_22 N3
2

FBC_CMD_20 A1 FBC_CMD_11 1KR2F-3-GP FBC_CMD_4 A0

P3 L2 P7
2

2
83,89 FBC_CMD_20 FBC_CMD_11 83 83,89 FBC_CMD_4

1
FBC_CMD_9 A2 CS# FBC_CMD_28 FBC_CMD_20 A1 FBC_CMD_11
N2 T2 P3 L2

2
83,89 FBC_CMD_9 A3 RESET# FBC_CMD_28 83,89 83,89 FBC_CMD_20 A2 CS# FBC_CMD_11 83
FBC_CMD_6 P8 R9006 FBC_CMD_9 N2 T2 FBC_CMD_28
83,89 FBC_CMD_6 A4 83,89 FBC_CMD_9 A3 RESET# FBC_CMD_28 83,89
FBC_CMD_17 P2 10KR2J-3-GP FBC_CMD_6 P8
83,89 FBC_CMD_17 FBC_CMD_3 A5 FBC_CMD_18 83,89 FBC_CMD_6 FBC_CMD_17 A4
83,89 FBC_CMD_3 R8 T7 FBC_CMD_18 83,89 83,89 FBC_CMD_17 P2
FBC_CMD_26 A6 NC#T7 FBC_CMD_3 A5 FBC_CMD_18
R2 L9 R8 T7

2
83,89 FBC_CMD_26 A7 NC#L9 83,89 FBC_CMD_3 A6 NC#T7 FBC_CMD_18 83,89
FBC_CMD_1 T8 L1 FBC_CMD_26 R2 L9
83,89 FBC_CMD_1 A8 NC#L1 83,89 FBC_CMD_26 A7 NC#L9
FBC_CMD_5 R3 J9 FBC_CMD_1 T8 L1
83,89 FBC_CMD_5 A9 NC#J9 83,89 FBC_CMD_1 A8 NC#L1
FBC_CMD_19 L7 J1 FBC_CMD_5 R3 J9
83,89 FBC_CMD_19 A10/AP NC#J1 83,89 FBC_CMD_5 A9 NC#J9
FBC_CMD_10 R7 FBC_CMD_19 L7 J1
83,89 FBC_CMD_10 A11 83,89 FBC_CMD_19 A10/AP NC#J1
FBC_CMD_7 N7 FBC_CMD_10 R7
83,89 FBC_CMD_7 A12/BC# 83,89 FBC_CMD_10 A11
FBC_CMD_29 T3 J8 FBC_CMD_7 N7
83,89 FBC_CMD_29 FBC_CMD_13 A13 VSS 83,89 FBC_CMD_7 FBC_CMD_29 A12/BC#
83,89 FBC_CMD_13 M7 M1 83,89 FBC_CMD_29 T3 J8
NC#M7 VSS FBC_CMD_13 A13 VSS
M9 83,89 FBC_CMD_13 M7 M1
VSS NC#M7 VSS
J2 M9
FBC_CMD_12 VSS CLKC1 VSS
83,89 FBC_CMD_12 M2 P9 J2
FBC_CMD_14 BA0 VSS FBC_CMD_12 VSS
83,89 FBC_CMD_14 N8 G8 83,89 FBC_CMD_12 M2 P9
FBC_CMD_30 BA1 VSS FBC_CMD_14 BA0 VSS
83,89 FBC_CMD_30 M3 B3 83,89 FBC_CMD_14 N8 G8

1
BA2 VSS FBC_CMD_30 BA1 VSS
T1 83,89 FBC_CMD_30 M3 B3
VSS R9017 BA2 VSS
A9 T1
CLKC1 VSS 243R2F-2-GP VSS
83 CLKC1 J7 T9 A9
CLKC1# CK VSS CLKC1 VSS
C
83 CLKC1# K7 E1 83 CLKC1 J7 T9 C
CK# VSS CLKC1# CK VSS
P1 K7 E1

2
VSS 83 CLKC1# CK# VSS
FBC_CMD_27 K9 CLKC1# P1
83 FBC_CMD_27 CKE VSS
G1 FBC_CMD_27 K9
83 FBC_CMD_27
1

VSSQ CKE
F9 G1
R9008 DQMC#6 VSSQ VSSQ
83 DQMC#6 D3 E8 F9
DQMC#7 DMU VSSQ DQMC#5 VSSQ
10KR2J-3-GP 83 DQMC#7 E7 E2 83 DQMC#5 D3 E8
DML VSSQ DQMC#4 DMU VSSQ
D8 83 DQMC#4 E7 E2
VSSQ DML VSSQ
D1 D8
2

FBC_CMD_21 VSSQ VSSQ

83,89 FBC_CMD_21 L3 B9 D1
FBC_CMD_8 WE# VSSQ FBC_CMD_21 VSSQ
83,89 FBC_CMD_8 K3 B1 83,89 FBC_CMD_21 L3 B9
FBC_CMD_24 CAS# VSSQ FBC_CMD_8 WE# VSSQ
83,89 FBC_CMD_24 J3 G9 83,89 FBC_CMD_8 K3 B1
RAS# VSSQ FBC_CMD_24 CAS# VSSQ
83,89 FBC_CMD_24 J3 G9
RAS# VSSQ
K4W1G1646E-HC12-GP
Close to VRAM side
K4W1G1646E-HC12-GP

+1.5V_RUN_GPU
Place under / near VRAM +1.5V_RUN_GPU
Place under / near VRAM
SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP
C9034

C9033

C9031

C9032

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP
1

C9038

C9037

C9036

C9035
1

1
2

2
B B

+1.5V_RUN_GPU
+1.5V_RUN_GPU
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C9020

C9019

C9018

C9017

C9016

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

C9025

C9024

C9023

C9022

C9021
1

1
2

2
A A

UMA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VRAM
Size Document Number Rev
A2
Vostro Calpella SA
Date: Tuesday, September 08, 2009 Sheet 90 of 90
5 4 3 2 1