BTS–IV(R/Sb06–221)803 Reg.No.

B.Tech.DegreeIV SemesterRegular/Supplementary
Examination
April 2022
CS 19-202-0403
COMPUTERARCHITECTURE AND ORGANIZATION
(2019 Scheme)
Time: 3 Hours Maximum Marks: 60

Course Outcome
On successfUIcompletion of the course, the studentswill be able to:

COI : Acquire knowledge about structure, functions and characteristics of computer systems.
C02: Identify the addressing modes used in instructions.
C03: Determine the set of control signals generated and their timing sequence, given an instruction.
C04: Demonstrate how addition, multiplication and division operations are implemented inside a computer
system.
C05: Explain each level of memory hierarchy.
C06: Show how cache mapping affect the location of the data and the replacement policies.
C07: Map a virtual addressto physical address.
C08: Identify and compare different methods for computer I/O.
Bloom’s TaxonomyLevels(BL): LI – Remember,L2 – Understand,L3 – Apply, L4 -Analyze,/
L5 – Evaluate,L6 – Create 1.:
I
PO – ProgrammeOutcome

PART A
(Answer all questions)

1. (8 x 3 = 24) Marks BL CO PO
(a) Distinguish register transfer notations and assembly language 3 L2 2 1,2
notations.
(b) Discusson the interconnection betweenprocessorand memory with a 3 L2 I 1 ,2

neat diagram.
(C) Define register file and ALU. 3 Ll 1 1

(d) Discuss microprogrammed control. 3 L2 3 1 ,2,

4

(e) Differentiate betweenSRAM and DRAM. 3 L2 5

(f) Describe memory interleaving with neat diagrams. 3 L2 5

(g) Discuss vectored interrupts. 3 LI 8

(h) Explain centralized bus arbitration. 3 L2 8

PART B
(4 x 12= 48)
II. (a) Explain the various addressing modes. 6 Ll 2
(b) Discuss stack and its basic operations. 6 LI 1

OR
III. (a) Describe various operations to be performed while calling a subroutine. 6 LI 1

(b) Discuss the types of instructions with examples. 6 L2 2

IV. (a) Illustrate with an example bit pair recoding ofmultipliers. 6 L3 4 1 ,3,
4

(b) Explain n bit ripple carry adder and its delay calculation. 6 L2 4 1,3
4
OR
(P.T.0.
 2

BTS–IV(R/SF06–22–0803

V. (a) Illustrate a 16-bit carry save look ahead adder and derive the 6 L3 4 1 ,3,4
expressions for carry signals.
(b) Explain the principle of non- restoringdivision with an example. 6 1.1 4 1 ,3,4

VI. (a) Explain the three mapping techniques used in cache memory. 12 1.2 6 1 ,3,4
OR
VII. (a) Discuss LRU page replacement algorithm. 5 L2 6 1 ,3 ,4

(b) Describe virtual memory and addresstranslation using TLB . 7 L2 7 1,3,4

VIII. (a) Explaintheworking of parallelports. 8 Ll 8 1 ,3

(b) Discuss interrupt nesting. 4 L2 8 1,3

OR
IX. (a) Explain the detailed operation on DMA. 8 L2 8 1,3
(b) DescribePCI bus. 4 Ll 8 1,3

Bloom’sTaxonomyLevels
Ll = 33.3%,L2 = 58.33%,L3 = 8.3%
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