PIC18F24K20/25K20/44K20/45K20

PIC18F24K20/25K20/44K20/45K20
Silicon Errata and Data Sheet Clarification

The PIC18F24K20/25K20/44K20/45K20 devices that For example, to identify the silicon revision level
you have received conform functionally to the current using MPLAB IDE in conjunction with a hardware
Device Data Sheet (DS41303H), except for the debugger:
anomalies described in this document. 1. Using the appropriate interface, connect the
The silicon issues discussed in the following pages are device to the hardware debugger.
for silicon revisions with the Device and Revision IDs 2. Open an MPLAB IDE project.
listed in Table 1. The silicon issues are summarized in 3. Configure the MPLAB IDE project for the
Table 2. appropriate device and hardware debugger.
The errata described in this document will be addressed 4. Based on the version of MPLAB IDE you are
in future revisions of the PIC18F24K20/25K20/44K20/ using, do one of the following:
45K20 silicon. a) For MPLAB IDE 8, select Programmer >
Note: This document summarizes all silicon Reconnect.
errata issues from all revisions of silicon, b) For MPLAB X IDE, select Window >
previous as well as current. Only the Dashboard and click the Refresh Debug
issues indicated in the last column of Tool Status icon ( ).
Table 2 apply to the current silicon revi- 5. Depending on the development tool used, the
sion (AF). part number and Device Revision ID value
Data Sheet clarifications and corrections start on page appear in the Output window.
13, following the discussion of silicon issues. Note: If you are unable to extract the silicon
The silicon revision level can be identified using the revision level, please contact your local
current version of MPLAB® IDE and Microchip’s Microchip sales office for assistance.
programmers, debuggers, and emulation tools, which The DEVREV values for the various PIC18F24K20/
are available at the Microchip corporate web site 25K20/44K20/45K20 silicon revisions are shown in
(www.microchip.com). Table 1.

TABLE 1: SILICON DEVREV VALUES

Revision ID for Silicon Revision(2) (5-bit)
Part Number Device ID(1) (11-bit)
A4 A7 A9 AB A4 A7 A8 AE AF
PIC18F24K20 105h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
PIC18F25K20 103h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
PIC18F44K20 104h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
PIC18F45K20 102h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID:DEVREV”.
2: Refer to the “PIC18F2XK20/4XK20 Flash Memory Programming Specification” (DS41297) for detailed
information on Device and Revision IDs for your specific device.
3: Shaded cells in this table indicate older device revisions that are no longer in production.

 2008-2015 Microchip Technology Inc. DS80000425P-page 1

PIC18F24K20/25K20/44K20/45K20
TABLE 2: SILICON ISSUE SUMMARY
Affected Revisions(1)

0x11 AB

0x1B AE
0x1C AF
A4
A7
A9

0x16 A4
0x18 A7
0x19 A8
Item
Module Feature Issue Summary
Number

0xA
0xC
0xE
ECCP CCP1CON 1. Changing CCP1M bits may X X X X
cause capture of Timer1 value.
ECCP Full-Bridge 2. Direction change issue. X X X X
mode
MSSP SPI SPI Clock 3. Shortened SPI high time. X X X X
MSSP C I2 Slew Rate 4. Slow slew rate when X X X X
SLRCON<2> is set.
ADC Offset 5. Time dependent on offset. X X X X
MSSP I2C Receiving 6. Address may be received as X X X X
data.
MSSP I2C Master mode 7. Master mode not functional. X
MSSP SPI SPI Master 8. Improper sampling of last bit. X X X X
MSSP SPI SPI Master 9. SSPBUF improperly reloads on X X X X
SS pin transitions.
MSSP SPI SPI Master 10. Improper extra pulse on SCK X X X X
pin.
EUSART Synchronous 11. Duty cycle of CK output is X X X X
Master mode skewed when SPBRG is odd.
EUSART Synchronous 12. LS bit corruption during X X X X
Master mode transmission when SPBRG = 3.
EUSART Synchronous 13. Clock fails to stop at end of X X X X
Master mode character transmission when
SPBRG = 0.
Internal Fixed — 14. FVRST bit activates prematurely. X X
Voltage Refer-
ence (FVR)
High Low Voltage — 15. IVRST bit activates prematurely. X X
Detect (HLVD)
BOR FVR 16. Unexpected BOR occurrence. X X
System Clocks — 17. HFINTOSC output accuracy. X X X X
POR/BOR — 18. Unexpected code execution at X X X X
low VDD.
POR — 19. Premature POR release. X X X X
POR — 20. POR may become stuck. X X X X
Clocks EC mode 21. 48 MHz maximum frequency. X X
Comparators Interrupt-on- 22. Presetting interrupt-on-change X X X X
Change issue.
Data EEPROM Endurance 23. Endurance is limited to 10K X X X X X X X
Memory cycles.
Program Flash Endurance 24. Endurance is limited to 1K X X X X X X X
Memory cycles.
Configuration Bits CONFIG3H 25. HFOFST bit erases to ‘0’ instead X X X X
of ‘1’.
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2: Shaded cells in this table indicate older device revisions that are no longer in production.

DS80000425P-page 2  2008-2015 Microchip Technology Inc.

 PIC18F24K20/25K20/44K20/45K20
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Affected Revisions(1)

0x11 AB

0x1B AE
0x1C AF
A4
A7
A9

0x16 A4
0x18 A7
0x19 A8
Item
Module Feature Issue Summary
Number

0xA
0xC
0xE
EUSART Asynchronous 26. RCIDL bit may stay low X X X X
Receive mode improperly.
PORTB Interrupts Interrupt-on- 27. False interrupt when setting X X X X X X X X X
Change interrupt enable.
ADC ADC 28. ADC conversion may be limited X X X X X X X
Conversion to half scale.
ECCP Full-Bridge 29. Wrong dead-band time. X X X X X X X X X
mode
ECCP Full-Bridge 30. Wrong signal start time. X X X X X X X X X
mode
MSSP SPI SPI Clock 31. Improper SCK output. X X X X X X X X X
MSSP SPI SPI Master 32. Improper sampling of last bit. X X X X X X X X X
MSSP SPI SPI Master 33. Improper handling of write X X X X X X X X X
collision.
MSSP I2C I2C Master 34. Improper handling of Stop event. X X X X X X X X X
EUSART OERR Flag 35. Clearing SPEN bit does not clear X X X X X X X X X
OERR flag.
EUSART BAUDCTL 36. RCIDL bit may stay low X X X X X X X X X
improperly.
PORTB Interrupts Interrupt-on- 37. False interrupt when waking X X X X X X X X X
Change from Sleep.
BOR Reset 38. Reset on configuring the analog X X X X X X X X X
comparators to the FVR.
Wake-up from Wake-up 39. Device may not wake-up under X X X X X X X X X
Low-Power Sleep Sources specific conditions.
mode
Low-Voltage LVD in Sleep 40. LVD erroneously triggers upon X X X X X X X X X
Detect wake-up from Sleep if band gap
is disabled in Sleep mode.
Timer1/3 Interrupt 41. When the timer is operated in X X X X X X X X X
Asynchronous External Input
mode, unexpected interrupt flag
generation may occur.
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2: Shaded cells in this table indicate older device revisions that are no longer in production.

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PIC18F24K20/25K20/44K20/45K20
Silicon Errata Issues 4. Module: MSSP I2C

Note 1: This document summarizes all silicon Slew rate is slower than I2C specifications when
errata issues from all specified revisions the SLRCON<2> bit is set.
of silicon. Work around
2: Shaded cells in this section indicate latest Clear SLRCON<2> bit when using the I2C
silicon in production. peripheral.
Affected Silicon Revisions
1. Module: ECCP

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
Changing the CCP1M<3:0> bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1. X X X X
Work around
5. Module: ADC
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and Offset error is 3 LSb typical, 7 LSb maximum,
before Timer1 is restarted. including an acquisition time-dependent
component (~2 LSb).
Affected Silicon Revisions
Work around
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

The time dependent error is insignificant when the

time between conversions is less than 100 ms.
X X X X When the time since the previous conversion is
greater than 100 ms then take two ADC
2. Module: ECCP conversions and discard the first.
Changing direction in Full-Bridge mode does not Affected Silicon Revisions
insert dead time between changing the active

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

drivers in common legs of the bridge. 0xE

Work around
X X X X
None.
Affected Silicon Revisions 6. Module: MSSP I2C
If a new address byte is received while the BF flag
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

is set, the SSPOV bit is properly set and an ACK is

not properly generated. If only the SSPOV bit is set
X X X X (BF flag was cleared) and a matching address is
clocked in, that received byte will be improperly
3. Module: MSSP SPI loaded into the SSPBUF register and an ACK will
be improperly generated.
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), the first SPI high time Work around
may be short. None.
Work around Affected Silicon Revisions
Option 1: Ensure TMR2 value rolls over to zero
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

immediately before writing to SSPBUF.

Option 2: Turn Timer2 off and clear TMR2 before
writing SSPBUF. Enable TMR2 after X X X X
SSPBUF is written.
Affected Silicon Revisions
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X

DS80000425P-page 4  2008-2015 Microchip Technology Inc.

 PIC18F24K20/25K20/44K20/45K20
7. Module: MSSP I2C 11. Module: EUSART
I2C Master mode is not functional (Rev. A4 only). In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
Work around
output will be skewed by one baud clock count.
Use software to emulate Master mode.
Work around
Affected Silicon Revisions
High values of SPBRG will minimize the effect of
this anomaly.

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

Affected Silicon Revisions

X

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
8. Module: MSSP SPI
X X X X
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
12. Module: EUSART
data stream (bit 0) at the SDI pin will not be
sampled properly. In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
Work around
previous character is still in the TX shift register,
None. the LS bit of the TXREG character may be
corrupted during transmission.
Affected Silicon Revisions
Work around
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

When SPBRG is set to 3, wait until the TRMT bit of

the TXSTA register is set before loading TXREG
X X X X with the next character to be transmitted.

9. Module: MSSP SPI Affected Silicon Revisions

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift
register on every high-to-low transition of the SS X X X X
pin.
Work around 13. Module: EUSART
Avoid using the SS pin when the CKE bit is set and In Synchronous Master mode, if the SPBRG
the MSSP is configured for SPI Master mode. register is equal to 0 when the TXEN bit is set, then
writing to TXREG will properly start transmission.
Affected Silicon Revisions
However, the clock will be improperly out of phase
0x1B

0x1C

with the data bits and the clock will not stop at the
0x16

0x18

0x19
0x11
0xA

0xC

0xE

end of the character transmission.

X X X X Work around
Set SPBRG register to non-zero value before
10. Module: MSSP SPI setting the TXEN bit.
When SPI is enabled in Master mode with Affected Silicon Revisions
CKE = 1 and CKP = 0, a 1/FOSC wide pulse will
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

occur on the SCK pin.

Work around
X X X X
Configure SCK pin as an input until after the MSSP
is setup.
Affected Silicon Revisions
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X

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PIC18F24K20/25K20/44K20/45K20
14. Module: Internal Fixed Voltage Reference 16. Module: BOR
(FVR)
An unexpected Brown-out Reset may occur when
The FVRST bit of the CVRCON2 register activates the fixed voltage reference is inactive and BOR is
prematurely (Rev. A4 and A7 only). activated, thereby activating the fixed voltage ref-
erence simultaneously. This error is caused by a
Work around premature FVRST stable flag (Rev. A4 and A7
Wait an additional 20 µs after FVRST is sensed only) and only affects Brown-out disable in Sleep
high before using the fixed voltage reference. and software enabled BOR modes.
Enable the FVR by setting the FVREN bit of the
Work around
CVRCON2 register before activating any
peripheral that automatically enables the FVR. Enable the FVR by setting the FVREN bit of the
Peripherals that automatically enable the FVR CVRCON2 register and then wait an additional 20
include the Brown-out Reset, the High/Low- µs after FVRST is sensed high before enabling
Voltage Detect, and the HFINTOSC. BOR. Brown-out disable in Sleep mode with
automatic enable on wake-up cannot be used.
Affected Silicon Revisions
Affected Silicon Revisions
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
X X
X X
15. Module: High Low Voltage Detect (HLVD)
17. Module: System Clocks
The IVRST bit of the HLVDCON register activates
prematurely (Rev. A4 and A7 only). HFINTOSC output frequency is 16 MHz ±3%,
25°C to 85°C.
Work around
Work around
Wait an additional 20 µs after IVRST is sensed
high before using the fixed voltage reference. None.
Enable the FVR by setting the FVREN bit of the
Affected Silicon Revisions
CVRCON2 register before activating any

0x1B

0x1C
peripheral that automatically enables the FVR.

0x16

0x18

0x19
0x11
0xA

0xC

0xE

Peripherals that automatically enable the FVR

include the Brown-out Reset, the High/Low-
X X X X
Voltage Detect, and the HFINTOSC.
Affected Silicon Revisions 18. Module: POR/BOR
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

The POR rearm voltage may be below the low end

of the BOR range, causing unexpected code
X X execution below the BOR range.
Work around
Use external power monitor to hold the device in
Reset below 1.1V.
Affected Silicon Revisions
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X

DS80000425P-page 6  2008-2015 Microchip Technology Inc.

 PIC18F24K20/25K20/44K20/45K20
19. Module: POR 22. Module: Comparators
The POR may release around 0.8V (below the When the CxON bit is clear, the output from the
POR rearm voltage of 1.2V, nominal) when VDD comparator will be properly forced to zero, but the
rises from below 0.60V (when BOR is not enabled) CxPOL bit will improperly have no effect on the
or 0.33V (when BOR is enabled). CxOUT bit. This prevents presetting the compara-
tor change-on-interrupt mismatch latches as
Work around
described in the data sheet.
Use Power-up Timer when operating with the EC,
EXTRC or HFINTOSC oscillator modes. Ensure Work around
that VDD rise time is less than the Power-up Timer Configure one of the unused comparator input
time. channels as a digital output. Use that digital output
to manipulate the comparator output to the desired
Affected Silicon Revisions
CxOUT non-interrupt level. When the comparator
is then set to the desired inputs, the mismatch

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

latches will be preset to the non-interrupt level and

the CxIF flag can then be cleared.
X X X X
Affected Silicon Revisions
20. Module: POR

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
The part may hang in the Reset state when VDD
rises to the operating range at a rate faster than X X X X
7500V per second. Recovery from the hung state
is possible only by first lowering VDD to below 0.3V,
23. Module: Data EEPROM Memory
followed by raising VDD to the operating range.
The write/erase endurance of Data EE Memory is
Work around
limited to 10K cycles.
Slow VDD rise time by adding series resistance
between the voltage supply and the VDD pin and Work around
increasing the VDD bypass capacitance. VDD Use error correction method that stores data in
bypassing should remain on the pin side of the multiple locations.
series resistor.
Affected Silicon Revisions
Affected Silicon Revisions

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X X X X
X X X X
24. Module: Program Flash Memory
21. Module: Clocks
The write/erase endurance of the PFM is limited to
EC mode operation is limited to a maximum of 1K cycles when VDD is above 3V. Endurance
48 MHz (Rev. A4 and A7 only). degrades when VDD is below 3V.
Work around Work around
Divide external clock by 4 and use HS-PLL Clock For data tables in Program Flash Memory use
mode for external clocking above 48 MHz. error correction method that stores data in multiple
locations.
Affected Silicon Revisions
Affected Silicon Revisions
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X
X X X X X X X

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PIC18F24K20/25K20/44K20/45K20
25. Module: Configuration Bits 28. Module: ADC
Bit 3 of CONFIG3H defaults to ‘0’ after a Bulk After extended stress, the Most Significant bit
Erase instead of ‘1’ as specified in the data sheet. (MSb) of the ADC conversion result can become
stuck at ‘0’. Conversions resulting in code 511 or
Work around
less are still accurate, but conversions that should
Program the HFOFST bit to the desired state after result in codes greater than 511 are, instead,
a Bulk Erase. All MPLAB® IDE programming tools pinned at 511.
currently perform this way.
The potential for failures is a function of several
Affected Silicon Revisions factors:
• The potential for failures increases over the life

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

of the part. No failures have ever been seen for

accelerated stress estimated to be equivalent
X X X X to 34 years at room temperature. The failure
rate after accelerated stress estimated to be
26. Module: EUSART equivalent to 146 years at room temperature
can be as high as 10% for VDD = 1.8V. The time
In Asynchronous Receive mode, the RCIDL bit of to failure will decrease as the operating
the BAUDCON register will properly go low when temperature increases.
an invalid Start bit less than 1/8th of a bit time is
• The potential for failures is highest at low VDD
received. The RCIDL bit will then stay low improp-
and decreases as VDD increases.
erly until a valid Start bit is received.
Work around
Work around
1. Restrict the input voltage to less than 1/2 of the
When monitoring the RCIDL bit, measure the
ADC voltage reference so that the expected
length of time between the RCIDL going low and
result is always a code less than or equal to 511.
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by 2. Use manual acquisition time (ACQT<2:0> =
resetting the EUSART module. The EUSART 000) and put the part to Sleep after each
module is reset when the SPEN bit of the RCSTA conversion.
register is cleared. Affected Silicon Revisions
Affected Silicon Revisions

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X X X X
X X X X
29. Module: ECCP
27. Module: PORTB Changing direction in Full-Bridge mode inserts a
Setting a PORTB interrupt-on-change enable bit of dead-band time of 4/FOSC * TMR2 Prescale
the IOCB register while the corresponding PORTB instead of 1/FOSC * TMR2 Prescale as specified in
input is high will cause an RBIF interrupt. the data sheet.

Work around Work around

Set the IOCB bits to the desired configuration, then None.
read PORTB to clear the mismatch latches. Affected Silicon Revisions
Finally, clear the RBIF bit before setting the RBIE
0x1B

0x1C
0x16

0x18

0x19
0x11

bit.
0xA

0xC

0xE

Affected Silicon Revisions

X X X X X X X X X
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X X X X X X

DS80000425P-page 8  2008-2015 Microchip Technology Inc.

 PIC18F24K20/25K20/44K20/45K20
30. Module: ECCP 33. Module: MSSP SPI
ECCP – In Full-Bridge mode when PR2 = In SPI Master mode, if the SSPBUF register is
CCPR1L and DC1B[1:0] <>‘00’ and the direction written while a byte is actively being transmitted,
is changed, then the dead time before the modu- an extra clock pulse will be improperly generated
lated output starts is compromised. The modulated at the end of the transmission. Further writes to the
signal improperly starts immediately with the direc- SSPBUF register will be inhibited although 8 or 9
tion change and stays on for TOSC * TMR2 clock pulses will be generated for each attempted
Prescale * DC1B[1:0]. write. The WCON bit of the SSPCON register is
properly set indicating that a write collision
Work around
occurred. However, the write collision condition
Avoid changing direction when the duty cycle is can only be cleared by resetting the MSSP
within three Least Significant steps of 100% duty module. Clear the MSSP by clearing the SSPEN
cycle. Instead, clear the DC1B[1:0] bits before the bit of the SSPCON1 register.
direction change and then set them to the desired
value after the direction change is complete. Work around
Use the SSPIF bit of the PIR1 register or the BF bit
Affected Silicon Revisions
of the SSPSTAT register to determine that the
0x1B transmission is complete before writing the

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

SSPBUF register. In the event that a write collision

does occur, use the slave select feature to
X X X X X X X X X resynchronize the slave clock.

31. Module: MSSP SPI Affected Silicon Revisions

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011) and the CKE bit of the
SSPSTAT register is ‘1’, then when SSPBUF is X X X X X X X X X
written, the SCK output is improperly immediately
driven to the non-Idle state together with the MSb
34. Module: MSSP I2C
value of the SSPBUF. The duration at which SDO
and SCK remain at these levels may be shorter In Master I2C Receive mode if a Stop condition
than a full half-bit period. The remaining bits in the occurs in the middle of an address or data
byte are output properly. reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
Work around
register will remain set improperly. If a Start
None. condition occurs after the improper Stop condition
then nine additional clocks will be generated
Affected Silicon Revisions
followed by the RCEN bit going low.
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

Work around
Use low-impedance pull-ups on the SDA line to
X X X X X X X X X reduce the possibility of noise glitches which may
trigger an improper Stop event. Use a time-out
32. Module: MSSP SPI event timer to detect the unexpected Stop
condition and resulting stuck RCEN bit. Clear the
In SPI Master mode, when the CKE bit of the
stuck RCEN bit by clearing the SSPEN bit of
SSPSTAT register is cleared and the SMP bit of
SSPCON1.
the SSPSTAT register is set, then the last bit of the
incoming data stream (bit 0) at the SDI pin will not Affected Silicon Revisions
be sampled properly.
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

Work around
None. X X X X X X X X X
Affected Silicon Revisions
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X X X X X X

 2008-2015 Microchip Technology Inc. DS80000425P-page 9

PIC18F24K20/25K20/44K20/45K20
35. Module: EUSART 37. Module: Interrupt-on-Change
The OERR flag of the RCSTA register is reset only When any interrupt-on-change is enabled and the
by clearing the CREN bit of the RCSTA register or corresponding input is high, then waking from
by a device Reset. Clearing the SPEN bit of the Sleep by a source other than interrupt-on-change
RCSTA register does not clear the OERR flag. may cause the RBIF interrupt flag bit to become
set improperly.
Work around
Clear the OERR flag by clearing the CREN bit Work around
instead of clearing the SPEN bit. 1. Use the INTx interrupt in lieu of interrupt-on-
change.
Affected Silicon Revisions
Or

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

2. Store the state of the PORTB inputs before

entering Sleep. Upon waking, if an RBIF is
X X X X X X X X X detected, then compare the PORTB levels
with those stored. If they are the same, then
36. Module: EUSART clear and ignore the RBIF interrupt.

In Asynchronous Receive mode, the RCIDL bit of Affected Silicon Revisions

the BAUDCON register will properly go low when

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE
an invalid Start bit less than 1/16th of a bit time is
received. The RCIDL bit will then properly go high
1/8th of a bit time later. However, if another invalid X X X X X X X X X
Start bit occurs less than 1 bit time after the leading
edge of the first invalid Start bit, then the RCIDL bit 38. Module: BOR
will improperly stay high then improperly go low
one bit time later. The RCIDL bit will then stay low An unexpected Brown-out Reset may occur when
improperly until a valid Start bit is received. enabling the comparator with the Fixed Voltage
Reference (FVR) selected as the VIN+ input.
Work around
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and Disconnect the FVR from the VIN+ comparator
the RCIF flag going high. If this time is greater than inputs prior to enabling the comparator and then
one character time, then restore the RCIDL bit by reconnect it after enabling the comparator.
resetting the EUSART module. The EUSART Affected Silicon Revisions
module is reset when the SPEN bit of the RCSTA

0x1B

0x1C
0x16

0x18

0x19
0x11

register is cleared.
0xA

0xC

0xE

Affected Silicon Revisions

X X X X X X X X X
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X X X X X X

DS80000425P-page 10  2008-2015 Microchip Technology Inc.

 PIC18F24K20/25K20/44K20/45K20
39. Module: Wake-up from Low-Power Sleep 40. Module: Low-Voltage Detect
mode
If Low-Voltage Detect is enabled, the band gap is
The device may not wake from Sleep when both of disabled in Sleep, and the part is put to Sleep for a
the following conditions are met: short period of time, the LVD will trigger
immediately upon waking-up from Sleep.
1. The device is in Sleep mode for <1 ms;
2. On waking, the device executes a SLEEP Work around
instruction within 100 µs. Do not disable the band gap in Sleep when using
Under these conditions, the oscillator may stop the LVD.
before completing execution of the SLEEP
Affected Silicon Revisions
instruction. The device will enter Sleep mode but

0x1B

0x1C
will not wake-up on any enabled wake-up event,

0x16

0x18

0x19
0x11
0xA

0xC

0xE
including the Watchdog Timer.
Work around X X X X X X X X X
1. Disable High-Speed Start-up
41. Module: Timer1/3
Disabling High-Speed Start-up in the Configuration
Word will delay the device executing code on When Timer1 or Timer3 is operated in
wake-up by 250 µs, nominally, allowing the Asynchronous External Input mode, unexpected
oscillator to stabilize. interrupt flag generation may occur if an external
The wake-up time from Sleep will increase by clock edge arrives too soon following a firmware
about 250 µs, nominally. write to the TMRxH:TMRxL registers. An
unexpected interrupt flag event may also occur
2. BOR enabled during Sleep when enabling the module or switching from
Configuring the device for hardware only BOR or Synchronous to Asynchronous mode.
software-controlled BOR and enabling SBOREN,
Work around
the voltage reference is on during Sleep.
This issue only applies when operating the timer
The device will wake-up and the oscillator will be
in Asynchronous mode. Whenever possible,
stable. This will add 20 µA (nominal) to the Sleep
operate the timer module in Synchronous mode
current.
to avoid spurious timer interrupts.
3. Enable the FVR during Sleep
If Asynchronous mode must be used in the
In the same manner as the BOR, the FVR will keep application, potential strategies to mitigate the
the voltage reference on during Sleep, causing the issue may include any of the following:
oscillator to be stable on wake-up.
• Design the firmware so it does not rely on
4. Avoid executing SLEEP within 100 µs of any the TMRxIF flag or keep the respective
wake-up event interrupt disabled. The timer still counts
This can be achieved by adding more instructions normally and does not reset to 0x0000
(NOP) before executing the SLEEP instruction. This when the spurious interrupt flag event is
minimizes the probability of the SLEEP instruction generated.
only partially executing. • Design the firmware so that it does not
write to the TMRxH:TMRxL registers or
Affected Silicon Revisions does not periodically disable/enable the
timer, or switch modes. Reading from the
0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

timer does not trigger the spurious interrupt

flag events.
X X X X X X X X X • If the firmware must use the timer inter-
rupts and must write to the timer (or dis-
able/enable, or mode switch the timer),
implement code to suppress the spurious
interrupt event, should it occur. This can be
achieved by following the process shown in
Example 1.

 2008-2015 Microchip Technology Inc. DS80000425P-page 11

PIC18F24K20/25K20/44K20/45K20
EXAMPLE 1: ASYNCHRONOUS TIMER MODE WORK AROUND TO AVOID SPURIOUS
INTERRUPT
//Timer1 update procedure in asynchronous mode
//The code below uses Timer1 as example

T1CONbits.TMR1ON = 0; //Stop timer from incrementing

PIE1bits.TMR1IE = 0; //Temporarily disable Timer1 interrupt vectoring
TMR1H = 0x00; //Update timer value
TMR1L = 0x00;
T1CONbits.TMR1ON = 1; //Turn on timer

//Now wait at least two full T1CKI periods + 2TCY before re-enabling Timer1 interrupts.
//Depending upon clock edge timing relative to TMR1H/TMR1L firmware write operation,
//a spurious TMR1IF flag event may sometimes assert. If this happens, to suppress
//the actual interrupt vectoring, the TMR1IE bit should be kept clear until
//after the "window of opportunity" (for the spurious interrupt flag event has passed).
//After the window is passed, no further spurious interrupts occur, at least
//until the next timer write (or mode switch/enable event).

while(TMR1L < 0x02); //Wait for 2 timer increments more than the Updated Timer
//value (indicating more than 2 full T1CKI clock periods elapsed)
NOP(); //Wait two more instruction cycles
NOP();
PIR1bits.TMR1IF = 0; //Clear TMR1IF flag, in case it was spuriously set
PIE1bits.TMR1IE = 1; //Now re-enable interrupt vectoring for timer 1

Affected Silicon Revisions

0x1B

0x1C
0x16

0x18

0x19
0x11
0xA

0xC

0xE

X X X X X X X X X

DS80000425P-page 12  2008-2015 Microchip Technology Inc.

 PIC18F24K20/25K20/44K20/45K20
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS41303H):

Note: Corrections are shown in bold. Where

possible, the original bold text formatting
has been removed for clarity.

1. Module: Product Identification System

The temperature range values have been
corrected.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. [X](1) X /XX XXX

Examples:
Device Tape and Reel Temperature Package Pattern a) PIC18F45K20 - E/P 301 = Industrial temp.,
Option Range PDIP package, QTP pattern #301.
b) PIC18F24K20 - I/SO = Industrial temp., SOIC
package.
Device: PIC18F24K20; PIC18F25K20; PIC18F44K20; PIC18F26K20; c) PIC18F44K20 - E/P = Extended temp., PDIP
PIC18F45K20; PIC18F44K20; PIC18F45K20; PIC18F46K20. package.
d) PIC18F46K20 - I/PT = Industrial temp., TQFP
package, tape and reel.
Tape and Reel Blank = Standard packaging (tube or tray)
Option: T = Tape and Reel(1)

Temperature I = -40C to +85C (Industrial)

Range: E = -40C to +125C (Extended)

Package: PT = TQFP (Thin Quad Flatpack)

SS = SSOP
SO = SOIC Note 1: Tape and Reel identifier only appears in the
SP = SPDIP (Skinny Plastic DIP) catalog part number description. This
P = PDIP identifier is used for ordering purposes and
ML = QFN is not printed on the device package. Check
MV = UQFN with your Microchip Sales Office for package
availability with the Tape and Reel option.

Pattern: QTP, SQTP, Code or Special Requirements

(blank otherwise)

 2008-2015 Microchip Technology Inc. DS80000425P-page 13

PIC18F24K20/25K20/44K20/45K20
APPENDIX A: DOCUMENT Rev K Document (05/2013)
REVISION HISTORY Added MPLAB X IDE; Added Module 40, Low-Voltage
Detect.
Rev A Document (12/2008) Data Sheet Clarifications: Added Module 2, Electrical
Initial release of this document. Characteristics.

Rev B Document (05/2009) Rev L Document (12/2013)

Updated Errata to new format; Added Module 11: Data Sheet Clarification: Updated Module 2 (Electrical
PORTB and Module 12: ADC; minor edits. Characteristics, Table 26-8).

Clarifications/Corrections to the Data Sheet: Added

Module 1: MSSP; Module 2: Electrical Specifications;
Rev M Document (4/2014)
Module 3: Electrical Specifications. Data Sheet Clarifications: Added Modules 3, 4, 5, 6, 7,
8.
Rev C Document (06/2009)
Clarifications/Corrections to the Data Sheet:
Rev N Document (7/2014)
Deleted Module 1: MSSP: Figure 17-17 Baud Rate Added Module 41, Timer1/3 to Silicon Errata Issues
Generator Block Diagram, updating subsequent num- section.
bering. Added Module 3 MSSP: Register 17-3
SSPADD; Added Module 4 MSSP: Section 17.4.2 Rev P Document (9/2015)
Operation; Added Module 5 MSSP: Figure 17-16
MSSP Block Diagram; Added Module 6 MSSP: Sec- Data Sheet Clarifications:
tions 17.4.7.1, 17.4.8, 17.4.9, 17.4.17.1, 17.4.17.2, Removed modules 1-8. Added Module 1, Product
17.4.17.3: SSPADD, changing <6:0> to <7:0>. Identification System.

Rev D Document (11/2009)

Updated to add revision 0x1B.
Data Sheet Clarifications: Deleted Modules 1, 2, 3, 4,
5, 6.

Rev E Document (04/2010)

Updated to include early revisions of silicon, revision
IDs 0xA through 0x11. These early revisions were
described in DS80366 errata, which is now obsolete.

Rev F Document (05/2010)

Updated Table 1.

Rev G Document (07/2010)

Removed ADC Work around #2 and changed #3 to #2
(Module 28).

Rev H Document (07/2011)

Updated errata to the new format; Updated Module 16;
Added Modules 38 and 39; Updated Table 2 to include
the new modules.
Data Sheet Clarifications: Added Module 1.

Rev J Document (07/2012)

Added Silicon revision AF.

DS80000425P-page 14  2008-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications.
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
conveyed, implicitly or otherwise, under any Microchip Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
intellectual property rights unless otherwise stated. Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2008-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-796-6

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2008-2015 Microchip Technology Inc. DS80000425P-page 15

 Worldwide Sales and Service
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DS80000425P-page 16  2008-2015 Microchip Technology Inc.