Lab8_-ARM-Memory
Lab8_-ARM-Memory
Dalloul
T.A. at Computer Engineering Dept.,
IUG
1
𝑏𝑢𝑠 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = × 𝑏𝑢𝑠 𝑤𝑖𝑑𝑡ℎ (𝑏𝑦𝑡𝑒𝑠)
𝑏𝑢𝑠 𝑐𝑦𝑐𝑙𝑒 𝑡𝑖𝑚𝑒
1
1
𝑏𝑢𝑠 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = × 𝑏𝑢𝑠 𝑤𝑖𝑑𝑡ℎ (𝑏𝑦𝑡𝑒𝑠)
𝑏𝑢𝑠 𝑐𝑦𝑐𝑙𝑒 𝑡𝑖𝑚𝑒
1
𝑏𝑢𝑠 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = 2×10𝑛𝑠 × 2 𝑏𝑦𝑡𝑒 = 100 𝑀𝐵/𝑆
1
𝑏𝑢𝑠 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = 2×10𝑛𝑠+10𝑛𝑠 × 2 𝑏𝑦𝑡𝑒 = 66.6 𝑀𝐵/𝑆
1
𝑏𝑢𝑠 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = 2×10𝑛𝑠 × 4 𝑏𝑦𝑡𝑒 = 200 𝑀𝐵/𝑆
1
𝑏𝑢𝑠 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = 2×10𝑛𝑠+10𝑛𝑠 × 4 𝑏𝑦𝑡𝑒 = 126 𝑀𝐵/𝑆
LDR R2,=0x7698E39F
LDR R1,=0x80000000
STR R2,[R1]
0x80000000 0X9F
0x80000001 0XE3
0x80000002 0X98
0x80000003 0X76
0x80000000 0X76
0x80000001 0X98
0x80000002 0XE3
0x80000003 0X9F
2
STR Rr,[R13] ;Rr can be any registers (R0-R12)
SUB R13,R13,#4 ;decrement stack pointer
LDR R13,=0X04100000
LDR R2, =0X04000000
BL FIND_SUM
ADD R0,#1
ADD R1,#1
HERE B HERE
FIND_SUM
; PUSHING INTO STACK
3
STR R0,[R13]
SUB R13,#4
STR R1,[R13]
SUB R13,#4
END
4
𝑆𝑇𝑇𝑟𝑎𝑛𝑠𝑙𝑎𝑡𝑒𝑑 = 𝑆𝑅𝐴𝑀 𝐴𝐷𝐷𝑅𝐸𝑆𝑆(𝐷𝑖𝑔𝑖𝑡 4 𝑡𝑜 0) ∗ 20 + 4 ∗ 𝑏𝑖𝑡𝑛𝑢𝑚𝑏𝑒𝑟
𝐵𝑖𝑡𝐴𝑑𝑑𝑟𝑒𝑠𝑠 = 𝑆𝑡𝑎𝑟𝑡𝑒𝑟 𝑑𝑖𝑔𝑖𝑡 ‖2 + 𝑆𝑇6 ‖𝑆𝑇5−0
5
6
AREA LOOKUP_EXAMPLE,READONLY,CODE
ENTRY
ADR R2,OUR_FIXED_DATA ;point to OUR_FIXED_DATA
LDRB R0,[R2] ;load R0 with the contents
;of memory pointed to by R2
ADD R1,R1,R0 ;add R0 to R1
HERE B HERE ;stay here forever
OUR_FIXED_DATA
DCB 0x55,0x33,1,2,3,4,5,6
7
DCD 0x23222120,0x30
DCW 0x4540,0x50
END
LDR R0,=0x12345678
LDR R1,=0x86427531
ADD R2,R0,R1