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9S12DT128DGV2

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9S12DT128DGV2

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MC9S12DT128

Device User Guide

Covers MC9S12DT128E, MC9S12DG128E,
MC9S12DJ128E, MC9S12DG128, MC9S12DJ128,
MC9S12DB128, MC9S12A128, SC515846, SC515847,
SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204,
SC102205
HCS12
Microcontrollers

9S12DT128DGV2/D
V02.17
03 Jun 2010

freescale.com
Device User Guide — 9S12DT128DGV2/D V02.17

Revision History

Version Revision Effective Author Description of Changes

Number Date Date
18 Jun 18 June
V01.00 Initial version (parent doc v2.03 dug for dp256).
2001 2001
23 July 23 July
V01.01 Updated version after review
2001 2001
Changed Partname, added pierce mode, updated electrical
23 Sep 23 Sep
V01.02 characteristics
2001 2001
some minor corrections
12 Oct 12 Oct
V01.03 Replaced Star12 by HCS12
2001 2001
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
27 Feb 27 Feb
V01.04 Pierce, NVM reliability
2002 2002
New document numbering. Corrected Typos
4 Mar 4 Mar Increased VDD to 2.35V, removed min. oscillator startup
V01.05
2002 2002 Removed Document order number except from Cover Sheet
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
8 July 22 July
V01.06 Chip Configuration Summary
2002 2002
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
NEW MASKSET
Changed part number from DTB128 to DT128
Functional Changes:
ROMCTL changes in Emulation Mode
80 Pin Byteflight package Option available
Flash with 2 Bit Backdoor Key Enable
11 Jan 11 Jan
V02.00 Additional CAN0 routing to PJ7,6
2002 2002
Improved BDM with sync and acknowledge capabilities
New Part ID number
Improvements:
Significantly improved NVM reliability data
Corrections:
Interrupt vector Table
01 Feb 01 Feb Updated Block User Guide versions in preface
V02.01
2002 2002 Updated Appendix A Electrical Characteristics

2 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Version Revision Effective Author Description of Changes

Number Date Date
Changed XCLKS to PE7 in Table 2-2
Updated device part numbers in Figure 2-1
Updated BDM clock in Figure 3-1
Removed SIM description in overview & nUPOSC spec in Table A-15
08 Mar 08 Mar
V02.02 Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH
2002 2002
(Table A-6), CINS (Table A-9), CIN (Table A-6 & A-15),
Updated interrupt pulse timing variables in Table A-6
Updated device part numbers in Figure 2-1
Added document numbers on cover page and Table 0-2
Cleaned up Fig. 1-1, 2-1
Updated Section 1.5 descriptions
Corrected PE assignment in Table 2-2, Fig. 2-5,6,7.
14 Mar 14 Mar
V02.03 Corrected NVM sizes in Sections 16, 17
2002 2002
Added IREF spec for 1ATD in Table A-8
Added Blank Check in A.3.1.5 and Table A-11
Updated CRG spec in Table A-15
Added:
Pull-up columns to signal table,
Example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
16 Aug 16 Aug Device specific info on CRG
V02.04
2002 2002 Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
Changed leakage current for ADC inputs down to +-1uA
Minor modification of PLL frequency/ voltage gain values
Corrected:
Pin names/functions on 80 pin packages
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
12 Sep 12 Sep Corrected:
V02.05
2002 2002 Register address mismatches in 1.5.1
Removed document order no. from Revision History pages
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing
CAN0/1/4, BDLC, IIC and/or Byteflight
Added 2L40K mask set in section 1.6
Added OSC User Guide in Preface, “Document References”
06 Nov 06 Nov
V02.06 Added oscillator clock connection to BDM in S12_CORE in fig 3-1
2002 2002
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Added new section: “Oscillator (OSC) Block Description”
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz

Freescale Semiconductor 3
Device User Guide — 9S12DT128DGV2/D V02.17

Version Revision Effective Author Description of Changes

Number Date Date
Added 3L40K mask set in section 1.6
Corrected register entries in section 1.5.1 “Detailed Memory Map”
Updated description for ROMCTL in section 2.3.31
Updated section 4.3.3 “Unsecuring the Microcontroller”
29 Jan 29 Jan Corrected and updated device-specific information for OSC
V02.07
2003 2003 (section 8.1) & Byteflight (section 15.1)
Updated footnote in Table A-4 “Operating Conditions”
Changed reference of VDDM to VDDR in section A.1.8
Removed footnote on input leakage current in Table A-6 “5V I/O
Characteristics”
Added part numbers MC9S12DT128E, MC9S12DG128E, and
26 Feb 26 Feb
V02.08 MC9S12DJ128E in “Preface” and related part number references
2003 2003
Removed mask sets 0L40K and 2L40K from Table 1-3
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;
updated Fig.3-1 “Clock Connections” to show the individual HCS12
blocks
Corrected PIM module name and document order number in Table
0-2 “Document References”
Corrected ECT pulse accumulators description in section 1.2
“Features”
Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments
Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in
15 Oct 15 Oct Table 2.1 “Signal Properties”
V02.09
2003 2003 Mentioned “S12LRAE” bootloader in Flash section 17
Corrected footnote on clamp of TEST pin under Table A-1
“Absolute Maximum Ratings”
Corrected minimum bus frequency to 0.25MHz in Table A-4
“Operating Conditions”
Replaced “burst programming” by “row programming” in A.3 “NVM,
Flash and EEPROM”
Corrected blank check time for EEPROM in Table A-11 “NVM
Timing Characteristics”
Corrected operating frequency in Table A-18 “SPI Master/Slave
Mode Timing Characteristics
Added A128 information in “Derivative Differences”, 2.1 “Device
Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4
Added lead-free package option (PVE) in Table 0-2 “Derivative
6 Feb 6 Feb
V02.10 Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber
2004 2004
Example”
Added an “AEC qualified” row in the “Derivative Differences” tables
0-1 & 0-2.
Added part numbers SC515846, SC515847, SC515848, and
SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2,
and section 23.
3 May 3 May
V02.11 Corrected and added maskset 4L40K in tables 0-1 & 0-2 and
2004 2004
section 1.6.
Corrected BDLC module availability in DB128 80QFP part in
“Derivative Differences” table 0-2.

4 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Version Revision Effective Author Description of Changes

Number Date Date
Added maskset 0L94R
Added items VIH,EXTAL, VIL,EXTAL, & VHYS,EXTAL in table A-15
06 Dec 06 Dec
V02.12 “Oscillator characteristics”
2004 2004
Removed item “Oscillator” from table A-4 “Operating Conditions” as
it is already covered in table “Oscillator Characteristics”
04 Mar 04 Mar
V02.13 Amended feature list of A128 in Table 0-1 “Derivative Differences”
2005 2005
Updated cover page
Added part numbers SC101161DT, SC101161DG, SC101161DJ,
28 Apr 28 Apr SC102202, SC102203, SC102204, & SC102205
V02.14
2005 2005 Added masksets 5L40K &1L59W
Changed TJavg to 85°C in table A-12 “NVM Reliability” & added
footnote concerning data retention
05 Oct 05 Oct Updated “NVM Reliability” table A-12 format with added data.
V02.15
2005 2005 Added figure A-2 “Typical Endurance vs Temperature”
12 Apr 12 Apr
V02.16 Added maskset 2L94R
2008 2008
3 Jun 3 Jun
V02.17 Added maskset 1L59W for MC9S12A128
2010 2010

Freescale Semiconductor 5
Device User Guide — 9S12DT128DGV2/D V02.17

6 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Table of Contents

Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.1 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.6 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Section 2 Signal Description

2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.3 TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . 64
2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . 65
2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 65
2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 65
2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.15 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.17 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.18 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.19 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.20 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Freescale Semiconductor 7
Device User Guide — 9S12DT128DGV2/D V02.17

2.3.21 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.3.22 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.23 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7. . . . . . . . . . . . . . . 68
2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . 69
2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . 69
2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . 70
2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . 70
2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . 70
2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.49 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.50 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.51 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.52 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.53 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.54 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.55 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.56 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . 73
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins . . . . . . . . . . . . 73
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 74
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 74
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 74
2.4.7 VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . 74

Section 3 System Clock Description

3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Section 4 Modes of Operation

4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Section 5 Resets and Interrupts

5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Section 6 HCS12 Core Block Description

6.1 CPU Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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6.1.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.2 HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . 85
6.2.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 85
6.3.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.5 HCS12 Background Debug Module (BDM) Block Description . . . . . . . . . . . . . . . . . 86
6.5.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.6 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Section 7 Clock and Reset Generator (CRG) Block Description

7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Section 8 Oscillator (OSC) Block Description

8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Section 9 Enhanced Capture Timer (ECT) Block Description

Section 10 Analog to Digital Converter (ATD) Block Description

Section 11 Inter-IC Bus (IIC) Block Description

Section 12 Serial Communications Interface (SCI) Block Description

Section 13 Serial Peripheral Interface (SPI) Block Description

Section 14 J1850 (BDLC) Block Description

Section 15 Byteflight (BF) Block Description

15.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Section 16 Pulse Width Modulator (PWM) Block Description

Section 17 Flash EEPROM 128K Block Description

Section 18 EEPROM 2K Block Description

Section 19 RAM Block Description

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Section 20 MSCAN Block Description

Section 21 Port Integration Module (PIM) Block Description

Section 22 Voltage Regulator (VREG) Block Description

Section 23 Printed Circuit Board Layout Proposal

Appendix A Electrical Characteristics

A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 101
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

A.8.1 General Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Appendix B Package Information

B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
B.3 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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List of Figures

Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 1-1 MC9S12DT128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 1-2 MC9S12DT128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128E, MC9S12DT128,
MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12DB128
MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204, and SC102205 . . . . . . . . . . . . . . . . . . 58
Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204 Bondout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-3 Pin Assignments in 80 QFP for MC9S12DB128, SC515846, and SC102202 Bond-
out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . 91
Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204) Colpitts Oscillator . . . . . . . . . . . . . . . . . . . . . . 92
Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . 93
Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204) Pierce Oscillator . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128, SC515846, and
SC102202) Pierce Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure A-2 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure A-4 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure A-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure A-6 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure A-7 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure A-8 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure A-9 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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Figure A-10 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . 138

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List of Tables

Table 0-1 Derivative Differences1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 0-2 Derivative Differences for MC9S12DB1281. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 0-3 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
$0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) ................... 32
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) ................................. 32
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) .............................................................. 33
$0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) .................................. 33
$0018 - $0019Reserved ..................................................................................................... 33
$001A - $001B Device ID Register ((Table 1-3)) ............................................................... 33
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, (Table 1-4)) ............ 33
$001E - $001EMEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) .................. 33
$001F - $001FINT map 2 of 2 (HCS12 Interrupt) ............................................................... 34
$0020 - $0027 Reserved .................................................................................................... 34
$0028 - $002F BKP (HCS12 Breakpoint) ........................................................................... 34
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) ................................. 34
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) .................. 34
$0034 - $003F CRG (Clock and Reset Generator) ............................................................ 35
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) ................................... 35
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ................................ 38
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) ........................................ 39
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ...................................................... 41
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ....................................................... 41
$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................. 42
$00E0 - $00E7 IIC (Inter IC Bus) ....................................................................................... 42
$00E8 - $00EF BDLC (Byte Level Data Link Controller J1850) ......................................... 43
$00F0 - $00F7 SPI1 (Serial Peripheral Interface) .............................................................. 43
$00F8 - $00FF Reserved ................................................................................................... 43
$0100 - $010F Flash Control Register (fts128k2) .............................................................. 44
$0110 - $011B EEPROM Control Register (eets2k) .......................................................... 44
$011C - $011F Reserved for RAM Control Register .......................................................... 45
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ................................ 45
$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ................................................ 46

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Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 47
$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) ................................................ 48
$01C0 - $01FF Reserved ................................................................................................... 49
$0200 - $023F Reserved .................................................................................................... 49
$0240 - $027F PIM (Port Integration Module) .................................................................... 50
$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ................................................ 52
$02C0 - $02FF Reserved ................................................................................................... 53
$0300 - $035F Byteflight .................................................................................................... 53
$0360 - $03FF Reserved ................................................................................................... 55
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 2-2 MC9S12DT128 Power and Ground Connection Summary . . . . . . . . . . . . . . . 72
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 23-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . 117
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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Derivative Differences and Document References

Derivative Differences
(Table 0-1) and (Table 0-2) show the availability of peripheral modules on the various derivatives. For
details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
Table 0-1 Derivative Differences1
MC9S12DT128E3 MC9S12DG128E3 MC9S12DJ128E3
MC9S12DT128 MC9S12DG128 MC9S12DJ128
Modules SC5158494 SC5158474 SC5158484 MC9S12A128
SC101161DT 5 SC101161DG5 SC101161DJ5
6
SC102205 SC1022036 SC1022046
# of CANs 3 2 2 0
CAN4 ✓ ✓ ✓ ✕
CAN1 ✓ ✕ ✕ ✕
CAN0 ✓ ✓ ✓ ✕
J1850/BDLC ✕ ✕ ✓ ✕
IIC ✓ ✓ ✓ ✓
Byteflight ✕ ✕ ✕ ✕
Package 112 LQFP 112 LQFP/80 QFP2 112 LQFP/80 QFP2 112 LQFP/80 QFP2
Package Code PV PV/FU PV/FU PV/FU
1L40K3, 3L40K, 1L40K3, 3L40K, 1L40K3, 3L40K,
0L94R, 4L40K4, 0L94R, 4L40K4, 0L94R, 4L40K4, 3L40K, 0L94R,
Mask set
1L59W5, 5L40K6, 1L59W5, 5L40K6, 1L59W5, 5L40K6, 2L94R, 1L59W
2L94R 2L94R 2L94R
Temp Options M, V, C M, V, C M, V, C C
AEC qualified Yes Yes Yes No
An errata exists An errata exists An errata exists An errata exists
Notes
contact Sales Office contact Sales Office contact Sales Office contact Sales Office

Table 0-2 Derivative Differences for MC9S12DB1281

MC9S12DB128 MC9S12DB128
Modules SC5158464 SC5158464
SC1022026 SC1022026
# of CANs 2 0
CAN4 ✓ ✕
CAN1 ✕ ✕
CAN0 ✓ ✕
J1850/BDLC ✕ ✕
IIC ✕ ✕
Byteflight ✓ ✓
Package 112 LQFP 80 QFP2

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MC9S12DB128 MC9S12DB128
Modules SC5158464 SC5158464
SC1022026 SC1022026
Package Code PV/PVE FU
3L40K, 0L94R, 3L40K, 0L94R,
Mask set 4L40K4, 5L40K6, 4L40K4, 5L40K6,
2L94R 2L94R
Temp Options M, V, C/M, V M, V, C
AEC qualified Yes Yes
An errata exists An errata exists
Notes
contact Sales Office contact Sales Office
NOTE:
1. ✓: Available for this device, ✕: Not available for this device.
2. 80 Pin bond-out for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847,
SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 is the same; MC9S12DB128, SC515846, and
SC102202 have a different bond-out.
3. Part numbers MC9S12DT128E, MC9S12DG128E, and MC9S12DJ128E are associated with the mask set 1L40K.
4. Part numbers SC515846, SC515847, SC515848, and SC515849 are associated with the mask set 4L40K.
5. Part numbers SC101161DT, SC101161DG, SC101161DJ are associated with the mask set 1L59W.
6. Part numbers SC102202, SC102203, SC102204, and SC102205 are associated with the mask set 5L40K which is not for
volume production.

The following figure provides an ordering number example for the MC9S12D128 devices.
MC9S12 DJ128 C FU Temperature Options
Package Option C = -40˚C to 85˚C
Temperature Option V = -40˚C to 105˚C
M = -40˚C to 125˚C
Device Title
Package Options
Controller Family FU = 80QFP
PV = 112LQFP
PVE = lead-free 112LQFP

Figure 0-1 Order Partnumber Example

The following items should be considered when using a derivative.

• Registers
– Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a
derivative without CAN0 (see (Table 0-1) and (Table 0-2)).
– Do not write or read CAN1 registers (after reset: address range $0180 - $01BF), if using a
derivative without CAN1 (see (Table 0-1) and (Table 0-2)).
– Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a
derivative without CAN4 (see (Table 0-1) and (Table 0-2)).
– Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC (see (Table 0-1) and (Table 0-2)).
– Do not write or read IIC registers (after reset: address range $00E0 - $00E7), if using a
derivative without IIC (see (Table 0-1) and (Table 0-2)).

20 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

– Do not write or read Byteflight registers (after reset: address range $0300 - $035F), if using a
derivative without Byteflight registers (see (Table 0-1) and (Table 0-2)).
• Interrupts
– Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for
unused interrupts, if using a derivative without CAN0 (see (Table 0-1) and (Table 0-2)).
– Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for
unused interrupts, if using a derivative without CAN1 (see (Table 0-1) and (Table 0-2)).
– Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for
unused interrupts, if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)).
– Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused
interrupts, if using a derivative without BDLC (see (Table 0-1) and (Table 0-2)).
– Fill the IIC interrupt vector ($FFC0, $FFC1) according to your coding policies for unused
interrupts, if using a derivative without IIC (see (Table 0-1) and (Table 0-2)).
– Fill the four Byteflight interrupt vectors ($FFA0 - $FFA7) according to your coding policies for
unused interrupts, if using a derivative without Byteflight (see (Table 0-1) and (Table 0-2)).
• Ports
– The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5,
PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0 (see (Table 0-1) and
(Table 0-2)).
– The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if
using a derivative without CAN1 (see (Table 0-1) and (Table 0-2)).
– The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7,
PM6, PM5 and PM4, if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)).
– The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
derivative without BDLC (see (Table 0-1) and (Table 0-2)).
– The IIC pin functionality (SCL, SCA) is not available on port PJ7 and PJ6, if using a derivative
without IIC (see (Table 0-1) and (Table 0-2)).
– The Byteflight pin functionality (BF_PSLM, BF_PERR, BF_PROK, BF_PSYN, TX_BF,
RX_BF) is not available on port PM7, PM6, PM5, PM4, PM3 and PM2, if using a derivative
without Byteflight (see (Table 0-1) and (Table 0-2)).
– Do not write MODRR1 and MODRR0 Bit of Module Routing Register (PIM_9DTB128 Block
User Guide), if using a derivative without CAN0 (see (Table 0-1) and (Table 0-2)).
– Do not write MODRR3 and MODRR2 Bit of Module Routing Register (PIM_9DTB128 Block
User Guide), if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)).
• Pins not available in 80 pin QFP package for MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204

Freescale Semiconductor 21
Device User Guide — 9S12DT128DGV2/D V02.17

– Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
– Port J[1:0]
Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must
be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at
Base+$026C.
– Port K
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefore care must be taken not to clear this bit.
– Port M[7:6]
PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
– Port P6
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
– Port S[7:4]
PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
– PAD[15:8] (ATD1 channels)
Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1
registers!
• Pins not available in 80 pin QFP package for MC9S12DB128, SC515846, and SC102202
– Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
– Port J[7:6, 1:0]
Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must
be taken not to disable the pull enables on PJ[7:6, 1:0] by clearing the bits PERJ7, PERJ6,
PERJ1 and PERJ0 at Base+$026C.
– Port K
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefore care must be taken not to clear this bit.
– Port M[1:0]
PM1:0 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
– Port P6
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.

22 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

– Port S[3:2]
PS3:2 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
– PAD[15:8] (ATD1 channels)
Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1
registers!

Document References
The Device User Guide provides information about the MC9S12DT128 device made up of standard
HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes all
the individual Block User Guides of the implemented modules. In a effort to reduce redundancy all module
specific information is located only in the respective Block User Guide. If applicable, special
implementation details of the module are given in the block description sections of this document.
See Table 0-3 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-3 Document References
User Guide Version Document Order Number
HCS12 CPU Reference Manual V02 S12CPUV2/D
HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D
HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D
HCS12 Background Debug Module (BDM) Block Guide V04 S12BDMV4/D
HCS12 Breakpoint (BKP) Block Guide V01 S12BKPV1/D
Clock and Reset Generator (CRG) Block User Guide V04 S12CRGV4/D
Oscillator (OSC) Block User Guide V02 S12OSCV2/D
Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide V01 S12ECT16B8CV1/D
Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide V02 S12ATD10B8CV2/D
Inter IC Bus (IIC) Block User Guide V02 S12IICV2/D
Asynchronous Serial Interface (SCI) Block User Guide V02 S12SCIV2/D
Serial Peripheral Interface (SPI) Block User Guide V02 S12SPIV2/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide V01 S12PWM8B8CV1/D
128K Byte Flash (FTS128K) Block User Guide V02 S12FTS128KV2/D
2K Byte EEPROM (EETS2K) Block User Guide V01 S12EETS2KV1/D
Byte Level Data Link Controller -J1850 (BDLC) Block User Guide V01 S12BDLCV1/D
Motorola Scalable CAN (MSCAN) Block User Guide V02 S12MSCANV2/D
Voltage Regulator (VREG) Block User Guide V01 S12VREGV1/D
Port Integration Module (PIM_9DTB128) Block User Guide V02 S12DTB128PIMV2/D
Byteflight (BF) Block User Guide V01 S12BFV1/D

Freescale Semiconductor 23
Device User Guide — 9S12DT128DGV2/D V02.17

24 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Section 1 Introduction

1.1 Overview
The MC9S12DT128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K
bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules
(MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128 has full 16-bit data paths
throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory
can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and
performance to be adjusted to suit operational requirements.

1.2 Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. 20-bit ALU
iv. Instruction queue
v. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Module)
• CRG (Clock and Reset Generator)
– Choice of low current Colpitts oscillator or standard Pierce Oscillator
– PLL
– COP watchdog
– real time interrupt
– clock monitor
• 8-bit and 4-bit ports with interrupt functionality

Freescale Semiconductor 25
Device User Guide — 9S12DT128DGV2/D V02.17

– Digital filtering
– Programmable rising or falling edge trigger
• Memory
– 128K Flash EEPROM
– 2K byte EEPROM
– 8K byte RAM
• Two 8-channel Analog-to-Digital Converters
– 10-bit resolution
– External conversion trigger capability
• Three 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Enhanced Capture Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
• Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Two Synchronous Serial Peripheral Interface (SPI)
– Byteflight
• Byte Data Link Controller (BDLC)

26 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

• SAE J1850 Class B Data Communications Network Interface

– Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in
Automotive Applications
• Inter-IC Bus (IIC)
– Compatible with I2C Bus standard
– Multi-master operation
– Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP and 80-Pin QFP package options
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
– Operation at 50MHz equivalent to 25MHz Bus Speed
– Development support
– Single-wire background debug™ mode
– On-chip hardware breakpoints

1.3 Modes of Operation

User modes
• Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Freescale use only)
– Special Peripheral Mode (Freescale use only)
Low power modes
• Stop Mode
• Pseudo Stop Mode
• Wait Mode

Freescale Semiconductor 27
Device User Guide — 9S12DT128DGV2/D V02.17

1.4 Block Diagram

Figure 1-1 shows a block diagram of the MC9S12DT128 device.

28 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Figure 1-1 MC9S12DT128 Block Diagram

VRH VRH VRH
128K Byte Flash EEPROM ATD0 ATD1
VRL VRL VRL
VDDA VDDA VDDA
8K Byte RAM VSSA VSSA VSSA
AN0 PAD00 AN0 PAD08
2K Byte EEPROM AN1 PAD01 AN1 PAD09
AN2 PAD02 AN2 PAD10
VDDR

AD0

AD1
AN3 PAD03 AN3 PAD11
VSSR AN4 PAD04 AN4 PAD12
VREGEN Voltage Regulator AN5 PAD05 AN5 PAD13
VDD1,2 AN6 PAD06 AN6 PAD14
VSS1,2 AN7 PAD07 AN7 PAD15

Single-wire Background PIX0 PK0 XADDR14

BKGD Debug Module CPU PIX1 PK1 XADDR15
PPAGE
PIX2 PK2

DDRK
XADDR16

PTK
XFC
Clock and PIX3 PK3 XADDR17
VDDPLL
PLL Reset PIX4 PK4 XADDR18
VSSPLL Generation Periodic Interrupt
PIX5 PK5 XADDR19
EXTAL Module COP Watchdog
ROMCTL ECS PK7 ECS ROMCTL
XTAL Clock Monitor
RESET Breakpoints IOC0 PT0
IOC1 PT1
PE0 XIRQ
IOC2 PT2
PE1 IRQ

DDRT
Enhanced Capture

PTT
System IOC3 PT3
PE2 R/W
Integration Timer IOC4 PT4
DDRE
PTE

PE3 LSTRB
Module IOC5 PT5
PE4 ECLK (SIM) IOC6 PT6
PE5 MODA
IOC7 PT7
PE6 MODB
PE7 NOACC/XCLKS RXD PS0
SCI0
TXD PS1
TEST
RXD PS2
SCI1

DDRS
PTS
TXD PS3
MISO PS4
Multiplexed Address/Data Bus

Signals shown in Bold-Italics are not available in the 80 Pin Package Option for DG and DJ128
MOSI PS5
SPI0 SCK PS6
SS PS7
DDRA DDRB

Signals shown in Bold are not available in any of the two the 80 Pin Package Options
BDLC RxB
PTA PTB (J1850) TxB
Module to Port Routing

Signals shown in Italics are not available in the 80 Pin Package Option for B128
RxCAN PM0
CAN0
TxCAN PM1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DATA15 ADDR15 PA7
DATA14 ADDR14 PA6
DATA13 ADDR13 PA5
DATA12 ADDR12 PA4
DATA11 ADDR11 PA3
DATA10 ADDR10 PA2
ADDR9 PA1
ADDR8 PA0

RxCAN PM2
DDRM
CAN1 PTM
TxCAN PM3
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0

RX_BF PM4
BYTE-
FLIGHT TX_BF PM5
BF_PSYN PM6
BF_PROK PM7
DATA9
DATA8

DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0

Multiplexed BF_PERR
Wide Bus
BF_PSLM
RxCAN KWJ0 PJ0
CAN0,4
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0

DDRJ

Multiplexed
PTJ

TxCAN KWJ1 PJ1

Narrow Bus SDA KWJ6 PJ6
IIC
SCL KWJ7 PJ7
Internal Logic 2.5V I/O Driver 5V
PWM0 KWP0 PP0
VDD1,2 VDDX
PWM1 KWP1 PP1
VSS1,2 VSSX
PWM2 KWP2 PP2
DDRP
PTP

PWM3 KWP3 PP3

A/D Converter 5V & PWM4 KWP4 PP4
PLL 2.5V Voltage Regulator Reference PP5
PWM5 KWP5
VDDPLL VDDA PWM6 KWP6 PP6
VSSPLL VSSA PWM7 KWP7 PP7
MISO KWH0 PH0
MOSI KWH1 PH1
Voltage Regulator 5V & I/O
VDDR SCK KWH2 PH2
DDRH
PTH

VSSR SPI1 SS KWH3 PH3

KWH4 PH4
KWH5 PH5
KWH6 PH6
KWH7 PH7

Freescale Semiconductor 29
Device User Guide — 9S12DT128DGV2/D V02.17

1.5 Device Memory Map

(Table 1-1) and (Figure 1-2) show the device memory map of the MC9S12DT128 after reset. Note that
after reset the EEPROM ($0000 – $07FF) is hidden by the register space ($0000 - $03FF) and the RAM
($0000 - $1FFF). The bottom 1K Bytes of RAM ($0000 - $03FF) are hidden by the register space.
Table 1-1 Device Memory Map
Size
Address Module (Bytes)
$0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$0018 – $0019 Reserved 2
$001A – $001B Device ID register (PARTID) 2
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO) 4
$0020 – $0027 Reserved 8
$0028 – $002F CORE (Background Debug Module) 8
$0030 – $0033 CORE (PPAGE, Port K) 4
$0034 – $003F Clock and Reset Generator (PLL, RTI, COP) 12
$0040 – $007F Enhanced Capture Timer 16-bit 8 channels 64
$0080 – $009F Analog to Digital Converter 10-bit 8 channels (ATD0) 32
$00A0 – $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$00C8 – $00CF Serial Communications Interface (SCI0) 8
$00D0 – $00D7 Serial Communications Interface (SCI1) 8
$00D8 – $00DF Serial Peripheral Interface (SPI0) 8
$00E0 – $00E7 Inter IC Bus 8
$00E8 – $00EF Byte Level Data Link Controller (BDLC) 8
$00F0 – $00F7 Serial Peripheral Interface (SPI1) 8
$00F8 – $00FF Reserved 8
$0100 – $010F Flash Control Register 16
$0110 – $011B EEPROM Control Register 12
$011C – $011F Reserved 4
$0120 – $013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32
$0140 – $017F Motorola Scalable CAN (CAN0) 64
$0180 – $01BF Motorola Scalable CAN (CAN1) 64
$01C0 – $01FF Reserved 64
$0200 – $023F Reserved 64
$0240 – $027F Port Integration Module (PIM) 64
$0280 – $02BF Motorola Scalable CAN (CAN4) 64
$02C0 – $02FF Reserved 64
$0300 – $035F Byteflight (BF) 96
$0360 – $03FF Reserved 160
$0000 – $07FF EEPROM array 2048
$0000 – $1FFF RAM array 8192
Fixed Flash EEPROM array
$4000 – $7FFF 16384
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
$8000 – $BFFF Flash EEPROM Page Window 16384

30 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Table 1-1 Device Memory Map

Size
Address Module (Bytes)
Fixed Flash EEPROM array
$C000 – $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end 16384
and 256 bytes of Vector Space at $FF80 – $FFFF

Figure 1-2 MC9S12DT128 Memory Map

$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400 $0800 2K Bytes EEPROM
$0800
$1000 $0FFF Mappable to any 2K Boundary
$2000
$2000 8K Bytes RAM

$3FFF Mappable to any 8K Boundary

$4000
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000 16K Page Window
eight * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED SPECIAL

SINGLE CHIP SINGLE CHIP

The address does not show the map after reset, but a useful map. After reset the map is:
$0000 – $03FF: Register Space
$0000 – $1FFF: 8K RAM
$0000 – $07FF: 2K EEPROM (not visible)

Freescale Semiconductor 31
Device User Guide — 9S12DT128DGV2/D V02.17

1.5.1 Detailed Register Map

$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0000 PORTA Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0001 PORTB Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0002 DDRA Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0003 DDRB Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0 0 0 0 0 0 0
$0004 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0005 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0006 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0007 Reserved
Write:
Read: Bit 1 Bit 0
$0008 PORTE Bit 7 6 5 4 3 2
Write:
Read: 0 0
$0009 DDRE Bit 7 6 5 4 3 Bit 2
Write:
Read: 0 0 0
$000A PEAR NOACCE PIPOE NECLK LSTRE RDWE
Write:
Read: 0 0
$000B MODE MODC MODB MODA IVIS EMK EME
Write:
Read: 0 0 0 0
$000C PUCR PUPKE PUPEE PUPBE PUPAE
Write:
Read: 0 0 0 0
$000D RDRIV RDPK RDPE RDPB RDPA
Write:
Read: 0 0 0 0 0 0 0
$000E EBICTL ESTR
Write:
Read: 0 0 0 0 0 0 0 0
$000F Reserved
Write:

$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0010 INITRM RAM15 RAM14 RAM13 RAM12 RAM11 RAMHAL
Write:
Read: 0 0 0 0
$0011 INITRG REG14 REG13 REG12 REG11
Write:
Read: 0 0
$0012 INITEE EE15 EE14 EE13 EE12 EE11 EEON
Write:
Read: 0 0 0 0
$0013 MISC EXSTR1 EXSTR0 ROMHM ROMON
Write:
Read: 0 0 0 0 0 0 0 0
$0014 Reserved
Write:

32 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$0015 ITCR WRINT ADR3 ADR2 ADR1 ADR0
Write:
Read:
$0016 ITEST INTE INTC INTA INT8 INT6 INT4 INT2 INT0
Write:

$0017 - $0017 MMC map 2 of 4 (HCS12 Module Mapping Control)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MTST1 Read: Bit 7 6 5 4 3 2 1 Bit 0
$0017
Test Only Write:

$0018 - $0019 Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0018 - Read: 0 0 0 0 0 0 0 0
Reserved
$0019 Write:

$001A - $001B Device ID Register ((Table 1-3))

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
$001A PARTIDH
Write:
Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
$001B PARTIDL
Write:

$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, (Table

1-4))

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
$001C MEMSIZ0
Write:
Read: rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0
$001D MEMSIZ1
Write:

$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0
$001E INTCR IRQE IRQEN
Write:

Freescale Semiconductor 33
Device User Guide — 9S12DT128DGV2/D V02.17

$001F - $001F INT map 2 of 2 (HCS12 Interrupt)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0
$001F HPRIO PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
Write:

$0020 - $0027 Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0020 - Read: 0 0 0 0 0 0 0 0
Reserved
$0027 Write:

$0028 - $002F BKP (HCS12 Breakpoint)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0
$0028 BKPCT0 BKEN BKFULL BKBDM BKTAG
Write:
Read:
$0029 BKPCT1 BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
Write:
Read: 0 0
$002A BKP0X BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0
Write:
Read:
$002B BKP0H Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$002C BKP0L Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0
$002D BKP1X BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0
Write:
Read:
$002E BKP1H Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$002F BKP1L Bit 7 6 5 4 3 2 1 Bit 0
Write:

$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0030 PPAGE PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
Write:
Read: 0 0 0 0 0 0 0 0
$0031 Reserved
Write:

$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0032 PORTK Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0033 DDRK Bit 7 6 5 4 3 2 1 Bit 0
Write:

34 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0034 - $003F CRG (Clock and Reset Generator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0034 SYNR SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
Write:
Read: 0 0 0 0
$0035 REFDV REFDV3 REFDV2 REFDV1 REFDV0
Write:
CTFLG Read: 0 0 0 0 0 0 0 0
$0036
TEST ONLY Write:
Read: 0 LOCK TRACK SCM
$0037 CRGFLG RTIF PORF LOCKIF SCMIF
Write:
Read: 0 0 0 0 0
$0038 CRGINT RTIE LOCKIE SCMIE
Write:
Read:
$0039 CLKSEL PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
Write:
Read: 0
$003A PLLCTL CME PLLON AUTO ACQ PRE PCE SCME
Write:
Read: 0
$003B RTICTL RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
Write:
Read: 0 0 0
$003C COPCTL WCOP RSBCK CR2 CR1 CR0
Write:
FORBYP Read: 0 0 0 0 0 0 0 0
$003D
TEST ONLY Write:
CTCTL Read: 0 0 0 0 0 0 0 0
$003E
TEST ONLY Write:
Read: 0 0 0 0 0 0 0 0
$003F ARMCOP
Write: Bit 7 6 5 4 3 2 1 Bit 0

$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0040 TIOS IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Write:
Read: 0 0 0 0 0 0 0 0
$0041 CFORC
Write: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Read:
$0042 OC7M OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Write:
Read:
$0043 OC7D OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
$0044 TCNT (hi)
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0045 TCNT (lo)
Write:
Read: 0 0 0 0
$0046 TSCR1 TEN TSWAI TSFRZ TFFCA
Write:
Read:
$0047 TTOV TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
Write:
Read:
$0048 TCTL1 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
Write:
Read:
$0049 TCTL2 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Write:

Freescale Semiconductor 35
Device User Guide — 9S12DT128DGV2/D V02.17

$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$004A TCTL3 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write:
Read:
$004B TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Write:
Read:
$004C TIE C7I C6I C5I C4I C3I C2I C1I C0I
Write:
Read: 0 0 0
$004D TSCR2 TOI TCRE PR2 PR1 PR0
Write:
Read:
$004E TFLG1 C7F C6F C5F C4F C3F C2F C1F C0F
Write:
Read: 0 0 0 0 0 0 0
$004F TFLG2 TOF
Write:
Read:
$0050 TC0 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0051 TC0 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0052 TC1 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0053 TC1 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0054 TC2 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0055 TC2 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0056 TC3 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0057 TC3 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0058 TC4 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0059 TC4 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005A TC5 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005B TC5 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005C TC6 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005D TC6 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005E TC7 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005F TC7 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0
$0060 PACTL PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
Write:
Read: 0 0 0 0 0 0
$0061 PAFLG PAOVF PAIF
Write:
Read:
$0062 PACN3 (hi) Bit 7 6 5 4 3 2 1 Bit 0
Write:

36 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0063 PACN2 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0064 PACN1 (hi) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0065 PACN0 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0
$0066 MCCTL MCZI MODMC RDMCL MCEN MCPR1 MCPR0
Write: ICLAT FLMC
Read: 0 0 0 POLF3 POLF2 POLF1 POLF0
$0067 MCFLG MCZF
Write:
Read: 0 0 0 0
$0068 ICPAR PA3EN PA2EN PA1EN PA0EN
Write:
Read: 0 0 0 0 0 0
$0069 DLYCT DLY1 DLY0
Write:
Read:
$006A ICOVW NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
Write:
Read:
$006B ICSYS SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ
Write:
Read:
$006C Reserved
Write:
TIMTST Read: 0 0 0 0 0 0 0
$006D TCBYP
Test Only Write:
Read:
$006E Reserved
Write:
Read:
$006F Reserved
Write:
Read: 0 0 0 0 0 0
$0070 PBCTL PBEN PBOVI
Write:
Read: 0 0 0 0 0 0 0
$0071 PBFLG PBOVF
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0072 PA3H
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0073 PA2H
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0074 PA1H
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0075 PA0H
Write:
Read:
$0076 MCCNT (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0077 MCCNT (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
$0078 TC0H (hi)
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0079 TC0H (lo)
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
$007A TC1H (hi)
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$007B TC1H (lo)
Write:

Freescale Semiconductor 37
Device User Guide — 9S12DT128DGV2/D V02.17

$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: Bit 15 14 13 12 11 10 9 Bit 8
$007C TC2H (hi)
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$007D TC2H (lo)
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
$007E TC3H (hi)
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$007F TC3H (lo)
Write:

$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0080 ATD0CTL0
Write:
Read: 0 0 0 0 0 0 0 0
$0081 ATD0CTL1
Write:
Read: ASCIF
$0082 ATD0CTL2 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE
Write:
Read: 0
$0083 ATD0CTL3 S8C S4C S2C S1C FIFO FRZ1 FRZ0
Write:
Read:
$0084 ATD0CTL4 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Write:
Read: 0
$0085 ATD0CTL5 DJM DSGN SCAN MULT CC CB CA
Write:
Read: 0 0 CC2 CC1 CC0
$0086 ATD0STAT0 SCF ETORF FIFOR
Write:
Read: 0 0 0 0 0 0 0 0
$0087 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0088 ATD0TEST0
Write:
Read: 0 0 0 0 0 0 0
$0089 ATD0TEST1 SC
Write:
Read: 0 0 0 0 0 0 0 0
$008A Reserved
Write:
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
$008B ATD0STAT1
Write:
Read: 0 0 0 0 0 0 0 0
$008C Reserved
Write:
Read:
$008D ATD0DIEN Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0 0 0 0 0 0 0
$008E Reserved
Write:
Read: Bit7 6 5 4 3 2 1 BIT 0
$008F PORTAD0
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0090 ATD0DR0H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0091 ATD0DR0L
Write:

38 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: Bit15 14 13 12 11 10 9 Bit8
$0092 ATD0DR1H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0093 ATD0DR1L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0094 ATD0DR2H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0095 ATD0DR2L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0096 ATD0DR3H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0097 ATD0DR3L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0098 ATD0DR4H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0099 ATD0DR4L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009A ATD0DR5H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$009B ATD0DR5L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009C ATD0DR6H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$009D ATD0DR6L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009E ATD0DR7H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$009F ATD0DR7L
Write:

$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00A0 PWME PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
Write:
Read:
$00A1 PWMPOL PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
Write:
Read:
$00A2 PWMCLK PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
Write:
Read: 0 0
$00A3 PWMPRCLK PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0
Write:
Read:
$00A4 PWMCAE CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
Write:
Read: 0 0
$00A5 PWMCTL CON67 CON45 CON23 CON01 PSWAI PFRZ
Write:
PWMTST Read: 0 0 0 0 0 0 0 0
$00A6
Test Only Write:
PWMPRSC Read: 0 0 0 0 0 0 0 0
$00A7
Test Only Write:
Read:
$00A8 PWMSCLA Bit 7 6 5 4 3 2 1 Bit 0
Write:

Freescale Semiconductor 39
Device User Guide — 9S12DT128DGV2/D V02.17

40 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$00C8 - $00CF SCI0 (Asynchronous Serial Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$00C8 SCI0BDH SBR12 SBR11 SBR10 SBR9 SBR8
Write:
Read:
$00C9 SCI0BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Write:
Read:
$00CA SCI0CR1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
Write:
Read:
$00CB SCI0CR2 TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Read: TDRE TC RDRF IDLE OR NF FE PF
$00CC SCI0SR1
Write:
Read: 0 0 0 0 0 RAF
$00CD SCI0SR2 BRK13 TXDIR
Write:
Read: R8 0 0 0 0 0 0
$00CE SCI0DRH T8
Write:
Read: R7 R6 R5 R4 R3 R2 R1 R0
$00CF SCI0DRL
Write: T7 T6 T5 T4 T3 T2 T1 T0

$00D0 - $00D7 SCI1 (Asynchronous Serial Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$00D0 SCI1BDH SBR12 SBR11 SBR10 SBR9 SBR8
Write:
Read:
$00D1 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Write:
Read:
$00D2 SCI1CR1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
Write:
Read:
$00D3 SCI1CR2 TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Read: TDRE TC RDRF IDLE OR NF FE PF
$00D4 SCI1SR1
Write:

Freescale Semiconductor 41
Device User Guide — 9S12DT128DGV2/D V02.17

$00D0 - $00D7 SCI1 (Asynchronous Serial Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 RAF
$00D5 SCI1SR2 BRK13 TXDIR
Write:
Read: R8 0 0 0 0 0 0
$00D6 SCI1DRH T8
Write:
Read: R7 R6 R5 R4 R3 R2 R1 R0
$00D7 SCI1DRL
Write: T7 T6 T5 T4 T3 T2 T1 T0

$00D8 - $00DF SPI0 (Serial Peripheral Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00D8 SPI0CR1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Write:
Read: 0 0 0 0
$00D9 SPI0CR2 MODFEN BIDIROE SPISWAI SPC0
Write:
Read: 0 0
$00DA SPI0BR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0
Write:
Read: SPIF 0 SPTEF MODF 0 0 0 0
$00DB SPI0SR
Write:
Read: 0 0 0 0 0 0 0 0
$00DC Reserved
Write:
Read:
$00DD SPI0DR Bit7 6 5 4 3 2 1 Bit0
Write:
Read: 0 0 0 0 0 0 0 0
$00DE Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00DF Reserved
Write:

$00E0 - $00E7 IIC (Inter IC Bus)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00E0 IBAD ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0
Write:
Read:
$00E1 IBFD IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
Write:
Read: 0 0
$00E2 IBCR IBEN IBIE MS/SL TX/RX TXAK IBSWAI
Write: RSTA
Read: TCF IAAS IBB 0 SRW RXAK
$00E3 IBSR IBAL IBIF
Write:
Read:
$00E4 IBDR D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: 0 0 0 0 0 0 0 0
$00E5 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00E6 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00E7 Reserved
Write:

42 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$00F0 - $00F7 SPI1 (Serial Peripheral Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00F0 SPI1CR1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Write:
Read: 0 0 0 0
$00F1 SPI1CR2 MODFEN BIDIROE SPISWAI SPC0
Write:
Read: 0 0
$00F2 SPI1BR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0
Write:
Read: SPIF 0 SPTEF MODF 0 0 0 0
$00F3 SPI1SR
Write:
Read: 0 0 0 0 0 0 0 0
$00F4 Reserved
Write:
Read:
$00F5 SPI1DR Bit7 6 5 4 3 2 1 Bit0
Write:
Read: 0 0 0 0 0 0 0 0
$00F6 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00F7 Reserved
Write:

$00F8 - $00FF Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$00F8 - Read: 0 0 0 0 0 0 0 0
Reserved
$00FF Write:

Freescale Semiconductor 43
Device User Guide — 9S12DT128DGV2/D V02.17

$0100 - $010F Flash Control Register (fts128k2)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: FDIVLD
$0100 FCLKDIV PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
Write:
Read: KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0
$0101 FSEC
Write:
Read: 0 0 0
$0102 FTSTMOD 0 0 0 WRALL 0
Write:
Read: 0 0 0
$0103 FCNFG CBEIE CCIE KEYACC BKSEL1 BKSEL0
Write:
Read:
$0104 FPROT FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
Write:
Read: CCIF 0 0 0
$0105 FSTAT CBEIF PVIOL ACCERR BLANK
Write:
Read: 0 0 0 0
$0106 FCMD CMDB6 CMDB5 CMDB2 CMDB0
Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0107
Factory Test Write:
Read: 0
$0108 FADDRHI Bit 14 13 12 11 10 9 Bit 8
Write:
Read:
$0109 FADDRLO Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$010A FDATAHI Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$010B FDATALO Bit 7 6 5 4 3 2 1 Bit 0
Write:
$010C - Read: 0 0 0 0 0 0 0 0
Reserved
$010F Write:

$0110 - $011B EEPROM Control Register (eets2k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: EDIVLD
$0110 ECLKDIV PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
Write:
Read: 0 0 0 0 0 0 0 0
$0111 Reserved
Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0112
Factory Test Write:
Read: 0 0 0 0 0 0
$0113 ECNFG CBEIE CCIE
Write:
Read: NV6 NV5 NV4
$0114 EPROT EPOPEN EPDIS EP2 EP1 EP0
Write:
Read: CCIF 0 0 0
$0115 ESTAT CBEIF PVIOL ACCERR BLANK
Write:
Read: 0 0 0 0
$0116 ECMD CMDB6 CMDB5 CMDB2 CMDB0
Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0117
Factory Test Write:
Read: 0 0 0 0 0 0
$0118 EADDRHI Bit 9 Bit 8
Write:

44 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0110 - $011B EEPROM Control Register (eets2k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0119 EADDRLO Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$011A EDATAHI Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$011B EDATALO Bit 7 6 5 4 3 2 1 Bit 0
Write:

$011C - $011F Reserved for RAM Control Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$011C - Read: 0 0 0 0 0 0 0 0
Reserved
$011F Write:

$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0120 ATD1CTL0
Write:
Read: 0 0 0 0 0 0 0 0
$0121 ATD1CTL1
Write:
Read: ASCIF
$0122 ATD1CTL2 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE
Write:
Read: 0
$0123 ATD1CTL3 S8C S4C S2C S1C FIFO FRZ1 FRZ0
Write:
Read:
$0124 ATD1CTL4 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Write:
Read: 0
$0125 ATD1CTL5 DJM DSGN SCAN MULT CC CB CA
Write:
Read: SCF 0 ETORF FIFOR 0 CC2 CC1 CC0
$0126 ATD1STAT0
Write:
Read: 0 0 0 0 0 0 0 0
$0127 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0128 ATD1TEST0
Write:
Read: 0 0 0 0 0 0
$0129 ATD1TEST1 0 SC
Write:
Read: 0 0 0 0 0 0 0 0
$012A Reserved
Write:
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
$012B ATD1STAT1
Write:
Read: 0 0 0 0 0 0 0 0
$012C Reserved
Write:
Read:
$012D ATD1DIEN Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0 0 0 0 0 0 0
$012E Reserved
Write:
Read: Bit7 6 5 4 3 2 1 BIT 0
$012F PORTAD1
Write:

Freescale Semiconductor 45
Device User Guide — 9S12DT128DGV2/D V02.17

$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: Bit15 14 13 12 11 10 9 Bit8
$0130 ATD1DR0H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0131 ATD1DR0L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0132 ATD1DR1H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0133 ATD1DR1L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0134 ATD1DR2H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0135 ATD1DR2L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0136 ATD1DR3H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0137 ATD1DR3L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0138 ATD1DR4H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$0139 ATD1DR4L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$013A ATD1DR5H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$013B ATD1DR5L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$013C ATD1DR6H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$013D ATD1DR6L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$013E ATD1DR7H
Write:
Read: Bit7 Bit6 0 0 0 0 0 0
$013F ATD1DR7L
Write:

$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXACT SYNCH
$0140 CAN0CTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ
Write:
Read: 0 SLPAK INITAK
$0141 CAN0CTL1 CANE CLKSRC LOOPB LISTEN WUPM
Write:
Read:
$0142 CAN0BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Read:
$0143 CAN0BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0
$0144 CAN0RFLG WUPIF CSCIF OVRIF RXF
Write:
Read:
$0145 CAN0RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Write:

46 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0
$0146 CAN0TFLG TXE2 TXE1 TXE0
Write:
Read: 0 0 0 0 0
$0147 CAN0TIER TXEIE2 TXEIE1 TXEIE0
Write:
Read: 0 0 0 0 0
$0148 CAN0TARQ ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
$0149 CAN0TAAK
Write:
Read: 0 0 0 0 0
$014A CAN0TBSEL TX2 TX1 TX0
Write:
Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0
$014B CAN0IDAC IDAM1 IDAM0
Write:
Read: 0 0 0 0 0 0 0 0
$014C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$014D Reserved
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
$014E CAN0RXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$014F CAN0TXERR
Write:
$0150 - CAN0IDAR0 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$0153 CAN0IDAR3 Write:
$0154 - CAN0IDMR0 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$0157 CAN0IDMR3 Write:
$0158 - CAN0IDAR4 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$015B CAN0IDAR7 Write:
$015C - CAN0IDMR4 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$015F CAN0IDMR7 Write:
$0160 - Read: FOREGROUND RECEIVE BUFFER see (Table 1-2)
CAN0RXFG
$016F Write:
$0170 - Read:
CAN0TXFG FOREGROUND TRANSMIT BUFFER see (Table 1-2)
$017F Write:

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
$xxx0 Standard ID Read: ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
CANxRIDR0 Write:
Extended ID Read: ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
$xxx1 Standard ID Read: ID2 ID1 ID0 RTR IDE=0
CANxRIDR1 Write:
Extended ID Read: ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
$xxx2 Standard ID Read:
CANxRIDR2 Write:
Extended ID Read: ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
$xxx3 Standard ID Read:
CANxRIDR3 Write:
$xxx4- CANxRDSR0 - Read: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
$xxxB CANxRDSR7 Write:

Freescale Semiconductor 47
Device User Guide — 9S12DT128DGV2/D V02.17

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: DLC3 DLC2 DLC1 DLC0
$xxxC CANRxDLR
Write:
Read:
$xxxD Reserved
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$xxxE CANxRTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$xxxF CANxRTSRL
Write:
Extended ID Read:
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
CANxTIDR0 Write:
$xx10
Standard ID Read:
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
Write:
Extended ID Read:
ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
CANxTIDR1 Write:
$xx11
Standard ID Read:
ID2 ID1 ID0 RTR IDE=0
Write:
Extended ID Read:
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
CANxTIDR2 Write:
$xx12
Standard ID Read:
Write:
Extended ID Read:
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
CANxTIDR3 Write:
$xx13
Standard ID Read:
Write:
$xx14- CANxTDSR0 - Read:
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
$xx1B CANxTDSR7 Write:
Read:
$xx1C CANxTDLR DLC3 DLC2 DLC1 DLC0
Write:
Read:
$xx1D CONxTTBPR PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$xx1E CANxTTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$xx1F CANxTTSRL
Write:

$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXACT SYNCH
$0180 CAN1CTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ
Write:
Read: 0 SLPAK INITAK
$0181 CAN1CTL1 CANE CLKSRC LOOPB LISTEN WUPM
Write:
Read:
$0182 CAN1BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Read:
$0183 CAN1BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0
$0184 CAN1RFLG WUPIF CSCIF OVRIF RXF
Write:

48 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0185 CAN1RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Write:
Read: 0 0 0 0 0
$0186 CAN1TFLG TXE2 TXE1 TXE0
Write:
Read: 0 0 0 0 0
$0187 CAN1TIER TXEIE2 TXEIE1 TXEIE0
Write:
Read: 0 0 0 0 0
$0188 CAN1TARQ ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
$0189 CAN1TAAK
Write:
Read: 0 0 0 0 0
$018A CAN1TBSEL TX2 TX1 TX0
Write:
Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0
$018B CAN1IDAC IDAM1 IDAM0
Write:
Read: 0 0 0 0 0 0 0 0
$018C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$018D Reserved
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
$018E CAN1RXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$018F CAN1TXERR
Write:
$0190 - CAN1IDAR0 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$0193 CAN1IDAR3 Write:
$0194 - CAN1IDMR0 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$0197 CAN1IDMR3 Write:
$0198 - CAN1IDAR4 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$019B CAN1IDAR7 Write:
$019C - CAN1IDMR4 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$019F CAN1IDMR7 Write:
$01A0 - Read: FOREGROUND RECEIVE BUFFER see (Table 1-2)
CAN0RXFG
$01AF Write:
$01B0 - Read:
CAN0TXFG FOREGROUND TRANSMIT BUFFER see (Table 1-2)
$01BF Write:

$01C0 - $01FF Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$01C0 - Read: 0 0 0 0 0 0 0 0
Reserved
$01FF Write:

$0200 - $023F Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$020C - Read: 0 0 0 0 0 0 0 0
Reserved
$023F Write:

Freescale Semiconductor 49
Device User Guide — 9S12DT128DGV2/D V02.17

$0240 - $027F PIM (Port Integration Module)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0240 PTT PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
Write:
Read: PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
$0241 PTIT
Write:
Read:
$0242 DDRT DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Write:
Read:
$0243 RDRT RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Write:
Read:
$0244 PERT PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Write:
Read:
$0245 PPST PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Write:
Read: 0 0 0 0 0 0 0 0
$0246 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0247 Reserved
Write:
Read:
$0248 PTS PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
Write:
Read: PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
$0249 PTIS
Write:
Read:
$024A DDRS DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
Write:
Read:
$024B RDRS RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Write:
Read:
$024C PERS PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
Write:
Read:
$024D PPSS PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
Write:
Read:
$024E WOMS WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
Write:
Read: 0 0 0 0 0 0 0 0
$024F Reserved
Write:
Read:
$0250 PTM PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
Write:
Read: PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
$0251 PTIM
Write:
Read:
$0252 DDRM DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
Write:
Read:
$0253 RDRM RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
Write:
Read:
$0254 PERM PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
Write:
Read:
$0255 PPSM PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
Write:
Read:
$0256 WOMM WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Write:
Read: 0 0
$0257 MODRR MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
Write:
Read:
$0258 PTP PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
Write:

50 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0240 - $027F PIM (Port Integration Module)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
$0259 PTIP
Write:
Read:
$025A DDRP DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Write:
Read:
$025B RDRP RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Write:
Read:
$025C PERP PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
Write:
Read:
$025D PPSP PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0
Write:
Read:
$025E PIEP PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
Write:
Read:
$025F PIFP PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
Write:
Read:
$0260 PTH PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
Write:
Read: PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0
$0261 PTIH
Write:
Read:
$0262 DDRH DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
Write:
Read:
$0263 RDRH RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
Write:
Read:
$0264 PERH PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
Write:
Read:
$0265 PPSH PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
Write:
Read:
$0266 PIEH PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
Write:
Read:
$0267 PIFH PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
Write:
Read: 0 0 0 0
$0268 PTJ PTJ7 PTJ6 PTJ1 PTJ0
Write:
Read: PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0
$0269 PTIJ
Write:
Read: 0 0 0 0
$026A DDRJ DDRJ7 DDRJ7 DDRJ1 DDRJ0
Write:
Read: 0 0 0 0
$026B RDRJ RDRJ7 RDRJ6 RDRJ1 RDRJ0
Write:
Read: 0 0 0 0
$026C PERJ PERJ7 PERJ6 PERJ1 PERJ0
Write:
Read: 0 0 0 0
$026D PPSJ PPSJ7 PPSJ6 PPSJ1 PPSJ0
Write:
Read: 0 0 0 0
$026E PIEJ PIEJ7 PIEJ6 PIEJ1 PIEJ0
Write:
Read: 0 0 0 0
$026F PIFJ PIFJ7 PIFJ6 PIFJ1 PIFJ0
Write:
$0270 - Read: 0 0 0 0 0 0 0 0
Reserved
$027F Write:

Freescale Semiconductor 51
Device User Guide — 9S12DT128DGV2/D V02.17

$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXACT SYNCH
$0280 CAN4CTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ
Write:
Read: 0 SLPAK INITAK
$0281 CAN4CTL1 CANE CLKSRC LOOPB LISTEN WUPM
Write:
Read:
$0282 CAN4BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Read:
$0283 CAN4BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0
$0284 CAN4RFLG WUPIF CSCIF OVRIF RXF
Write:
Read:
$0285 CAN4RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Write:
Read: 0 0 0 0 0
$0286 CAN4TFLG TXE2 TXE1 TXE0
Write:
Read: 0 0 0 0 0
$0287 CAN4TIER TXEIE2 TXEIE1 TXEIE0
Write:
Read: 0 0 0 0 0
$0288 CAN4TARQ ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
$0289 CAN4TAAK
Write:
Read: 0 0 0 0 0
$028A CAN4TBSEL TX2 TX1 TX0
Write:
Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0
$028B CAN4IDAC IDAM1 IDAM0
Write:
Read: 0 0 0 0 0 0 0 0
$028C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$028D Reserved
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
$028E CAN4RXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$028F CAN4TXERR
Write:
$0290 - CAN0IDAR0 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$0293 CAN0IDAR3 Write:
$0294 - CAN0IDMR0 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$0297 CAN0IDMR3 Write:
$0298 - CAN0IDAR4 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$029B CAN0IDAR7 Write:
$029C - CAN0IDMR4 -
Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$029F CAN0IDMR7
$02A0 - Read: FOREGROUND RECEIVE BUFFER see (Table 1-2)
CAN4RXFG
$02AF Write:
$02B0 - Read:
CAN4TXFG FOREGROUND TRANSMIT BUFFER see (Table 1-2)
$02BF Write:

52 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$02C0 - $02FF Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$02C0 - Read: 0 0 0 0 0 0 0 0
Reserved
$02FF Write:

$0300 - $035F Byteflight

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: SLPAK INITAK
$0300 BFMCR INITRQ MASTER ALARM SLPRQ WPULSE SSWAI
Write:
Read: 0 0 0
$0301 BFFSIZR FSIZ4 FSIZ3 FSIZ2 FSIZ1 FSIZ0
Write:
Read:
$0302 BFTCR1 TWX0T7 TWX0T6 TWX0T5 TWX0T4 TWX0T3 TWX0T2 TWX0T1 TWX0T0
Write:
Read:
$0303 BFTCR2 TWX0R7 TWX0R6 TWX0R5 TWX0R4 TWX0R3 TWX0R2 TWX0R1 TWX0R0
Write:
Read:
$0304 BFTCR3 TWX0D7 TWX0D6 TWX0D5 TWX0D4 TWX0D3 TWX0D2 TWX0D1 TWX0D0
Write:
Read: 0 0 0 0 0 0 0 0
$0305 Reserved
Write:
Read: RCVFIF RXIF 0
$0306 BFRISR SYNAIF SYNNIF SLMMIF XSYNIF OPTDF
Write:
Read: TXIF LOCKIF
$0307 BFGISR OVRNIF ERRIF SYNEIF SYNLIF ILLPIF WAKEIF
Write:
Read: 0 0
$0308 BFRIER RCVFIE RXIE SYNAIE SYNNIE SLMMIE XSYNIE
Write:
Read:
$0309 BFGIER TXIE OVRNIE ERRIE SYNEIE SYNLIE ILLPIE LOCKIE WAKEIE
Write:
Read: 0 0 0 0 RIVEC3 RIVEC2 RIVEC1 RIVEC0
$030A BFRIVEC
Write:
Read: 0 0 0 0 TIVEC3 TIVEC2 TIVEC1 TIVEC0
$030B BFTIVEC
Write:
Read:
$030C BFFIDAC FIDAC7 FIDAC6 FIDAC5 FIDAC4 FIDAC3 FIDAC2 FIDAC1 FIDAC0
Write:
Read:
$030D BFFIDMR FIDMR7 FIDMR6 FIDMR5 FIDMR4 FIDMR3 FIDMR2 FIDMR1 FIDMR0
Write:
Read: MVR7 MVR6 MVR5 MVR4 MVR3 MVR2 MVR1 MVR0
$030E BFMVR
Write:
Read: 0 0 0 0 0 0 0 0
$030F Reserved
Write:
Read: 0 0
$0310 BFPCTLBF PMEREN PSLMEN PERREN PROKEN PSYNEN BFEN
Write:
Read: 0 0 0 0 0 0 0 0
$0311 Reserved
Write:
TXBUFL RXBUFL
Read: 0 0 0 0 0 0
$0312 BFBUFLOCK OCK OCK
Write:
Read: 0 0 0 0 0 0 0 0
$0313 Reserved
Write:
Read:
$0314 BFFIDRJ FIDRJ7 FIDRJ6 FIDRJ5 FIDRJ4 FIDRJ3 FIDRJ2 FIDRJ1 FIDRJ0
Write:

Freescale Semiconductor 53
Device User Guide — 9S12DT128DGV2/D V02.17

$0300 - $035F Byteflight

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FIDRMR FIDRMR FIDRMR FIDRMR FIDRMR FIDRMR FIDRMR FIDRMR
Read:
$0315 BFFIDRMR 7 6 5 5 4 3 2 1
Write:
Read: 0 0 0 0 0 0 0 0
$0316 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0317 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0318 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0319 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$031A Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$031B Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$031C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$031D Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$031E Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$031F Reserved
Write:
Read:
$0320 BFTIDENT ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
Read:
$0321 BFTLEN LEN3 LEN2 LEN1 LEN0
Write:
$0322 - BFTDATA0- Read:
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
$032D BFTDATA11 Write:
$032E - Read:
Reserved
$032F Write:
Read:
$0330 BFRIDENT ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
Read:
$0331 BFRLEN LEN3 LEN2 LEN1 LEN0
Write:
$0332 - BFRDATA0- Read:
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA 0
$033D BFRDATA11 Write:
$033E- Read:
Reserved
$033F Write:
Read:
$0340 BFFIDENT ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
Read:
$0341 BFFLEN LEN3 LEN2 LEN1 LEN0
Write:
$0342 - BFFDATA0- Read:
DATA 7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
$034D BFFDATA11 Write:
$034E - Read:
Reserved
$034F Write:
$0350 - BFBUFCTL0 - Read: ABTAK 0 0
IFLG IENA LOCK ABTRQ CFG
$035F BFBUFCTL15 Write:

54 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

$0360 - $03FF Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0360 - Read: 0 0 0 0 0 0 0 0
Reserved
$03FF Write:

1.6 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset). The read-only value is a unique part ID for each revision of the chip. (Table 1-3) shows the
assigned part ID number.

Table 1-3 Assigned Part ID Numbers

Device Mask Set Number Part ID1
MC9S12DT128 1L40K $0111
MC9S12DT128 3L40K $0113
MC9S12DT128 4L40K $0114
MC9S12DT128 0L94R $0110
MC9S12DT128 1L59W $0115
MC9S12DT128 5L40K $0115
MC9S12DT128 2L94R $0115
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision

The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to HCS12 Module
Mapping Control (MMC) Block Guide for further details.

Table 1-4 Memory size registers

Freescale Semiconductor 55
Device User Guide — 9S12DT128DGV2/D V02.17

56 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Section 2 Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.

2.1 Device Pinout

The MC9S12DT128 and its derivatives are available in a 112-pin low profile quad flat pack (LQFP) and
in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal
Descriptions. Figure 2-1, Figure 2-2, and Figure 2-3 show the pin assignments for different packages.

Freescale Semiconductor 57
Device User Guide — 9S12DT128DGV2/D V02.17

PM4/BF_PSYN/RXCAN0/RXCAN4/MOSI0
PM5/BF_PROK/TXCAN0/TXCAN4/SCK0
PM2/RX_BF/RXCAN1/RXCAN0/MISO0
PM3/TX_BF/TXCAN1/TXCAN0/SS0

PJ6/KWJ6/RXCAN4/SDA/RXCAN0
PJ7/KWJ7/TXCAN4/SCL/TXCAN0

PM6/BF_PERR/RXCAN4
PM7/BF_PSLM/TXCAN4
PK7/ECS/ROMCTL

PM0/RXCAN0/RXB
PM1/TXCAN0/TXB
PP6/KWP6/PWM6
PP4/KWP4/PWM4
PP5/KWP5/PWM5

PP7/KWP7/PWM7

PS5/MOSI0
PS4/MISO0
PS6/SCK0

PS2/RXD1

PS0/RXD0
PS3/TXD1

PS1/TXD0
VREGEN
PS7/SS0
VDDX
VSSX

VSSA
VRL
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
SS1/PWM3/KWP3/PP3 1 84 VRH
SCK1/PWM2/KWP2/PP2 2 83 VDDA
MOSI1/PWM1/KWP1/PP1 3 82 PAD15/AN15/ETRIG1
MISO1/PWM0/KWP0/PP0 4 81 PAD07/AN07/ETRIG0
XADDR17/PK3 5 80 PAD14/AN14
XADDR16/PK2 6 79 PAD06/AN06
XADDR15/PK1 7 78 PAD13/AN13
XADDR14/PK0 8 77 PAD05/AN05
IOC0/PT0 9 76 PAD12/AN12
IOC1/PT1 10 75 PAD04/AN04
IOC2/PT2 11 74 PAD11/AN11
IOC3/PT3 12 MC9S12DT128E, MC9S12DT128, MC9S12DG128E, 73 PAD03/AN03
VDD1 13 MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, 72 PAD10/AN10
VSS1 14 MC9S12DB128, MC9S12A128, SC515846, SC515847, 71 PAD02/AN02
IOC4/PT4 15 SC515848, SC515849, SC101161DT, SC101161DG, 70 PAD09/AN09
IOC5/PT5 16 69 PAD01/AN01
SC101161DJ, SC102202, SC102203, SC102204,
IOC6/PT6 17 68 PAD08/AN08
SC102205
IOC7/PT7 18 112LQFP 67 PAD00/AN00
XADDR19/PK5 19 66 VSS2
XADDR18/PK4 20 65 VDD2
KWJ1/PJ1 21 64 PA7/ADDR15/DATA15
KWJ0/PJ0 22 63 PA6/ADDR14/DATA14
MODC/TAGHI/BKGD 23 62 PA5/ADDR13/DATA13
ADDR0/DATA0/PB0 24 61 PA4/ADDR12/DATA12
ADDR1/DATA1/PB1 25 60 PA3/ADDR11/DATA11
ADDR2/DATA2/PB2 26 59 PA2/ADDR10/DATA10
ADDR3/DATA3/PB3 27 58 PA1/ADDR9/DATA9
ADDR4/DATA4/PB4 28 57 PA0/ADDR8/DATA8
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
KWH7/PH7
KWH6/PH6
KWH5/PH5
KWH4/PH4
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4

SS1/KWH3/PH3
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST

SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0

Signals shown in Bold are not available on all the 80 pin package options
Signals shown in Bold-Italics are not available on the MC9S12DJ128E, MC9S12DJ128, MC9S12DG128E, MC9S12DG128, MC9S12A128,
SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 80 pin package options
Signals shown in Italics are not available on the MC9S12DB128, SC515846, and SC102202 80 pin package options

Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128E, MC9S12DT128,

MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12DB128
MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204, and SC102205

58 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

PJ6/KWJ6/RXCAN4/SDA/RXCAN0
PJ7/KWJ7/TXCAN4/SCL/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0

PM4/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN0/TXCAN4/SCK0
PM3/TXCAN1/TXCAN0/SS0
PM0/RXCAN0/RXB
PM1/TXCAN0/TXB
PP4/KWP4/PWM4
PP5/KWP5/PWM5
PP7/KWP7/PWM7

PS2//RXD1

PS0/RXD0
PS3/TXD1

PS1/TXD0
VREGEN
VDDX
VSSX

VSSA
VRL
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
SS1/PWM3/KWP3/PP3 1 60 VRH
SCK1/PWM2/KWP2/PP2 2 59 VDDA
MOSI1/PWM1/KWP1/PP1 3 58 PAD07/AN07/ETRIG0
MISO1/PWM0/KWP0/PP0 4 57 PAD06/AN06
IOC0/PT0 5 56 PAD05/AN05
IOC1/PT1 6 55 PAD04/AN04
IOC2/PT2 7 54 PAD03/AN03
IOC3/PT3 8 MC9S12DG128E, MC9S12DG128, 53 PAD02/AN02
VDD1 9 MC9S12DJ128E, MC9S12DJ128, 52 PAD01/AN01
VSS1 10 MC9S12A128, SC515847, 51 PAD00/AN00
IOC4/PT4 11 SC515848, SC101161DG, 50 VSS2
IOC5/PT5 12 SC101161DJ, SC102203, SC102204 49 VDD2
IOC6/PT6 13 80 QFP 48 PA7/ADDR15/DATA15
IOC7/PT7 14 47 PA6/ADDR14/DATA14
MODC/TAGHI/BKGD 15 46 PA5/ADDR13/DATA13
ADDR0/DATA0/PB0 16 45 PA4/ADDR12/DATA12
ADDR1/DATA1/PB1 17 44 PA3/ADDR11/DATA11
ADDR2/DATA2/PB2 18 43 PA2/ADDR10/DATA10
ADDR3/DATA3/PB3 19 42 PA1/ADDR9/DATA9
ADDR4/DATA4/PB4 20 41 PA0/ADDR8/DATA8
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7

MODB/IPIPE1/PE6
XCLKS/NOACC/PE7

MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0

Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128,

MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204 Bondout

Freescale Semiconductor 59
Device User Guide — 9S12DT128DGV2/D V02.17

PP4/KWP4/PWM4
PP5/KWP5/PWM5
PP7/KWP7/PWM7

PM5/BF_PROK

PM6/BF_PERR
PM4/BF_PSYN

PM7/BF_PSLM
PM2/RX_BF
PM3/TX_BF

PS5/MOSI0
PS4/MISO0

PS0/RXD0
PS6/SCK0

PS1/TXD0
VREGEN
PS7/SS0
VDDX
VSSX

VSSA
VRL
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
SS1/PWM3/KWP3/PP3 1 60 VRH
SCK1/PWM2/KWP2/PP2 2 59 VDDA
MOSI1/PWM1/KWP1/PP1 3 58 PAD07/AN07/ETRIG0
MISO1/PWM0/KWP0/PP0 4 57 PAD06/AN06
IOC0/PT0 5 56 PAD05/AN05
IOC1/PT1 6 55 PAD04/AN04
IOC2/PT2 7 54 PAD03/AN03
IOC3/PT3 8 53 PAD02/AN02
VDD1 9 52 PAD01/AN01
VSS1 10 MC9S12DB128, SC515846, 51 PAD00/AN00
IOC4/PT4 11 50 VSS2
SC102202
IOC5/PT5 12 80 QFP 49 VDD2
IOC6/PT6 13 48 PA7/ADDR15/DATA15
IOC7/PT7 14 47 PA6/ADDR14/DATA14
MODC/TAGHI/BKGD 15 46 PA5/ADDR13/DATA13
ADDR0/DATA0/PB0 16 45 PA4/ADDR12/DATA12
ADDR1/DATA1/PB1 17 44 PA3/ADDR11/DATA11
ADDR2/DATA2/PB2 18 43 PA2/ADDR10/DATA10
ADDR3/DATA3/PB3 19 42 PA1/ADDR9/DATA9
ADDR4/DATA4/PB4 20 41 PA0/ADDR8/DATA8
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0

Figure 2-3 Pin Assignments in 80 QFP for MC9S12DB128, SC515846, and SC102202
Bondout

2.2 Signal Properties Summary

(Table 2-1) summarizes the pin functionality. Signals shown in Bold are not available on all the 80-pin
package options. Signals shown in Bold-Italics are not available on the MC9S12DG128E,
MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848,
SC101161DG, SC101161DJ, SC102203, and SC102204 80-pin package options. Signals shown in Italics
are not available on MC9S12DB128, SC515846, and SC102202 80-pin package options.

60 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Table 2-1 Signal Properties

Internal Pull
Pin Name Pin Name Pin Name Pin Name Pin Name Powered Resistor
Description
Function 1 Function 2 Function 3 Function 4 Function 5 by Reset
CTRL State
EXTAL — — — — VDDPLL NA NA
Oscillator Pins
XTAL — — — — VDDPLL NA NA
RESET — — — — VDDR None None External Reset
TEST — — — — N.A. None None Test Input
Voltage Regulator
VREGEN — — — — VDDX NA NA
Enable Input
XFC — — — — VDDPLL NA NA PLL Loop Filter
Always Background Debug,
BKGD TAGHI MODC — — VDDR Up
Up Tag High, Mode Input
Port AD Input,
Analog Inputs,
PAD[15] AN1[7] ETRIG1 — — VDDA None None
External Trigger
Input (ATD1)
Port AD Input,
PAD[14:8] AN1[6:0] — — — VDDA None None Analog Inputs
(ATD1)
Port AD Input, Analog
PAD[7] AN0[7] ETRIG0 — — VDDA None None Inputs, External
Trigger Input (ATD0)
Port AD Input, Analog
PAD[6:0] AN0[6:0] — — — VDDA None None
Inputs (ATD0)
Port A I/O,
ADDR[15:8]/ PUCR/
PA[7:0] — — — VDDR Disabled Multiplexed
DATA[15:8] PUPAE
Address/Data
Port B I/O,
ADDR[7:0]/ PUCR/
PB[7:0] — — — VDDR Disabled Multiplexed
DATA[7:0] PUPBE
Address/Data
Mode
PUCR/ depen- Port E I/O, Access,
PE7 NOACC XCLKS — — VDDR
PUPEE Clock Select
dant1
Port E I/O, Pipe
PE6 IPIPE1 MODB — — VDDR While RESET pin Status, Mode Input
low:
Down Port E I/O, Pipe
PE5 IPIPE0 MODA — — VDDR
Status, Mode Input
Port E I/O, Bus Clock
PE4 ECLK — — — VDDR
Output
Mode
depen- Port E I/O, Byte
PE3 LSTRB TAGLO — — VDDR
Strobe, Tag Low
dant1
PUCR/ Port E I/O, R/W in
PE2 R/W — — — VDDR
PUPEE expanded modes
Port E Input,
PE1 IRQ — — — VDDR
Maskable Interrupt
Up
Port E Input, Non
PE0 XIRQ — — — VDDR
Maskable Interrupt
PERH/
PH7 KWH7 --- — — VDDR Disabled Port H I/O, Interrupt
PPSH

Freescale Semiconductor 61
Device User Guide — 9S12DT128DGV2/D V02.17

Internal Pull
Pin Name Pin Name Pin Name Pin Name Pin Name Powered Resistor
Description
Function 1 Function 2 Function 3 Function 4 Function 5 by Reset
CTRL State
PERH/
PH6 KWH6 --- — — VDDR Disabled Port H I/O, Interrupt
PPSH
PERH/
PH5 KWH5 --- — — VDDR Disabled Port H I/O, Interrupt
PPSH
PERH/
PH4 KWH4 --- — — VDDR Disabled Port H I/O, Interrupt
PPSH
PERH/ Port H I/O, Interrupt,
PH3 KWH3 SS1 — — VDDR Disabled
PPSH SS of SPI1
PERH/ Port H I/O, Interrupt,
PH2 KWH2 SCK1 — — VDDR Disabled
PPSH SCK of SPI1
PERH/ Port H I/O, Interrupt,
PH1 KWH1 MOSI1 — — VDDR Disabled
PPSH MOSI of SPI1
PERH/ Port H I/O, Interrupt,
PH0 KWH0 MISO1 — — VDDR Disabled
PPSH MISO of SPI1
Port J I/O, Interrupt,
PERJ/
PJ7 KWJ7 TXCAN4 SCL TXCAN0 VDDX Up TX of CAN4, SCL of
PPSJ
IIC
Port J I/O, Interrupt,
PERJ/
PJ6 KWJ6 RXCAN4 SDA RXCAN0 VDDX Up RX of CAN4, SDA of
PPSJ
IIC
PERJ/
PJ[1:0] KWJ[1:0] — — — VDDX Up Port J I/O, Interrupts
PPSJ
Port K I/O,
PUCR/
PK7 ECS ROMCTL — — VDDX Up Emulation Chip
PUPKE
Select, ROM Control
XADDR[19: PUCR/ Port K I/O, Extended
PK[5:0] — — — VDDX Up
14] PUPKE Addresses
Port M I/O, BF slot
PERM/
PM7 BF_PSLM TXCAN4 — — VDDX Disabled mismatch pulse, TX
PPSM
of CAN4
Port M I/O, BF illegal
PERM/ pulse/message
PM6 BF_PERR RXCAN4 — — VDDX Disabled
PPSM format error pulse,
RX of CAN4
Port M I/O, BF
PERM/ reception ok pulse,
PM5 BF_PROK TXCAN0 TXCAN4 SCK0 VDDX Disabled
PPSM TX of CAN0, CAN4,
SCK of SPI0
Port M I/O, BF sync
pulse (Rx/Tx) OK
PERM/
PM4 BF_PSYN RXCAN0 RXCAN4 MOSI0 VDDX Disabled pulse o/p, RX of
PPSM
CAN0, CAN4, MOSI
of SPI0
Port M I/O, TX of BF,
PERM/
PM3 TX_BF TXCAN1 TXCAN0 SS0 VDDX Disabled CAN1, CAN0, SS of
PPSM
SPI0
Port M I/O, RX of BF,
PERM/
PM2 RX_BF RXCAN1 RXCAN0 MISO0 VDDX Disabled CAN1, CAN0, MISO
PPSM
of SPI0

62 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

Internal Pull
Pin Name Pin Name Pin Name Pin Name Pin Name Powered Resistor
Description
Function 1 Function 2 Function 3 Function 4 Function 5 by Reset
CTRL State
PERM/ Port M I/O, TX of
PM1 TXCAN0 TXB — — VDDX Disabled
PPSM CAN0, RX of BDLC
PERM/ Port M I/O, RX of
PM0 RXCAN0 RXB — — VDDX Disabled
PPSM CAN0, RX of BDLC
PERP/ Port P I/O, Interrupt,
PP7 KWP7 PWM7 — — VDDX Disabled
PPSP Channel 7 of PWM
PERP/ Port P I/O, Interrupt,
PP6 KWP6 PWM6 — — VDDX Disabled
PPSP Channel 6 of PWM
PERP/ Port P I/O, Interrupt,
PP5 KWP5 PWM5 — — VDDX Disabled
PPSP Channel 5 of PWM
PERP/ Port P I/O, Interrupt,
PP4 KWP4 PWM4 — — VDDX Disabled
PPSP Channel 4 of PWM
Port P I/O, Interrupt,
PERP/
PP3 KWP3 PWM3 SS1 — VDDX Disabled Channel 3 of PWM,
PPSP
SS of SPI1
Port P I/O, Interrupt,
PERP/
PP2 KWP2 PWM2 SCK1 — VDDX Disabled Channel 2 of PWM,
PPSP
SCK of SPI1
Port P I/O, Interrupt,
PERP/
PP1 KWP1 PWM1 MOSI1 — VDDX Disabled Channel 1 of PWM,
PPSP
MOSI of SPI1
Port P I/O, Interrupt,
PERP/
PP0 KWP0 PWM0 MISO1 — VDDX Disabled Channel 0 of PWM,
PPSP
MISO2 of SPI1
PERS/ Port S I/O, SS of
PS7 SS0 — — — VDDX Up
PPSS SPI0
PERS/ Port S I/O, SCK of
PS6 SCK0 — — — VDDX Up
PPSS SPI0
PERS/ Port S I/O, MOSI of
PS5 MOSI0 — — — VDDX Up
PPSS SPI0
PERS/ Port S I/O, MISO of
PS4 MISO0 — — — VDDX Up
PPSS SPI0
PERS/ Port S I/O, TXD of
PS3 TXD1 — — — VDDX Up
PPSS SCI1
PERS/ Port S I/O, RXD of
PS2 RXD1 — — — VDDX Up
PPSS SCI1
PERS/ Port S I/O, TXD of
PS1 TXD0 — — — VDDX Up
PPSS SCI0
PERS/ Port S I/O, RXD of
PS0 RXD0 — — — VDDX Up
PPSS SCI0
PERT/ Port T I/O, Timer
PT[7:0] IOC[7:0] — — — VDDX Disabled
PPST channels
NOTES:
1. Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide.

Freescale Semiconductor 63
Device User Guide — 9S12DT128DGV2/D V02.17

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.

2.3.2 RESET — External Reset Pin

An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.

2.3.3 TEST — Test Pin

This input only pin is reserved for test.

NOTE: The TEST pin must be tied to VSS in all applications.

2.3.4 XFC — PLL Loop Filter Pin

PLL loop filter. Please ask your Freescale representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.

XFC

R
CP
MCU
CS

VDDPLL VDDPLL

Figure 2-4 PLL Loop Filter Connections

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin

The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.

64 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15]

PAD15 is a general purpose input pin and analog input of the analog to digital converter ATD1. It can act
as an external trigger input for the ATD1.

2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]

PAD14 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD1.

2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7]

PAD7 is a general purpose input pin and analog input of the analog to digital converter ATD0. It can act
as an external trigger input for the ATD0.

2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]

PAD6 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD0.

2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.

2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins

PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.

2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7

PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
(low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this
pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an
external clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since
this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is
an oscillator circuit on EXTAL and XTAL.

Freescale Semiconductor 65
Device User Guide — 9S12DT128DGV2/D V02.17

EXTAL
CDC *
MCU C1 Crystal or
ceramic resonator

XTAL
C2

VSSPLL

* Due to the nature of a translated ground Colpitts oscillator a

DC voltage bias is applied to the crystal
Please contact the crystal manufacturer for crystal DC
bias conditions and recommended capacitor value CDC.

Figure 2-5 Colpitts Oscillator Connections (PE7=1)

EXTAL
C1
MCU RB Crystal or
ceramic resonator
RS*
XTAL
C2
VSSPLL

* Rs can be zero (shorted) when used with higher frequency crystals.

Refer to manufacturer’s data.

Figure 2-6 Pierce Oscillator Connections (PE7=0)

EXTAL CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
(VDDPLL-Level)
MCU

XTAL not connected

Figure 2-7 External Clock Connections (PE7=0)

66 Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17

2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6

PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.

2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5

PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.

2.3.15 PE4 / ECLK — Port E I/O Pin 4

PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.

2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3

PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.

2.3.17 PE2 / R/W — Port E I/O Pin 2

PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.

2.3.18 PE1 / IRQ — Port E Input Pin 1

PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.19 PE0 / XIRQ — Port E Input Pin 0

PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.20 PH7 / KWH7 — Port H I/O Pin 7

PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

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2.3.21 PH6 / KWH6 — Port H I/O Pin 6

PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

2.3.22 PH5 / KWH5 — Port H I/O Pin 5

PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

2.3.23 PH4 / KWH4 — Port H I/O Pin 2

PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3

PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
1 (SPI1).

2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2

PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
1 (SPI1).

2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1

PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).

2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0

PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).

2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7

PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable
Controller Area Network controller 0 or 4 (CAN0, CAN4) or the serial clock pin SCL of the IIC module.

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2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6

PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable
Controller Area Network controller 0 or 4 (CAN0, CAN4) or the serial data pin SDA of the IIC module.

2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]

PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.

2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7

PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (ECS). While configurating MCU expanded modes, this pin is used to
enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit. For a complete list of modes refer to 4.2 Chip
Configuration Summary.

2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]

PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.

2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7

PM7 is a general purpose input or output pin. It can be configured as the slot mismatch output pulse pin
of Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area
Network controllers 4 (CAN4).

2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6

PM6 is a general purpose input or output pin. It can be configured as the illegal pulse or message format
error output pulse pin of Byteflight. It can be configured as the receive pin RXCAN of the Motorola
Scalable Controller Area Network controllers 4 (CAN4).

2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5

PM5 is a general purpose input or output pin. It can be configured as the reception OK output pulse pin of
Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area
Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).

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2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4

PM4 is a general purpose input or output pin. It can be configured as the correct synchronisation pulse
reception/transmission output pulse pin of Byteflight. It can be configured as the receive pin RXCAN of
the Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured
as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial
Peripheral Interface 0 (SPI0).

2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3

PM3 is a general purpose input or output pin. It can be configured as the transmit pinTX_BF of Byteflight.
It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network
controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the Serial Peripheral
Interface 0 (SPI0).

2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2

PM2 is a general purpose input or output pin. It can be configured as the receive pin RX_BF of Byteflight.
It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network
controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave
output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).

2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1

PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin
TXB of the BDLC.

2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0

PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin
RXB of the BDLC.

2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7

PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output.

2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6

PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output.

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2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5

PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output.

2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4

PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output.

2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3

PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).

2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2

PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).

2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1

PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).

2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0

PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).

2.3.49 PS7 / SS0 — Port S I/O Pin 7

PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).

2.3.50 PS6 / SCK0 — Port S I/O Pin 6

PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).

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2.3.51 PS5 / MOSI0 — Port S I/O Pin 5

PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).

2.3.52 PS4 / MISO0 — Port S I/O Pin 4

PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).

2.3.53 PS3 / TXD1 — Port S I/O Pin 3

PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).

2.3.54 PS2 / RXD1 — Port S I/O Pin 2

PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).

2.3.55 PS1 / TXD0 — Port S I/O Pin 1

PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).

2.3.56 PS0 / RXD0 — Port S I/O Pin 0

PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).

2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]

PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).

2.4 Power Supply Pins

MC9S12DT128 power and ground pins are described below.
Table 2-2 MC9S12DT128 Power and Ground Connection Summary
Pin Number Nominal
Mnemonic Description
112-pin QFP Voltage
VDD1, 2 13, 65 2.5V
Internal power and ground generated by internal regulator
VSS1, 2 14, 66 0V

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Pin Number Nominal

Mnemonic Description
112-pin QFP Voltage
VDDR 41 5.0V External power and ground, supply to pin drivers and internal
VSSR 40 0V voltage regulator.
VDDX 107 5.0V
External power and ground, supply to pin drivers.
VSSX 106 0V
VDDA 83 5.0V Operating voltage and ground for the analog-to-digital
converters and the reference for the internal voltage regulator,
VSSA 86 0V allows the supply voltage to the A/D to be bypassed
independently.
VRL 85 0V
Reference voltages for the analog-to-digital converter.
VRH 84 5.0V
VDDPLL 43 2.5V Provides operating voltage and ground for the Phased-Locked
Loop. This allows the supply voltage to the PLL to be
VSSPLL 45 0V bypassed independently. Internal power and ground
generated by internal regulator.
VREGEN 97 5V Internal Voltage Regulator enable/disable

NOTE: All VSS pins must be connected together in the application.

2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers

External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.

2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator

External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.

2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins

Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.

NOTE: No load allowed except for bypass capacitors.

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2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG

VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.

2.4.5 VRH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog to digital converter.

2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL

Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by
the internal voltage regulator.

NOTE: No load allowed except for bypass capacitors.

2.4.7 VREGEN — On Chip Voltage Regulator Enable

Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be
supplied externally.

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Section 3 System Clock Description

3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.

HCS12 CORE
BDM CPU

MEBI MMC
core clock
INT BKP

Flash

RAM

EEPROM

EXTAL ECT

ATD0, 1

bus clock PWM

CRG
SCI0, SCI1
oscillator clock
XTAL SPI0, 1

CAN0, 1, 4

IIC

BDLC

PIM

Figure 3-1 Clock Connections

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Section 4 Modes of Operation

4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12DT128. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset ((Table 4-1)). The MODC, MODB, and MODA bits in the MODE register show the current
operating mode and provide limited mode switching during operation. The states of the MODC, MODB,
and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal
allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is
visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the
ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.

Table 4-1 Mode Selection

BKGD = PE6 = PE5 = PK7 = ROMON Mode Description
MODC MODB MODA ROMCTL Bit
Special Single Chip, BDM allowed and ACTIVE. BDM is
0 0 0 X 1 allowed in all other modes but a serial command is
required to make BDM active.
0 1
0 0 1 Emulation Expanded Narrow, BDM allowed
1 0
0 1 0 X 0 Special Test (Expanded Wide), BDM allowed
0 1
0 1 1 Emulation Expanded Wide, BDM allowed
1 0
1 0 0 X 1 Normal Single Chip, BDM allowed
0 0
1 0 1 Normal Expanded Narrow, BDM allowed
1 1
Special Peripheral; BDM allowed but bus operations
1 1 0 X 1
would cause bus conflicts (must not be used)
0 0
1 1 1 Normal Expanded Wide, BDM allowed
1 1

For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide.

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS Description
1 Colpitts Oscillator selected
0 Pierce Oscillator/external clock selected

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Table 4-3 Voltage Regulator VREGEN

VREGEN Description
1 Internal Voltage Regulator enabled
Internal Voltage Regulator disabled, VDD1,2 and
0
VDDPLL must be supplied externally with 2.5V

4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
• Protection of the contents of FLASH,
• Protection of the contents of EEPROM,
• Operation in single-chip mode, No BDM possible
• Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.

4.3.1 Securing the Microcontroller

Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.

4.3.2 Operation of the Secured Microcontroller

4.3.2.1 Normal Single Chip Mode

This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.

4.3.2.2 Executing from External Memory

The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.

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4.3.3 Unsecuring the Microcontroller

In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode or via a .sequence of BDM commands. Unsecuring
is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.

4.4 Low Power Modes

The microcontroller features three main low power modes. Consult the respective Block User Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator User Guide (CRG).

4.4.1 Stop

Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.

4.4.2 Pseudo Stop

This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.

4.4.3 Wait

This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.

4.4.4 Run

Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.

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Section 5 Resets and Interrupts

5.1 Overview
Consult the Exception Processing section of the CPU Reference Manual for information on resets and
interrupts.

5.2 Vectors
5.2.1 Vector Table

(Table 5-1) lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
Vector Address Interrupt Source CCR Local Enable HPRIO Value
Mask to Elevate
$FFFE, $FFFF Reset None None –
$FFFC, $FFFD Clock Monitor fail reset None COPCTL (CME, FCME) –
$FFFA, $FFFB COP failure reset None COP rate select –
$FFF8, $FFF9 Unimplemented instruction trap None None –
$FFF6, $FFF7 SWI None None –
$FFF4, $FFF5 XIRQ / BF High Priority Sync Pulse X-Bit None / BFRIER (XSYNIE) –
$FFF2, $FFF3 IRQ I-Bit INTCR (IRQEN) $F2
$FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0
$FFEE, $FFEF Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE
$FFEC, $FFED Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC
$FFEA, $FFEB Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA
$FFE8, $FFE9 Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8
$FFE6, $FFE7 Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6
$FFE4, $FFE5 Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4
$FFE2, $FFE3 Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2
$FFE0, $FFE1 Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0
$FFDE, $FFDF Enhanced Capture Timer overflow I-Bit TSCR2 (TOF) $DE
$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC
$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA
$FFD8, $FFD9 SPI0 I-Bit SPICR1 (SPIE, SPTIE) $D8
SCICR2
$FFD6, $FFD7 SCI0 I-Bit $D6
(TIE, TCIE, RIE, ILIE)
SCICR2
$FFD4, $FFD5 SCI1 I-Bit $D4
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3 ATD0 I-Bit ATDCTL2 (ASCIE) $D2
$FFD0, $FFD1 ATD1 I-Bit ATDCTL2 (ASCIE) $D0
PIEJ
$FFCE, $FFCF Port J I-Bit $CE
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
$FFCC, $FFCD Port H I-Bit PIEH (PIEH7-0) $CC

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$FFCA, $FFCB Modulus Down Counter underflow I-Bit MCCTL (MCZI) $CA
$FFC8, $FFC9 Pulse Accumulator B Overflow I-Bit PBCTL (PBOVI) $C8
$FFC6, $FFC7 CRG PLL lock I-Bit PLLCR (LOCKIE) $C6
$FFC4, $FFC5 CRG Self Clock Mode I-Bit PLLCR (SCMIE) $C4
$FFC2, $FFC3 BDLC I-Bit DLCBCR1 (IE) $C2
$FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0
$FFBE, $FFBF SPI1 I-Bit SPICR1 (SPIE, SPTIE) $BE
$FFBC, $FFBD Reserved
$FFBA, $FFBB EEPROM I-Bit ECNFG (CCIE, CBEIE) $BA
$FFB8, $FFB9 FLASH I-Bit FCNFG (CCIE, CBEIE) $B8
$FFB6, $FFB7 CAN0 wake-up I-Bit CANRIER (WUPIE) $B6
$FFB4, $FFB5 CAN0 errors I-Bit CANRIER (CSCIE, OVRIE) $B4
$FFB2, $FFB3 CAN0 receive I-Bit CANRIER (RXFIE) $B2
$FFB0, $FFB1 CAN0 transmit I-Bit CANTIER (TXEIE[2:0]) $B0
$FFAE, $FFAF CAN1 wake-up I-Bit CANRIER (WUPIE) $AE
$FFAC, $FFAD CAN1 errors I-Bit CANRIER (CSCIE, OVRIE) $AC
$FFAA, $FFAB CAN1 receive I-Bit CANRIER (RXFIE) $AA
$FFA8, $FFA9 CAN1 transmit I-Bit CANTIER (TXEIE[2:0]) $A8
$FFA6, $FFA7 BF Receive FIFO not empty I-Bit BFRIER (RCVFIE) $A6
$FFA4, $FFA5 BF receive I-Bit BFBUFCTL[15:0] (IENA) $A4
$FFA2, $FFA3 BF Synchronization I-Bit BFRIER (SYNAIE, SYNNIE) $A2
BFBUFCTL[15:0] (IENA),
BFGIER (OVRNIE, ERRIE,
$FFA0, $FFA1 BF general I-Bit SYNEIE, SYNLIE, ILLPIE, $A0
LOCKIE, WAKEIE)
BFRIER (SLMMIE)
$FF98, $FF9F Reserved
$FF96, $FF97 CAN4 wake-up I-Bit CANRIER (WUPIE) $96
$FF94, $FF95 CAN4 errors I-Bit CANRIER (CSCIE, OVRIE) $94
$FF92, $FF93 CAN4 receive I-Bit CANRIER (RXFIE) $92
$FF90, $FF91 CAN4 transmit I-Bit CANTIER (TXEIE[2:0]) $90
$FF8E, $FF8F Port P Interrupt I-Bit PIEP (PIEP7-0) $8E
$FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C
$FF80 to
Reserved
$FF8B

5.3 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.

5.3.1 I/O pins

Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin
configuration of port A, B, E and K out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.

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NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be
configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to Table 2-1 for affected pins.

5.3.2 Memory

Refer to Table 1-1 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.

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84 Freescale Semiconductor
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Section 6 HCS12 Core Block Description

6.1 CPU Block Description

Consult the CPU Reference Manual for information on the CPU.

6.1.1 Device-specific information

When the CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods. So 1 cycle is
equivalent to 1 Bus Clock period.

6.2 HCS12 Module Mapping Control (MMC) Block Description

Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module.

6.2.1 Device-specific information

• INITEE
– Reset state: $01
– Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special
modes".
• PPAGE
– Reset state: $00
– Register is "Write anytime in all modes".
• MEMSIZ0
– Reset state: $13
• MEMSIZ1
– Reset state: $80

6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block

Description
Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module.

6.3.1 Device-specific information

• PUCR
– Reset state: $90

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6.4 HCS12 Interrupt (INT) Block Description

Consult the INT Block Guide for information on the HCS12 Interrupt module.

6.5 HCS12 Background Debug Module (BDM) Block Description

Consult the BDM Block Guide for information on the HCS12 Background Debug module.

6.5.1 Device-specific information

When the BDM Block Guide refers to alternate clock this is equivalent to oscillator clock.

6.6 HCS12 Breakpoint (BKP) Block Description

Consult the BKP Block Guide for information on the HCS12 Breakpoint module.

Section 7 Clock and Reset Generator (CRG) Block

Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.

7.1 Device-specific information

The Low Voltage Reset feature of the CRG is not available on this device.

Section 8 Oscillator (OSC) Block Description

Consult the OSC Block User Guide for information about the Oscillator module.

8.1 Device-specific information

The XCLKS input signal is active low (see 2.3.12 PE / NOACC / XCLKS — Port E I/O Pin 7).

Section 9 Enhanced Capture Timer (ECT) Block

Description

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Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer
module.When the ECT_16B8C Block User Guide refers to freeze mode this is equivalent to active BDM
mode.

Section 10 Analog to Digital Converter (ATD) Block

Description

There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT128.
Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter
module. When the ATD_10B8C Block User Guide refers to freeze mode this is equivalent to active BDM
mode.

Section 11 Inter-IC Bus (IIC) Block Description

Consult the IIC Block User Guide for information about the Inter-IC Bus module.

Section 12 Serial Communications Interface (SCI) Block

Description

There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DT128
device. Consult the SCI Block User Guide for information about each Serial Communications Interface
module.

Section 13 Serial Peripheral Interface (SPI) Block

Description

There are two Serial Peripheral Interfaces (SPI1 and SPI0) implemented on MC9S12DT128. Consult the
SPI Block User Guide for information about each Serial Peripheral Interface module.

Section 14 J1850 (BDLC) Block Description

Consult the BDLC Block User Guide for information about the J1850 module.

Section 15 Byteflight (BF) Block Description

Consult the BF Block User Guide for information about the 10 Mbps Byteflight module.

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15.1 Device-specific information

The read-only Module Version Register (BFMVR) contains the current version number of $80.

Section 16 Pulse Width Modulator (PWM) Block

Description

Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module.
When the PWM_8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode.

Section 17 Flash EEPROM 128K Block Description

Consult the FTS128K Block User Guide for information about the flash module.

Section 18 EEPROM 2K Block Description

Consult the EETS2K Block User Guide for information about the EEPROM module.

Section 19 RAM Block Description

This module supports single-cycle misaligned word accesses without wait states.

Section 20 MSCAN Block Description

There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12DT128.
Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.

Section 21 Port Integration Module (PIM) Block Description

Consult the PIM_9DTB128 Block User Guide for information about the Port Integration Module.

Section 22 Voltage Regulator (VREG) Block Description

Consult the VREG Block User Guide for information about the dual output linear voltage regulator.

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Section 23 Printed Circuit Board Layout Proposal

Table 23-1 Suggested External Component Values
Component Purpose Type Value
C1 VDD1 filter cap ceramic X7R 100 … 220nF

C2 VDD2 filter cap ceramic X7R 100 … 220nF

C3 VDDA filter cap ceramic X7R 100nF

C4 VDDR filter cap X7R/tantalum >= 100nF

C5 VDDPLL filter cap ceramic X7R 100nF

C6 VDDX filter cap X7R/tantalum >= 100nF

C7 OSC load cap

C8 OSC load cap

C9 / CS PLL loop filter cap

See PLL specification chapter
C10 / CP PLL loop filter cap

Colpitts mode only, if recommended by

C11 / CDC DC cutoff cap
quartz manufacturer

R1 / R PLL loop filter res See PLL Specification chapter

R2 / RB
Pierce mode only
R3 / RS

Q1 Quartz

The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 – C6).
• Central point of the ground star should be the VSSR pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
• VSSPLL must be directly connected to VSSR.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.

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Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator

VREGEN
VDDX

C6
VSSA C3
VSSX

VDDA

VDD1

C1
VSS1
VSS2
C2

VDD2

VSSR
C4

VDDR
C5

C11

Q1
C9

C10

VSSPLL
VDDPLL
R1

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Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,

MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204) Colpitts Oscillator

VDDX

VREGEN
VSSA C3
VSSX

VDDA

VDD1
VSS2
C1 C2
VSS1
VDD2

VSSR
C4

VDDR
C11

Q1
C10
C9

VSSPLL
VDDPLL
R1

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Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator

VREGEN
VDDX

C6
VSSA C3
VSSX

VDDA

VDD1

C1
VSS1
VSS2
C2

VDD2

VSSR
R3 VSSPLL
C4

VDDR
C5

Q1
C9

C10

VDDPLL

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Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,

MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204) Pierce Oscillator

VDDX

VREGEN
VSSA C3
VSSX

VDDA

VDD1
VSS2
C1 C2
VSS1
VDD2

VSSPLL
VSSR
C4

R3
C5

VDDR R2

Q1
C8

C7
C10
C9

VSSPLL
VDDPLL
R1

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Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128, SC515846, and
SC102202) Pierce Oscillator

VDDX

VREGEN
VSSA C3
VSSX

VDDA

VDD1
VSS2
C1 C2
VSS1
VDD2

VSSPLL
VSSR
C4

R3
C5

VDDR R2

Q1
C8

C7
C10
C9

VSSPLL
VDDPLL
R1

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Appendix A Electrical Characteristics

A.1 General
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.

A.1.1 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T:
Those parameters are achieved by design characterization on a small sample size from typical
devices. All values shown in the typical column are within this category.
D:
Those parameters are derived mainly from simulations.

A.1.2 Power Supply

The MC9S12DT128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL
and internal logic.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage
regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the
oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.

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NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.

A.1.3 Pins

There are four groups of functional pins.

A.1.3.1 5V I/O pins

Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some
of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.

A.1.3.2 Analog Reference

This class is made up by the two VRH and VRL pins.

A.1.3.3 Oscillator

The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.

A.1.3.4 TEST

This pin is used for production testing only.

A.1.3.5 VREGEN

This pin is used to enable the on chip voltage regulator.

A.1.4 Current Injection

Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.

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A.1.5 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).

Table A-1 Absolute Maximum Ratings1

Num Rating Symbol Min Max Unit
1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.0 V

2 Digital Logic Supply Voltage 2 VDD -0.3 3.0 V

3 PLL Supply Voltage (2) VDDPLL -0.3 3.0 V

4 Voltage difference VDDX to VDDR and VDDA ∆VDDX -0.3 0.3 V

5 Voltage difference VSSX to VSSR and VSSA ∆VSSX -0.3 0.3 V

6 Digital I/O Input Voltage VIN -0.3 6.0 V

7 Analog Reference VRH, VRL -0.3 6.0 V

8 XFC, EXTAL, XTAL inputs VILV -0.3 3.0 V

9 TEST input VTEST -0.3 10.0 V

Instantaneous Maximum Current
10 ID -25 +25 mA
Single pin limit for all digital I/O pins 3
Instantaneous Maximum Current
11 I -25 +25 mA
DL
Single pin limit for XFC, EXTAL, XTAL4
Instantaneous Maximum Current
12 IDT -0.25 0 mA
Single pin limit for TEST 5

13 Storage Temperature Range T

stg – 65 155 °C

NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
4. Those pins are internally clamped to VSSPLL and VDDPLL.
5. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications.

A.1.6 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.

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A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Series Resistance R1 1500 Ohm
Storage Capacitance C 100 pF
Human Body
Number of Pulse per pin –
positive – 3
negative 3
Series Resistance R1 0 Ohm
Storage Capacitance C 200 pF
Machine
Number of Pulse per pin –
positive – 3
negative 3
Minimum input voltage limit –2.5 V
Latch-up
Maximum input voltage limit 7.5 V

Table A-3 ESD and Latch-Up Protection Characteristics

Num C Rating Symbol Min Max Unit
1 C Human Body Model (HBM) VHBM 2000 – V

2 C Machine Model (MM) VMM 200 – V

3 C Charge Device Model (CDM) VCDM 500 – V

Latch-up Current at 125°C
4 C positive ILAT +100 – mA
negative –100
Latch-up Current at 27°C
5 C positive ILAT +200 – mA
negative –200

A.1.7 Operating Conditions

This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.

NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature TA and the junction temperature TJ. For power dissipation

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calculations refer to Section A.1.8 Power Dissipation and Thermal

Characteristics.
Table A-4 Operating Conditions
Rating Symbol Min Typ Max Unit
I/O, Regulator and Analog Supply Voltage VDD5 4.5 5 5.25 V

Digital Logic Supply Voltage 1 VDD 2.35 2.5 2.75 V

PLL Supply Voltage 1 VDDPLL 2.25 2.5 2.75 V

Voltage Difference VDDX to VDDR and VDDA ∆VDDX -0.1 0 0.1 V

Voltage Difference VSSX to VSSR and VSSA ∆VSSX -0.1 0 0.1 V

Bus Frequency fbus 0.252 - 25 MHz

MC9S12DT128C

Operating Junction Temperature Range T

J -40 - 100 °C

Operating Ambient Temperature Range 3 T

A -40 27 85 °C

MC9S12DT128V

Operating Junction Temperature Range TJ -40 - 120 °C

Operating Ambient Temperature Range 3 TA -40 27 105 °C

MC9S12DT128M

Operating Junction Temperature Range TJ -40 - 140 °C

Operating Ambient Temperature Range 3 TA -40 27 125 °C

NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
given operating range applies when this regulator is disabled and the device is powered from an external source.
2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper oper-
ation.
3. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the rela-
tion between ambient temperature TA and device junction temperature TJ.

A.1.8 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
T J = T A + ( P D • Θ JA )

T J = Junction Temperature, [°C ]

T A = Ambient Temperature, [°C ]

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P D = Total Chip Power Dissipation, [W]

Θ JA = Package Thermal Resistance, [°C/W]

The total power dissipation can be calculated from:

P D = P INT + P IO

P INT = Chip Internal Power Dissipation, [W]

Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled

P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA

∑
2
P IO = R DSON ⋅ I IO
i i

Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
For RDSON is valid:
V OL
R DSON = ------------ ;for outputs driven low
I OL
respectively
V DD5 – V OH
R DSON = ------------------------------------ ;for outputs driven high
I OH
2. Internal voltage regulator enabled
P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA

IDDR is the current shown in (Table A-7) and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.

∑ RDSON ⋅ IIOi
2
P IO =
i

Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.

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Table A-5 Thermal Package Characteristics1

Num C Rating Symbol Min Typ Max Unit
1 T Thermal Resistance LQFP112, single sided PCB2 θJA – – 54 o
C/W
Thermal Resistance LQFP112, double sided PCB
2 T θJA – – 41 oC/W
with 2 internal planes3

3 T Junction to Board LQFP112 θJB – – 31 o

C/W

4 T Junction to Case LQFP112 θJC – – 11 o

C/W

5 T Junction to Package Top LQFP112 ΨJT – – 2 o

C/W

6 T Thermal Resistance QFP 80, single sided PCB θJA – – 51 o

C/W
Thermal Resistance QFP 80, double sided PCB with
7 T θJA – – 41 oC/W
2 internal planes

8 T Junction to Board QFP80 θJB – – 27 oC/W

9 T Junction to Case QFP80 θJC – – 14 oC/W

10 T Junction to Package Top QFP80 ΨJT – – 3 oC/W

NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-3
3. PC Board according to EIA/JEDEC Standard 51-7

A.1.9 I/O Characteristics

This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all pins feature pull up/down resistances.

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Table A-6 5V I/O Characteristics

Conditions are shown in (Table A-4) unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Input High Voltage V 0.65*VDD5 – V
IH

T Input High Voltage V – – VDD5 + 0.3

2 P Input Low Voltage V – – 0.35*VDD5 V

T Input Low Voltage V VSS5 – 0.3 – – V

3 C Input Hysteresis V 250 mV

HYS

Input Leakage Current (pins in high ohmic input

4 P mode) Iin -1.0 – 1.0 µA
V =V or VSS5
in DD5

Output High Voltage (pins in output mode)

5 C Partial Drive IOH = –2.0mA V
OH VDD5 – 0.8 – – V
P Full Drive IOH = –10.0mA

Output Low Voltage (pins in output mode)

6 C Partial Drive IOL = +2.0mA V
OL – – 0.8 V
P Full Drive IOL = +10.0mA

Internal Pull Up Device Current,

7 P tested at V Max. IPUL – – –130 µA
IL

Internal Pull Up Device Current,

8 C tested at V Min. IPUH –10 – – µA
IH

Internal Pull Down Device Current,

9 P tested at V Min. IPDH – – 130 µA
IH

Internal Pull Down Device Current,

10 C tested at V Max. IPDL 10 – – µA
IL

11 D Input Capacitance Cin 6 – pF

Injection current1
12 T Single Pin limit IICS –2.5 – 2.5 mA
Total Device Limit. Sum of all injected currents IICP –25 25

13 P Port H, J, P Interrupt Input Pulse filtered 2 tPULSE 3 µs

14 P Port H, J, P Interrupt Input Pulse passed 2 tPULSE 10 µs

NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.

A.1.10 Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.

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A.1.10.1 Measurement Conditions

All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.

A.1.10.2 Additional Remarks

In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-7 Supply Current Characteristics
Conditions are shown in (Table A-4) unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
Run supply currents
1 P mA
Single Chip, Internal regulator enabled IDD5 55
Wait Supply current
2 P All modules enabled, PLL on IDDW 30 mA
P only RTI enabled (1) 5

Pseudo Stop Current (RTI and COP disabled) 1, 2

C -40°C 370
P 27°C 400 500
C 70°C 450
C 85°C 550
3 IDDPS µA
P “C” Temp Option 100°C 600 1600
C 105°C 650
P “V” Temp Option 120°C 800 2100
C 125°C 850
P “M” Temp Option 140°C 1200 5000

Pseudo Stop Current (RTI and COP enabled) (1), (2)

C -40°C 570
C 27°C 600
C 70°C 650
4 IDDPS µA
C 85°C 750
C 105°C 850
C 125°C 1200
C 140°C 1500

Stop Current (2)

C -40°C 12
P 27°C 25 100
C 70°C 100
C 85°C 130
5 IDDS µA
P “C” Temp Option 100°C 160 1200
C 105°C 200
P “V” Temp Option 120°C 350 1700
C 125°C 400
P “M” Temp Option 140°C 600 5000

Freescale Semiconductor 105

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NOTES:
1. PLL off, Oscillator in Colpitts Mode
2. At those low power dissipation levels TJ = TA can be assumed

106 Freescale Semiconductor

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A.2 ATD Characteristics

This section describes the characteristics of the analog to digital converter.

A.2.1 ATD Operating Characteristics

The (Table A-8) shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics

Conditions are shown in (Table A-4) unless otherwise noted

Num C Rating Symbol Min Typ Max Unit
Reference Potential
1 D Low VRL VSSA VDDA/2 V
High VRH VDDA/2 VDDA V
2 C Differential Reference Voltage1 VRH-VRL 4.50 5.00 5.25 V
3 D ATD Clock Frequency fATDCLK 0.5 2.0 MHz
ATD 10-Bit Conversion Period
4 D Clock Cycles2 NCONV10 14 28 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 7 14 µs
ATD 8-Bit Conversion Period
5 D Clock Cycles(2) NCONV8 12 26 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV8 6 13 µs
6 D Stop Recovery Time (VDDA=5.0 Volts) tSR 20 µs
7 P Reference Supply current (Both ATD modules on) IREF 0.75 mA
8 P Reference Supply current (Only one ATD module on) IREF 0.375 mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.

A.2.2 Factors influencing accuracy

Three factors – source resistance, source capacitance and current injection – have an influence on the
accuracy of the ATD.

A.2.2.1 Source Resistance:

Due to the input pin leakage current as specified in (Table A-6) in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS

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specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.

A.2.2.2 Source capacitance

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS– CINN).

A.2.2.3 Current injection

There are two cases to consider.

1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than
VRL unless the current is higher than specified as disruptive conditions.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-9 ATD Electrical Characteristics

Conditions are shown in (Table A-4) unless otherwise noted

Num C Rating Symbol Min Typ Max Unit
1 C Max input Source Resistance RS - - 1 KΩ

Total Input Capacitance

2 T Non Sampling CINN 10 pF
Sampling CINS 22

3 C Disruptive Analog Input Current INA -2.5 2.5 mA

4 C Coupling Ratio positive current injection Kp 10-4 A/A

5 C Coupling Ratio negative current injection Kn 10-2 A/A

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A.2.3 ATD accuracy

(Table A-10) specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table A-10 ATD Conversion Performance

Conditions are shown in (Table A-4) unless otherwise noted

VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz
Num C Rating Symbol Min Typ Max Unit
1 P 10-Bit Resolution LSB 5 mV
2 P 10-Bit Differential Nonlinearity DNL –1 1 Counts
3 P 10-Bit Integral Nonlinearity INL –2.5 ±1.5 2.5 Counts

4 P 10-Bit Absolute Error1 AE -3 ±2.0 3 Counts

5 P 8-Bit Resolution LSB 20 mV

6 P 8-Bit Differential Nonlinearity DNL –0.5 0.5 Counts
7 P 8-Bit Integral Nonlinearity INL –1.0 ±0.5 1.0 Counts

8 P 8-Bit Absolute Error(1) AE -1.5 ±1.0 1.5 Counts

NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.

For the following definitions see also Figure A-1.

Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
DNL ( i ) = ------------------------ – 1
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
Vn – V0
INL ( n ) = ∑ DNL ( i ) = -------------------- – n
1LSB
i=1

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DNL

LSB 10-Bit Absolute Error Boundary

Vi-1 Vi

$3FF
8-Bit Absolute Error Boundary
$3FE

$3FD

$3FC $FF

$3FB

$3FA

$3F9

$3F8 $FE

$3F7

$3F6

$3F5
10-Bit Resolution

8-Bit Resolution
$3F4 $FD

$3F3

9
Ideal Transfer Curve
8 2

6
10-Bit Transfer Curve
5

4 1

2
8-Bit Transfer Curve
1

0
5 10 15 20 25 30 35 40 45 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV

Figure A-1 ATD Accuracy Definitions

NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10.

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A.3 NVM, Flash and EEPROM

NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.

A.3.1 NVM timing

The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP.
The minimum program and erase times shown in (Table A-11) are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.

A.3.1.1 Single Word Programming

The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
1 1
t swpgm = 9 ⋅ --------------------- + 25 ⋅ ----------
f NVMOP f bus

A.3.1.2 Row Programming

This applies only to the Flash where up to 32 words in a row can be programmed consecutively by keeping
the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1
t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ----------
f NVMOP f bus

The time to program a whole row is:

t brpgm = t swpgm + 31 ⋅ t bwpgm
Row programming is more than 2 times faster than single word programming.

A.3.1.3 Sector Erase

Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:

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1
t era ≈ 4000 ⋅ ---------------------
f NVMOP
The setup time can be ignored for this operation.

A.3.1.4 Mass Erase

Erasing a NVM block takes:

1
t mass ≈ 20000 ⋅ ---------------------
f NVMOP
The setup time can be ignored for this operation.

A.3.1.5 Blank Check

The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t check ≈ location ⋅ t cyc + 10 ⋅ t cyc

Table A-11 NVM Timing Characteristics

Conditions are shown in (Table A-4) unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 D External Oscillator Clock fNVMOSC 0.5 50 1 MHz

2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 MHz

3 D Operating Frequency fNVMOP 150 200 kHz

4 P Single Word Programming Time tswpgm 46 2 74.5 3 µs

5 D Flash Row Programming consecutive word 4 tbwpgm 20.4 (2) 31 (3) µs

6 D Flash Row Programming Time for 32 Words (4) tbrpgm 678.4 (2) 1035.5 (3) µs

7 P Sector Erase Time tera 20 5 26.7 (3) ms

8 P Mass Erase Time tmass 100 (5) 133 (3) ms

9 D Blank Check Time Flash per block tcheck 11 6 32778 7 tcyc

10 D Blank Check Time EEPROM per block tcheck 11 (6) 1034(7) tcyc

NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus.
3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus.
Refer to formulae in Sections Section A.3.1.1 Single Word Programming- Section A.3.1.4 Mass Erasefor guidance.
4. Row Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block

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A.3.2 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.

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Table A-12 NVM Reliability Characteristics1

Conditions are shown in (Table A-4) unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
Flash Reliability Characteristics
Data retention after 10,000 program/erase cycles at an —
1 C
average junction temperature of TJavg ≤ 85°C
15 1002
tFLRET Years
Data retention with <100 program/erase cycles at an —
2 C
average junction temperature TJavg ≤ 85°C
20 1002

Number of program/erase cycles —

3 C 10,000 —
(–40°C ≤ TJ ≤ 0°C)
nFL Cycles
Number of program/erase cycles —
4 C
(0°C ≤ TJ ≤ 140°C)
10,000 100,0003

EEPROM Reliability Characteristics

Data retention after up to 100,000 program/erase cycles
5 C
at an average junction temperature of TJavg ≤ 85°C
15 1002 —
tEEPRET Years
Data retention with <100 program/erase cycles at an
6 C
average junction temperature TJavg ≤ 85°C
20 1002 —

Number of program/erase cycles

7 C 10,000 — —
(–40°C ≤ TJ ≤ 0°C)
nEEP Cycles
Number of program/erase cycles
8 C
(0°C < TJ ≤ 140°C)
100,000 300,0003 —

NOTES:
1. TJavg will not exeed 85°C considering a typical temperature profile over the lifetime of a consumer, industrial or automotive
application.
2. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618.
3. Spec table quotes typical endurance evaluated at 25°C for this product family, typical endurance at various temperature
can be estimated using the graph below. For additional information on how Freescale defines Typical Endurance, please
refer to Engineering Bulletin EB619.

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Figure A-2 Typical Endurance vs Temperature

500

450
Typical Endurance [103 Cycles]

400

350

300

250

200

150

100

0
-40 -20 0 20 40 60 80 100 120 140
Operating Temperature TJ [°C]
------ Flash
------ EEPROM

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116 Freescale Semiconductor

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A.4 Voltage Regulator

The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external
DC load is allowed.

Table A-13 Voltage Regulator Recommended Load Capacitances

Rating Symbol Min Typ Max Unit

Load Capacitance on VDD1, 2 CLVDD 220 nF

Load Capacitance on VDDPLL CLVDDfcPLL 220 nF

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A.5 Reset, Oscillator and PLL

This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).

A.5.1 Startup

(Table A-14) summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.

Table A-14 Startup Characteristics

Conditions are shown in (Table A-4) unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 T POR release level VPORR 2.07 V

2 T POR assert level VPORA 0.97 V

3 D Reset input pulse width, minimum input time PWRSTL 2 tosc

4 D Startup from Reset nRST 192 196 nosc

5 D Interrupt pulse width, IRQ edge-sensitive mode PWIRQ 20 ns

6 D Wait recovery startup time tWRS 14 tcyc

A.5.1.1 POR

The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.

A.5.1.2 SRAM Data Retention

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.

A.5.1.3 External Reset

When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.

A.5.1.4 Stop Recovery

Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.

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A.5.1.5 Pseudo Stop and Wait Recovery

The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts
fetching the interrupt vector.

A.5.2 Oscillator

The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset.By asserting the
XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before
asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start
from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the
internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also
determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A

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Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert
Frequency fCMFA.
Table A-15 Oscillator Characteristics
Conditions are shown in (Table A-4) unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1a C Crystal oscillator range (Colpitts) fOSC 0.5 16 MHz

1b C Crystal oscillator range (Pierce) 1 fOSC 0.5 40 MHz

2 P Startup Current iOSC 100 µA

3 C Oscillator start-up time (Colpitts) tUPOSC 82 1003 ms

4 D Clock Quality check time-out tCQOUT 0.45 2.5 s

5 P Clock Monitor Failure Assert Frequency fCMFA 50 100 200 KHz

6 P External square wave input frequency 4 fEXT 0.5 50 MHz

7 D External square wave pulse width low tEXTL 9.5 ns

8 D External square wave pulse width high tEXTH 9.5 ns

9 D External square wave rise time tEXTR 1 ns

10 D External square wave fall time tEXTF 1 ns

11 D Input Capacitance (EXTAL, XTAL pins) CIN 7 pF

DC Operating Bias in Colpitts Configuration on
12 C VDCBIAS 1.1 V
EXTAL Pin

13 P EXTAL Pin Input High Voltage4 VIH,EXTAL 0.75*VDDPLL V

T EXTAL Pin Input High Voltage4 VIH,EXTAL VDDPLL + 0.3 V

14 P EXTAL Pin Input Low Voltage4 VIL,EXTAL 0.25*VDDPLL V

T EXTAL Pin Input Low Voltage4 VIL,EXTAL VSSPLL - 0.3 V

15 C EXTAL Pin Input Hysteresis4 VHYS,EXTAL 250 mV

NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. fosc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. XCLKS =0 during reset

A.5.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.

A.5.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

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VDDPLL

Cs R XFC Pin
Phase VCO
fosc 1 fref fvco
∆ KΦ KV
refdv+1
Detector
fcmp

Loop Divider
1 1
synr+1 2

Figure A-3 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from (Table A-16).
The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used
for fOSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
( f 1 – f vco ) ( 60 – 50 )
----------------------- ------------------------
K 1 ⋅ 1V – 100
KV = K1 ⋅ e = – 100 ⋅ e = -90.48MHz/V
The phase detector relationship is given by:

K Φ = – i ch ⋅ K V = 316.7Hz/Ω
ich is the current in tracking mode.
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.

2 ⋅ ζ ⋅ f ref 1 f ref
f C < ------------------------------------------ ------ → f C < -------------- ;( ζ = 0.9 )
2 10 4 ⋅ 10

π⋅ ζ+ 1+ζ
  fC < 25kHz

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And finally the frequency relationship is defined as

f VCO
n = ------------- = 2 ⋅ ( synr + 1 ) = 50
f ref

With the above values the resistance can be calculated. The example is shown for a loop bandwidth
fC=10KHz:
2 ⋅ π ⋅ n ⋅ fC
R = ----------------------------- = 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ =~ 10kΩ
KΦ

The capacitance Cs can now be calculated as:

2
2⋅ζ 0.516
C s = ---------------------- ≈ --------------- ;( ζ = 0.9 ) = 5.19nF =~ 4.7nF
π ⋅ fC ⋅ R fC ⋅ R

The capacitance Cp should be chosen in the range of:

C s ⁄ 20 ≤ C p ≤ C s ⁄ 10 Cp = 470pF

A.5.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.

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0 1 2 3 N-1 N

tmin1
tnom
tmax1

tminN
tmaxN

Figure A-4 Jitter Definitions

The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:

 t max ( N ) t min ( N ) 
J ( N ) = max  1 – --------------------- , 1 – --------------------- 
 N ⋅ t nom N ⋅ t nom 

For N < 100, the following equation is a good fit for the maximum jitter:

j1
J ( N ) = -------- + j 2
N

J(N)

1 5 10 20 N

Figure A-5 Maximum bus clock jitter approximation

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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.

Table A-16 PLL Characteristics

Conditions are shown in (Table A-4) unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Self Clock Mode frequency fSCM 1 5.5 MHz

2 D VCO locking range fVCO 8 50 MHz

Lock Detector transition from Acquisition to Tracking
3 D |∆trk| 3 4 %1
mode

4 D Lock Detection |∆Lock| 0 1.5 %(1)

5 D Un-Lock Detection |∆unl| 0.5 2.5 %(1)

Lock Detector transition from Tracking to Acquisition
6 D |∆unt| 6 8 %(1)
mode

7 C PLLON Total Stabilization delay (Auto Mode) 2 tstab 0.5 ms

8 D PLLON Acquisition mode stabilization delay (2) tacq 0.3 ms

9 D PLLON Tracking mode stabilization delay (2) tal 0.2 ms

10 D Fitting parameter VCO loop gain K1 -100 MHz/V

11 D Fitting parameter VCO loop frequency f1 60 MHz

12 D Charge pump current acquisition mode | ich | 38.5 µA

13 D Charge pump current tracking mode | ich | 3.5 µA

14 C Jitter fit parameter 1(2) j1 1.1 %

15 C Jitter fit parameter 2(2) j2 0.13 %

NOTES:
1. % deviation from target frequency
2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
10KΩ.

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A.6 MSCAN
Table A-17 MSCAN Wake-up Pulse Characteristics

Conditions are shown in (Table A-4) unless otherwise noted

Num C Rating Symbol Min Typ Max Unit
1 P MSCAN Wake-up dominant pulse filtered tWUP 2 µs

2 P MSCAN Wake-up dominant pulse pass tWUP 5 µs

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A.7 SPI
A.7.1 Master Mode

Figure A-6 and Figure A-7 illustrate the master mode timing. Timing values are shown in (Table
A-18).
SS1
(OUTPUT)

2 1 11 3
SCK 4
(CPOL = 0)
(OUTPUT) 4
12
SCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

9 9 10

MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT

1.if configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure A-6 SPI Master Timing (CPHA = 0)

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SS1
(OUTPUT)
1
2 12 11 3
SCK
(CPOL = 0)
(OUTPUT)
4 4 11 12
SCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

9 10
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure A-7 SPI Master Timing (CPHA =1)

Table A-18 SPI Master Mode Timing Characteristics1

Conditions are shown in (Table A-4) unless otherwise noted, CLOAD = 200pF on all outputs

Num C Rating Symbol Min Typ Max Unit

1 P Operating Frequency fop DC 1/2 fbus

1 P SCK Period tsck = 1./fop tsck 4 2048 tbus

2 D Enable Lead Time tlead 1/2 — tsck

3 D Enable Lag Time tlag 1/2 tsck

4 D Clock (SCK) High or Low Time twsck tbus − 30 1024 tbus ns

5 D Data Setup Time (Inputs) tsu 25 ns

6 D Data Hold Time (Inputs) thi 0 ns

9 D Data Valid (after SCK Edge) tv 25 ns

10 D Data Hold Time (Outputs) tho 0 ns

11 D Rise Time Inputs and Outputs tr 25 ns

12 D Fall Time Inputs and Outputs tf 25 ns

NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in (Table A-19).

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A.7.2 Slave Mode

Figure A-8 and Figure A-9 illustrate the slave mode timing. Timing values are shown in (Table A-19).
SS
(INPUT)

1 12 11 3
SCK
(CPOL = 0)
(INPUT)
2 4 4
11 12
SCK
(CPOL = 1)
(INPUT) 8
7 9 10 10
MISO
(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT

5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

Figure A-8 SPI Slave Timing (CPHA = 0)

SS
(INPUT)
1 3
2 12 11
SCK
(CPOL = 0)
(INPUT)
4 4 11 12
SCK
(CPOL = 1)
(INPUT)
9 10 8
MISO
(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT

7 5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

Figure A-9 SPI Slave Timing (CPHA =1)

Freescale Semiconductor 131

Device User Guide — 9S12DT128DGV2/D V02.17

Table A-19 SPI Slave Mode Timing Characteristics

Conditions are shown in (Table A-4) unless otherwise noted, CLOAD = 200pF on all outputs
Num C Rating Symbol Min Typ Max Unit
1 P Operating Frequency fop DC 1/4 fbus

1 P SCK Period tsck = 1./fop tsck 4 2048 tbus

2 D Enable Lead Time tlead 1 tcyc

3 D Enable Lag Time tlag 1 tcyc

4 D Clock (SCK) High or Low Time twsck tcyc − 30 ns

5 D Data Setup Time (Inputs) tsu 25 ns

6 D Data Hold Time (Inputs) thi 25 ns

7 D Slave Access Time ta 1 tcyc

8 D Slave MISO Disable Time tdis 1 tcyc

9 D Data Valid (after SCK Edge) tv 25 ns

10 D Data Hold Time (Outputs) tho 0 ns

11 D Rise Time Inputs and Outputs tr 25 ns

12 D Fall Time Inputs and Outputs tf 25 ns

132 Freescale Semiconductor

Device User Guide — 9S12DT128DGV2/D V02.17

A.8 External Bus Timing

A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing
values shown on table (Table A-20). All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.

A.8.1 General Multiplexed Bus Timing

The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.

Freescale Semiconductor 133

Device User Guide — 9S12DT128DGV2/D V02.17

1, 2
3 4

ECLK
PE4

5 6 16 10
9 15 11
Addr/Data
data addr data
(read)
PA, PB
7
8

12 14 13
Addr/Data
data addr data
(write)
PA, PB

17 18 19
Non-Multiplexed
Addresses
PK5:0

20 21 22 23
ECS
PK7

24 25 26
R/W
PE2

27 28 29
LSTRB
PE3

30 31 32
NOACC
PE7

33 34 35 36
PIPO0
PIPO1, PE6,5

Figure A-10 General External Bus Timing

134 Freescale Semiconductor

Device User Guide — 9S12DT128DGV2/D V02.17

Table A-20 Expanded Bus Timing Characteristics

Conditions are shown in (Table A-4) unless otherwise noted, CLOAD = 50pF

Num C Rating Symbol Min Typ Max Unit

1 P Frequency of operation (E-clock) fo 0 25.0 MHz

2 P Cycle time tcyc 40 ns

3 D Pulse width, E low PWEL 19 ns

4 D Pulse width, E high1 PWEH 19 ns

5 D Address delay time tAD 8 ns

6 D Address valid time to E rise (PWEL–tAD) tAV 11 ns

7 D Muxed address hold time tMAH 2 ns

8 D Address hold to data valid tAHDS 7 ns

9 D Data hold to address tDHA 2 ns

10 D Read data setup time tDSR 13 ns

11 D Read data hold time tDHR 0 ns

12 D Write data delay time tDDW 7 ns

13 D Write data hold time tDHW 2 ns

14 D Write data setup time(1) (PWEH–tDDW) tDSW 12 ns

15 D Address access time(1) (tcyc–tAD–tDSR) tACCA 19 ns

16 D E high access time(1) (PWEH–tDSR) tACCE 6 ns

17 D Non-multiplexed address delay time tNAD 6 ns

18 D Non-muxed address valid to E rise (PWEL–tNAD) tNAV 15 ns

19 D Non-multiplexed address hold time tNAH 2 ns

20 D Chip select delay time tCSD 16 ns

21 D Chip select access time(1) (tcyc–tCSD–tDSR) tACCS 11 ns

22 D Chip select hold time tCSH 2 ns

23 D Chip select negated time tCSN 8 ns

24 D Read/write delay time tRWD 7 ns

25 D Read/write valid time to E rise (PWEL–tRWD) tRWV 14 ns

26 D Read/write hold time tRWH 2 ns

27 D Low strobe delay time tLSD 7 ns

28 D Low strobe valid time to E rise (PWEL–tLSD) tLSV 14 ns

29 D Low strobe hold time tLSH 2 ns

30 D NOACC strobe delay time tNOD 7 ns

31 D NOACC valid time to E rise (PWEL–tNOD) tNOV 14 ns

Freescale Semiconductor 135

Device User Guide — 9S12DT128DGV2/D V02.17

Table A-20 Expanded Bus Timing Characteristics

Conditions are shown in (Table A-4) unless otherwise noted, CLOAD = 50pF

Num C Rating Symbol Min Typ Max Unit

32 D NOACC hold time tNOH 2 ns

33 D IPIPO[1:0] delay time tP0D 2 7 ns

34 D IPIPO[1:0] valid time to E rise (PWEL–tP0D) tP0V 11 ns

35 D IPIPO[1:0] delay time(1) (PWEH-tP1V) tP1D 2 25 ns

36 D IPIPO[1:0] valid time to E fall tP1V 11 ns

NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.

136 Freescale Semiconductor

Device User Guide — 9S12DT128DGV2/D V02.17

Appendix B Package Information

B.1 General
This section provides the physical dimensions of the MC9S12DT128 packages.

Freescale Semiconductor 137

Device User Guide — 9S12DT128DGV2/D V02.17

B.2 112-pin LQFP package

4X 0.20 T L-M N 4X 28 TIPS 0.20 T L-M N J1 4X P

PIN 1
112 85
IDENT J1

1 84
CL

VIEW Y X
108X G
X=L, M OR N

VIEW Y
B V

L M
B1 J AA
V1

28 57 F BASE
METAL
D
29 56
0.13 M T L-M N
N
SECTION J1-J1
A1 ROTATED 90 ° COUNTERCLOCKWISE

S1 NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
S 3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
C2 VIEW AB 6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
C 0.050 θ2 PROTRUSION SHALL NOT CAUSE THE D
0.10 T 112X DIMENSION TO EXCEED 0.46.

SEATING MILLIMETERS
PLANE
DIM MIN MAX
θ3 A 20.000 BSC
T A1 10.000 BSC
B 20.000 BSC
B1 10.000 BSC
C --- 1.600
C1 0.050 0.150
C2 1.350 1.450
θ D 0.270 0.370
E 0.450 0.750
F 0.270 0.330
G 0.650 BSC
J 0.090 0.170
R R2
K 0.500 REF
P 0.325 BSC
R1 0.100 0.200
R R1 0.25 R2 0.100 0.200
S 22.000 BSC
GAGE PLANE S1 11.000 BSC
V 22.000 BSC
V1 11.000 BSC
Y 0.250 REF
(K) Z 1.000 REF
C1 θ1 AA 0.090 0.160
E θ 0° 8 °
(Y) θ1 3 ° 7 °
θ2 11 ° 13 °
(Z) θ3 11 ° 13 °
VIEW AB

Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987)

138 Freescale Semiconductor

Device User Guide — 9S12DT128DGV2/D V02.17

B.3 80-pin QFP package

60 41
61 40

S
S
B

D
D
P

S
S
B
-A- -B-

C A-B
H A-B
L B V

0.05 D

M
M
-A-,-B-,-D-

0.20
0.20
DETAIL A
DETAIL A

21
80

1 20
F
-D-
A
0.20 M H A-B S D S

0.05 A-B
J N
S
0.20 M C A-B S D S

D
M
E DETAIL C 0.20 M C A-B S D S

SECTION B-B
C DATUM
VIEW ROTATED 90 °
-H- PLANE
-C- 0.10
SEATING H
PLANE M
G

NOTES: MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982. DIM MIN MAX
2. CONTROLLING DIMENSION: MILLIMETER. A 13.90 14.10
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF B 13.90 14.10
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC C 2.15 2.45
U BODY AT THE BOTTOM OF THE PARTING LINE. D 0.22 0.38
4. DATUMS -A-, -B- AND -D- TO BE E 2.00 2.40
T DETERMINED AT DATUM PLANE -H-.
F 0.22 0.33
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-. G 0.65 BSC
DATUM -H- 6. DIMENSIONS A AND B DO NOT INCLUDE H --- 0.25
PLANE R MOLD PROTRUSION. ALLOWABLE J 0.13 0.23
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH K 0.65 0.95
AND ARE DETERMINED AT DATUM PLANE -H-. L 12.35 REF
7. DIMENSION D DOES NOT INCLUDE DAMBAR M 5° 10 °
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN N 0.13 0.17
EXCESS OF THE D DIMENSION AT MAXIMUM P 0.325 BSC
K Q MATERIAL CONDITION. DAMBAR CANNOT Q 0° 7°
W BE LOCATED ON THE LOWER RADIUS OR R 0.13 0.30
THE FOOT.
S 16.95 17.45
X T 0.13 ---
DETAIL C U 0° ---
V 16.95 17.45
W 0.35 0.45
X 1.6 REF

Figure 1 80-pin QFP Mechanical Dimensions (case no. 841B)

Freescale Semiconductor 139

Device User Guide — 9S12DT128DGV2/D V02.17

140 Freescale Semiconductor

Device User Guide — 9S12DT128DGV2/D V02.17

User Guide End Sheet

Freescale Semiconductor 141

FINAL PAGE OF
142
PAGES

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2008.

9S12DT128DGV2/D
V02.17, 03 Jun 2010

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