bq2004

Fast-Charge IC
Features General Description ment of the battery, or switch de-
pression. For safety, fast charge is
➤ Fast charge and conditioning of The bq2004 Fast Charge IC pro- inhibited unless/until the battery
nickel cadmium or nickel-metal vides comprehensive fast charge con- temperature and voltage are within
hydride batteries trol functions together with high-speed configured limits.
switching power control circuitry on a Temperature, voltage, and time are
➤ Hysteretic PWM switch-mode monolithic CMOS device.
current regulation or gated con- monitored throughout fast charge.
trol of an external regulator Integration of closed-loop current Fast charge is terminated by any of
control circuitry allows the bq2004 the following:
➤ Easily integrated into systems or to be the basis of a cost-effective so-
used as a stand-alone charger n Rate of temperature time
lution for stand-alone and system- (∆ T/∆ t)
➤ Pre-charge qualification of tem- integrated chargers for batteries of
perature and voltage one or more cells. n Peak voltage detection (PVD)

➤ Configurable, direct LED outputs Switch-activated discharge-before- n Negative delta voltage (-∆ V)
display battery and charge status charge allows bq2004-based chargers
to support battery conditioning and n Maximum voltage
➤ Fast-charge termination by ∆ tem- capacity determination. n Maximum temperature
perature/∆ time, peak volume de-
tection, -∆V, maximum voltage, High-efficiency power conversion is n Maximum time
maximum temperature, and maxi- accomplished using the bq2004 as a
hysteretic PWM controller for After fast charge, optional top-off
mum time
switch-mode regulation of the charg- and pulsed current maintenance
➤ Optional top-off charge and ing current. The bq2004 may alterna- phases are available.
pulsed current maintenance tively be used to gate an externally
charging regulated charging current.
➤ Logic-level controlled low-power Fast charge may begin on applica-
mode (< 5µA standby current) tion of the charging supply, replace-

Pin Connections Pin Names

DCMD Discharge command SNS Sense resistor input

DSEL Display select LED1 Charge status output 1

DCMD 1 16 INH
VSEL Voltage termination LED2 Charge status output 2
DSEL 2 15 DIS
select
VSEL 3 14 MOD
VSS System ground
TM1 Timer mode select 1
TM1 4 13 VCC VCC 5.0V ±10% power
TM2 5 12
TM2 Timer mode select 2
VSS
MOD Charge current control
TCO 6 11 LED2 TCO Temperature cutoff
DIS Discharge control
TS 7 10 LED1 TS Temperature sense output
BAT 8 9 SNS
BAT Battery voltage INH Charge inhibit input
16-Pin Narrow DIP
or Narrow SOIC
PN2004E01.eps

SLUS063B–APRIL 2005 H

1
bq2004

Pin Descriptions SNS Charging current sense input

SNS controls the switching of MOD based on
DCMD Discharge-before-charge control input an external sense resistor in the current
path of the battery. SNS is the reference po-
The DCMD input controls the conditions tential for both the TS and BAT pins. If
that enable discharge-before-charge. DCMD SNS is connected to VSS, then MOD switches
is pulled up internally. A negative-going high at the beginning of charge and low at
pulse on DCMD initiates a discharge to end- the end of charge.
of-discharge voltage (EDV) on the BAT pin,
followed by a new charge cycle start. Tying LED1– Charge status outputs
D C M D to g r o und e nabl e s a u t om a t ic LED2
discharge-before-charge on every new charge Push-pull outputs indicating charging
cycle start. status. See Table 2.
DSEL Display select input VSS Ground
This three-state input configures the charge VCC VCC supply input
status display mode of the LED1 and LED2
outputs. See Table 2. 5.0V, ±10% power input.
VSEL Voltage termination select input MOD Charge current control output
This three-state input controls the voltage- MOD is a push-pull output that is used to
termination technique used by the bq2004. control the charging current to the battery.
When high, PVD is active. When floating, MOD switches high to enable charging cur-
-∆V is used. When pulled low, both PVD and rent to flow and low to inhibit charging
-∆V are disabled. current flow.

TM1– Timer mode inputs DIS Discharge control output

TM2
TM1 and TM2 are three-state inputs that Push-pull output used to control an external
configure the fast charge safety timer, voltage transistor to discharge the battery before
termination hold-off time, “top-off”, and charging.
trickle charge control. See Table 1.
INH Charge inhibit input
TCO Temperature cut-off threshold input
When low, the bq2004 suspends all charge
Input to set maximum allowable battery actions, drives all outputs to high imped-
temperature. If the potential between TS ance, and assumes a low-power operational
and SNS is less than the voltage at the TCO state. When transitioning from low to high,
input, then fast charge or top-off charge is ter- a new charge cycle is started.
minated.

TS Temperature sense input

Input, referenced to SNS, for an external
thermister monitoring battery temperature.

BAT Battery voltage input

BAT is the battery voltage sense input, refer-
enced to SNS. This is created by a high-
impedance resistor-divider network con-
nected between the positive and the negative
terminals of the battery.

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 bq2004

Functional Description Discharge-Before-Charge

Figure 3 shows a block diagram and Figure 4 shows a The DCMD input is used to command discharge-before-
state diagram of the bq2004. charge via the DIS output. Once activated, DIS be-
comes active (high) until VCELL falls below VEDV, at
Battery Voltage and Temperature which time DIS goes low and a new fast charge cycle be-
Measurements gins.

Battery voltage and temperature are monitored for The DCMD input is internally pulled up to VCC (its inac-
maximum allowable values. The voltage presented on tive state). Leaving the input unconnected, therefore,
the battery sense input, BAT, should represent a results in disabling discharge-before-charge. A negative
two-cell potential for the battery under charge. A going pulse on DCMD initiates discharge-before-charge
resistor-divider ratio of: at any time regardless of the current state of the
bq2004. If DCMD is tied to V SS , discharge-before-
RB1 N charge will be the first step in all newly started charge
= -1
RB2 2 cycles.
is recommended to maintain the battery voltage within
the valid range, where N is the number of cells, RB1 is
Starting a Charge Cycle
the resistor connected to the positive battery terminal, A new charge cycle (see Figure 2) is started by:
and RB2 is the resistor connected to the negative bat-
tery terminal. See Figure 1. 1. VCC rising above 4.5V

Note: This resistor-divider network input impedance to 2. VCELL falling through the maximum cell voltage,
end-to-end should be at least 200kΩ and less than 1MΩ. VMCV where:

A ground-referenced negative temperature coefficient ther- VMCV = 0.8 ∗ VCC ± 30mV

mistor placed in proximity to the battery may be used as a
3. A transition on the INH input from low to high.
low-cost temperature-to-voltage transducer. The tempera-
ture sense voltage input at TS is developed using a If DCMD is tied low, a discharge-before-charge is exe-
resistor-thermistor network between VCC and VSS. See cuted as the first step of the new charge cycle. Other-
Figure 1. Both the BAT and TS inputs are referenced to wise, pre-charge qualification testing is the first step.
SNS, so the signals used inside the IC are:
The battery must be within the configured temperature
VBAT - VSNS = VCELL and voltage limits before fast charging begins.
and The valid battery voltage range is VEDV < VBAT < VMCV
where:
VTS - VSNS = VTEMP
VEDV = 0.4 ∗ VCC ± 30mV

Negative Temperature
Coefficient Thermister
VCC

PACK +
RT1
PACK+
TS
bq2004 RB1 N
bq2004 RT2 T
BAT
C
RB2
SNS PACK -
SNS PACK-

Fg2004a.eps

Figure 1. Voltage and Temperature Monitoring

3
bq2004

Dis- Charge Fast Charging Top-Off Pulse-Trickle

charge Pending* (Optional)
(Optional) (Pulse-Trickle)

DIS

260 s 260 s
Switch-mode
MOD Configuration
2080 s Note*
260 s 260 s
or
External
MOD Regulation
2080 s Note*
(SNS Grounded)
Mode 1, LED2 Status Output

Mode 1, LED1 Status Output

Mode 2, LED2 Status Output

Mode 2, LED1 Status Output

Mode 3, LED2 Status Output

Mode 3, LED1 Status Output

Battery within temperature/voltage limits.

Battery discharged to 0.4 * VCC. Battery outside

temperature/voltage limits.

Discharge-Before-Charge started

*See Table 3 for pulse-trickle period. TD200401a.eps

Figure 2. Charge Cycle Phases

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 bq2004

The valid temperature range is VHTF < VTEMP < VLTF, Each sample is an average of voltage measurements
where: taken 57µs apart. The IC takes 32 measurements in
PVD mode and 16 measurements in -∆V mode. The re-
VLTF = 0.4 ∗ VCC ± 30mV sulting sample periods (9.17ms and 18.18ms, respec-
VHTF = [(1/4 ∗ VLTF) + (3/4 ∗ VTCO)] ± 30mV tively) filter out harmonics centered around 55Hz and
109Hz. This technique minimizes the effect of any AC
Note: The low temperature fault (LTF) threshold is not line ripple that may feed through the power supply from
enforced if the IC is configured for PVD termination either 50Hz or 60Hz AC sources. Tolerance on all tim-
(VSEL = high). ing is ±16%.
VTCO is the voltage presented at the TCO input pin, and is Voltage Termination Hold-off
configured by the user with a resistor divider between VCC
and ground. The allowed range is 0.2 to 0.4 ∗ VCC. A hold-off period occurs at the start of fast charging.
During the hold-off period, -∆V termination is disabled.
If the temperature of the battery is out of range, or the
This avoids premature termination on the voltage
voltage is too low, the chip enters the charge pending
spikes sometimes produced by older batteries when
state and waits for both conditions to fall within their al-
fast-charge current is first applied. ∆T/∆t, maximum
lowed limits. The MOD output is modulated to provide
voltage and maximum temperature terminations are
the configured trickle charge rate in the charge pending
not affected by the hold-off period.
state. There is no time limit on the charge pending
state; the charger remains in this state as long as the T/ t Termination
voltage or temperature conditons are outside of the al-
The bq2004 samples at the voltage at the TS pin every
lowed limits. If the voltage is too high, the chip goes to
34s, and compares it to the value measured two samples
the battery absent state and waits until a new charge
earlier. If VTEMP has fallen 16mV ±4mV or more, fast
cycle is started.
charge is terminated. If VSEL = high, the ∆T/∆t termi-
Fast charge continues until termination by one or more nation test is valid only when VTCO < VTEMP < VTCO +
of the six possible termination conditions: 0.2 ∗ VCC. Otherwise the ∆T/∆t termination test is valid
only when VTCO < VTEMP < VLTF.
n Delta temperature/delta time (∆T/∆t)
n Peak voltage detection (PVD) Temperature Sampling
n Negative delta voltage (-∆ V) Each sample is an average of 16 voltage measurements
taken 57µs apart. The resulting sample period
n Maximum voltage (18.18ms) filters out harmonics around 55Hz. This tech-
nique minimizes the effect of any AC line ripple that
n Maximum temperature may feed through the power supply from either 50Hz or
n Maximum time 60Hz AC sources. Tolerance on all timing is ±16%.

PVD and - V Termination Maximum Voltage, Temperature, and Time

The bq2004 samples the voltage at the BAT pin once Anytime VCELL rises above VMCV, the LEDs go off and
every 34s. When -∆V termination is selected, if VCELL is charging ceases immediately. If VCELL then falls back be-
lower than any previously measured value by 12mV low VMCV before tMCV = 1.5s ±0.5s, the chip transitions to
±4mV (6mV/cell), fast charge is terminated. When PVD the Charge Complete state (maximum voltage termina-
termination is selected, if VCELL is lower than any previ- tion). If VCELL remains above VMCV at the expiration of
tMCV, the bq2004 transitions to the Battery Absent state
(battery removal). See Figure 4.
VSEL Input Voltage Termination
Maximum temperature termination occurs anytime
Low Disabled VTEMP falls below the temperature cutoff threshold
Float -∆V VTCO. Unless PVD termination is enabled (VSEL =
High PVD high), charge will also be terminated if VTEMP rises
above the low temperature fault threshold, VLTF, after
fast charge begins. The VLTF threshold is not enforced
when the IC is configured for PVD termination.
ously measured value by 6mV ±2mV (3mV/cell), fast
charge is terminated. The PVD and -∆V tests are valid Maximum charge time is configured using the TM pin.
in the range 0.4 ∗ VCC < VCELL < 0.8 ∗ VCC. Time settings are available for corresponding charge
rates of C/4, C/2, 1C, and 2C. Maximum time-out termi-
Voltage Sampling nation is enforced on the fast-charge phase, then reset,

5
bq2004

and enforced again on the top-off phase, if selected. top-off is enabled and C/32 when top-off is disabled.
There is no time limit on the trickle-charge phase. Both pulse trickle and top-off may be disabled by tying
TM1 and TM2 to VSS.
Top-off Charge
Charge Status Indication
An optional top-off charge phase may be selected to
follow fast charge termination for the C/2 through 4C Charge status is indicated by the LED1 and LED2 out-
rates. This phase may be necessary on NiMH or other puts. The state of these outputs in the various charge cy-
battery chemistries that have a tendency to terminate cle phases is given in Table 2 and illustrated in Figure 2.
charge prior to reaching full capacity. With top-off en-
abled, charging continues at a reduced rate after In all cases, if VCELL exceeds the voltage at the MCV
fast-charge termination for a period of time equal to pin, both LED1 and LED2 outputs are held low regard-
the fast-charge safety time (See Table 1.) During top- less of other conditions. Both can be used to directly
off, the MOD pin is enabled at a duty cycle of 260µs ac- drive an LED.
tive for every 1820µs inactive. This modulation results
in an average rate 1/8th that of the fast charge rate. Charge Current Control
Maximum voltage, time, and temperature are the only The bq2004 controls charge current through the MOD
termination methods enabled during top-off. output pin. The current control circuitry is designed to
support implementation of a constant-current switching
Pulse-Trickle Charge regulator or to gate an externally regulated current
Pulse-trickle charging follows the fast charge and op- source.
tional top-off charge phases to compensate for self- When used in switch mode configuration, the nominal
discharge of the battery while it is idle in the charger. regulated current is:
The configured pulse-trickle rate is also applied in the
charge pending state to raise the voltage of an over- IREG = 0.225V/RSNS
discharged battery up to the minimum required before
fast charge can begin. Charge current is monitored at the SNS input by the
voltage drop across a sense resistor, RSNS, between the
In the pulse-trickle mode, MOD is active for 260µs of a low side of the battery pack and ground. RSNS is sized
period specified by the settings of TM1 and TM2. See to provide the desired fast charge current.
Table 1. The resulting trickle-charge rate is C/64 when

Table 1. Fast-Charge Safety Time/Hold-Off/Top-Off Table

Corresponding Typical Typical Pulse- Pulse-

Fast-Charge Fast-Charge Safety PVD, -∆ V Hold-Off Top-Off Trickle Trickle
Rate TM1 TM2 Time (minutes) Time (seconds) Rate Rate Period (Hz)
C/4 Low Low 360 137 Disabled Disabled Disabled
C/2 Float Low 180 820 Disabled C/32 240
1C High Low 90 410 Disabled C/32 120
2C Low Float 45 200 Disabled C/32 60
4C Float Float 23 100 Disabled C/32 30
C/2 High Float 180 820 C/16 C/64 120
1C Low High 90 410 C/8 C/64 60
2C Float High 45 200 C/4 C/64 30
4C High High 23 100 C/2 C/64 15

Note: Typical conditions = 25°C, VCC = 5.0V.

6
 bq2004

If the voltage at the SNS pin is less than VSNSLO, the VSNSLO = 0.04 ∗ VCC ± 25mV
MOD output is switched high to pass charge current to
VSNSHI = 0.05 ∗ VCC ± 25mV
the battery.
When used to gate an externally regulated current
When the SNS voltage is greater than VSNSHI, the MOD
source, the SNS pin is connected to VSS, and no sense
output is switched low—shutting off charging current to
resisitor is required.
the battery.

Table 2. bq2004 LED Status Display Options

Mode 1 Charge Status LED1 LED2
Battery absent Low Low
Fast charge pending or discharge-before-charge in progress High High
DSEL = VSS
Fast charge in progress Low High
Charge complete, top-off, and/or trickle High Low
Mode 2 Charge Status LED1 LED2
Battery absent, fast charge in progress or complete Low Low
Fast charge pending High Low
DSEL = Floating
Discharge in progress Low High
Top-off in progress High High
Mode 3 Charge Status LED1 LED2
Battery absent Low Low
1/8s high
Fast charge pending or discharge-before-charge in progress Low
DSEL = VCC 1/8s low
Fast charge in progress Low High
Fast charge complete, top-off, and/or trickle High Low

TM1 TM2 TCO

Timing TCO TS
OSC
Control Check
LED1
Display LTF
LED2 Check
Control
DSEL
VTS - VSNS

VBAT - VSNS A/D SNS

DCMD Charge Control
State Machine
DVEN EDV
Check

Discharge MOD PWR MCV

BAT
Control Control Control Check

DIS MOD INH VCC VSS

BD200401.eps

Figure 3. Block Diagram

7
bq2004

New Charge Cycle Started by

Any One of: Rising Edge
on DCMD
VCC Rising to Valid Level

Battery Replacement Yes

DCMD Tied to Ground?
(VCELL Falling through VMCV)

Inhibit (INH) Released No

VCELL < VEDV Discharge-

VEDV < VCELL < VMCV
Before-Charge
Battery Voltage?

Charge VCELL < VEDV VCELL > VMCV

Pending VCELL > VMCV
VTEMP > VLTF or
VTEMP < VHTF VCELL >
Pulse VMCV
Battery Temperature? Trickle
Charge

VHTF < VTEMP < VLTF*

Battery
VEDV < VCELL < VMCV Absent
and
VHTF < VTEMP < VLTF*
Pulse t > tMCV Pulse
Fast
Charge Trickle Trickle
VCELL > VMCV Charge Charge

- V or VCELL <
T/ t or VMCV
VTEMP < VTCO Charge
or Complete
Maximum Time Out VCELL > VCELL >
VMCV VMCV

Top-Off Pulse
Top-Off Trickle
Selected? Yes Charge Charge
VTEMP < VTCO
No or Maximum
Time Out

*VSEL = High disables LTF threshold enforcement

SD2004.eps

Figure 4. State Diagram

8
 bq2004

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

VCC VCC relative to VSS -0.3 +7.0 V
DC voltage applied on any pin ex-
VT -0.3 +7.0 V
cluding VCC relative to VSS
TOPR Operating ambient temperature -20 +70 °C Commercial
TSTG Storage temperature -55 +125 °C
TSOLDER Soldering temperature - +260 °C 10 sec max.
TBIAS Temperature under bias -40 +85 °C

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

DC Thresholds (TA = TOPR; VCC ±10%)

Symbol Parameter Rating Tolerance Unit Notes

High threshold at SNS result-
VSNSHI 0.05 * VCC ±0.025 V
ing in MOD = Low
Low threshold at SNS result-
VSNSLO 0.04 * VCC ±0.025 V
ing in MOD = High
VTEMP ≥ VLTF inhib-
VLTF Low-temperature fault 0.4 * VCC ±0.030 V
its/terminates charge
VTEMP ≤ VHTF inhibits
VHTF High-temperature fault (1/4 * VLTF) + (3/4 * VTCO) ±0.030 V
charge
VCELL < VEDV inhibits
VEDV End-of-discharge voltage 0.4 * VCC ±0.030 V
fast charge
VCELL > VMCV inhibits/
VMCV Maximum cell voltage 0.8 * VCC ±0.030 V
terminates charge
TS input change for∆T/∆t
VTHERM -16 ±4 mV VCC = 5V, TA = 25°C
detection
BAT input change for -∆V
-∆V -12 ±4 mV VCC = 5V, TA = 25°C
detection
BAT input change for PVD
PVD -6 ±2 mV VCC = 5V, TA = 25°C
detection

9
bq2004

Recommended DC Operating Conditions (TA = TOPR)

Symbol Condition Minimum Typical Maximum Unit Notes

VCC Supply voltage 4.5 5.0 5.5 V

VBAT Battery input 0 - VCC V

VCELL BAT voltage potential 0 - VCC V VBAT - VSNS

VTS Thermistor input 0 - VCC V

VTEMP TS voltage potential 0 - VCC V VTS - VSNS

VTCO Temperature cutoff 0.2 * VCC - 0.4 * VCC V Valid ∆ T/∆ t range

Logic input high 2.0 - - V DCMD, INH

VIH
Logic input high VCC - 0.3 - - V TM1, TM2, DSEL, VSEL

Logic input low - - 0.8 V DCMD, INH

VIL
Logic input low - - 0.3 V TM1, TM2, DSEL, VSEL

DIS, MOD, LED1, LED2,

VOH Logic output high VCC - 0.8 - - V
IOH ≤ -10mA

DIS, MOD, LED1, LED2,

VOL Logic output low - - 0.8 V
IOL ≤ 10mA

ICC Supply current - 1 3 mA Outputs unloaded

ISB Standby current - - 1 µA INH = VIL

IOH DIS, LED1, LED2, MOD source -10 - - mA @VOH = VCC - 0.8V

IOL DIS, LED1, LED2, MOD sink 10 - - mA @VOL = VSS + 0.8V

Input leakage - - ±1 µA INH, BAT, V = VSS to VCC

IL
Input leakage 50 - 400 µA DCMD, V = VSS to VCC

µA TM1, TM2, DSEL, VSEL,

IIL Logic input low source - - 70
V = VSS to VSS + 0.3V

µA TM1, TM2, DSEL, VSEL,

IIH Logic input high source -70 - -
V = VCC - 0.3V to VCC

TM1, TM2, DSEL, and VSEL

IIZ Tri-state -2 - 2 µA should be left disconnected
(floating) for Z logic input state

Note: All voltages relative to VSS except as noted.

10
 bq2004

Impedance

Symbol Parameter Minimum Typical Maximum Unit

RBAT Battery input impedance 50 - - MΩ
RTS TS input impedance 50 - - MΩ
RTCO TCO input impedance 50 - - MΩ
RSNS SNS input impedance 50 - - MΩ

Timing (TA = 0 to +70°C; VCC ±10%)

Symbol Parameter Minimum Typical Maximum Unit Notes

Pulse width for DCMD µs Pulse start for charge or discharge
tPW 1 - -
and INH pulse command before charge
dFCV Time base variation -16 - 16 % VCC = 4.75V to 5.25V
MOD output regulation
fREG - - 300 kHz
frequency
Maximum voltage termi- Time limit to distinguish battery re-
tMCV 1 - 2 s
nation time limit moved from charge complete.

Note: Typical is at TA = 25°C, VCC = 5.0V.

11
bq2004

Data Sheet RevisionHistory

Change No. Page No. Description Nature of Change
1 10 Standby current ISB Was 5 A max; is 1 A max
Was: VSNSHI - (0.01 * V CC)
2 9 VBSNSLO Rating
Is: 0.04 * V CC
2 7 Correction in Peak Voltage Detect Termination section Was VCELL; is VBAT
2 3 Added block diagram Diagram insertion
2 7 Added VSEL/terminationtable Table insertion
2 8 Added values to Table 3 Top-off rate values
3 7 VSEL/Termination Low, High changed
4 All Revised and expanded format of this data sheet Clarification

Was: (1/3 VLTF ) + (2/3 VTCO)

5 9 Corrected VHTF rating
Is: (1/4 VLTF ) + (3/4 VTCO)
Deleted industrial tempera-
6 9 TOPR
ture range
Was: (1/4 * VLTF ) + (2/3 * VTCO)
7 9 Corrected VHTF DC threshold Is: (1/4 * VLTF ) + (3/4 * VTCO)
Was: ±0.010
8 9 Corrected VSNSLO tolerance Is: ±0.025

Notes: Change 1 = Apr. 1994 B “Final” changes from Dec. 1993 A “Preliminary.”
Change 2 = Sept. 1996 C changes from Apr. 1994 B.
Change 3 = April 1997 C changes from Sept. 1996 C.
Change 4 = Oct. 1997 D changes from April 1997 C.
Change 5 = Jan. 1998 E changes from Oct. 1997 D.
Change 6 = June 1999 F changes from Jan. 1998 E.
Change 7 = Feb. 2001 G changes from June 1999 F.
Change 8 = Apr. 2005 H changes from Feb. 2001 G.

Ordering Information

bq2004

Package Option:
PN = 16-pin narrow plastic DIP
SN = 16-pin narrow SOIC

Device:
bq2004 Fast-Charge IC

12
 bq2004

16-Pin DIP Narrow (PN)

16-Pin PN (0.300" DIP)

Inches Millimeters
Dimension Min. Max. Min. Max.
A 0.160 0.180 4.06 4.57
A1 0.015 0.040 0.38 1.02
B 0.015 0.022 0.38 0.56
B1 0.055 0.065 1.40 1.65
C 0.008 0.013 0.20 0.33
D 0.740 0.770 18.80 19.56
E 0.300 0.325 7.62 8.26
E1 0.230 0.280 5.84 7.11
e 0.300 0.370 7.62 9.40
G 0.090 0.110 2.29 2.79
L 0.115 0.150 2.92 3.81
S 0.020 0.040 0.51 1.02

13
bq2004

16-Pin SOIC Narrow (SN)

16-Pin SN (0.150" SOIC)

Inches Millimeters
D Dimension Min. Max. Min. Max.
B
e A 0.060 0.070 1.52 1.78
A1 0.004 0.010 0.10 0.25
B 0.013 0.020 0.33 0.51
E
C 0.007 0.010 0.18 0.25
H D 0.385 0.400 9.78 10.16
E 0.150 0.160 3.81 4.06

A e 0.045 0.055 1.14 1.40

C A1 H 0.225 0.245 5.72 6.22
L 0.015 0.035 0.38 0.89
.004
L

14
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ2004PN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -20 to 70 2004PN Samples
-A4
BQ2004SN ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 70 2004 Samples
(-A4, A4)
BQ2004SNG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 70 2004 Samples
(-A4, A4)
BQ2004SNTR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 70 2004 Samples
(-A4, A4)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ2004SNTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ2004SNTR SOIC D 16 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
BQ2004PN N PDIP 16 25 506 13.97 11230 4.32
BQ2004SN D SOIC 16 40 506.6 8 3940 4.32
BQ2004SNG4 D SOIC 16 40 506.6 8 3940 4.32

Pack Materials-Page 3
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