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Assign05_logic

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Htayhtay Thwe
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13 views

Assign05_logic

Uploaded by

Htayhtay Thwe
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 5

( Lecture No. 6,7,8 )


1. For the parallel adder in the Figure below, determine the complete sum by
analyzing the circuit's logical operation. Verify your result by longhand addition
of the two input numbers.

2. The input waveforms in Figure below are applied to a 2-bit adder. Determine
the waveform for the sum and the output carry in relation to the inputs by
constructing a timing diagram.
3. The waveforms in the Figure below are applied to the comparator as shown.
Determine the output (A=B) waveform.

4. For the 4-bit comparator in Figure below, plot each output waveform for the
inputs shown below. The outputs are active-HIGH.
5. If the waveforms in the Figure below are applied to an active-HIGH S-R latch,
draw the resulting Q output waveform in relation to the inputs. Assume that Q
starts LOW.

6. Determine the output of a gated D latch for the inputs in the Figure below.
Assuming that initially Q = 0.

7. For a positive edge-triggered D flip-flop with the input as shown in Figure


below, determine the Q output relative to the clock. Assume that Q starts LOW.

8. The Q output of an edge-triggered D flip-flop is shown in relation to the clock


signal in Figure below. Determine the input waveform on the D input that is
required to produce this output if the flip-flop is a positive edge-triggered type.
9. For a negative edge-triggered J-K flip-flop with the inputs in Figure below,
develop the Q output waveform relative to the clock. Assume that Q is initially
LOW.

10. Determine the Q waveform relative to the clock if the signals shown in the Figure
below are applied to the inputs of the positive-edge trigger J-K flip-flop. Assume that
Q is initially LOW.

10. A leading-edge clocked serial in/serial out shift register has a data-output waveform as shown
in the figure below. What binary number is stored in the 8-bit register if the first data bit out
(left-most) is the LSB?
11. The input signals for the shift register are shown in the Figure below. The
serial data input (SER) is 0. The parallel data inputs are D0 = 1, D1 = 0, D2 =
1, and D3 = 0 as shown. Develop the data-output waveform in relation to the
inputs.

12. For the ripple counter shown in the Figure below, show the complete timing
diagram for eight clock pulses, showing the clock, Q0, and Q1 waveforms.

Assuming Q0 and Q1 are initially 0.

>>>>>>>>>>>>>>>>>>> <<<<<<<<<<<<<<<<<<<

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