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Lab7 - Combinational Arithmetic Circuits

Digital Electronics Lab7 - Combinational Arithmetic Circuits

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7 views

Lab7 - Combinational Arithmetic Circuits

Digital Electronics Lab7 - Combinational Arithmetic Circuits

Uploaded by

alaminuiu07
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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United International University (UIU)

Dept. of Electrical & Electronic Engineering (EEE)


EEE 224: Digital Electronics Laboratory

Lab 7: Combinational Arithmetic Circuits

PURPOSE

The purpose of this laboratory project is to familiarize students with the hierarchical digital design
using simulation software available in the laboratory. In this lab, we will design a combinational
device with Xilinx ISE Design Suite: a 4-bit arithmetic logic unit (ALU).

This device will be used in the data-path of a simple computer we implement in a later lab.

PRELAB

Combinational Arithmetic Devices


The goal is to review digital arithmetic and design very simple ALU-like circuit.

1) Review course material from Mano. Pay particular attention to the material on number systems
and binary arithmetic, the implementation of combinational devices to perform such operations,
and the interpretation of IEEE standard symbols for combinational logic.

2) Construct a truth-table for a combinational circuit comp_2bit with a 1-bit enable EN, a 2-bit
input A (A1, A0), a 2-bit input B (B1, B0), and a 2-bit output Z (Z1, Z0). The inputs A and B
represent 2-bit binary numbers. When disabled (EN = 0), Z = x0 (binary 00). When enabled,
the value of the output Z depends upon the values of A and B, as shown below:
Condition Z (Hex) Z (Binary)
A<B x1 01
A>B x2 10
A=B x3 11

3) Design a combinational circuit that realizes the functionality of comp_2bit using a 2-bit 4-to-1
line multiplexer (such as the 74LS153 – see TTL Databook for details) and a minimal number
of logic gates. Using functional decomposition, attempt to implement the design using no more
than the multiplexer, an AND gate, an OR gate and four inverters. Your lab write-up for every
circuit designed should also include a description of the circuit's functionality (as you
understand it) and an explanation what factors led to final implementation of your design. A
good lab book should include any "false starts" which provided additional knowledge that led
you to the final implementation presented.

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4) Construct a truth-table for a 2-bit adder add_2bit with a 2-bit input A (A1..A0), a 2-bit input B
(B1..B0), a 2-bit output S (S1..S0) and a 1-bit output Cout. Refer to the textbook if you require
assistance. Design the combinational circuit that realizes the functionality of add_2bit.

5) Design a 3-bit 2-to-1 line multiplexer. Your design should accept two 3-bit inputs (labeled I0
and I1), a 1-bit select input (labeled S) and produce a 3-bit output (labeled MUX). Refer to the
textbook if you require assistance. You may design this circuit with existing multiplexers
(recommended), logic gates (not recommended), or programmable logic devices (PLD).
√Include the logic diagram of your 3-bit, 2-to-1 line multiplexer in your lab book.

6) Design a combinational circuit both_2bit with two 2-bit inputs (A and B) and a 1-bit input
Add/Comp. The design has one 3-bit output C whose value is determined as follows. When
Add/Comp = 1, C = A + B (i.e. C2C1C0 = CoutS1S0 from add_2bit). When Add/Comp = 0, the
value of C is x1, x2, or x3 as described in the table for Z in circuit comp_2bit (i.e. C2 = 0, and
C1C0 = Z1Z0). √Include the logic diagram of your design in your lab book

EXPERIMENT

√√ Demonstrate the function of each of your circuits (as you implement them one at a time) to
your lab instructor. Be prepared to answer questions about the function of the devices and the
design choices you faced in the implementation. You will be asked to demonstrate the
functionality of your design for some input values.

1. Implement your design with Verilog HDL using structural model and save the module as
comp_2bit.v. Use vectors to provide the necessary bit-values from the multi-bit inputs in
an organized fashion. √Include a printout of your module in your lab book.

2. Write a behavioral Verilog module for the combinational circuit that realizes the
functionality of add_2bit. Save the circuit as add_2bit.v and √include a printout of your
design module in your lab book along with any necessary commentary.

3. Implement the 3-bit 2-to-1 line multiplexer using Verilog HDL. Save the circuit as
mux_3bit_2to1.v. √Include printout of your 3-bit, 2-to-1 line multiplexer in your lab book.

4. Write the design module (both_2bit.v) and a test bench (both_2bit_tb.v) and simulate the
circuit. You should try the hierarchical design method by using the modules defined earlier.
Using the user-defined module allows you to avoid recreating each element and focus on
the design of a simplified module. √Include a printout of the modules and timing diagram
in your lab book.

FINAL REPORT
All that is required for this Lab is your Verilog modules and timing diagram printouts.

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