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DSD hw 5

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13 views5 pages

DSD hw 5

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Ali Ahmad
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© © All Rights Reserved
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CPE 344 Digital System Design

Assignment 5

Design the video graphics array (VGA) controller using VHDL and reproduce RTL view on Quartus

Introduction

The monitor screen for a standard VGA format contains 640 columns by 480 rows of picture elements called
pixels as shown in Figure 1. An image is displayed on the screen by turning on or off individual pixels. The
monitor continuously scans through the entire screen turning on or off one pixel at a time at a very fast speed.
The scan starts from row 0, column 0 at the top left corner, and moves to the right until it reaches the last
column in the row. When the scan reaches the end of a row, it continues at the beginning of the next row.
When the scan reaches the last pixel at the bottom right corner of the screen, it goes back to the top left corner
of the screen, and repeats the scanning process again. In order to reduce flicker on the screen, the entire screen
must be scanned 60 times per second or higher. During the horizontal and the vertical retraces, all the pixels
are turned off.

Figure VGA monitor with 640 columns x 480 rows

The VGA monitor is controlled by five signals: red, green, blue, horizontal synchronization, and vertical
synchronization. The three color signals, referred to collectively as the RGB signal, are used to control the
color of a pixel at a location on the screen.
Figure VGA controller

Synchronization Timing

You will design a VGA controller for a standard screen displaying a resolution of 640 x 480. A 25 MHz clock
will be used to drive the controller, which is sufficient to accomplish this resolution. A standard monitor
operates at 60Hz i.e. it refreshes itself 60 times in a second.
First, we drive the timing for Horizontal Row Scan signal, HRS. This signal consist of four regions, the sync
pulse (SP), the back porch (BP), horizontal video (HV) and the front porch (FP). The SP signals the beginning
of new line and accomplish by bringing the HS signal low for 96 pixel clock cycles. The signals are than
brought high for the back porch where the pixels are not written yet to the screen at the left. After the BP the
HS signal remains high for the horizontal video period where the pixels are written to the screen proceeding
from left to right. Finally the HS signal also remains high during the FP where no pixel is written to the
screen.
The timing for all four regions of Horizontal Scan signal is given in figure below.

Figure Horizontal Video

Pixel clock = 25 Mhz Pixel Time = 0.04 usec


Horizontal Video, HV = 640 pixels = 640 x 0.04 uS = 25.6 usec
Sync Pulse, SP = 96 pixels = 3.84 usec.
Back Porch, BP = 48 pixels = 1.92 usec.
Front Porch, FP= 16 pixels = 640 nsec.
Horizontal Scan Signal (One Horizontal Line) = 640 + 96 + 48 +16 = 800 pixel clocks = 32 us

The figure and calculations above show that it would need to scan for 800 pixel clocks in order to write
640 pixels in a horizontal line.
As a standard VGA monitor operates at 60Hz i.e. 60 frames per second. One frame must be written in 1/60th
second or 16.67 msec. So it is possible to write 521 horizontal lines which are consistent with our target
resolution 640 x 480. Since 521 is greater than 480, it is perfect for synchronizing the Vertical Sync signal
(VS). VS signal also has, the Sync Pulse (SP), Back Porch (BP), Front Porch (FP) and Vertical Video (VV)
regions.

Figure Vertical Video

Pixel clock = 25 Mhz Pixel Time = 0.04 usec


Horizontal Scan signal = 32 us
Vertical Video, VV = 480 lines = 480 x 32 us = 15.360 usec
Sync Pulse, SP = 2 lines x 32 us = 0.064 ms.
Back Porch, BP = 29 lines x 32 us = 0.928ms.
Front Porch, FP= 10 lines x 32 us = 0.320 ms.
Vertical Scan Signal (One Horizontal Line) = 480 + 2 + 29 +10 = 521 lines x 32 us = 16.672ms
The figure and calculations above show that it scans through 521 horizontal lines to display 480
horizontal lines in a frame.

In Lab (Transfer VHDL code into the FPGA board as well)

Task-Part 1

In this lab you will write VHDL description of a digital system ‘VGA Stripes’ for Altera FPGA boards. The
system should display fifteen green and fifteen red horizontal lines on a VGA monitor’s screen as shown in
figure 14.10. A reset pin should be available to wipe out the stripes when pressed.

Figure

The system may have following components in it:

i. Clock Divider (CLKDIV):


On the Altera FPGA board a clock source of 100 MHz is available whereas the VGA controller requires 25
MHz clock frequency.
Figure Clock divider

Generate a test bench for CLKDIV to show the results in simulation using Quartus.

ii. VGA Controller (VGA_CONT640x480)


The module will count the pixel clocks and generate the horizontal and vertical synchronization signals.
Another signal that indicate the time for writing pixel in 640 x480 display area will also be generated in this
module.

Figure VGA Controller

HSYNC should get LOW (0) for 96 pixel clocks (Horizontal Sync period) in the beginning of each horizontal
row. It is HIGH (1) for rest of the time that includes Back Porch, Horizontal Video, and Front Porch as shown
in figure 14.3.
VSYNC should get LOW (0) for 2 horizontal cycles in the beginning of each frame. It is HIGH (1) for rest of
the time that includes Back Porch, Horizontal Video, and Front Porch as shown in figure 14.4.
HCount is horizontal 10 bit counter that counts the number of pixels. It starts from zero and counts up to 799
for one horizontal row scan and then reset itself to count for next row.
VCount counts (10 bits) the number of horizontal lines. It starts from zero and counts up to 519 in one frame.
The counter then reset to start count for next frame.
VIDON signals HIGH when the pixel data should be written on VGA display i.e. when the horizontal and
vertical counters are within the 640 x 480 display area. It gets HIGH when both Horizontal Video and Vertical
Video signals are high and LOW otherwise.

Generate a test bench for VGA_CONT640x480 to show the results in simulation using ISim or
Modelsim.

iii. Stripes Generator (STRIPES_GEN)

The module is responsible for filling the RED and GREEN colors in the vertical lines. The goal is to generate
a display on VGA monitor screen that shows 15 RED and 15 GREEN lines as in figure 14.10.
Figure

Top Level Module (VGA_TOP)


Now it is time to assemble all above three components. Assemble them as in figure below

Red(2:0) Green(2:0) Blue(1:0)

Figure

The system has CLK and RESET signal as inputs and three-color signals R, G and B as outputs making 8 bit
value for each pixel in VGA color screen.
Note that VGA_CONT640x480‘s output signals HSYNC and VSYNC are not used in the STRIPES_GEN
module. Instead they are used to generate VIDON signal inside the VGA_CONT640x480 module.

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