JUSTICE BASHEER AHMED SAYEED COLLEGE FOR WOMEN

(Autonomous) Afternoon Session Chennai 18.

S.I.E.T.

DECODERS
&
DEMULTIPLEXERS Mrs. A.Prema

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 Data Processing
Circuits
Multiplexers & De-
Multiplexers

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 MULTIPLEXERS
• A multiplexers (MUX) is a device that allows digital
information from several sources to be routed onto a
single line for transmission that line to a common
destination.
• The basic multiplexers has several data input lines
and a single output line.
• MUX is also called as data selector because the
output bit depends on the input data bit that is
selected.

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 Functional diagram of MUX

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 2x1 multiplexer

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 Four-to-One Line multiplexer

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 4x1 Multiplexer

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 8x1 Multiplexer

A B C F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

MS LS
B Z = A′.B'.C'.I0 + B
A'.B'.C.I 1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

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 8x1 Multiplexer

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 Demultiplexers
● De-multiplexer means “one into many”.
● It is a combinational logic circuit with one input and
many outputs.
● A demultiplexer has
− 1 data input, N control inputs, 2N outputs
● A demultiplexer routes (or connects) the data input to
the selected output.
− The value of the control inputs determines the output that
is selected.
● A demultiplexer performs the opposite function of a
multiplexer.

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 Demultiplexers

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 De-multiplexers
Ou W W=
tOu
0 X A'.B'.I
I I X=
tOu
1 Y
n A.B'.I
tOu
2 Z Y=
S1 S0t3 A'.B.I
Z=
A.B.I
A B
A B W X Y Z
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I

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 Decoders

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 Decoders
• Decoder is a combinational circuit that that converts binary information from n
input lines to a maximum of 2n unique output lines.
• If the n-bit coded information has n unused combinations, the decoder may have
fewer than 2 outputs.
• A decoder is a logic circuit that accepts a set of inputs that represents a binary
number and activates only the output that corresponds to the input number.
• In other words, a decoder circuit looks at its inputs, determines which binary
number is present there, and activates the one output that corresponds to that
number ; all other outputs remain inactive.
• Converting from Binary to Decimal is called Decode.

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 Decoders
❖The decoders presented here are called n- to- m -line decoders, where m < or equal to 2 .
❖Their n purpose is to generate the 2 (or fewer) minterms of n input variables.
❖Each combination of inputs will assert a unique output.

Ou W W=
B I tOu
0 X A'.B'
X=
A 0
I tOu
1 Y A.B'
tOu Y=
ms
1 2 Z
t3
A'.B
Z=
b
Active-high outputs A.B
A B W X Y Z
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

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 Decoders
W=
Ou W
tOu
(A'.B')'
X=
B I 0 X
A 0
I tOu
1 Y (A.B')'
Y=
1 tOu
2 Z (A'.B)'
ms t3 Z=
b (A.B)'
Active-low
outputs
A B W X Y Z
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

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 Decoders
Consider the three-to-eight-line decoder circuit as shown below

❖ The three inputs are decoded into eight outputs, each

representing one of the minterms of the three input variables.
❖The three inverters provide the complement of the inputs,
and each one of the eight AND gates generates one of the
minterms.
❖A particular application of this decoder is binary-to-octal
conversion.
❖The input variables represent a binary number, and the
outputs represent the eight digits of a number in the octal
number system.
❖However, a three-to-eight-line decoder can be used for
decoding any three-bit code to provide eight outputs, one
for each element of the code.

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 Decoders
The operation of the decoder may be clarified by the truth table given below

❖ For each possible input combination, there are seven outputs that are equal to 0

and only one that is equal to 1.

❖The output whose value is equal to 1 represents the minterm equivalent of the
binary number currently available in the input lines.

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 Decoders
⮚Example: Design BCD-to-Decimal decoder

❖ Here the decoder should have four inputs to accept the coded digit and ten outputs , one for
each decimal digit.
❖This will give 4-to-10 line decoder.
❖ There are six don’t-care condition and they must be taken into consideration when we simplify
each of the output function
❖Six input combinations will never occur so we mark their corresponding minterm squares with
X’s as shown below.

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 Decoders
❖It is the designers responsibility to decide on how to treat the don’t-care conditions.
❖Using the don’t-care terms we obtain the following circuit.

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 Decoders
❖An analysis of the circuit shows that the six invalid input combination will produce outputs as
listed below.

❖Another reasonable design would be to make all outputs equal to 0 when an invalid input
combination occurs.

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 Combinational Logic
Implementation
❖Any combinational circuit with n inputs and m outputs can be implemented with an
n-to-2n line decoder and m OR gates.
❖The procedure for implementing a combinational circuit by means of a decoder and
OR gates requires that the Boolean function for the circuit be expressed as a sum of
minterms.
❖This can be obtained from the truth table or by expanding the functions to their sum
of minterms.
❖A decoder is then chosen that generates all the minterms of the input variables.
❖ The inputs to each OR gate are selected from the decoder outputs according to the
list of minterms of each function.

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 Combinational Logic
Implementation
❖Example: Implement a full-adder circuit with a decoder and two OR gates.

❖From the truth table of the full adder , we obtain the

functions for the combinational circuit in sum-of-
minterms form as :
S(x, y, z) = ∑ (1, 2, 4, 7)
C(x, y, z) = ∑ (3, 5, 6, 7)

❖Since there are three inputs and a total of eight minterms, we need a
three-to-eight line decoder.

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 Combinational Logic
Implementation
❖The implementation is shown below

❖The decoder generates the eight minterms

for x, y, z.
❖The OR gate for output S forms the
logical sum of minterms 1, 2, 4, and 7.
❖The OR gate for output C forms the
logical sum of minterms 3, 5, 6, and 7.

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 Decoder with Enable
❖ Some decoders are constructed with NAND gates.
❖Since a NAND gate produces the AND operation with an inverted output, it becomes more
economical to generate the decoder minterms in their complemented form.
❖Decoders include one or more enable inputs to control the circuit operation.
❖A two-to-four-line decoder with an enable input constructed with NAND gates is shown
below:

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 Decoder with Enable
❖ The circuit operates with complemented outputs and a complement enable input.
❖The decoder is enabled when E is equal to 0 (i.e., active-low enable).
❖Only one output can be equal to 0 at any given time.
❖all other outputs are equal to 1.
❖The output whose value is equal to 0 represents the minterm selected by inputs A and B.
❖The circuit is disabled when E is equal to 1, regardless of the values of the other two inputs.
❖ When the circuit is disabled, none of the outputs are equal to 0 and none of the minterms are
selected.
❖In general, a decoder may operate with complemented or uncomplemented outputs.
❖The enable input may be activated with a 0 or with a 1 signal.
❖Some decoders have two or more enable inputs that must satisfy a given logic condition in
order to enable the circuit.

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 Demultiplexer
❖ A decoder with enable input can function as a demultiplexer — a circuit that receives n information from
a single line and directs it to one of 2 possible output lines.
❖The selection of a specific output is controlled by the bit combination of n selection lines.
❖The one-to-four-line decoder can function as a one-to-four-line demultiplexer when E is taken as a data
input line and A and B are taken as the selection inputs.
❖The single input variable E has a path to all four outputs, but the input
information is directed to only one of the output lines, as specified by the
binary combination of the two selection lines A and B.
❖ This feature can be verified from the truth table of the circuit.
❖ For example, if the selection lines AB = 10, output D2 will be the
same as the input value E , while all other outputs are maintained at 1.
❖ Because decoder and demultiplexer operations are obtained from the
same circuit, a decoder with an enable input is referred to as a decoder –
demultiplexer .

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 Demultiplexer
❖ Decoders with enable inputs can be connected together to form a larger decoder circuit.
❖The below figure shows two 3-to-8-line decoders with enable inputs connected to form a 4-to-16-line
decoder.

❖When w = 0, the top decoder is enabled and the other is

disabled.
❖The bottom decoder outputs are all 0’s, and the top eight
outputs generate minterms 0000 to 0111.
❖When w = 1, the enable conditions are reversed: The bottom
decoder outputs generate minterms 1000 to 1111, while the
outputs of the top decoder are all 0’s.

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 Decoder with Enable
Ou W
B I
low- tOu
0 X
0
level A I tOu
1 Y
enable 1
tOu
2 Z
Enabl E
t3
e n

En A B W X Y Z
0 0 0 1 0 0 0
0 0 1 0 1 0 0
enable
0 1 0 0 0 1 0
d
0 1 1 0 0 0 1
disable 1 x x 0 0 0 0
d

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 Decoder
• Decoders are used in many types of applications. One
example is in computers for I/O selection.
• Computer must communicate with a variety of external
devices called peripherals by sending and/or receiving
data through what is known as input/output (I/O) ports
• Each I/O port has a number, called an address, which
uniquely identifies it. When the computer wants to
communicate with a particular device, it issues the
appropriate address code for the I/O port to which that
particular device is connected.
• The binary port address is decoded and appropriate
decoder output is activated to enable the I/O port.
• Binary data are transferred within the computer on a
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 Encoders

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 Encoder
•An encoder is a combinational logic circuit that
essentially performs a “reverse” of decoder functions.
•An encoder has 2N inputs and N outputs.
•An encoder accepts an active level on one of its
inputs, representing digit, such as a decimal or octal
digits, and converts it to a coded output such as BCD
or binary.
•Encoders can also be devised to encode various
symbols and alphabetic characters.
•Converting from Decimal to Binary is called Encode.
•The process of converting from familiar symbols or
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numbers to a coded format is called encoding. 32
 Encoder Design

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 Encoders
D I
0
C I Out Z
1 0Out Y
B I
1
2
A I
3

A B C D Y Z
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

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 Multiplexer Vs Encoder
•A multiplexer or MUX is a combination circuit
that contains more than one input line, one
output line and more than one selection line.
•Whereas, an encoder is also considered a type
of multiplexer but without a single output line.
•It is a combinational logic function that has 2N
input lines and N output lines.

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 Thank You

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